Power module control method and power device

Abstract

The invention provides a power module control method and power equipment, and relates to the technical field of power control. The method comprises the following steps: carrying out logic processing on the same-phase overcurrent signals of a plurality of power modules to generate a common current-limiting control signal, and carrying out current-limiting control on the plurality of power modules under the condition that the current-limiting control signal is effective; in the process of the current limiting control, monitoring the outer tube driving high level duration lost by each power module due to the current limiting control; and adjusting the current limiting control duration of each power module according to the length difference of the lost outer tube driving high level. During the current-limiting control process, the outer tube driving high level length loss of each module is monitored in real time, the energy rebalance is realized through differentially adjusting the current-limiting time length, the energy can be dynamically compensated, and the efficient power control is realized.

Description

Technical Field

[0001] This application relates to the field of power control technology, and more specifically, to a control method and power device for a power module. Background Technology

[0002] Against the backdrop of global energy structure transformation and large-scale deployment of renewable energy, energy storage systems are increasingly becoming a key support for building new power systems. As the core equipment of energy storage systems, energy storage converters (PCS) are constantly developing towards higher integration and greater power density. Under this trend, using multiple sets of three-phase power modules in parallel combined with carrier interleaved modulation technology has become an effective means to improve system capacity and reduce output current ripple.

[0003] However, with the increase in the number of parallel modules, the complexity of system protection design increases significantly. Cycle-by-Cycle (CBC) overcurrent protection, as a commonly used final hardware protection measure in PCS, faces severe challenges in the implementation of multi-module parallel scenarios. Traditional solutions require sampling the three-phase inverter inductor current of each power module separately and comparing it with the protection threshold to independently generate overcurrent signals for each path. Taking a two-module parallel system as an example, a total of 6 overcurrent signals need to be processed; if expanded to n modules in parallel, the controller needs to process 3n overcurrent signals. This not only consumes a large amount of controller pin resources but also increases the complexity and cost of system hardware design, restricting the further development of PCS systems towards higher power levels and more compact integration. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a power module control method and a power device to improve the above-mentioned problems existing in the prior art.

[0005] In a first aspect, embodiments of this application provide a control method for a power module. The method includes: performing logical processing on the same phase overcurrent signal of multiple power modules to generate a shared current limiting control signal, and performing current limiting control on the multiple power modules when the current limiting control signal is valid; during the current limiting control process, monitoring the duration of the external transistor drive high level lost by each power module due to the current limiting control; and adjusting the current limiting control duration of each power module according to the difference in the duration of the lost external transistor drive high level.

[0006] In the above implementation process, by logically processing the overcurrent signals of the same phase from multiple power modules, a shared current-limiting control signal is generated, thus achieving unified current-limiting control for multiple power modules. Furthermore, the energy loss of each power module due to current-limiting control is monitored and adjusted accordingly. This adjustment allows for fine-grained control of each power module, balancing the lost high-level drive duration of the external transistors and preventing system performance degradation or device damage caused by severe overcurrent in individual modules.

[0007] Optionally, the logic processing is OR logic; the current limiting control of the plurality of power modules includes: maintaining the current limiting control signal valid when the overcurrent signal of any of the power modules is valid; and performing current limiting control on the same phase of the plurality of power modules when the current limiting control signal is valid.

[0008] In the above implementation process, under this condition, as long as any power module detects an overcurrent in that phase, the system will immediately enable the shared current limiting control signal.

[0009] Optionally, during the current limiting control process, monitoring the duration of the high-level drive of the external transistor lost by each power module due to the current limiting control includes: recording the current cumulative value of the drive time lost by each power module due to the current limiting control during the current limiting control process; using the maximum value among the current cumulative values ​​of all power modules as the target cumulative value; and continuously monitoring the duration of the current limiting control for power modules whose current cumulative value has not reached the target cumulative value.

[0010] In the above implementation process, by monitoring the drive time lost by each power module due to current limiting control, and using the maximum lost time among all modules as a benchmark, the current limiting duration of modules that do not reach this benchmark is continuously monitored. This achieves dynamic equalization tracking of the high-level drive time loss of the external transistors in each power module within the system. This method identifies the impact of current limiting control on the output distribution of the high-level drive time of the external transistors, providing data support for subsequent optimization of control strategies and reduction of output differences between modules, thereby improving the reliability and efficiency of system operation.

[0011] Optionally, adjusting the current limiting control duration of each power module based on the difference in the duration of the high-level drive of the lost external tube includes: for power modules whose current cumulative value is less than the target cumulative value, if the overcurrent signal has been restored to an invalid state, continuing to apply current limiting control to them until their current cumulative value reaches the target cumulative value.

[0012] In the above implementation process, the current imbalance is caused by the combined effects of interleaved current generation and wave-by-wave current limiting (CBC) characteristics. Interleaved current generation is a common method for parallel connection of PCS power modules, which connects multiple identical or similar circuit units (such as DC-DC converters, power switching modules, battery cells, etc.) in parallel. The key is to ensure that these parallel units operate with staggered (interleaved) phases. Traditional current sharing control cannot overcome the current imbalance caused by the wave-by-wave current limiting (CBC) characteristics under interleaved current generation. For power modules whose current cumulative loss is lower than the target value for the high-level duration of the external transistor drive, even if the overcurrent signal has disappeared (i.e., the current has returned to normal), the current limiting duration is actively extended until the energy loss catches up with the preset target. This provides data support for subsequent optimization of control strategies and reduction of energy differences between modules, thereby improving the reliability and efficiency of system operation.

[0013] Optionally, adjusting the current limiting control duration of each power module according to the difference in the high-level duration of the lost external tube drive further includes: clearing all current cumulative values ​​when the current cumulative value of all power modules reaches the target cumulative value and the overcurrent signal is invalid.

[0014] In the above implementation process, synchronous reset eliminates accumulated errors, prevents old data from interfering with the next round of current limiting judgment, improves control accuracy, avoids long-term integral drift, reduces the risk of software word length overflow and rounding errors, enhances algorithm stability, and provides data support for subsequent optimization of control strategies and reduction of energy differences between modules, thereby improving the reliability and efficiency of system operation.

[0015] Secondly, embodiments of this application provide a power device, the power device comprising: a control module, a plurality of power modules, and a monitoring module corresponding to each power module; the monitoring module is connected to each power module; the control module is electrically connected to the monitoring module and the power modules; the control module is used to perform logical processing on the same phase overcurrent signal of the plurality of power modules to generate a shared current limiting control signal, and to perform current limiting control on the plurality of power modules when the current limiting control signal is valid; the monitoring module is used to monitor the duration of the external tube drive high level lost by each power module due to the current limiting control during the current limiting control process; and to send the information on the duration of the lost external tube drive high level to the control module, the control module adjusting the current limiting control duration of each power module according to the difference in the duration of the lost external tube drive high level.

[0016] In the above implementation process, unified current limiting control reduces the complexity of multi-module collaboration and improves system response speed and reliability; real-time quantification of the high-level duration loss of external tube drives of each module provides accurate data support for differentiated current limiting and ensures fair energy distribution; dynamic adjustment of current limiting duration based on energy differences effectively balances device aging and thermal stress and extends the service life of the whole machine.

[0017] Optionally, the monitoring module is specifically used to: record the count value of the power module recorded by the monitoring module as the current cumulative value, and take the maximum value of the count value of each power module as the target cumulative value; for power modules whose current cumulative value has not reached the target cumulative value, continuously monitor the duration of their current limiting control.

[0018] In the above implementation process, the maximum value is used as the target to ensure that the energy balance benchmark is aligned with the most stressed module, avoiding undercompensation and improving protection integrity. The all-digital comparison and judgment method has low algorithm complexity and low execution latency, allowing it to be embedded into existing DSP / FPGA platforms to improve real-time performance. The target value is automatically refreshed periodically and adaptively adjusted according to operating conditions, taking into account device differences and aging drift to maintain long-term current sharing accuracy.

[0019] Optionally, the monitoring module is further configured to: clear all current cumulative values ​​when the current cumulative value of all power modules reaches the target cumulative value and the overcurrent signal is invalid.

[0020] In the above implementation process, zero-reference synchronous reset eliminates accumulated errors, ensuring that the next current limiting cycle starts from the same origin, maintaining consistent equalization accuracy over a long period. This avoids counter overflow and the associated risk of misjudgment, improving the reliability and security of system operation.

[0021] Optionally, the monitoring module includes a counter, which is used to characterize the lost high-level duration of the external tube drive by measuring the width or number of suppressed drive pulses of each of the power modules.

[0022] In the above implementation process, the impact of current limiting on the switching / conduction frequency of power devices is directly quantified, and the difference in the duration of the high-level drive of the external transistor is directly related to the module's output level. The purely digital interface eliminates the need for analog sampling, provides strong anti-interference capabilities, and saves on ADC and signal conditioning circuits, thus reducing hardware costs. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A first flowchart of the power module control method provided in the embodiments of this application; Figure 2 The in-phase overcurrent signal provided in the embodiments of this application is processed using OR logic; Figure 3 This is a second flowchart of a power module control method provided in an embodiment of this application; Figure 4 A schematic diagram of current sharing in the wave-by-wave current limiting process provided in the embodiments of this application; Figure 5 A schematic diagram of a power device provided in an embodiment of this application.

[0025] Icons: 100 - Control module; 200 - Power module; 300 - Monitoring module. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of the embodiments of this application.

[0027] In a multi-power module 200 system with carrier interleaved parallel operation, cycle-by-cycle current limiting (CBC) is a commonly used final hardware overcurrent protection in PCS. However, individually controlling the current of each channel using CBC would consume significant controller resources. Furthermore, due to the inherent characteristics of CBC, when two modules share the same overcurrent signal under interleaved signaling conditions, significant circulating current problems can easily arise.

[0028] The following formula is the derivation of the circulation current of the positive half-cycle of phase A of two modules connected in parallel, where... , , These represent the average value of the A-arm output voltage of module x during the switching cycle, the duty cycle of transistor T1, and the inductance value of the inverter inductor, respectively. , , These represent the changes in the circulating current of phase A of the two modules, namely, half-bus voltage, switching cycle duration, and one switching cycle.

[0029]

[0030] Ignoring ripple within a cycle, when no wave-by-wave current limiting occurs, the duty cycles of the two paths are the same within each switching cycle, i.e. Substituting this into the above equation, we can obtain that the two circulating currents are 0.

[0031] Under interleaved current generation, the high-level drives of the external transistors in the two modules are interleaved, resulting in different duty cycle losses due to wave-by-wave current limiting. Taking the first module's A phase reaching the overcurrent point as an example, since overcurrent often occurs in the later stages of the high-level drive and wave-by-wave current limiting is performed simultaneously in both modules A, the second module's A phase loses more duty cycle. Because the duty cycle losses in wave-by-wave current limiting caused by the overcurrent in the first module's A phase differ between the two modules, the second module loses more duty cycle in wave-by-wave current limiting. Substituting into the above formula, we can obtain This means that within one cycle, the change in the circulating current of phase A of both modules (ignoring inductor ripple) is not zero, and the phase A current of the first module that reaches the overcurrent point first is larger, meaning it outputs more power. Once phase A of the first module enters the wave-by-wave current limiting state, its actual output ratio will further increase, causing that phase to repeatedly trigger wave-by-wave current limiting, and even triggering system shutdown or other protection actions. This phenomenon contradicts the original design intention of wave-by-wave current limiting, which should have a certain fault ride-through capability.

[0032] To address this issue, embodiments of this application provide a control method and a power device for a power module.

[0033] In a first aspect, embodiments of this application provide a control method for a power module; please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a first flowchart of a power module control method provided in an embodiment of this application. A connection diagram of the power module can be found in [reference needed]. Figure 5 .

[0034] The control method for the power modules includes: logically processing the overcurrent signals of the same phase of multiple power modules 200 to generate a shared current limiting control signal, and performing current limiting control on multiple power modules 200 when the current limiting control signal is valid; during the current limiting control process, monitoring the duration of the high-level external transistor drive lost by each power module 200 due to the current limiting control; and adjusting the current limiting control duration of each power module 200 according to the difference in the duration of the lost high-level external transistor drive.

[0035] In the above implementation process, by logically integrating the overcurrent signals of the same phase of multiple power modules 200, a unified current limiting control signal is generated, and synchronous current limiting control is implemented for each module accordingly. During the current limiting process, the loss of high-level duration of the external tube drive caused by current limiting of each module is monitored in real time. Based on the difference in energy loss, the current limiting control duration of each module is dynamically adjusted to achieve current limiting balance and improve system reliability and stability.

[0036] In one embodiment of this application, all power modules 200 synchronously implement current limiting measures during the effective period of the current limiting control signal. Under normal operation, the modules output rated voltage and current, transmitting a certain amount of power (energy). However, during current limiting, the high-level drive of the external transistor is forcibly reduced, resulting in a decrease in the actual output power. The integral of this reduced power over time represents the lost duration of the high-level drive of the external transistor. Different modules experience different durations of lost high-level drive, and according to the relevant derivation above, this condition will lead to uneven power output from the modules. By monitoring the differences in the duration of the high-level drive of the in-phase external transistor among different modules, and adjusting the current limiting duration based on the energy loss difference, the fundamental goal is to make the total sacrifice of all modules during current limiting more equitable. For modules with less loss of high-level drive, it indicates that they output more power during current limiting. The system may appropriately extend their subsequent current limiting control duration to reduce their output, allowing them to return to normal operation sooner and balance their accumulated energy loss.

[0037] Optionally, please refer to Figure 2 , Figure 2 The in-phase overcurrent signal provided in the embodiments of this application is processed using OR logic.

[0038] The logic processing is OR logic; current limiting control is performed on multiple power modules 200, including: maintaining the current limiting control signal valid when the overcurrent signal of any power module 200 is valid; and performing current limiting control on the same phase of multiple power modules 200 when the current limiting control signal is valid.

[0039] In the above implementation process, based on OR logic, the overcurrent signal of the same phase of all parallel power modules 200 is continuously monitored. These overcurrent signals are input into an OR logic circuit, and the signal remains valid as long as the overcurrent signal of any one module is still valid. When the current limiting control signal is valid, the main controller (such as a DSP / FPGA) issues a unified current limiting command to the phase drive circuit of all power modules 200. During the current limiting period, the controller calculates the instantaneous energy loss of each module in real time through the current / voltage sensor of each module, integrates it, and obtains the cumulative loss of the high-level drive duration of the external transistor.

[0040] For non-interleaved carrier operation, to save resources, the overcurrent signals of the same phase current from different modules can be ANDed and processed to generate the final overcurrent signal. Figure 2 OC_x1 and OC_x2 are the x-phase inverter inductor current overcurrent signals of the first and second modules, respectively, when the high level is active. OC_x is the two overcurrent signals obtained by ORing OC_x1 and OC_x2 (AND logic is used if the low level is active). By using OC_x to simultaneously perform wave-by-wave current limiting protection on both x-phase channels, the wave-by-wave current limiting function can be realized while reducing the number of overcurrent signals that the controller needs to process.

[0041] In one embodiment of this application, issuing a unified current limiting command to the phase drive circuit of all power modules 200 can enable all modules to take current limiting measures synchronously, such as reducing the duty cycle of the PWM drive signal; directly reducing the pulse width; or entering a specific current limiting mode.

[0042] Optionally, please refer to Figure 3 , Figure 3 This is a second flowchart of a power module control method provided in an embodiment of this application. And in conjunction with... Figure 4 , Figure 4 This is a schematic diagram of current sharing in the process of wave-by-wave current limiting provided by the counter in the embodiments of this application.

[0043] During the current limiting control process, the duration of the high-level drive of the external tube lost by each power module 200 due to the current limiting control is monitored, including: during the current limiting control process, recording the current cumulative value of the drive time lost by each power module 200 due to the current limiting control; using the maximum value among the current cumulative values ​​of all power modules 200 as the target cumulative value; for power modules 200 whose current cumulative value has not reached the target cumulative value, the duration of their current limiting control is continuously monitored.

[0044] In the above implementation process, the overcurrent signals of the same phase of multiple parallel power modules 200 are logically processed to generate a shared global current limiting control signal. Once this signal is valid, a unified current limiting operation is implemented on all relevant power modules 200. During the execution of current limiting control, the system monitors and records in real time the duration of the external tube drive high level lost by each power module 200 due to current limiting. This energy loss can be quantified by recording the cumulative current limiting time of each module. The system uses the maximum cumulative current limiting time of all modules as the benchmark target. For modules whose cumulative time has not reached this benchmark, their current limiting state will continue until their cumulative time is equal to the benchmark value, thereby ensuring that the stress impact experienced by all modules in the current limiting event tends to be consistent. Through the global current limiting signal, a rapid and consistent coordinated response is ensured when any module or system faces the risk of overcurrent, effectively preventing the escalation of the fault. By monitoring energy loss and adjusting the current limiting duration differently, the stress differences between modules are intelligently compensated. This avoids a single module being in an adverse working state for a long time, thereby delaying device aging and extending the overall lifespan of the system.

[0045] In one embodiment of this application, reference may be made to Figure 4 Each power module 200 is equipped with an independent counter to quantify its cumulative output during the current limiting process. During the effective period of the current limiting control signal, the counters of all modules synchronously increment. When the global current limiting condition is lifted (or during real-time monitoring), the current values ​​of each module's counter are compared. The counter values ​​directly reflect the module's relative output level in this event. Modules with lower counter values ​​indicate that they are experiencing a higher output, and the system will delay their return to normal operation. Modules with higher counter values ​​will resume normal operation first or immediately. This mechanism ensures that after several current limiting events, the cumulative duration of the high-level drive on the external transistor is the same for all modules, thus avoiding circulating current and uneven output.

[0046] Optionally, the current limiting control duration of each power module 200 is adjusted according to the difference in the duration of the high-level drive of the lost external tube, including: for power modules 200 whose current cumulative value is less than the target cumulative value, if their overcurrent signal has been restored to an invalid state, the current limiting control continues to be applied to them until their current cumulative value reaches the target cumulative value.

[0047] In the above implementation process, the overcurrent signals of each power module 200 are logically processed to generate a shared global current limiting signal. When this signal is valid, all associated power modules 200 synchronously enter the current limiting control state. During the current limiting control process, the system monitors and records the duration of the external tube drive high level lost by each power module 200 due to current limiting. This energy loss can be quantified by recording the cumulative current limiting time of each module. The system uses the maximum value of the cumulative current limiting time of all modules as the benchmark target value. When the global current limiting signal becomes invalid again due to the disappearance of the fault, the system checks the cumulative value of each module: for power modules 200 whose current cumulative value is less than the target cumulative value, even if their own overcurrent signal has become invalid again, the system will continue to apply individual current limiting control to them; this individual current limiting control will continue until the cumulative value of the module also reaches the target cumulative value before it is released.

[0048] In one embodiment of this application, a global current-limiting signal is generated through logical operations, and all modules are synchronously controlled to enter the current-limiting state. Each power module 200 is configured with an independent counter. During the validity period of the global current-limiting signal, the counters of all modules synchronously accumulate counts at a fixed frequency. This count value directly quantifies the cumulative stress borne by the module during the current-limiting period. When the global current-limiting signal becomes invalid again, the system compares the current values ​​of the counters of each module and finds the maximum value as the baseline target value. Subsequently, the system executes a recovery strategy: modules whose counter values ​​have reached or exceeded the target value immediately resume normal operation; for power modules 200 whose counter values ​​are less than the target value, even after their overcurrent signal has become invalid again, current-limiting control continues to be applied, and their counters continue to accumulate until their count values ​​also reach the target value before the restriction is lifted.

[0049] Optionally, the current limiting control duration of each power module 200 is adjusted according to the difference in the high-level duration of the lost external tube drive. It also includes: clearing all current cumulative values ​​when the current cumulative value of all power modules 200 reaches the target cumulative value and the overcurrent signal is invalid.

[0050] In the above implementation process, the overcurrent signals of each power module 200 are logically processed to generate a shared global current limiting signal. During the effective period of the global current limiting signal, the system continuously records the cumulative current limiting time of each power module 200 as a quantitative indicator of its energy loss. The system uses the maximum cumulative current limiting time of all modules as the target value. For modules whose cumulative time is less than the target value, current limiting control continues to be applied to them individually until their cumulative time reaches the target value. When the cumulative current limiting time of all power modules 200 has reached the target value and all overcurrent signals have been deactivated, the system clears the current cumulative value of all power modules 200. The entire system is reset, ready to respond to the next overcurrent event.

[0051] In one embodiment of this application, a global current limiting signal is generated, and all modules are synchronously controlled to enter the current limiting state. Each power module 200 is configured with an independent counter. During the validity period of the global current limiting signal, all counters synchronously accumulate counts. When the global current limiting signal becomes invalid again, the system finds the maximum value among all counters as the target value. Modules whose counter values ​​are less than the target value continue to have their counters accumulated while being current limited, until the count value reaches the target value. When the counter values ​​of all power modules 200 have reached the target value and all overcurrent signals have become invalid again, the system resets the counters of all power modules 200. The entire system is reset, ready to respond to the next overcurrent event.

[0052] exist Figure 4In this process, the original drive signal is trimmed in real time using an FPGA. The core logic is to count the number of high-level signals lost by the two modules due to the current limiting phase during each phase. , ), and take the maximum value. The count of any module has not been reached. The blocking state is maintained until the number of high-level pulses lost by all modules is consistent, and the counter is reset uniformly after the overcurrent signal is restored, thus ensuring that the high-level pulse widths lost by all power modules 200 after wave-by-wave current limiting are exactly the same. The processed drive signals are shown in the figure. The black outlines of the first and second external tube drive signals are the original waveforms, and the red part represents the blocking interval that was forcibly pulled low during wave-by-wave current limiting and current sharing processing. When the overcurrent wave-by-wave current limiting signal is effective, blocking is triggered by the original signal states of the two external tube drives: for the first external tube, if the original signal is high, it enters blocking (output is forcibly pulled low); for the second external tube, after current and current sharing processing, the corresponding time domain interval enters blocking. At this time, the two drive signals show the blocking area of ​​the red diagonal line, and the power tube is temporarily turned off to avoid the risk of overcurrent. After the blocking is triggered, the counter enters the self-incrementing stage: It continuously increases during the first wave blocking period; It continues to self-increase during the second wave blocking period; Real-time acquisition and The maximum value is used to ensure that the longest blocking duration is used as the basis for judgment. During this stage, the system continuously compares the counter value with... Size relationship: If Then the two-way blocking state continues (such as the first path). (Continue to maintain the wave blocking). When Growth to equal to Furthermore, when the overcurrent limiting signal fails, all counters are cleared and the wave blocking logic is released. In other words, the two external transistor drives are restored to their original signals, and the power transistors re-enter the normal driving state.

[0053] Optionally, this control logic is primarily applicable to power conversion circuits that require multi-phase interleaved parallel operation and current-by-wave (CBC) protection. Typical applications include: multi-phase parallel Buck converters, which, in multi-phase VRM power supply systems for CPUs and GPUs, ensure consistent drive signal pulse widths for each phase after CBC protection, preventing uneven current distribution due to premature exit of current limiting in one phase; interleaved parallel Boost PFC circuits, suitable for medium-to-high power AC input front-end stages, maintaining consistent high-level loss in each parallel unit during overcurrent events to prevent increased circulating current or magnetization of components; multi-module parallel inverters (such as T-type / three-level topologies), particularly suitable for multi-module PCS scenarios, maintaining symmetrical drive of each module during the recovery phase after CBC protection, reducing DC components and circulating current; and parallel LLC resonant converters, where this logic helps achieve balanced recovery of soft-switching states after current limiting in multi-module parallel architectures of half-bridge / full-bridge LLC converters.

[0054] Secondly, embodiments of this application provide a power device, which includes: a control module 100, a plurality of power modules 200, and a monitoring module 300 corresponding to each power module 200; the monitoring module 300 is connected to each power module 200; the control module 100 is electrically connected to the monitoring module 300 and the power modules 200; the control module 100 is used to perform logical processing on the overcurrent signals of the same phase of the plurality of power modules 200 to generate a shared current limiting control signal, and to perform current limiting control on the plurality of power modules 200 when the current limiting control signal is valid; the monitoring module 300 is used to monitor the duration of the high-level external transistor drive lost by each power module 200 due to the current limiting control during the current limiting control process; and to send the information on the duration of the lost high-level external transistor drive to the control module 100; the control module 100 adjusts the current limiting control duration of each power module 200 according to the difference in the duration of the lost high-level external transistor drive.

[0055] In the above implementation process, multiple power modules 200 operate in parallel, jointly undertaking the power output task. A monitoring module 300 is connected to each power module 200, meaning each power module 200 is connected to a dedicated monitoring module 300. Its core function is to monitor the duration of the high-level external tube drive lost by the connected power module 200 due to current limiting control during the current limiting process; and to send the monitored information on the lost high-level external tube drive duration to the control module 100. The control module 100 is electrically connected to all monitoring modules 300 and all power modules 200, serving as the system's control center. It is responsible for: logically processing the overcurrent signals of the same phase from multiple power modules 200 to generate a shared current limiting control signal; and, when this signal is valid, performing unified current limiting control on all power modules 200; receiving energy loss information from each monitoring module 300, and adjusting the current limiting control duration of each power module 200 based on the differences in the lost high-level external tube drive duration, to achieve power output balance.

[0056] Optionally, the monitoring module is specifically used to: record the count value of the power module 200 recorded by the monitoring module 300 as the current cumulative value, and take the maximum value of the count value of each power module 200 as the target cumulative value; for power modules 200 whose current cumulative value has not reached the target cumulative value, continuously monitor the duration of their current limiting control.

[0057] In the above implementation process, during current limiting control, the duration of the high-level drive of the external transistor lost by the power module 200 due to current limiting control is quantitatively monitored. Specifically, the monitoring module 300 records the current limiting duration of its corresponding power module 200 through an internal counter, and this count value is recorded as the current cumulative value of the power module 200. The monitored information on the duration of the lost high-level drive of the external transistor (i.e., the current cumulative value) is sent to the control module 100. The counter mechanism of the monitoring module 300 quantifies the abstract energy loss into a precise current cumulative value, providing a reliable data foundation for subsequent equalization control and improving the accuracy and objectivity of the control.

[0058] Optionally, the monitoring module is also used to: clear all current cumulative values ​​when the current cumulative value of all power modules 200 reaches the target cumulative value and the overcurrent signal is invalid.

[0059] In the above implementation process, the reset mechanism is crucial to ensuring the continuous and reliable operation of the system. It ensures that after each complete current limiting protection and stress equalization cycle, all monitoring data is reset, allowing the system to be ready to respond to the next overcurrent event with a completely new initial state. This effectively avoids the infinite growth of accumulated values ​​and malfunctions in the control logic, ensuring the periodicity and stability of the control.

[0060] Optionally, the monitoring module 300 includes a counter for characterizing the duration of lost high-level drive pulses of the external tube by measuring the width or number of suppressed drive pulses of each power module 200.

[0061] In the above implementation, the counter quantifies energy loss by measuring and accumulating the duration for which each PWM drive pulse is limited or clipped (e.g., the difference between the normal pulse width and the actual output pulse width after current limiting). This method enables very fine and continuous energy loss assessment. The counter can directly count complete drive pulses that are completely shielded or disabled due to current limiting, with simple logic and low computational burden, making it suitable for energy loss assessment in units of switching cycles.

[0062] In summary, this application provides a control method and power device for a power module, relating to the field of power control technology. The method includes: logically processing the overcurrent signals of the same phase from multiple power modules 200 to generate a shared current-limiting control signal; and, when the current-limiting control signal is valid, performing current-limiting control on the multiple power modules 200; during the current-limiting control process, monitoring the duration of the external transistor drive high level lost by each power module 200 due to the current-limiting control; and adjusting the current-limiting control duration of each power module 200 according to the difference in the duration of the lost external transistor drive high level. By monitoring the loss of the external transistor drive high level duration of each module in real time during the current-limiting control process and achieving output rebalancing through differentiated adjustment of the current-limiting duration, dynamic energy compensation can be achieved, resulting in efficient power control.

[0063] In the several embodiments provided in this application, it should be understood that the disclosed device can also be implemented in other ways. The device embodiments described above are merely illustrative; for example, the block diagrams in the accompanying drawings illustrate the possible architecture, functions, and operations of the device according to various embodiments of this application. In this regard, each block in the block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram, and combinations of block diagrams, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0064] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0065] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0066] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0067] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

[0068] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A control method for a power module, characterized in that, The method includes: The overcurrent signals of the same phase from multiple power modules are logically processed to generate a shared current limiting control signal, and current limiting control is applied to multiple power modules when the current limiting control signal is valid. During the current limiting control process, the duration of the high-level external transistor drive lost by each power module due to the current limiting control is monitored; Based on the difference in the duration of the high-level drive of the external tube, the current limiting control duration of each power module is adjusted.

2. The method according to claim 1, characterized in that, in, The logical processing is OR logic; The current limiting control of the multiple power modules includes: The current limiting control signal remains valid if the overcurrent signal of any of the power modules is valid. And when the current limiting control signal is valid, current limiting control is applied to the same phase of the multiple power modules.

3. The method according to claim 1, characterized in that, During the current limiting control process, monitoring the duration of the external transistor drive high level lost by each power module due to the current limiting control includes: During the current limiting control process, the current cumulative value of the drive time lost by each power module due to the current limiting control is recorded; The maximum value among the current cumulative values ​​of all the power modules is taken as the target cumulative value; For power modules whose current cumulative value has not reached the target cumulative value, the duration of their current limiting control is continuously monitored.

4. The method according to claim 3, characterized in that, The step of adjusting the current limiting control duration of each power module based on the difference in the duration of the high-level drive of the lost external transistor includes: For power modules whose current cumulative value is less than the target cumulative value, if the overcurrent signal has been restored to an invalid state, current limiting control will continue to be applied to them until their current cumulative value reaches the target cumulative value.

5. The method according to claim 4, characterized in that, The step of adjusting the current limiting control duration of each power module based on the difference in the high-level driving duration of the lost external transistor also includes: If the current cumulative value of all power modules reaches the target cumulative value and the overcurrent signal is invalid, then all the current cumulative values ​​are cleared.

6. A power device, characterized in that, The power device includes: a control module, a plurality of power modules as described in any one of claims 1 to 5, and a monitoring module corresponding to the power modules; The monitoring module is connected to the power module; the control module is electrically connected to both the monitoring module and the power module. The control module is used to perform logical processing on the same phase overcurrent signal of multiple power modules to generate a shared current limiting control signal, and to perform current limiting control on multiple power modules when the current limiting control signal is valid; The monitoring module is used to monitor the duration of the high-level external transistor drive lost by each power module due to the current limiting control during the current limiting control process; and send the information of the lost high-level external transistor drive duration to the control module. The control module adjusts the current limiting control duration of each power module according to the difference in the lost high-level external transistor drive duration.

7. The power device according to claim 6, characterized in that, The monitoring module is specifically used for: The count value of the power module recorded by the monitoring module is recorded as the current cumulative value, and the maximum value of the count value of each power module is taken as the target cumulative value. For power modules whose current cumulative value has not reached the target cumulative value, the duration of their current limiting control is continuously monitored.

8. The power device according to claim 7, characterized in that, The control module is further configured to: clear the current cumulative value of all monitoring modules when the current cumulative value of all power modules reaches the target cumulative value and the overcurrent signal is invalid.

9. The power device according to claim 6, characterized in that, The monitoring module includes a counter, which is used to characterize the lost high-level duration of the external tube drive by measuring the width or number of suppressed drive pulses of each of the power modules.

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