On-satellite anti-interference clock processing circuit and management method
By using an onboard anti-interference clock processing circuit and management method, the instability problem caused by clock signal fluctuations in the onboard FPGA system is solved, achieving clock signal stability and automatic system reset and recovery. It is applicable to FPGA chips with different frequency bands and power requirements.
Patent Information
- Application Number
- CN202511609895.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-05
- Publication Date
- 2026-02-27
AI Technical Summary
In extreme environments, the clock signal of onboard FPGA systems is prone to fluctuations, leading to system instability. Traditional methods cannot completely solve the clock instability problem.
An on-board anti-interference clock processing circuit was designed, including a signal source, a power attenuation circuit, a bidirectional clamping circuit, and an impedance matching circuit. Combined with an FPGA chip and a crystal oscillator, the stability of the clock signal is ensured through power adjustment, voltage limiting, and impedance matching. A digital clock manager is used to automatically identify and reset the clock signal when it is lost.
It achieves clock signal stability and automatic system reset recovery under extreme environments, and is suitable for FPGA chips with different frequency bands and power requirements, with wide applicability and high practicality.
Smart Images
Figure CN121585097A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of spaceborne hardware and software technology, specifically to an onboard anti-interference clock processing circuit and management method. Background Technology
[0002] Field-Programmable Gate Arrays (FPGAs), as highly configurable hardware platforms, rely on precise timing control for their functionality, and clock signals ensure the normal and orderly operation of the FPGA. Spaceborne FPGA systems need to operate for extended periods in extreme environments, and clock stability directly determines system reliability. Externally input clock signals may fluctuate during long-term operation, potentially causing product malfunctions. Traditional methods improve clock transmission stability in hardware, but cannot completely eliminate clock instability.
[0003] Therefore, it is essential to propose an on-board anti-interference clock processing circuit that can overcome the above problems.
[0004] It is understood that the above statements only provide background information related to the present invention and do not necessarily constitute prior art. Summary of the Invention
[0005] The purpose of this invention is to provide an onboard anti-interference clock processing circuit and management method to avoid clock instability caused by long-term onboard operation.
[0006] To achieve the above objectives, the present invention provides an on-board anti-interference clock processing circuit, comprising: a signal source for outputting clock signals of different frequency bands; a power attenuation circuit connected to the output terminal of the signal source for adjusting the power and impedance matching of the clock signals output by the signal source; a bidirectional clamping circuit connected to the output terminal of the power attenuation circuit for limiting the positive and negative voltage amplitudes of the clock signals output by the power attenuation circuit; an impedance matching circuit connected to the output terminal of the bidirectional clamping circuit for ensuring that the clock signals output by the bidirectional clamping circuit are compatible with the load impedance; an FPGA chip, the first clock pin of which is connected to the output terminal of the power attenuation circuit; and a crystal oscillator, the output terminal of which is connected to the second clock pin of the FPGA chip to provide a global reference clock signal for the FPGA chip.
[0007] Preferably, the power attenuation circuit includes: a π-type power attenuator, comprising variable resistors *R1, *R2, and *R3; wherein, variable resistor *R1 is connected in series with the output terminal of the signal source, and variable resistors *R2 and *R3 are connected in series and then in parallel across the two ends of variable resistor *R1; and a variable capacitor *C1, one end of which is connected to the output terminal of the π-type power attenuator, and the other end of which is connected to the input terminal of the bidirectional clamping circuit.
[0008] Preferably, the bidirectional clamping circuit includes: a first series diode group, including a second diode and a first diode connected in forward series, the positive terminal of the first series diode group being connected to the output terminal of the power attenuation circuit and the negative terminal being connected to the power supply; and a second series diode group, including a third diode and a fourth diode connected in reverse series, the negative terminal of the second series diode group being connected to the output terminal of the power attenuation circuit and the positive terminal being connected to the ground terminal.
[0009] Preferably, the impedance matching circuit includes: a first resistor, one end of which is connected to the output terminal of the power attenuation circuit and the other end of which is connected to the power supply; and a second resistor, one end of which is connected to the output terminal of the power attenuation circuit and the other end of which is connected to the ground terminal.
[0010] Preferably, the output terminal of the signal source is connected to the ground terminal to provide a voltage reference zero point.
[0011] This invention also provides a management method for an on-board anti-interference clock processing circuit, implemented using the aforementioned on-board anti-interference clock processing circuit, comprising the following steps: S1, after the circuit is powered on, the FPGA chip receives a first clock signal from a signal source through a first clock pin, and processes it through the digital clock manager inside the FPGA chip to obtain a second clock signal and a third clock signal; S2, the FPGA chip divides the second clock signal into a fourth clock signal and the third clock signal into a fifth clock signal through the digital clock manager; S3, the FPGA chip receives the clock signal input from the crystal oscillator through the second clock pin. The frequency is f0, and the rising edges of the fourth and fifth clock signals are detected at intervals of 1 / f0; S4. If no rising edge of the fourth or fifth clock signal is detected within a preset time period t, the reset flag of the digital clock manager is set to 1; S5. The FPGA chip detects the rising edge of the reset flag at intervals of 1 / f0. If the rising edge of the reset flag is detected, a reset signal of the digital clock manager is generated and the reset signal is set to 1; S6. After the digital clock manager receives the reset signal as 1 and completes the reset, the second and third clock signals are restored, and the circuit resumes normal operation.
[0012] Preferably, the first clock signal is output from a signal source and processed by a power attenuation circuit, a bidirectional clamping circuit, and an impedance matching circuit before being input to the first clock pin of the FPGA chip.
[0013] Preferably, in step S3, the clock frequency f0 of the second clock pin is greater than or equal to twice the clock frequency of the fourth clock signal, and the clock frequency f0 of the second clock pin is greater than or equal to the clock frequency of the fifth clock signal.
[0014] Preferably, in step S4, the preset time period t is greater than the period of the second clock signal, and the preset time period t is greater than the period of the third clock signal.
[0015] Preferably, in the FPGA chip, the process of detecting the fourth clock signal and the fifth clock signal is independent of the process of detecting the reset flag.
[0016] In summary, compared with the prior art, the on-board anti-interference clock processing circuit and management method provided by the present invention ensures that the output clock signal can meet the power requirements of FPGA chips with different frequency bands and different power requirements through power attenuation circuit and bidirectional clamping circuit, which has wide applicability and strong practicality; at the same time, the management method of the on-board anti-interference clock processing circuit can automatically identify the problem of unstable clock signal causing the system to fail to work, and can automatically reset and restore the system to work without manual command. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the on-board anti-interference clock processing circuit in this invention; Figure 2 This is a flowchart of the on-board anti-interference clock processing circuit management method in this invention. Detailed Implementation
[0018] The following is in conjunction with the appendix Figure 1 To be continued Figure 2 The present invention will be further illustrated by describing a preferred embodiment in detail.
[0019] It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions. They are only used to facilitate and clarify the purpose of illustrating the embodiments of the present invention, and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationship, or adjustments to the size should still fall within the scope of the technical content disclosed in the present invention, provided that they do not affect the effects and objectives that the present invention can produce.
[0020] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only the expressly listed elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0021] like Figure 1As shown, a first aspect of the present invention provides an on-board anti-interference clock processing circuit, comprising: Signal source 1 is used to output clock signals of different frequency bands; The power attenuation circuit 2 is connected to the output terminal of the signal source 1 and is used to adjust the power and impedance of the clock signal output by the signal source 1. The bidirectional clamping circuit 3 is connected to the output terminal of the power attenuation circuit 2 and is used to limit the positive and negative voltage amplitudes of the clock signal output by the power attenuation circuit 2. Impedance matching circuit 4 is connected to the output terminal of the bidirectional clamping circuit 3 to ensure that the clock signal output by the bidirectional clamping circuit 3 is compatible with the load impedance. The first clock pin CLK1 of the FPGA chip U1 is connected to the output of the power attenuation circuit 2; The output of crystal oscillator G1 is connected to the second clock pin CLK0 of the FPGA chip U1 to provide a global reference clock signal for the FPGA chip U1.
[0022] It should be noted that signal source 1 is used to provide an initial clock signal source, serving as the timing reference for the entire circuit. When signal source 1 outputs clock signals at different frequency bands, the frequency of its output clock signal must meet the requirements of FPGA chip U1. Simultaneously, signal source 1 is also connected to the ground terminal GND to establish a voltage reference zero point for the output signal, providing a stable level reference for subsequent circuits. Furthermore, the ground terminal establishes a closed loop for the clock signal current, suppressing common-mode noise interference to the original clock signal and improving the overall system's noise immunity.
[0023] Furthermore, the power attenuation circuit 2 includes a π-type power attenuator and a variable capacitor *C1 connected to the output terminal of the π-type power attenuator. The π-type power attenuator is composed of variable resistors *R1, *R2, and *R3. Variable resistor *R1 is connected in series with the signal source 1, and variable resistors *R2 and *R3 are connected in series with each other. These series-connected variable resistors *R2 and *R3 are then connected in parallel across variable resistor *R1. It can be understood that by adjusting the resistance values of variable resistors *R1, *R2, and *R3, the power attenuation of the clock signal output from signal source 1 can be achieved. The output terminal of the π-type power attenuator is then connected to one end of the variable capacitor *C1, achieving filtering, noise reduction, DC isolation, and AC pass-through.
[0024] Furthermore, the bidirectional clamping circuit 3 includes: The first series diode group includes a second diode D2 and a first diode D1 connected in forward series; wherein, the output terminal of the power attenuation circuit 2 is connected to the positive terminal of the first series diode group, and the negative terminal of the first series diode group is connected to the power supply VCC. The second series diode group includes a third diode D3 and a fourth diode D4 connected in reverse series; wherein, the output terminal of the power attenuation circuit 2 is connected to the negative terminal of the second series diode group, and the positive terminal of the second series diode group is connected to the ground terminal GND.
[0025] In a preferred embodiment of the present invention, the bidirectional clamping circuit 3 is used to limit the amplitude of the clock signal output by the power attenuation circuit 2 to 0~VCC.
[0026] Furthermore, the impedance matching circuit 4 includes: The first resistor R1 has one end connected to the output terminal of the power attenuation circuit 2 and the other end connected to the power supply VCC. The second resistor R2 has one end connected to the output terminal of the power attenuation circuit 2 and the other end connected to the ground terminal GND.
[0027] In a preferred embodiment of the present invention, the impedance matching circuit 4 can ensure that the clock signal output by the bidirectional clamping circuit 3 is matched with the load impedance.
[0028] like Figure 2 As shown, a second aspect of the present invention provides a management method for an on-board anti-interference clock processing circuit, implemented using the aforementioned on-board anti-interference clock processing circuit, specifically comprising the following steps: S1. After the on-board anti-interference clock processing circuit is powered on, the first clock pin CLK1 of the FPGA chip U1 receives the first clock signal CLK11 from signal source 1 at a frequency of [frequency missing]. The second clock signal CLK22 and the third clock signal CLK33 are obtained through processing by the Digital Clock Manager (DCM) inside the FPGA chip U1; wherein, the frequency of the second clock signal CLK22 is a multiple of the frequency of the first clock signal CLK11. The frequency of the third clock signal CLK33 is divided by the frequency of the first clock signal CLK11 to [a specific value]. ; S2, the digital clock manager inside the FPGA chip U1 divides the second clock signal CLK22 into the fourth clock signal CLK44, and divides the third clock signal CLK33 into the fifth clock signal CLK55; S3. The clock frequency of the second clock pin CLK0 of the crystal oscillator G1 input to the FPGA chip U1 is f0, and the FPGA chip U1 detects the rising edge of the fourth clock signal CLK44 and the fifth clock signal CLK55 every 1 / f0 interval. S4. If the rising edge of the fourth clock signal CLK44 or the fifth clock signal CLK55 is not detected within the preset time period t, it is considered that the clock corresponding to the first clock signal CLK11 is out of lock, and the reset flag of DCM is set to 1; otherwise, the reset flag is 0 (i.e., the initial state). S5. The FPGA chip U1 detects the rising edge of the reset flag every 1 / f0 interval. If the rising edge of the reset flag is detected, a DCM reset signal is generated and the reset signal is set to 1. Otherwise, the reset signal is 0 (i.e., the initial state). After S6 and DCM receive the reset signal as 1 and complete the reset, the second clock signal CLK22 and the third clock signal CLK33 are restored, and the on-board anti-interference clock processing circuit resumes normal operation.
[0029] Furthermore, the first clock signal CLK11 is emitted by the signal source 1 and is processed sequentially by the power attenuation circuit 2, the bidirectional clamping circuit 3 and the impedance matching circuit 4 before being output to the first clock pin CLK1 of the FPGA chip U1.
[0030] It is understandable that in the above steps, f0 is the frequency of crystal oscillator G1. The FPGA chip U1 detects whether the clock signals CLK44, CLK55 and the reset flag of DCM change from 0 to 1 in each clock cycle provided by crystal oscillator G1. This is done simultaneously in two separate processes. When CLK44 and CLK55 change from 0 to 1, it proves that these two clocks still exist. When the reset flag of DCM changes from 0 to 1, it proves that one or both clocks of CLK44 and CLK55 have stopped. In addition, if CLK44 and CLK55 are normal, it will not cause the reset flag of DCM to change from 0 to 1.
[0031] Furthermore, in step S3, the clock frequency f0 of the second clock pin CLK0 is greater than or equal to twice the clock frequency of the fourth clock signal CLK44, and the clock frequency f0 of the second clock pin CLK0 is greater than or equal to the clock frequency of the fifth clock signal CLK55.
[0032] Furthermore, in step S4, the time period t is greater than the period of the second clock signal CLK22, and the time period t is greater than the period of the third clock signal CLK33.
[0033] It is understood that the time period t is the time for determining clock loss, and it can be configured to adapt to the clock stability requirements under different environments.
[0034] Furthermore, it can be understood that in step S4, when the clock corresponding to the first clock signal CLK11 is unlocked, the second clock signal CLK22 and / or the third clock signal CLK33 will disappear. That is, if either of the two clock signals disappears, the DCM needs to be reset so that the on-board anti-interference clock processing circuit can resume normal operation.
[0035] In summary, the on-board anti-interference clock processing circuit and management method provided by this invention, through power attenuation circuit and bidirectional clamping circuit, ensures that the output clock signal can meet the power requirements of FPGA chips in different frequency bands, exhibiting wide applicability and strong practicality. Furthermore, the management method of this on-board anti-interference clock processing circuit can automatically identify problems caused by unstable clock signals leading to system malfunction, automatically resetting and restoring system operation without manual commands.
[0036] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A satellite anti-interference clock processing circuit, characterized in that, include: A signal source, used to output clock signals in different frequency bands; A power attenuation circuit, connected to the output terminal of the signal source, is used to adjust the power and match the impedance of the clock signal output by the signal source. A bidirectional clamping circuit, connected to the output of the power attenuation circuit, is used to limit the positive and negative voltage amplitudes of the clock signal output by the power attenuation circuit. An impedance matching circuit is connected to the output terminal of the bidirectional clamping circuit to ensure that the clock signal output by the bidirectional clamping circuit is compatible with the load impedance. The FPGA chip has its first clock pin connected to the output of the power attenuation circuit. A crystal oscillator, whose output is connected to the second clock pin of the FPGA chip, provides a global reference clock signal for the FPGA chip.
2. The on-board anti-interference clock processing circuit as described in claim 1, characterized in that, The rate attenuation circuit includes: A π-type power attenuator includes variable resistors *R1, *R2, and *R3; wherein, variable resistor *R1 is connected in series with the output terminal of the signal source, and variable resistors *R2 and *R3 are connected in series and then in parallel across the two ends of variable resistor *R1. A variable capacitor C1 is connected at one end to the output of the π-type power attenuator and at the other end to the input of the bidirectional clamping circuit.
3. The on-board anti-interference clock processing circuit as described in claim 2, characterized in that, The bidirectional clamping circuit includes: The first series diode group includes a second diode and a first diode connected in forward series. The positive terminal of the first series diode group is connected to the output terminal of the power attenuation circuit, and the negative terminal is connected to the power supply. The second series diode group includes a third diode and a fourth diode connected in reverse series. The negative terminal of the second series diode group is connected to the output terminal of the power attenuation circuit, and the positive terminal is connected to the ground terminal.
4. The on-board anti-interference clock processing circuit as described in claim 1, characterized in that, The impedance matching circuit includes: The first resistor has one end connected to the output terminal of the power attenuation circuit and the other end connected to the power supply. The second resistor has one end connected to the output terminal of the power attenuation circuit and the other end connected to the ground terminal.
5. The on-board anti-interference clock processing circuit as described in claim 1, characterized in that, The output terminal of the signal source is connected to the ground terminal to provide a voltage reference zero point.
6. A management method for an on-board anti-interference clock processing circuit, implemented using the on-board anti-interference clock processing circuit as described in any one of claims 1-5, characterized in that, Includes the following steps: S1. After the circuit is powered on, the FPGA chip receives the first clock signal from the signal source through the first clock pin, and obtains the second clock signal and the third clock signal through the digital clock manager inside the FPGA chip. S2. The FPGA chip uses a digital clock manager to divide the second clock signal into a fourth clock signal and the third clock signal into a fifth clock signal. S3. The FPGA chip receives the clock signal input from the crystal oscillator through the second clock pin, with a frequency of f0, and detects the rising edges of the fourth and fifth clock signals at intervals of 1 / f0. S4. If the rising edge of the fourth or fifth clock signal is not detected within the preset time period t, the reset flag of the digital clock manager is set to 1. S5. The FPGA chip detects the rising edge of the reset flag at intervals of 1 / f0. If the rising edge of the reset flag is detected, a reset signal of the digital clock manager is generated and the reset signal is set to 1. S6. After the digital clock manager receives a reset signal of 1 and completes the reset, the second clock signal and the third clock signal are restored, and the circuit resumes normal operation.
7. The management method for the on-board anti-interference clock processing circuit as described in claim 6, characterized in that, The first clock signal is output from a signal source and processed by a power attenuation circuit, a bidirectional clamping circuit, and an impedance matching circuit before being input to the first clock pin of the FPGA chip.
8. The management method for the on-board anti-interference clock processing circuit as described in claim 6, characterized in that, In step S3, the clock frequency f0 of the second clock pin is greater than or equal to twice the clock frequency of the fourth clock signal, and the clock frequency f0 of the second clock pin is greater than or equal to the clock frequency of the fifth clock signal.
9. The management method for the on-board anti-interference clock processing circuit as described in claim 6, characterized in that, In step S4, the preset time period t is greater than the period of the second clock signal, and the preset time period t is greater than the period of the third clock signal.
10. The management method for the on-board anti-interference clock processing circuit as described in claim 6, characterized in that, In an FPGA chip, the processes for detecting the fourth and fifth clock signals are independent of the process for detecting the reset flag.