Multi-channel voltage converter and clock circuit therefor and power management chip

Abstract

The disclosure provides a multi-channel voltage converter, a clock circuit thereof and a power management chip, comprising a reference clock circuit and a channel clock circuit, in a discontinuous conduction mode, the channel clock circuit is used to determine a channel target sub-clock signal of a next period at a channel delay time after the end of a channel target sub-clock signal of a current period, generate a channel clock signal of the next period based on the channel target sub-clock signal of the next period, and obtain a channel clock signal with a lower frequency to ensure stable output of each channel under light load. The channel clock circuit is used to control other channel clock circuits to be non-enabled in a phase-shift delay time after the channel target sub-clock signal enters the next period, and the other channel clock signals are controlled to be invalid (low level) at a rising edge of a channel clock signal to generate phase-shifted channel clock signals, thereby ensuring that each channel works in phase shift in the discontinuous conduction mode.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more particularly to a multi-channel voltage converter, its clock circuit, and a power management chip. Background Technology

[0002] A power management integrated circuit (PMIC) is a common analog chip whose main function is to provide power management for various electronic devices. It is responsible for managing the power supply of various chips on the circuit board of electronic products and typically includes multi-channel direct current (DC) to DC converters and / or multi-channel low dropout regulators (LDOs).

[0003] For a PMIC containing multi-channel DC-DC converters, the channel clock signal of each channel DC-DC converter in continuous conduction mode is generated by a reference clock module with phase shift of a reference clock signal. In discontinuous conduction mode, the channel clock signal is generated by the channel clock module of the corresponding channel DC-DC converter. The channel clock module generates a clock signal with a frequency lower than that of the reference clock signal to maintain the normal output of the corresponding channel DC-DC converter under light load.

[0004] If the above technical solution is adopted, the DC-DC converters of each channel can operate in phase shifts in continuous conduction mode. However, in discontinuous conduction mode, since the internal clock modules of each DC-DC converter are completely independent, it is impossible to guarantee that the DC-DC converters of each channel can operate in phase shifts. Summary of the Invention

[0005] This disclosure provides a multi-channel voltage converter, its clock circuit, and a power management chip, which can ensure that each channel in the multi-channel voltage converter operates out of phase in discontinuous conduction mode.

[0006] In a first aspect, this disclosure provides a clock circuit for a multi-channel voltage converter, including a reference clock circuit and N channel clock circuits, wherein the N output terminals of the reference clock circuit are connected one-to-one with the N input terminals of each channel clock circuit, and N is an integer greater than or equal to 2.

[0007] The reference clock circuit is configured to generate a reference clock signal and perform phase reversal processing on the reference clock signal to obtain N sub-clock signals.

[0008] Each channel clock circuit is configured to determine the channel operating mode based on the channel load detection voltage; when the channel operating mode is a discontinuous conduction mode, at the channel delay time after the end of the current cycle's channel target sub-clock signal, determine the channel target sub-clock signal for the next cycle, generate the channel clock signal for the next cycle based on the channel target sub-clock signal for the next cycle, and control other channel clock circuits to be disabled during the phase delay time after the channel target sub-clock signal enters the next cycle.

[0009] In each cycle, the rising edge of the channel clock signal is aligned with the rising edge of the channel target sub-clock signal, and the channel target sub-clock signal of the next cycle is the signal among the N sub-clock signals whose rising edge is closest to the channel delay time after the end of the current cycle.

[0010] In some embodiments of this disclosure, each channel clock circuit includes a clock selection circuit and a mode detection circuit. The N input terminals of the clock selection circuit are connected one-to-one with the N output terminals of the reference clock circuit. The first input terminal of the mode detection circuit is connected to the channel load detection voltage, the second input terminal of the mode detection circuit is connected to the detection reference voltage, and the output terminal of the mode detection circuit is connected to the control terminal of the clock selection circuit.

[0011] The mode detection circuit is configured to determine the channel mode detection signal based on whether the channel load detection voltage is greater than the detection reference voltage.

[0012] The clock selection circuit is configured to: when the channel mode detection signal is a continuous conduction mode signal, select one of the N sub-clock signals as the channel target sub-clock signal; when the channel mode detection signal is a discontinuous conduction mode signal, determine the channel target sub-clock signal in the continuous conduction mode as the channel target sub-clock signal for the first cycle in the discontinuous conduction mode; and in the current cycle of the discontinuous conduction mode, after the channel delay time signal is flipped to invalid, determine the sub-clock signal whose rising edge arrives first among the N sub-clock signals as the channel target sub-clock signal for the next cycle.

[0013] In some embodiments of this disclosure, each channel clock circuit further includes a clock determination circuit, the input of which is connected to the output of the clock selection circuit, and the control terminal of which is connected to a phase delay time signal.

[0014] The clock determination circuit is configured to, when the phase delay time signal is valid, pull up the channel clock signal on the rising edge of the channel target sub-clock signal and pull down the channel clock signal after the duty cycle delay time.

[0015] In some embodiments of this disclosure, the clock selection circuit includes N D flip-flops, N+1 OR gates, N NOR gates, N switches, a first selector, and a second selector. The first input terminals of the first selector and the second selector are connected to the power supply voltage. The second input terminal of the first selector is connected to the channel delay time signal. The second input terminal of the second selector is grounded. The control terminals of the first selector and the second selector are connected to a first strobe signal. The output terminal of the first selector is connected to the reset terminals of the N D flip-flops. The output terminal of the second selector is connected to the first input terminal of the N+1th OR gate.

[0016] The non-inverting outputs of the N D flip-flops are connected one-to-one with the first inputs of the first OR gate to the Nth OR gate. The second inputs of the first OR gate to the Nth OR gate are connected to the output of the NOR gate. The outputs of the first OR gate to the Nth OR gate are connected one-to-one with the inputs of the N D flip-flops. The non-inverting output of each D flip-flop is connected to one input of the NOR gate. The clock terminal of each D flip-flop is connected to the input of a switch and one output of the reference clock circuit.

[0017] The second input terminal of the (N+1)th OR gate of the i-th channel clock circuit is connected to the non-inverting output terminal of the j-th D flip-flop. The output terminal of the (N+1)th OR gate of the i-th channel clock circuit is connected to the control terminal of the j-th switch. The control terminals of the remaining N-1 switches are connected one-to-one with the non-inverting output terminals of the remaining N-1 D flip-flops. The output terminals of the N switches are connected to the output terminal of the clock selection circuit. Where i is any integer greater than or equal to 1 and less than or equal to M, j is any integer greater than or equal to 1 and less than or equal to N, M is the number of channels in the multi-channel voltage converter, and j = 1 + (i-1)N / M.

[0018] In some embodiments of this disclosure, the clock determination circuit includes a third selector, a NAND gate, a duty cycle delay unit, and a first D flip-flop. The first input terminal of the third selector and the input terminal of the first D flip-flop are connected to the power supply voltage. The second input terminal of the third selector is connected to the phase delay time signal. The control terminal of the third selector is connected to a second strobe signal. The output terminal of the third selector is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is connected to the output terminal of the duty cycle delay unit. The output terminal of the NAND gate is connected to the reset terminal of the first D flip-flop.

[0019] The clock terminal of the first D flip-flop is connected to the output terminal of the clock selection circuit, the non-inverting output terminal of the first D flip-flop is connected to the clock output terminal of the channel clock circuit, and the inverting output terminal of the first D flip-flop is connected to the input terminal of the duty cycle delay unit.

[0020] In some embodiments of this disclosure, each channel clock circuit further includes a pull-down resistor, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop. The pull-down resistor is connected between the output of the clock selection circuit and ground. The clock terminal of the second D flip-flop is connected to the inverting output of the first D flip-flop. The input of the second D flip-flop is connected to the output of the mode detection circuit. The non-inverting output of the second D flip-flop is connected to the input of the third D flip-flop, the control terminal of the third selector, and the input of the fourth D flip-flop.

[0021] The clock terminals of the third and fourth D flip-flops are connected to the output terminals of the clock selection circuit. The non-inverting output terminal of the third D flip-flop is connected to the control terminals of the first and second selectors. The reset terminal of the fourth D flip-flop is connected to the phase delay time signal. The non-inverting output terminal of the fourth D flip-flop is connected to the second input terminal of the first selector.

[0022] In some embodiments of this disclosure, the channel clock circuit further includes a clamping subtractor, a voltage-to-time conversion circuit, and a phase-shifting delay unit. The non-inverting input of the clamping subtractor is connected to the detection reference voltage, the inverting input of the clamping subtractor is connected to the channel load detection voltage, the output of the clamping subtractor is connected to the input of the voltage-to-time conversion circuit, the reset terminal of the voltage-to-time conversion circuit is connected to the output of the phase-shifting delay unit, the input of the phase-shifting delay unit is connected to the clock output of the channel clock circuit, the control terminal of the voltage-to-time conversion circuit is connected to the control output of the clock selection circuit, and the output of the voltage-to-time conversion circuit is connected to the reset terminal of the clock selection circuit.

[0023] The clamping subtractor is configured to determine the differential voltage between the channel load detection voltage and the detection reference voltage. The phase-shift delay is configured to delay the rising edge of the channel clock signal by the phase-shift delay time to determine the conversion reset signal.

[0024] The voltage-time conversion circuit is configured to convert the differential voltage into the channel delay time when the channel clock circuit is enabled, so as to determine the channel delay time signal; and to determine the phase-out delay time signal based on the channel delay time signal and the conversion reset signal.

[0025] In some embodiments of this disclosure, the voltage-time conversion circuit includes a fifth D flip-flop, an RS flip-flop, an inverter, an AND gate, a time comparator, a transistor, a current source, and a capacitor. The power supply voltage is connected to the non-inverting input of the time comparator, the first plate of the capacitor, and the first terminal of the transistor through the current source. The inverting input of the time comparator is connected to the output of the clamping subtractor. The second plate of the capacitor and the second terminal of the transistor are grounded. The output of the time comparator is connected to the first input of the AND gate. The enable signal is connected to the second input of the AND gate through the inverter. The output of the AND gate is connected to the set terminal of the RS flip-flop.

[0026] The reset terminals of the RS flip-flop and the fifth D flip-flop are connected to the output terminal of the phase-delayed circuit. The non-inverting output terminal of the RS flip-flop is connected to the enable terminal of the other channel clock circuit and the reset terminal of the clock selection circuit. The clock terminal of the fifth D flip-flop is connected to the control output terminal of the clock selection circuit. The input terminal of the fifth D flip-flop is connected to the power supply voltage. The inverting output terminal of the fifth D flip-flop is connected to the control terminal of the transistor.

[0027] In a second aspect, this disclosure provides a multichannel voltage converter, including any of the clock circuits provided in the first aspect.

[0028] Thirdly, this disclosure provides a power management chip, including any of the multi-channel voltage converters provided in the second aspect.

[0029] In the technical solution disclosed herein, during discontinuous conduction mode, the channel clock circuit determines the target sub-clock signal for the next cycle at the channel delay time after the current cycle's target sub-clock signal ends. Based on this target sub-clock signal, the channel clock signal for the next cycle is generated. This allows for frequency reduction of the sub-clock signal, resulting in a lower-frequency channel clock signal to ensure stable output of each channel under light load. Furthermore, by controlling the disabling of other channel clock circuits during the phase-shift delay time after the target sub-clock signal enters the next cycle, the channel clock circuit can disable other channel clock signals. This allows for invalidation (low level) of other channel clock signals at the rising edge of one channel clock signal, generating a phase-shifted channel clock signal and ensuring phase-shifted operation of each channel during discontinuous conduction mode.

[0030] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0031] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings:

[0032] Figure 1 A schematic diagram of the clock system of a multi-channel voltage converter provided for the prior art.

[0033] Figure 2 A schematic diagram of the clock circuit of a multi-channel voltage converter provided for embodiments of this disclosure.

[0034] Figure 3 This is a schematic diagram of ten sub-clock signals provided in an embodiment of the present disclosure.

[0035] Figure 4 This is a circuit diagram of a channel clock circuit provided in an embodiment of the present disclosure.

[0036] Figure 5 This is a circuit diagram of a voltage-time conversion circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “electrically connecting” two or more parts together shall mean that these parts are joined directly together or joined through one or more intermediate components.

[0039] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0040] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0041] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0042] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0043] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0044] Figure 1 A schematic diagram of a clock system for a multi-channel voltage converter, provided for reference in the prior art, is shown below. Figure 1 As shown, the clock system includes a reference clock module 10 and N channel clock modules 20. The N output terminals of the reference clock module 10 are connected one-to-one with the input terminals of the N channel clock modules 20, where N is an integer greater than or equal to 2.

[0045] The reference clock module 10 can generate a reference clock signal and phase-shift the reference clock signal to generate N sub-clock signals (the first sub-clock signal CLK_1 to the Nth sub-clock signal CLK_N), and provide each sub-clock signal to the corresponding channel clock module 20. When the number of channels is small, the reference clock module 10 can generate the sub-clock signals using frequency division or phase inversion; when the number of channels is large, a delay-locked loop (PLL) can be used to generate the sub-clock signals.

[0046] For example, when N=2, the reference clock module 10 generates a phase difference of 180°. The system provides a first sub-clock signal CLK_1 and a second sub-clock signal CLK_2, and provides the first sub-clock signal CLK_1 to the first channel clock module and the second sub-clock signal CLK_2 to the second channel clock module.

[0047] For example, the channel clock module 20 includes a frequency and phase detector (PFD), a charge pump (CP), a first subtractor, a second subtractor, a frequency reduction comparator (CMP1), and a voltage-controlled oscillator (VCO). The first input terminal of the frequency and phase detector (PFD) is connected to an output terminal of the reference clock module 10, the second input terminal of the frequency and phase detector (PFD) is connected to an output terminal of the channel clock module 20, the enable terminal of the frequency and phase detector (PFD) is connected to the output terminal of the frequency reduction comparator (CMP1), the non-inverting input terminal of the frequency reduction comparator (CMP1) is connected to the detection reference voltage (Vlowclp), and the inverting input terminal of the frequency reduction comparator (CMP1) is connected to the load detection voltage (Vcomp).

[0048] The output of the frequency and phase detector PFD is connected to the non-inverting input of the first subtractor via a charge pump CP. The inverting input of the first subtractor is connected to the output of the second subtractor. The non-inverting input of the second subtractor is connected to the detection reference voltage Vlowclp. The inverting input of the second subtractor is connected to the load detection voltage Vcomp. The output of the second subtractor is connected to the output of the channel clock module 20 via a voltage-controlled oscillator VCO.

[0049] For example, the load sense voltage Vcomp is the voltage after error amplification and compensation between the output feedback voltage and the reference voltage of the voltage converter. It can characterize the load size of the voltage converter. In the continuous conduction mode of a peak current DC-DC converter, the load sense voltage Vcomp can also characterize the peak value of the inductor current in each switching cycle. When the load of the voltage converter increases, the load sense voltage Vcomp increases, indicating that the peak current of the inductor current in each switching cycle increases. When the load of the voltage converter decreases, the load sense voltage Vcomp decreases, indicating that the peak current of the inductor current in each switching cycle decreases. In practical applications, the peak value of the inductor current cannot be infinitely small and is usually set between 100mA and 500mA. The load sense voltage Vcomp when the peak value of the inductor current is set to the minimum current value is the sensing reference voltage Vlowclp.

[0050] When a channel operates in continuous conduction mode, Vcomp > Vlowclp, and the frequency reduction comparator CMP1 outputs a low level, indicating that the channel does not need to be down-clocked. Since the output voltage Vdf of the second subtractor is at least 0, the output voltage Vdf of the second subtractor is 0. The phase-locked loop module composed of the frequency and phase detector PFD, the charge pump CP, and the voltage-controlled oscillator VCO ensures that the channel clock signal CLK_SW output by the channel clock module 20 is consistent with the sub-clock signal received by the channel clock module 20.

[0051] When a channel operates in the discontinuous conduction mode, Vcomp < Vlowclp, the down-frequency comparator CMP1 outputs a high level, indicating that the channel needs to down-frequency. At this time, the phase-frequency detector PFD is turned off, and the phase-locked loop module no longer compares the phase difference between the channel clock signal CLK_SW and the received sub-clock signal. The output voltage Vc of the charge pump CP remains unchanged, the output voltage Vdf of the second subtractor is positive, and the control voltage of the voltage-controlled oscillator VCO is Vc - Vdf. The voltage-controlled oscillator VCO generates the channel clock signal based on Vc - Vdf.

[0052] In the discontinuous conduction mode, as the load decreases, the load detection Vcomp decreases, the output voltage Vdf of the second subtractor increases, the control voltage Vc - Vdf of the voltage-controlled oscillator VCO decreases, and the frequency of the channel clock signal decreases, that is, the switching frequency of the channel DC-DC converter decreases to ensure the stability of its output.

[0053] In summary, when a channel operates in the continuous conduction mode, the corresponding channel clock signal CLK_SW is a sub-clock signal generated by misphasing the reference clock signal, which can ensure that each channel operates with misphasing. However, when a channel operates in the discontinuous conduction mode, the channel clock signal CLK_SW is the clock signal generated by the corresponding channel clock module 20. Since the channel clock modules 20 are completely independent of each other, it is impossible to ensure that each channel operates with misphasing, and there are certain application risks.

[0054] In view of this, the present disclosure provides a clock circuit for a multi-channel voltage converter. In the discontinuous conduction mode, at the channel delay time after the end of the channel target sub-clock signal in the current cycle by the channel clock circuit, the channel target sub-clock signal for the next cycle is determined, and the channel clock signal for the next cycle is generated based on the channel target sub-clock signal for the next cycle, so as to down-frequency the sub-clock signal and obtain a channel clock signal with a lower frequency to ensure stable output of each channel under light load. By controlling other channel clock circuits to be disabled within the misphasing delay time after the channel target sub-clock signal enters the next cycle by the channel clock circuit, it is possible to control other channel clock signals to be invalid (low level) at the rising edge of one channel clock signal, so as to generate misphased channel clock signals, thereby ensuring that each channel operates with misphasing in the discontinuous conduction mode.

[0055] The following uses several specific embodiments to describe in detail the clock circuit of the multi-channel voltage converter provided by the present disclosure.

[0056] Figure 2 FIG. is a schematic structural diagram of a clock circuit of a multi-channel voltage converter provided for an embodiment of the present disclosure, as Figure 2As shown, the clock circuit 100 of the multi-channel voltage converter includes a reference clock circuit 110 and N channel clock circuits 120. The N output terminals (from the first output terminal to the Nth output terminal) of the reference clock circuit 110 are connected one-to-one with the N input terminals (from the first output terminal to the Nth output terminal) of each channel clock circuit 120, where N is an integer greater than or equal to 2.

[0057] The reference clock circuit 110 is configured to generate a reference clock signal CLK0 and perform phase reversal processing on the reference clock signal CLK0 to obtain N sub-clock signals (the first sub-clock signal CLK_1 to the Nth sub-clock signal CLK_N).

[0058] Each channel clock circuit 120 is configured to determine the channel operating mode based on the channel load detection voltage Vcomp. When the channel operating mode is discontinuous conduction mode, at the channel delay time Tc after the end of the current cycle's channel target sub-clock signal, the channel target sub-clock signal CLK_set for the next cycle is determined. Based on the channel target sub-clock signal CLK_set for the next cycle, the channel clock signal CLK_SW for the next cycle is generated. During the phase delay time Tp after the channel target sub-clock signal CLK_set enters the next cycle, the other channel clock circuits are disabled.

[0059] Within each cycle, the rising edge of the channel clock signal CLK_SW is aligned with the rising edge of the channel target sub-clock signal CLK_set. The channel target sub-clock signal CLK_set for the next cycle is the signal whose rising edge is closest to the channel delay time Tc at the end of the current cycle among the N sub-clock signals (from the first sub-clock signal CLK_1 to the Nth sub-clock signal CLK_N).

[0060] For example, such as Figure 2 As shown, the reference clock circuit 110 includes a reference clock generation module 111 and a delay phase-locked loop module 112. The output terminal of the reference clock generation module 111 is connected to the input terminal of the delay phase-locked loop module 112. The N output terminals (from the first output terminal to the Nth output terminal) of the delay phase-locked loop module 112 are connected one-to-one with the N input terminals (from the first output terminal to the Nth output terminal) of each channel clock circuit 120.

[0061] The reference clock generation module 111 generates a reference clock signal CLK0. The delay phase-locked loop module 112 delays and phase-locks the reference clock signal CLK0 to obtain and output N sub-clock signals (the first sub-clock signal CLK_1 to the Nth sub-clock signal CLK_N). For example, the reference clock circuit 110 can generate ten sub-clock signals (the first sub-clock signal CLK_1 to the tenth sub-clock signal CLK_10), such as... Figure 3 As shown, Figure 3This is a schematic diagram of ten sub-clock signals provided in an embodiment of the present disclosure.

[0062] Figure 4 A circuit diagram of a channel clock circuit provided in an embodiment of this disclosure is shown below. Figure 4 As shown, each channel clock circuit 120 includes a mode detection circuit and a clock selection circuit. The first input terminal of the mode detection circuit is connected to the channel load detection voltage Vcomp, the second input terminal of the mode detection circuit is connected to the detection reference voltage Vlowclp, and the output terminal of the mode detection circuit is connected to the control terminal of the clock selection circuit. The N input terminals of the clock selection circuit are connected one-to-one with the N output terminals (from the first output terminal to the Nth output terminal) of the reference clock circuit 110.

[0063] For example, such as Figure 4 As shown, the mode detection circuit includes a down-conversion comparator CMP1. The non-inverting input of the down-conversion comparator CMP1 is connected to the detection reference voltage Vlowclp, the inverting input of the down-conversion comparator CMP1 is connected to the load detection voltage Vcomp, and the output of the down-conversion comparator CMP1 is connected to the control terminal of the clock selection circuit.

[0064] The mode detection circuit determines the channel mode detection signal Dec based on whether the channel load detection voltage Vcomp is greater than the detection reference voltage Vlowclp. When the channel load detection voltage Vcomp is greater than the detection reference voltage Vlowclp, the channel mode detection signal Dec is a continuous conduction mode signal (low level). When the channel load detection voltage Vcomp is less than the detection reference voltage Vlowclp, the channel mode detection signal Dec is a discontinuous conduction mode signal (high level).

[0065] See also Figure 4 The clock selection circuit includes N D flip-flops (the first D flip-flop Q1 to the Nth flip-flop QN), N+1 OR gates (the first OR gate OR1 to the Nth OR gate ORN and the N+1th OR gate OR0), NOR gate NOR, N switches (the first switch S1 to the Nth switch SN), a first selector Mux1 and a second selector Mux2.

[0066] The first input terminal of the first selector Mux1 and the first input terminal of the second selector Mux2 are connected to the power supply voltage. The second input terminal of the first selector Mux1 is connected to the channel delay time signal Set. The second input terminal of the second selector Mux2 is grounded. The control terminals of the first selector Mux1 and the second selector Mux2 are connected to the first strobe signal Ctrl1. The output terminal of the first selector Mux1 is connected to the reset terminal of N D flip-flops (from the first D flip-flop Q1 to the Nth flip-flop QN). The output terminal of the second selector Mux2 is connected to the first input terminal of the N+1th OR gate OR0.

[0067] The non-inverting outputs of N D flip-flops (from the first D flip-flop Q1 to the Nth flip-flop QN) are connected one-to-one with the first inputs of the first OR gate OR1 to the Nth OR gate ORN. The second inputs of the first OR gate OR1 to the Nth OR gate ORN are connected to the output of the NOR gate NOR. The outputs of the first OR gate OR1 to the Nth OR gate ORN are connected one-to-one with the inputs of the N D flip-flops (from the first D flip-flop Q1 to the Nth flip-flop QN). The non-inverting output of each D flip-flop (each of the first D flip-flop Q1 to the Nth flip-flop QN) is connected to one input of the NOR gate NOR. The clock input of each D flip-flop (each of the first D flip-flop Q1 to the Nth flip-flop QN) is connected to the input of a switch (one of the first switch S1 to the Nth switch SN) and one output of the reference clock circuit 110.

[0068] The second input of the (N+1)th OR gate OR0 of the i-th channel clock circuit is connected to the non-inverting output of the j-th D flip-flop Qi. The output of the (N+1)th OR gate OR0 of the i-th channel clock circuit is connected to the control terminal of the j-th switch Sj. The control terminals of the remaining N-1 switches (switches other than the j-th switch Sj) are connected one-to-one with the non-inverting outputs of the remaining N-1 D flip-flops (D flip-flops other than the j-th D flip-flop Qj). The output terminals of the N switches (from the first switch S1 to the Nth switch SN) are connected to the output terminal of the clock selection circuit.

[0069] Where i is any integer greater than or equal to 1 and less than or equal to M, M is the number of channels of the multi-channel voltage converter, j is any integer greater than or equal to 1 and less than or equal to N, j=1+(i-1)N / M.

[0070] For example, Figure 4 The channel clock circuit 120 shown is the first channel clock circuit. In the first channel clock circuit, the second input terminal of the (N+1)th OR gate OR0 is connected to the positive output terminal of the first D flip-flop Q1, the output terminal of the (N+1)th OR gate OR0 is connected to the control terminal of the first switch S1, and the control terminals of the second switch S2 to the Nth switch SN are connected one-to-one with the positive output terminals of the second D flip-flop Q2 to the Nth D flip-flop QN.

[0071] For example, when the channel mode detection signal Dec is a continuous conduction mode signal (low level), the channel clock signal CLK_SW does not need to be down-clocked, the first strobe signal Ctrl1 is low, and the first selector Mux1 outputs a high level. Then, the N D flip-flops (from the first D flip-flop Q1 to the Nth flip-flop QN) are in a reset state, and the N D flip-flops (from the first D flip-flop Q1 to the Nth flip-flop QN) output a low level. Switches other than the j-th switch Sj are turned off. For example, Figure 4In the channel clock circuit 120 shown, when the channel mode detection signal Dec is a continuous conduction mode signal (low level), the second switch S2 to the Nth switch SN are turned off.

[0072] At this time, the second selector Mux2 outputs a high level, the N+1 OR gate OR0 outputs a high level, the j-th switch Sj connected to the output of the N+1 OR gate OR0 is turned on, and the j-th sub-clock signal CLK_j received by the j-th switch Sj is the channel target sub-clock signal CLK_set, that is, CLK_set=CLK_j.

[0073] For example, Figure 4 In the channel clock circuit 120 shown, when the channel mode detection signal Dec is a continuous conduction mode signal (low level), the first switch S1 is turned on, and the first sub-clock signal CLK_1 is the channel target sub-clock signal CLK_set, that is, CLK_set=CLK_1.

[0074] Thus, when the channel mode detection signal Dec is a continuous conduction mode signal (low level), the clock selection circuit selects one of the N sub-clock signals (the first sub-clock signal CLK_1 to the Nth sub-clock signal CLK_N) as the channel target sub-clock signal CLK_set.

[0075] For example, when the channel mode detection signal Dec is a discontinuous conduction mode signal (high level), and the first strobe signal Ctrl1 is low at the start of the first cycle of the discontinuous conduction mode, then the channel target sub-clock signal CLK_set_T1 of the first cycle in the discontinuous conduction mode maintains the channel target sub-clock signal CLK_set in the continuous conduction mode, that is, CLK_set_T1 = CLK_set. For example, Figure 4 In the channel clock circuit 120 shown, when the channel mode detection signal Dec is a discontinuous conduction mode signal (high level), CLK_set_T1=CLK_set=CLK_1.

[0076] Subsequently, when the channel delay time signal Set toggles to active (high level), the first strobe signal Ctrl1 toggles from low to high level, and the first selector Mux1 outputs the channel delay time signal Set. That is, the output of the first selector Mux1 remains high, so the N D flip-flops (from the first D flip-flop Q1 to the Nth flip-flop QN) remain in the reset state, and the outputs of the N D flip-flops (from the first D flip-flop Q1 to the Nth flip-flop QN) remain low. All switches except the j-th switch Sj remain off. At this time, the second selector Mux2 outputs low level, the N+1th OR gate OR0 outputs low level, and the j-th switch Sj connected to the output of the N+1th OR gate OR0 is turned off. Therefore, the first switches S1 to the Nth switches SN are turned off.

[0077] When the channel delay time signal Set toggles to invalid (low level), N D flip-flops (from the first D flip-flop Q1 to the Nth flip-flop QN) exit the reset state, the outputs of N D flip-flops (from the first D flip-flop Q1 to the Nth flip-flop QN) are low, the NOR gate outputs high, and the first OR gate OR1 to the Nth OR gate ORN output high.

[0078] Subsequently, at the rising edge of the sub-clock signal that first reaches the rising edge among the first sub-clock signal CLK_1 to the Nth sub-clock signal CLK_N, the D flip-flop receiving the sub-clock signal outputs a high level, and the switch receiving the sub-clock signal is turned on. Therefore, the sub-clock signal can be transmitted to the output of the clock selection circuit. Thus, the sub-clock signal is the channel target sub-clock signal CLK_set_T2 of the second cycle.

[0079] For example, in Figure 3 Based on the embodiment shown, in the first cycle of the discontinuous conduction mode, after the channel delay time signal Set flips to invalid (low level), the signal that first reaches the rising edge among the first sub-clock signal CLK_1 to the Nth sub-clock signal CLK_N is the eighth sub-clock signal CLK_8, then CLK_set_T2=CLK_8.

[0080] Similarly, in the z-th cycle of the discontinuous conduction mode, it can be determined that the first rising edge of the N sub-clock signals (from the first sub-clock signal CLK_1 to the Nth sub-clock signal CLK_N) after the channel delay time signal Set flips to invalid (low level) is the channel target sub-clock signal CLK_set_Tz+1 of the z+1-th cycle, where z is any integer greater than or equal to 1.

[0081] Thus, when the channel mode detection signal Dec is a discontinuous conduction mode signal (high level), the clock selection circuit can determine that the channel target sub-clock signal CLK_set in the continuous conduction mode is the channel target sub-clock signal CLK_set_T1 of the first cycle in the discontinuous conduction mode. In the current cycle of the discontinuous conduction mode, the sub-clock signal whose rising edge arrives first among the N sub-clock signals (the first sub-clock signal CLK_1 to the Nth sub-clock signal CLK_N) after the channel delay time signal Set is flipped to invalid (low level) can be determined as the channel target sub-clock signal of the next cycle.

[0082] See also Figure 4 Each channel clock circuit 120 also includes a clock determination circuit. The input of the clock determination circuit is connected to the output of the clock selection circuit, and the control of the clock determination circuit is connected to the phase delay time signal Set_ok.

[0083] For example, the clock determination circuit includes a third selector Mux3, a NAND gate NA, a duty cycle delay unit Delay1, and a first D flip-flop Qa. The first input of the third selector Mux3 and the input of the first D flip-flop Qa are connected to the power supply voltage. The second input of the third selector Mux3 is connected to the phase-out delay time signal Set_ok. The control terminal of the third selector Mux3 is connected to the second strobe signal Ctrl2. The output of the third selector Mux3 is connected to the first input of the NAND gate NA.

[0084] The second input of the NAND gate NA is connected to the output of the duty cycle delay Delay1. The output of the NAND gate NA is connected to the reset terminal of the first D flip-flop Qa. The clock terminal of the first D flip-flop Qa is connected to the output of the clock selection circuit. The non-inverting output of the first D flip-flop Qa is connected to the clock output of the channel clock circuit 120. The inverting output of the first D flip-flop Qa is connected to the input of the duty cycle delay Delay1.

[0085] When the channel mode detection signal Dec is a continuous conduction mode signal (low level), the second strobe signal Ctrl2 is low level, the third selector Mux3 outputs a high level, and the NAND gate NA outputs a low level. On the rising edge of the channel target sub-clock signal CLK_set, the channel clock signal CLK_SW output by the first D flip-flop Qa flips from invalid (low level) to valid (high level), and the input signal of the duty cycle delay unit Delay1 flips from high level to low level.

[0086] The duty cycle delay unit Delay1 has a duty cycle delay time Td. Delay1 delays the falling edge of the input signal by this time Td. Therefore, at the duty cycle delay time Td after the channel clock signal CLK_SW transitions from low to high, Delay1 outputs a low level, the first D flip-flop Qa is reset, and the channel clock signal CLK_SW transitions from active (high) to inactive (low). The duty cycle delay time Td can be flexibly set according to actual needs.

[0087] When the channel mode detection signal Dec is a discontinuous conduction mode signal (high level), in the first cycle of the discontinuous conduction mode, after the channel clock signal CLK_SW flips from high to low, the second strobe signal Ctrl2 flips to high, and the third selector Mux3 outputs the phase delay time signal Set_ok. At this time, the phase delay time signal Set_ok is low, so the third selector Mux3 outputs low, the NAND gate NA outputs high, the first D flip-flop Qa is in the reset state, and the channel clock signal CLK_SW remains low until the channel target sub-clock signal CLK_set_T1 flips to high. Then, the first D flip-flop Qa exits the reset state, ensuring that the first D flip-flop Qa responds to the channel target sub-clock signal CLK_set_T2.

[0088] In other cycles of the discontinuous conduction mode, the second strobe signal Ctrl2 is high. When the phase delay time signal Set_ok is valid (high), the third selector Mux3 outputs a high level, the NAND gate NA outputs a low level, the first D flip-flop Qa exits the reset state, and on the rising edge of the channel target sub-clock signal CLK_set, the channel clock signal CLK_SW output by the first D flip-flop Qa flips from invalid (low level) to valid (high level), and the input signal of the duty cycle delay unit Delay1 flips from high level to low level.

[0089] The duty cycle delay timer Delay1 delays the falling edge of the input signal by a duty cycle delay time Td. At the duty cycle delay time Td after the channel clock signal CLK_SW flips from low to high, the duty cycle delay timer Delay1 outputs a low level, the first D flip-flop Qa is in the reset state, and the channel clock signal CLK_SW flips from valid (high level) to invalid (low level).

[0090] Thus, when the phase delay time signal Set_ok is valid (high level), the clock determination circuit pulls the channel clock signal CLK_SW high on the rising edge of the channel target sub-clock signal and pulls the channel clock signal CLK_SW low after the duty cycle delay time Td.

[0091] For example, the channel clock circuit 120 also includes a clamping subtractor, a voltage-to-time conversion circuit, and a phase-shifting delay unit Delay2. The non-inverting input of the clamping subtractor is connected to the detection reference voltage Vlowclp, the inverting input of the clamping subtractor is connected to the channel load detection voltage Vcomp, and the output of the clamping subtractor is connected to the input of the voltage-to-time conversion circuit.

[0092] The reset terminal of the voltage-time conversion circuit is connected to the output terminal of the phase-shifting delay Delay2. The input terminal of the phase-shifting delay Delay2 is connected to the clock output terminal of the channel clock circuit 120. The control terminal of the voltage-time conversion circuit is connected to the control output terminal of the clock selection circuit. The output terminal of the voltage-time conversion circuit is connected to the reset terminal of the clock selection circuit.

[0093] The clamping subtractor receives the channel load detection voltage Vcomp and the detection reference voltage Vlowclp, and calculates the differential voltage Vlowclp-Vcomp between them. The phase-shifting delay unit Delay2 receives the channel clock signal CLK_SW, delays the rising edge of CLK_SW by a phase-shifting delay time Tp, and outputs the conversion reset signal Reset.

[0094] Figure 5 A circuit diagram of a voltage-time conversion circuit provided in an embodiment of this disclosure is shown below. Figure 5 As shown, the voltage-time conversion circuit includes a fifth D flip-flop Qe, an RS flip-flop Qf, an inverter, an AND gate, a time comparator CMP2, a transistor M, a current source IB, and a capacitor C.

[0095] The power supply voltage is connected to the non-inverting input of time comparator CMP2, the first plate of capacitor C, and the first terminal of transistor M through current source IB. The inverting input of time comparator CMP2 is connected to the output of clamp subtractor. The second plate of capacitor C and the second terminal of transistor M are grounded. The output of time comparator CMP2 is connected to the first input of AND gate. The enable signal Sel_BLK is connected to the second input of AND gate through inverter. The output of AND gate is connected to the set terminal of RS flip-flop Qf.

[0096] The reset terminals of RS flip-flop Qf and the fifth D flip-flop Qe are connected to the output of the phase-shifting delay circuit Delay2. The non-inverting output of RS flip-flop Qf is connected to the enable terminal of other channel clock circuits and the reset terminal of the clock selection circuit. The clock terminal of the fifth D flip-flop Qe is connected to the control output of the clock selection circuit. The input terminal of the fifth D flip-flop Qe is connected to the power supply voltage. The inverting output terminal of the fifth D flip-flop Qe is connected to the control terminal of transistor M.

[0097] The enable signal Sel_BLK of one channel clock circuit 120 depends on the phase delay time signal Set_ok of the other channel clock circuits 120. When the phase delay time signal Set_ok of any channel clock circuit 120 is valid (high level), the enable signal Sel_BLK of that channel clock circuit 120 is invalid (high level).

[0098] Similarly, the phase delay time signal Set_ok of one channel clock circuit 120 determines the enable signal Sel_BLK of other channel clock circuits 120. When the phase delay time signal Set_ok of the channel clock circuit 120 is valid (high level), the enable signal Sel_BLK of all other channel clock circuits 120 is invalid (high level).

[0099] Since the channel clock signal CLK_SW flips from invalid (low level) to valid (high level) during the time that the phase delay time signal Set_ok remains valid (high level), it is possible to control other channel clock circuits 120 to be disabled while one channel clock circuit 120 pulls the channel clock signal CLK_SW high, so that the channel clock circuits 120 generate phase-out channel clock signals CLK_SW.

[0100] The following discussion focuses on the operation of the voltage-time conversion circuit when the enable signal Sel_BLK of the channel clock circuit 120 is active (low level).

[0101] For example, when the channel mode detection signal Dec is a continuous conduction mode signal (low level), the voltage-time conversion circuit does not work, and the phase delay time signal Set_ok output by the RS flip-flop Qf remains invalid (low level).

[0102] When the channel mode detection signal Dec is a discontinuous conduction mode signal (high level) and the channel delay time signal Set flips from invalid (low level) to valid (high level), the fifth D flip-flop Qe provides a low level signal to the transistor M, then the transistor M is turned off, the current source IB starts to charge the capacitor C, and the voltage across the capacitor C rises from 0.

[0103] When the voltage across capacitor C is less than the differential voltage Vlowclp-Vcomp, time comparator CMP2 outputs a low level, and the phase delay time signal Set_ok output by RS flip-flop Qf remains inactive (low level). When the voltage across capacitor C rises to the differential voltage Vlowclp-Vcomp, the output of time comparator CMP2 flips from low to high, and the phase delay time signal Set_ok output by RS flip-flop Qf flips from inactive (low level) to active (high level), which can disable other channel clock circuits. Specifically, when the phase delay time signal Set_ok flips from inactive (low level) to active (high level), the channel delay time signal Set flips from active (high level) to inactive (low level).

[0104] Therefore, the time for the channel delay signal Set to remain valid (high level) is the time required for the voltage across capacitor C to rise from 0 to the differential voltage Vlowclp-Vcomp, which is the channel delay time Tc. The time required for the voltage across capacitor C to rise from 0 to the differential voltage Vlowclp-Vcomp is positively correlated with the differential voltage Vlowclp-Vcomp. Thus, the differential voltage Vlowclp-Vcomp is positively correlated with the channel delay time Tc. The larger the differential voltage Vlowclp-Vcomp is, the longer the channel delay time Tc is.

[0105] When the reset signal Reset flips from invalid (low level) to valid (high level), the RS flip-flop Qf is in the reset state, and the phase delay time signal Set_ok output by the RS flip-flop Qf flips from valid (high level) to invalid (low level). At the same time, the fifth D flip-flop Qe is in the reset state, and the signal provided by the fifth D flip-flop Qe to the transistor M flips to high level, and the transistor M turns on to release the charge stored in the capacitor C to ground.

[0106] Therefore, the rising edge of the phase delay time signal Set_ok corresponds to the falling edge of the channel delay time signal Set, and the phase delay time signal Set_ok is pulled low after the phase delay time Tp is delayed from the rising edge of the channel clock signal CLK_SW. Thus, the time during which the phase delay time signal Set_ok remains valid (high level) includes the phase delay time Tp, so that the time difference between the channel clock signals CLK_SW is not less than the phase delay time Tp.

[0107] Thus, when the channel clock circuit 120 is enabled, the voltage-time conversion circuit can convert the differential voltage Vlowclp-Vcomp into the channel delay time Tc to determine the channel delay time signal Set; based on the channel delay time signal Set and the conversion reset signal Reset, the phase-out delay time signal Set_ok is determined.

[0108] In summary, in discontinuous conduction mode, the channel clock circuit 120 determines the target sub-clock signal for the next cycle at the channel delay time after the current cycle's target sub-clock signal ends. Based on this target sub-clock signal, the channel clock signal for the next cycle is generated. This allows for frequency downclocking of the sub-clock signal, resulting in a lower-frequency channel clock signal to ensure stable output of each channel under light load. Furthermore, by disabling other channel clock circuits during the phase delay time after the target sub-clock signal enters the next cycle, the channel clock circuit 120 can control other channel clock signals to be invalid (low level) at the rising edge of one channel clock signal, thus generating a phase-shifted channel clock signal and ensuring phase-shifted operation of each channel in discontinuous conduction mode.

[0109] In some embodiments, see continue to see Figure 4 Each channel clock circuit 120 also includes a pull-down resistor Rd, a second D flip-flop Qb, a third D flip-flop Qc, and a fourth D flip-flop Qd. The pull-down resistor Rd is connected between the output of the clock selection circuit and ground. The clock terminal of the second D flip-flop Qb is connected to the inverted output of the first D flip-flop Qa. The input terminal of the second D flip-flop Qb is connected to the output of the mode detection circuit. The non-inverted output terminal of the second D flip-flop Qb is connected to the input of the third D flip-flop Qc, the control terminal of the third selector Mux3, and the input of the fourth D flip-flop Qd.

[0110] The clock terminals of the third D flip-flop Qc and the fourth D flip-flop Qd are connected to the output of the clock selection circuit. The non-inverting output of the third D flip-flop Qc is connected to the control terminal of the first selector Mux1 and the control terminal of the second selector Mux2. The reset terminal of the fourth D flip-flop Qd is connected to the phase delay time signal Set_ok. The non-inverting output of the fourth D flip-flop Qd is connected to the second input of the first selector Mux1.

[0111] For example, when the channel mode detection signal Dec is a continuous conduction mode signal (low level), the second strobe signal Ctrl2 output by the second D flip-flop Qb and the first strobe signal Ctrl1 output by the third D flip-flop Qc are both low level.

[0112] When the channel mode detection signal Dec is a discontinuous conduction mode signal (high level), when the channel clock signal CLK_SW flips from valid (high level) to invalid (low level), the second strobe signal Ctrl2 output by the second D flip-flop Qb flips from low level to high level. At this time, the phase delay time signal Set_ok is invalid (low level).

[0113] Subsequently, when the next rising edge of the channel target sub-clock signal CLK_set arrives, the channel delay time signal Set output by the fourth D flip-flop Qd toggles from invalid (low level) to valid (high level), and the first strobe signal Ctrl1 output by the third D flip-flop Qc toggles from low level to high level.

[0114] When the phase delay time signal Set_ok toggles from invalid (low level) to valid (high level), the channel delay time signal Set toggles from valid (high level) to invalid (low level). When the first switch S1 to the Nth switch SN is turned off, the channel target sub-clock signal CLK_set is pulled down to 0 by the pull-down resistor Rd. Afterwards, when the channel target sub-clock signal CLK_set is pulled high, the channel delay time signal Set toggles from invalid (low level) to valid (high level).

[0115] Embodiments of this disclosure also provide a multi-channel voltage converter, including the clock circuit 100 provided in any of the above embodiments.

[0116] The multi-channel voltage converter provided in this disclosure includes the clock circuit 100 provided in any of the above embodiments, and has the same functional modules and beneficial effects as the clock circuit 100, which will not be described again here.

[0117] Embodiments of this disclosure also provide a power management chip, including the clock circuit 100 provided in any of the above embodiments.

[0118] The power management chip provided in this disclosure includes the clock circuit 100 provided in any of the above embodiments, and has the same functional modules and beneficial effects as the clock circuit 100, which will not be described again here.

[0119] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0120] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0121] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A clock circuit for a multi-channel voltage converter, characterized in that, It includes a reference clock circuit and N channel clock circuits. The N output terminals of the reference clock circuit are connected one-to-one with the N input terminals of each channel clock circuit, where N is an integer greater than or equal to 2. The reference clock circuit is configured to generate a reference clock signal and perform phase-shifting processing on the reference clock signal to obtain N sub-clock signals. Each channel clock circuit is configured to determine the channel operating mode based on the channel load detection voltage; when the channel operating mode is a discontinuous conduction mode, at the channel delay time after the end of the channel target sub-clock signal of the current cycle, determine the channel target sub-clock signal of the next cycle, generate the channel clock signal of the next cycle based on the channel target sub-clock signal of the next cycle, and control other channel clock circuits to be disabled during the phase delay time after the channel target sub-clock signal enters the next cycle; In each cycle, the rising edge of the channel clock signal is aligned with the rising edge of the channel target sub-clock signal, and the channel target sub-clock signal of the next cycle is the signal among the N sub-clock signals whose rising edge is closest to the channel delay time after the end of the current cycle. Each channel clock circuit includes a clock selection circuit and a mode detection circuit; the N input terminals of the clock selection circuit are connected one-to-one with the N output terminals of the reference clock circuit; the first input terminal of the mode detection circuit is connected to the channel load detection voltage; the second input terminal of the mode detection circuit is connected to the detection reference voltage; and the output terminal of the mode detection circuit is connected to the control terminal of the clock selection circuit. The mode detection circuit is configured to determine the channel mode detection signal based on whether the channel load detection voltage is greater than the detection reference voltage. The clock selection circuit is configured to: when the channel mode detection signal is a continuous conduction mode signal, select one of the N sub-clock signals as the channel target sub-clock signal; when the channel mode detection signal is a discontinuous conduction mode signal, determine the channel target sub-clock signal in the continuous conduction mode as the channel target sub-clock signal for the first cycle in the discontinuous conduction mode; and in the current cycle of the discontinuous conduction mode, after the channel delay time signal is flipped to invalid, determine the sub-clock signal whose rising edge arrives first among the N sub-clock signals as the channel target sub-clock signal for the next cycle.

2. The clock circuit according to claim 1, characterized in that, Each channel clock circuit also includes a clock determination circuit; The input terminal of the clock determination circuit is connected to the output terminal of the clock selection circuit, and the control terminal of the clock determination circuit is connected to the phase delay time signal. The clock determination circuit is configured to, when the phase delay time signal is valid, pull up the channel clock signal on the rising edge of the channel target sub-clock signal and pull down the channel clock signal after the duty cycle delay time.

3. The clock circuit according to claim 2, characterized in that, The clock selection circuit includes N D flip-flops, N+1 OR gates, NOR gates, N switches, a first selector, and a second selector; The first input terminal of the first selector and the first input terminal of the second selector are connected to the power supply voltage. The second input terminal of the first selector is connected to the channel delay time signal. The second input terminal of the second selector is grounded. The control terminals of the first selector and the second selector are connected to the first strobe signal. The output terminal of the first selector is connected to the reset terminal of the N D flip-flops. The output terminal of the second selector is connected to the first input terminal of the (N+1)th OR gate. The non-inverting outputs of the N D flip-flops are connected one-to-one with the first inputs of the first OR gate to the Nth OR gate. The second inputs of the first OR gate to the Nth OR gate are connected to the output of the NOR gate. The outputs of the first OR gate to the Nth OR gate are connected one-to-one with the inputs of the N D flip-flops. The non-inverting output of each D flip-flop is connected to one input of the NOR gate. The clock input of each D flip-flop is connected to the input of a switch and one output of the reference clock circuit. The second input terminal of the (N+1)th OR gate of the i-th channel clock circuit is connected to the non-inverting output terminal of the j-th D flip-flop. The output terminal of the (N+1)th OR gate of the i-th channel clock circuit is connected to the control terminal of the j-th switch. The control terminals of the remaining N-1 switches are connected one-to-one with the non-inverting output terminals of the remaining N-1 D flip-flops. The output terminals of the N switches are connected to the output terminal of the clock selection circuit. Where i is any integer greater than or equal to 1 and less than or equal to M, M is the number of channels of the multi-channel voltage converter, j is any integer greater than or equal to 1 and less than or equal to N, j=1+(i-1)N / M.

4. The clock circuit according to claim 3, characterized in that, The clock determination circuit includes a third selector, a NAND gate, a duty cycle delay unit, and a first D flip-flop; The first input terminal of the third selector and the input terminal of the first D flip-flop are connected to the power supply voltage. The second input terminal of the third selector is connected to the phase delay time signal. The control terminal of the third selector is connected to the second strobe signal. The output terminal of the third selector is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is connected to the output terminal of the duty cycle delay unit. The output terminal of the NAND gate is connected to the reset terminal of the first D flip-flop. The clock terminal of the first D flip-flop is connected to the output terminal of the clock selection circuit, the non-inverting output terminal of the first D flip-flop is connected to the clock output terminal of the channel clock circuit, and the inverting output terminal of the first D flip-flop is connected to the input terminal of the duty cycle delay unit.

5. The clock circuit according to claim 4, characterized in that, Each channel clock circuit also includes a pull-down resistor, a second D flip-flop, a third D flip-flop, and a fourth D flip-flop; The pull-down resistor is connected between the output of the clock selection circuit and ground. The clock terminal of the second D flip-flop is connected to the inverting output of the first D flip-flop. The input of the second D flip-flop is connected to the output of the mode detection circuit. The non-inverting output of the second D flip-flop is connected to the input of the third D flip-flop, the control terminal of the third selector, and the input of the fourth D flip-flop. The clock terminals of the third and fourth D flip-flops are connected to the output terminals of the clock selection circuit. The non-inverting output terminal of the third D flip-flop is connected to the control terminals of the first and second selectors. The reset terminal of the fourth D flip-flop is connected to the phase delay time signal. The non-inverting output terminal of the fourth D flip-flop is connected to the second input terminal of the first selector.

6. The clock circuit according to any one of claims 1-5, characterized in that, The channel clock circuit also includes a clamping subtractor, a voltage-time conversion circuit, and a phase-out delay; The non-inverting input of the clamping subtractor is connected to the detection reference voltage, the inverting input of the clamping subtractor is connected to the channel load detection voltage, the output of the clamping subtractor is connected to the input of the voltage-time conversion circuit, the reset terminal of the voltage-time conversion circuit is connected to the output of the phase-shift delay unit, the input of the phase-shift delay unit is connected to the clock output of the channel clock circuit, the control terminal of the voltage-time conversion circuit is connected to the control output of the clock selection circuit, and the output of the voltage-time conversion circuit is connected to the reset terminal of the clock selection circuit. The clamping subtractor is configured to determine the differential voltage between the channel load detection voltage and the detection reference voltage; The phase-delay delayer is configured to delay the rising edge of the channel clock signal by the phase-delay time to determine the conversion reset signal; The voltage-time conversion circuit is configured to convert the differential voltage into the channel delay time when the channel clock circuit is enabled, so as to determine the channel delay time signal. Based on the channel delay time signal and the conversion reset signal, the phase misalignment delay time signal is determined.

7. The clock circuit according to claim 6, characterized in that, The voltage-time conversion circuit includes a fifth D flip-flop, an RS flip-flop, an inverter, an AND gate, a time comparator, a transistor, a current source, and a capacitor; The power supply voltage is connected to the non-inverting input of the time comparator, the first plate of the capacitor, and the first terminal of the transistor through the current source. The inverting input of the time comparator is connected to the output of the clamping subtractor. The second plate of the capacitor and the second terminal of the transistor are grounded. The output of the time comparator is connected to the first input of the AND gate. The enable signal is connected to the second input of the AND gate through the inverter. The output of the AND gate is connected to the set terminal of the RS flip-flop. The reset terminals of the RS flip-flop and the fifth D flip-flop are connected to the output terminal of the phase-delayed circuit. The non-inverting output terminal of the RS flip-flop is connected to the enable terminal of the other channel clock circuit and the reset terminal of the clock selection circuit. The clock terminal of the fifth D flip-flop is connected to the control output terminal of the clock selection circuit. The input terminal of the fifth D flip-flop is connected to the power supply voltage. The inverting output terminal of the fifth D flip-flop is connected to the control terminal of the transistor.

8. A multi-channel voltage converter, characterized in that, Includes the clock circuit described in any one of claims 1-7.

9. A power management chip, characterized in that, Includes the multichannel voltage converter as described in claim 8.

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