Gating circuit and multiplexer

Abstract

The application provides a gating circuit and a multiplexer. The circuit comprises a first switch module, a second switch module, a voltage generating module, a first current generating module and a second current generating module, the second switch module is electrically connected with the first switch module, the voltage generating module, the first current generating module and the second current generating module, the voltage generating module is electrically connected with the first current generating module and the second current generating module, the first switch module and the second switch module are both used for being electrically connected with a positive electrode of a battery, the first switch module is used for being electrically connected with a battery output bus, and the second switch module is used for being electrically connected with a switch common bus. The gating circuit provided by the embodiment of the application effectively breaks through the speed bottleneck of the traditional scheme, greatly improves the overall switching frequency of the multiplexer and the real-time response of the system, and can meet the demand of the next generation battery management system for high-frequency and real-time voltage sampling.

Description

Technical Field

[0001] This application belongs to the field of multiplexer technology, and particularly relates to a gating circuit and a multiplexer. Background Technology

[0002] With the increasing demands for range and safety from electric vehicles, large-scale energy storage systems, and high-end portable devices, multi-cell series lithium battery packs have become a core energy supply solution. High-precision, real-time monitoring of the voltage of each individual battery cell by the battery management chip is crucial for ensuring the safe operation and extended lifespan of the battery pack. In the voltage monitoring link, the high-voltage multiplexer undertakes the core task of "selecting the voltage of a single battery cell and transmitting it to the analog-to-digital converter." To achieve functions such as rapid battery fault diagnosis and real-time triggering of dynamic balancing, the multiplexer needs to have high-speed channel switching capabilities at the nanosecond to microsecond level.

[0003] Currently, mainstream multiplexer gating schemes in the industry typically employ a "back-to-back high-voltage PMOS transistor and gate bias resistor" topology. The core design idea is to use the bias resistor in conjunction with a global gate pull-down circuit, utilizing the IR voltage drop generated across the bias resistor by the pull-down current to drive the PMOS transistor to conduct, thereby achieving the gating and transmission of battery voltage. However, due to the inherent parasitic capacitance of the PMOS transistor's gate, and the need to balance high-voltage isolation and bias current stability in the value of the bias resistor, the RC charging and discharging circuit formed by these two components has a large time constant. During the switch-off phase, the charge on the gate capacitance needs to be slowly charged through the bias resistor, and the gate potential cannot quickly recover to the high-level state required for turn-off. Summary of the Invention

[0004] This application provides a gating circuit and a multiplexer that can solve the problem that in the existing gating circuit, during the switch-off phase, the charge on the gate capacitor needs to be slowly charged through the bias resistor, and the gate potential cannot be quickly restored to the high-level state required for turn-off.

[0005] In a first aspect, embodiments of this application provide a selection circuit, including a first switch module, a second switch module, a voltage generation module, a first current generation module, and a second current generation module. The second switch module is electrically connected to the first switch module, the voltage generation module, the first current generation module, and the second current generation module, respectively. The voltage generation module is electrically connected to the first current generation module and the second current generation module, respectively. Both the first switch module and the second switch module are used to be electrically connected to the positive terminal of the battery. The first switch module is used to be electrically connected to the battery output bus, and the second switch module is used to be electrically connected to the switch common bus.

[0006] The first current generating module is used to receive a first clock signal, and the second current generating module is used to receive a second clock signal. When the first clock signal is a first level signal and the second clock signal is a second level signal, the first current generating module is used to generate a first current according to the first level signal, and the voltage generating module is used to generate a first voltage according to the first current, and transmit the first voltage to a common node, where the common node is the connection point between the first switching module and the second switching module. Both the first switching module and the second switching module are used to conduct voltage according to the common node, so that the voltage output by the battery is transmitted to the battery output bus and the switch common bus.

[0007] When the first clock signal is a third-level signal and the second clock signal is a fourth-level signal, the second current generation module is used to generate a second current according to the second clock signal to increase the rising slope of the voltage of the common node. Both the first switch module and the second switch module are used to turn off according to the voltage of the common node.

[0008] In one possible implementation of the first aspect, the first switching module includes a first switching transistor and a second switching transistor. The gates of the first switching transistor and the second switching transistor are respectively electrically connected to the second switching module, the voltage generating module, and the first current generating module. The drain of the first switching transistor is electrically connected to the positive terminal of the battery. The source of the first switching transistor is electrically connected to the source of the second switching transistor. The drain of the second switching transistor is electrically connected to the battery output bus.

[0009] In one possible implementation of the first aspect, the second switching module includes a third switching transistor and a fourth switching transistor. The gates of the third switching transistor and the fourth switching transistor are respectively electrically connected to the first switching module, the voltage generating module, and the first current generating module. The drain of the third switching transistor is electrically connected to the positive terminal of the battery. The source of the third switching transistor is electrically connected to the source of the fourth switching transistor and the voltage generating module. The drain of the fourth switching transistor is electrically connected to the switch common bus.

[0010] When the voltage of the selected battery cell is greater than the voltage of the non-selected battery cell, the voltage of the common bus in the selection circuit corresponding to the selected battery cell is transmitted to the source of the fourth switch and the common node through the body diode of the fourth switch in the selection circuit corresponding to the non-selected battery cell, thereby pulling up the voltage of the common node and turning off the first switch module in the selection circuit corresponding to the non-selected battery cell.

[0011] In one possible implementation of the first aspect, the voltage generating module includes a first transistor, a second transistor, and a third transistor. The source of the first transistor is electrically connected to the second switching module. The gate of the first transistor is electrically connected to the drain of the first transistor and the source of the second transistor, respectively. The source of the third transistor is electrically connected to the drain of the second transistor and the gate of the second transistor, respectively. The drain of the third transistor is electrically connected to the first current generating module and the second current generating module, respectively.

[0012] In one possible implementation of the first aspect, the voltage generating module further includes a first resistor, a first end of which is electrically connected to the source of the first transistor, and a second end of which is electrically connected to the drain of the third transistor.

[0013] In one possible implementation of the first aspect, the first current generating module includes a fifth switching transistor and a first current source. The gate of the fifth switching transistor is used to receive the first clock signal. The drain of the fifth switching transistor is electrically connected to the voltage generating module, the first switching module, and the second switching module, respectively. The source of the fifth switching transistor is electrically connected to the first terminal of the first current source, and the second terminal of the first current source is grounded.

[0014] In one possible implementation of the first aspect, the second current generating module includes a current generating unit and a current mirror unit, wherein the current mirror unit is electrically connected to the current generating unit, the voltage generating module, the first switching module, the second switching module and the first current generating module, respectively.

[0015] The current generating unit is used to generate a reference current when the second clock signal is a fourth level signal, and the current mirror unit is used to generate the second current according to the reference current.

[0016] In one possible implementation of the first aspect, the current generating unit includes a sixth switching transistor and a second current source. The gate of the sixth switching transistor is used to receive the second clock signal. The drain of the sixth switching transistor is electrically connected to the current mirror unit. The source of the sixth switching transistor is electrically connected to the first terminal of the second current source. The second terminal of the second current source is grounded.

[0017] In one possible implementation of the first aspect, the current mirror unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor being electrically connected to the gate of the fifth transistor, the drain of the fourth transistor, and the current generating unit, respectively; the source of the fourth transistor and the source of the fifth transistor being electrically connected to the second switching module and the voltage generating module, respectively; and the drain of the fifth transistor being electrically connected to the voltage generating module, the first switching module, the second switching module, and the first current generating module, respectively.

[0018] Secondly, embodiments of this application provide a multiplexer, including a plurality of gating circuits as described in any of the first aspects. The first switch module and the second switch module in each gating circuit are electrically connected to the positive terminal of the corresponding battery and serve as a plurality of input terminals of the multiplexer, respectively. Each first switch module is electrically connected to the battery output bus and serves as the output terminal of the multiplexer.

[0019] The beneficial effects of the embodiments of this application compared with the prior art are:

[0020] The gating circuit provided in this application includes a first switch module, a second switch module, a voltage generation module, a first current generation module, and a second current generation module. When the first clock signal is a first level signal and the second clock signal is a second level signal, the first current generation module generates a first current according to the first level signal, and the voltage generation module generates a first voltage according to the first current, and transmits the first voltage to the common node. Both the first switch module and the second switch module are turned on according to the voltage of the common node, so that the voltage output by the battery can be stably transmitted to the battery output bus, and simultaneously transmitted to the switch common bus. When the first clock signal is a third level signal and the second clock signal is a fourth level signal, the second current generation module generates a second current according to the second clock signal. This second current forms a fast charging path from the common terminal of the first switch module and the voltage generation module to the common node, significantly increasing the rise slope of the common node voltage, accelerating the charging process of the gate capacitor connected at the common node, and enabling the common node voltage to be established rapidly. Under this action, the first switch module and the second switch module can be quickly turned off, cutting off the connection between the positive terminal of the battery and the battery output bus and the switch common bus.

[0021] Therefore, the selection circuit provided in this application embodiment, through the synergistic effect of the first current generation module and the voltage generation module, provides a stable driving voltage for the switching module to turn on, ensuring the accuracy of voltage transmission. Simultaneously, addressing the slow turn-off problem caused by passive charging and discharging of resistors in traditional solutions, a second current generation module is innovatively introduced. This module actively injects a second current to accelerate the rise of the common node voltage, significantly improving the turn-off speed of the first and second switching modules and substantially shortening the turn-off delay time. This design effectively overcomes the speed bottleneck of traditional solutions, greatly improving the overall switching frequency of the multiplexer and the real-time response of the system, meeting the requirements of next-generation battery management systems for high-frequency, real-time voltage sampling. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic block diagram of a gating circuit provided in one embodiment of this application;

[0024] Figure 2 This is a schematic block diagram of a gating circuit provided in another embodiment of this application;

[0025] Figure 3 This is a circuit connection diagram of a gating circuit provided in an embodiment of this application;

[0026] Figure 4 This is a schematic diagram of the circuit connection of two gating circuits provided in an embodiment of this application;

[0027] Figure 5 This is a circuit connection diagram of a gating circuit provided in another embodiment of this application;

[0028] Figure 6 This is a waveform diagram of a clock signal provided in an embodiment of this application.

[0029] In the figure, 101 is the first switch module; 102 is the second switch module; 103 is the voltage generation module; 104 is the first current generation module; 105 is the second current generation module; 1051 is the current generation unit; and 1052 is the current mirror unit. Detailed Implementation

[0030] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0031] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0032] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0033] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0034] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0036] Currently, mainstream multiplexer gating schemes in the industry typically employ a "back-to-back high-voltage PMOS transistor and gate bias resistor" topology. The core design idea is to use the bias resistor in conjunction with a global gate pull-down circuit, utilizing the IR voltage drop generated across the bias resistor by the pull-down current to drive the PMOS transistor to conduct, thereby achieving the gating and transmission of battery voltage. However, due to the inherent parasitic capacitance of the PMOS transistor's gate, and the need to balance high-voltage isolation and bias current stability in the value of the bias resistor, the RC charging and discharging circuit formed by these two components has a large time constant. During the switch-off phase, the charge on the gate capacitance needs to be slowly charged through the bias resistor, and the gate potential cannot quickly recover to the high-level state required for turn-off.

[0037] To address the aforementioned issues, the gating circuit provided in this application includes a first switch module, a second switch module, a voltage generation module, a first current generation module, and a second current generation module. When the first clock signal is a first-level signal and the second clock signal is a second-level signal, the first current generation module generates a first current based on the first-level signal, and the voltage generation module generates a first voltage based on the first current, transmitting the first voltage to the common node. Both the first and second switch modules are turned on based on the voltage of the common node, enabling the battery output voltage to be stably transmitted to the battery output bus and simultaneously transmitted to the switch common bus. When the first clock signal is a third-level signal and the second clock signal is a fourth-level signal, the second current generation module generates a second current based on the second clock signal. This second current forms a fast charging path from the common terminal of the first switch module and the voltage generation module to the common node, significantly increasing the rise slope of the common node voltage and accelerating the charging process of the gate capacitor connected at the common node, allowing the common node voltage to be rapidly established. Under this effect, the first and second switch modules can be quickly turned off, disconnecting the connection between the battery's positive terminal and the battery output bus and the switch common bus.

[0038] Therefore, the selection circuit provided in this application embodiment, through the synergistic effect of the first current generation module and the voltage generation module, provides a stable driving voltage for the switching module to turn on, ensuring the accuracy of voltage transmission. Simultaneously, addressing the slow turn-off problem caused by passive charging and discharging of resistors in traditional solutions, a second current generation module is innovatively introduced. This module actively injects a second current to accelerate the rise of the common node voltage, significantly improving the turn-off speed of the first and second switching modules and substantially shortening the turn-off delay time. This design effectively overcomes the speed bottleneck of traditional solutions, greatly improving the overall switching frequency of the multiplexer and the real-time response of the system, meeting the requirements of next-generation battery management systems for high-frequency, real-time voltage sampling.

[0039] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0040] Figure 1 A schematic block diagram of a gating circuit according to an embodiment of this application is shown. See also... Figure 1 As shown, the selection circuit includes a first switch module 101, a second switch module 102, a voltage generation module 103, a first current generation module 104, and a second current generation module 105. The second switch module 102 is electrically connected to the first switch module 101, the voltage generation module 103, the first current generation module 104, and the second current generation module 105, respectively. The voltage generation module 103 is electrically connected to the first current generation module 104 and the second current generation module 105, respectively. Both the first switch module 101 and the second switch module 102 are used to be electrically connected to the positive terminal of the battery. The first switch module 101 is used to be electrically connected to the battery output bus, and the second switch module 102 is used to be electrically connected to the switch common bus.

[0041] Specifically, the first current generation module 104 receives the first clock signal CLK1, and the second current generation module 105 receives the second clock signal CLK2. When the first clock signal CLK1 is a first level signal (e.g., a high level signal) and the second clock signal CLK2 is a second level signal (e.g., a low level signal), the first current generation module 104 generates a first current based on the first level signal, and the voltage generation module 103 generates a first voltage based on the first current, and transmits the first voltage to the common node. The first switch module 101 and the second switch module 102 are both turned on based on the voltage of the common node, so that the voltage output by the battery can be stably transmitted to the battery output bus, and simultaneously transmitted to the switch common bus. When the first clock signal CLK1 is a third-level signal (e.g., a low-level signal) and the second clock signal CLK2 is a fourth-level signal (e.g., a high-level signal), the second current generation module 105 generates a second current according to the second clock signal CLK2. This second current forms a fast charging path from the common terminal of the first switch module 101 and the voltage generation module 103 to the common node, significantly increasing the rise slope of the common node voltage and accelerating the charging process of the gate capacitor connected at the common node, thus enabling the common node voltage to be established rapidly. Under this effect, the first switch module 101 and the second switch module 102 can be quickly turned off, disconnecting the connection between the positive terminal of the battery and the battery output bus and the switch common bus.

[0042] Therefore, the selection circuit provided in this embodiment provides a stable driving voltage for the switching module to turn on through the synergistic effect of the first current generation module 104 and the voltage generation module 103, ensuring the accuracy of voltage transmission. Simultaneously, addressing the slow turn-off problem caused by passive charging and discharging of resistors in traditional solutions, a second current generation module 105 is innovatively introduced. This module actively injects a second current to accelerate the rise of the common node voltage, significantly improving the turn-off speed of the first switching module 101 and the second switching module 102, and significantly shortening the turn-off delay time. This design effectively overcomes the speed bottleneck of traditional solutions, greatly improving the overall switching frequency of the multiplexer and the real-time response of the system, and can meet the requirements of next-generation battery management systems for high-frequency, real-time voltage sampling.

[0043] It should be noted that the above-mentioned gating circuit can serve as the core channel unit of the multiplexer. Multiple gating circuits constitute a multiplexer. In each gating circuit, the first switch module 101 and the second switch module 102 are electrically connected to the positive terminal of the corresponding single battery cell, forming multiple independent battery voltage input terminals VIN of the multiplexer, enabling individual gating and adaptation for each battery cell. The second switch module 102 in each gating circuit is electrically connected to the switch common bus VPUB, forming a globally unified isolation potential reference bus. The first switch module 101 in each gating circuit is electrically connected to the battery output bus, forming a unified voltage output terminal VOUT of the multiplexer, used to transmit the selected single battery cell voltage to subsequent sampling units such as analog-to-digital converters.

[0044] In one embodiment of this application, such as Figure 2 As shown, the second current generating module 105 includes a current generating unit 1051 and a current mirror unit 1052. The current mirror unit 1052 is electrically connected to the current generating unit 1051, the voltage generating module 103, the first switch module 101, the second switch module 102, and the first current generating module 104.

[0045] Specifically, the current generation unit 1051 generates a stable reference current when the second clock signal CLK2 is the fourth level signal (high level signal), and the current mirror unit 1052 generates a second current by mirroring the reference current. The second current can be quickly injected into the common node to provide sufficient drive for the rapid rise of the voltage of the common node, thereby realizing the rapid turn-off of the first switch module 101 and the second switch module 102.

[0046] The following is combined with Figures 3 to 6 The circuit diagram and clock signal waveform diagram shown herein provide a detailed description of the working principle of the gating circuit provided in the embodiments of this application.

[0047] In one embodiment of this application, such as Figure 3 As shown, the first switching module 101 includes a first switching transistor DMP3 and a second switching transistor DMP4. The gate of the first switching transistor DMP3 and the gate of the second switching transistor DMP4 are electrically connected to the second switching module 102, the voltage generation module 103 and the first current generation module 104, respectively. The drain of the first switching transistor DMP3 is electrically connected to the positive terminal of the battery, the source of the first switching transistor DMP3 is electrically connected to the source of the second switching transistor DMP4, and the drain of the second switching transistor DMP4 is electrically connected to the battery output bus.

[0048] Specifically, the first switching module 101 consists of a first switching transistor DMP3 and a second switching transistor DMP4 with their sources coupled together. Their gates share a common gate drive signal (the voltage of the common node). The drain of the first switching transistor DMP3 is connected to the positive terminal of the corresponding single battery cell, serving as the battery voltage input terminal. The drain of the second switching transistor DMP4 is connected to the battery output bus, serving as the voltage output terminal. When both the first switching transistor DMP3 and the second switching transistor DMP4 are turned on, stable transmission of the selected battery voltage from the battery positive terminal to the battery output bus can be achieved. Simultaneously, the cooperative working characteristics of the two switching transistors enhance the anti-interference capability and reliability of the voltage transmission path, providing an accurate battery voltage signal for subsequent sampling units.

[0049] It should be noted that both the first switching transistor DMP3 and the second switching transistor DMP4 have built-in parasitic body diodes. The conduction characteristics of the body diodes determine the unidirectional nature of voltage transmission. Even when the first switching transistor DMP3 is off, the voltage output from the battery can still be conducted to its source through the body diode of the first switching transistor DMP3. However, the voltage can only stop at the source node where the two transistors are coupled. Only when the second switching transistor DMP4 is turned on under the action of the gate drive signal can the battery voltage at the source node be successfully transmitted to the battery output bus through the conduction channel of the second switching transistor DMP4. This achieves effective selection and output of the battery voltage, further ensuring the controllability of voltage transmission and avoiding accidental leakage or signal crosstalk in the non-selected state.

[0050] For example, designers can select the types of the first switching transistor DMP3 and the second switching transistor DMP4 according to the actual situation, that is, they can use fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For example, both the first switching transistor DMP3 and the second switching transistor DMP4 can be selected as PMOS transistors.

[0051] It should be noted that the embodiments provided in this application only show one circuit structure as the first switch module 101, and do not mean that only this one circuit structure can realize the function of the first switch module 101. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0052] In one embodiment of this application, such as Figure 3 As shown, the second switch module 102 includes a third switch transistor DMP1 and a fourth switch transistor DMP2. The gates of the third switch transistor DMP1 and the fourth switch transistor DMP2 are electrically connected to the first switch module 101, the voltage generation module 103, and the first current generation module 104, respectively. The drain of the third switch transistor DMP1 is electrically connected to the positive terminal of the battery. The source of the third switch transistor DMP1 is electrically connected to the source of the fourth switch transistor DMP2 and the voltage generation module 103, respectively. The drain of the fourth switch transistor DMP2 is electrically connected to the switch common bus.

[0053] Specifically, the second switching module 102 consists of a third switch DMP1 and a fourth switch DMP2 with their sources coupled together. Their gates share a common gate drive signal (the voltage of the common node). The drain of the third switch DMP1 is connected to the positive terminal of the corresponding single battery cell, serving as the battery voltage input terminal. The drain of the fourth switch DMP2 is connected to the common bus of the switch, serving as the potential reference transmission terminal. When both the third switch DMP1 and the fourth switch DMP2 are turned on, stable transmission of the selected battery voltage from the battery positive terminal to the common bus of the switch can be achieved, providing a unified isolation potential reference for the global non-selected channels. Simultaneously, the cooperative working characteristics of the two switches enhance the stability of potential transmission and the ability to resist crosstalk. Together with the first switching module 101, this achieves the dual functions of battery voltage selection and channel isolation, ensuring system reliability during multi-channel switching.

[0054] It should be noted that both the third switch DMP1 and the fourth switch DMP2 have built-in parasitic body diodes. The conduction characteristics of the body diodes determine the unidirectional nature of voltage transmission. Even when the third switch DMP1 is off, the voltage output from the battery can still be conducted to its source through the body diode of the third switch DMP1. However, the voltage can only stop at the source node where the two switches are coupled. Only when the fourth switch DMP2 is turned on under the action of the gate drive signal can the battery voltage at the source node be successfully transmitted to the switch common bus through the conduction channel of the fourth switch DMP2. This further ensures the controllability of voltage transmission and avoids accidental leakage or signal crosstalk in the non-selected state.

[0055] For example, designers can select the types of the third switch DMP1 and the fourth switch DMP2 according to the actual situation, that is, they can use fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For example, both the third switch DMP1 and the fourth switch DMP2 can be selected as PMOS transistors.

[0056] It should be noted that the embodiments provided in this application only show one circuit structure as the second switch module 102, and do not mean that only this one circuit structure can realize the function of the second switch module 102. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0057] Another drawback of existing technology is that the voltage of a single cell can reach tens of volts after multiple cells are connected in series, and there are dynamic fluctuations and line noise. Unselected channels need to maintain extremely high isolation to prevent safety hazards such as voltage sampling distortion, charge crosstalk between battery nodes, or even local short circuits caused by leakage current or mis-conduction.

[0058] The gating circuit provided in this application, due to the presence of the fourth switch DMP2, ensures that when the voltage of the selected battery cell is greater than the voltage of the unselected battery cell, the first switch DMP3, the second switch DMP4, the third switch DMP1, and the fourth switch DMP2 in the gating circuit corresponding to the selected battery cell are all turned on, transmitting the voltage of the selected battery cell to the switch common bus. The voltage (high potential) of the switch common bus can be transmitted to the source and common node of the fourth switch DMP2 in the gating circuit corresponding to the unselected battery cell through the body diode, thereby pulling up the voltage of the common node of the gating circuit corresponding to the unselected battery cell to a level close to the voltage level of the selected battery cell. This causes the gate-source voltage difference (VGS) between the two switches to fail to meet the turn-on threshold requirement, thus reliably turning them off. This effectively isolates the unselected battery cell from the selected battery cell and other battery nodes, avoiding the risk of charge crosstalk or leakage between batteries with different potentials. Furthermore, since the drains of the second switching transistors DMP4 in all the gating circuits are connected together, when the voltage of the battery output bus is the voltage of the selected battery cell, the source potential of the first switching transistor DMP3 in the gating circuit corresponding to the non-selected battery cell is the voltage of the non-selected battery cell, and the source potential of the second switching transistor DMP4 is close to the voltage level of the selected battery cell (due to the conduction characteristics of the body diode). Therefore, the gate potential (i.e., the voltage of the common node) must be increased to ensure that the first switching transistor DMP3 will not conduct, thus preventing leakage.

[0059] It should be noted that when the voltage of the selected battery cell is less than the voltage of the non-selected battery cell, since the voltage of the non-selected battery cell is inherently higher than the voltage of the selected battery cell, the voltage of the common node in the selection circuit corresponding to the non-selected battery cell is greater than the voltage level of the selected battery cell. Therefore, the body diodes of the second switch DMP4 and the fourth switch DMP2 in the selection circuit corresponding to the non-selected battery cell are both reverse biased, so there is no need to worry about leakage.

[0060] For example, such as Figure 4 As shown, the voltage of VC4 is greater than the voltage of VC3. If VC4 is turned on, VC3 needs to be turned off. When VC4 is turned on, all four switches corresponding to VC4 are turned on. At this time, VOUT is equal to the voltage of VC4, and VPUB is equal to the voltage of VC4. Since the drain of the fourth switch DMP2 corresponding to VC4 is connected to the drain of the fourth switch DMP2 corresponding to VC3, the voltage of VPUB can be transmitted to the source and common node through the body diode of the fourth switch DMP2 corresponding to VC3 (transmitted to the common node through the voltage generation module 103). This makes the source voltage of the fourth switch DMP2 corresponding to VC3 and the voltage of the common node close to the voltage level of VC4. This forces the gate-source voltage difference (VGS) of the first switch DMP3 and the third switch DMP1 corresponding to VC3 to be maintained in a safe range that is close to zero or even positive, and absolutely cannot be turned on. This physically eliminates any possibility that VGS will reach the turn-on threshold due to noise or crosstalk. This is an active, global isolation hardening, rather than a traditional passive defense.

[0061] In one embodiment of this application, such as Figure 3 As shown, the voltage generation module 103 includes a first transistor PM1, a second transistor PM2, and a third transistor PM3. The source of the first transistor PM1 is electrically connected to the second switching module 102. The gate of the first transistor PM1 is electrically connected to the drain of the first transistor PM1 and the source of the second transistor PM2. The source of the third transistor PM3 is electrically connected to the drain of the second transistor PM2 and the gate of the second transistor PM2. The drain of the third transistor PM3 is electrically connected to the first current generation module 104 and the second current generation module 105.

[0062] Specifically, the voltage generation module 103 consists of a first transistor PM1, a second transistor PM2, and a third transistor PM3 connected in series in a diode configuration. Through this diode-connected topology, under the influence of the first current provided by the first current generation module 104, the module utilizes the superposition effect of the gate-source voltages (VGS) when the transistors are turned on to generate a stable voltage drop (total voltage drop of 3*VGS). The module then calculates the first voltage, VIN - 3*VGS, and transmits this first voltage to the common node. This provides a precise and stable gate drive bias for the synchronous turn-on of the first switching module 101 and the second switching module 102. Simultaneously, the series connection of the three transistors enhances the robustness of the bias voltage to process fluctuations and environmental changes, ensuring the stability and accuracy of the voltage transmission process.

[0063] For example, designers can select the types of the first transistor PM1, the second transistor PM2, and the third transistor PM3 according to the actual situation; that is, they can use fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For instance, the first transistor PM1, the second transistor PM2, and the third transistor PM3 can all be selected as PMOS transistors.

[0064] It should be noted that VGS is determined by the first current I1 and the transistor's WL, that is, the absolute value of VGS is:

[0065]

[0066] in, c is the hole mobility in the PMOS transistor. ox V is the capacitance per unit area of ​​the gate oxide layer, W / L is the width-to-length ratio of the PMOS transistor, and V is the capacitance per unit area of ​​the gate oxide layer. THP This is the threshold voltage of the PMOS transistor.

[0067] It should be noted that the embodiments provided in this application only show one circuit structure as the voltage generation module 103, and do not represent that only this one circuit structure can realize the function of the voltage generation module 103. Other circuit structures that can realize this function can also be substituted, and are not limited to this. In addition, other numbers of transistors can be used to form the voltage generation module 103, and Zener diodes can be used to replace the three transistors mentioned above. At the same time, the third transistor PM3 can be replaced with the output terminal of the cascode current mirror. By utilizing the high output impedance characteristics of the cascode current mirror, the bias branch current can be stabilized, and the anti-interference capability of the reference voltage drop to process and temperature changes can be improved. The specific implementation architecture of the voltage generation module 103 is not limited here.

[0068] In one embodiment of this application, such as Figure 5 As shown, the voltage generation module 103 also includes a first resistor R1, the first end of which is electrically connected to the source of the first transistor PM1, and the second end of which is electrically connected to the drain of the third transistor PM3.

[0069] Specifically, the first resistor R1 is used to establish a deterministic DC potential for the bias node, avoiding bias voltage drift caused by process fluctuations, temperature changes, and other factors. This significantly enhances the robustness of the output bias voltage of the voltage generation module 103 to process and environmental changes, ensuring a stable voltage drop output of three times VGS. Furthermore, the first resistor R1 provides an additional current path, accelerating the charging and discharging process during gate potential switching, effectively improving the establishment speed of the common node potential, further optimizing the switching response efficiency of the gating circuit, and simultaneously helping to suppress high-frequency noise interference to the bias node, ensuring the stability of the gate drive signal, and providing reliable support for the precise on / off control of the first switching module 101 and the second switching module 102.

[0070] In one embodiment of this application, such as Figure 5 As shown, the first current generation module 104 includes a fifth switch transistor DMN1 and a first current source. The gate of the fifth switch transistor DMN1 is used to receive the first clock signal CLK1. The drain of the fifth switch transistor DMN1 is electrically connected to the voltage generation module 103, the first switch module 101 and the second switch module 102 respectively. The source of the fifth switch transistor DMN1 is electrically connected to the first terminal of the first current source, and the second terminal of the first current source is grounded.

[0071] Specifically, when the first clock signal CLK1 is high, the fifth switch DMN1 is turned on, and the constant current (first current) output by the first current source flows into the voltage generation module 103 through the turned-on fifth switch DMN1, providing it with a stable bias current. When the first clock signal CLK1 is low, the fifth switch DMN1 is turned off, the current path of the first current source is cut off, and the bias current of the voltage generation module 103 is terminated. This, in conjunction with the subsequent action of the second current generation module 105, achieves the turn-off control of the switching module. Through the clock-controlled characteristics of the fifth switch DMN1 and the constant current output characteristics of the first current source, this module achieves both precise timing control of the bias current and ensures the current stability of the voltage generation module 103, ensuring reliable voltage generation at the common node during the turn-on phase of the selection circuit.

[0072] For example, designers can select the type of the fifth switch DMN1 according to the actual situation, that is, it can be a fully controllable power device such as a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor. For example, the fifth switch DMN1 can be selected as an NMOS transistor.

[0073] It should be noted that the embodiments provided in this application only show one circuit structure as the first current generating module 104, and do not mean that only this one circuit structure can realize the function of the first current generating module 104. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0074] In one embodiment of this application, such as Figure 5 As shown, the current generating unit 1051 includes a sixth switch DMN2 and a second current source. The gate of the sixth switch DMN2 is used to receive the second clock signal CLK2. The drain of the sixth switch DMN2 is electrically connected to the current mirror unit 1052. The source of the sixth switch DMN2 is electrically connected to the first terminal of the second current source. The second terminal of the second current source is grounded.

[0075] Specifically, when the second clock signal CLK2 is high, the sixth switch DMN2 is turned on, and the constant reference current output by the second current source is transmitted to the current mirror unit 1052 through the turned-on sixth switch DMN2, providing the current mirror unit 1052 with a precise current replication reference. When the second clock signal CLK2 is low, the sixth switch DMN2 is turned off, the reference current transmission path is cut off, and the current generation unit 1051 stops working. Through the clock-controlled on / off state of the sixth switch DMN2 and the constant current output characteristic of the second current source, this unit achieves precise timing control and stable output of the reference current, providing a reliable basis for the current mirror unit 1052 to generate the second current, thereby ensuring the high-speed turn-off function of the first switch module 101 and the second switch module 102.

[0076] For example, designers can select the type of the sixth switch DMN2 according to the actual situation, that is, it can be a fully controllable power device such as a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor. For example, the sixth switch DMN2 can be selected as an NMOS transistor.

[0077] In one embodiment of this application, such as Figure 5 As shown, the current mirror unit 1052 includes a fourth transistor PM4 and a fifth transistor PM5. The gate of the fourth transistor PM4 is electrically connected to the gate of the fifth transistor PM5, the drain of the fourth transistor PM4, and the current generating unit 1051, respectively. The source of the fourth transistor PM4 and the source of the fifth transistor PM5 are both electrically connected to the second switching module 102 and the voltage generating module 103, respectively. The drain of the fifth transistor PM5 is electrically connected to the voltage generating module 103, the first switching module 101, the second switching module 102, and the first current generating module 104, respectively.

[0078] Specifically, the current mirror unit 1052 consists of a fourth transistor PM4 and a fifth transistor PM5 with a mirror-symmetric structure. Through the transistor mirror principle, it accurately replicates the reference current output by the current generation unit 1051, generating a second current in a fixed proportion to the reference current. The fourth transistor PM4 serves as a reference transistor, receiving and conducting the reference current to provide a stable reference for mirror replication. The fifth transistor PM5 acts as an output transistor, injecting the replicated second current into the common node, rapidly charging the gate capacitor to raise the common node voltage, ensuring high-speed turn-off of the first switching module 101 and the second switching module 102. Simultaneously, the mirror structure ensures the stability and accuracy of the second current. Combined with the collaborative work of the two transistors, this guarantees the reliability of the turn-off drive and enhances the circuit's adaptability to process fluctuations and environmental changes, ensuring high-speed switching of the selection circuit.

[0079] It should be noted that the rise rate of the common node voltage depends on the current and capacitance. The gate capacitance includes all parasitic capacitances connected to the gate node. Without the presence of the fifth transistor PM5, under normal circumstances, after the switching transistors (first switching transistor DMP3, second switching transistor DMP4, third switching transistor DMP1, and fourth switching transistor DMP2) are turned off, the voltage of the common node can only be gradually increased through the first transistor PM1, the second transistor PM2, and the third transistor PM3, and the current becomes smaller and smaller, resulting in a very slow voltage rise. Because of the added channel of the fifth transistor PM5, by setting an appropriate pulse width of the second clock signal CLK2, the voltage of the common node can be increased more quickly, allowing the switching transistors to be turned off in time.

[0080] It should be noted that, as Figure 6 As shown, the first clock signal CLK1 and the second clock signal CLK2 are inverted signals. When the first clock signal CLK1 is high, the second clock signal CLK2 is low; when the first clock signal CLK1 is low, the second clock signal CLK2 is high.

[0081] For example, designers can select the types of the fourth transistor PM4 and the fifth transistor PM5 according to the actual situation, that is, they can use fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For example, both the fourth transistor PM4 and the fifth transistor PM5 can be selected as PMOS transistors.

[0082] For example, designers can select the value of the reference current according to the actual situation. For instance, the reference current can be selected as 10 times the first current.

[0083] It should be noted that the embodiments provided in this application only show one circuit structure as the second current generating module 105, and do not mean that only this one circuit structure can realize the function of the second current generating module 105. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0084] Through the aforementioned circuit design and parameter selection, this application constructs an active fast charging path from the source of the third switch DMP1 to the common node. This path can actively and rapidly pull up the potential of the common node at the timing node where the switch needs to be turned off, thereby reducing the delay time of the switch turn-off process to a fraction of that of the traditional resistor pull-down scheme, successfully achieving nanosecond-level high-speed turn-off effect, and greatly improving the overall channel switching frequency and system response real-time performance of the multiplexer. Simultaneously, for adjacent battery channels with potential differences, the voltage of their common node no longer passively follows the current potential relying on a weak pull-up mechanism as in traditional schemes. Instead, it is actively pulled up to a level close to the potential of the selected battery cell through the potential reference function of the switch common bus, effectively avoiding accidental connection between battery nodes with different potentials and fundamentally eliminating the risk of leakage and mis-connection in non-selected channels.

[0085] This application also discloses a multiplexer, including multiple gating circuits as described above. By integrating multiple gating circuits, the multiplexer can achieve independent gating and high-speed switching sampling of the voltage of each battery in a multi-cell series lithium battery pack. With the active isolation mechanism of each gating circuit, the risk of leakage and false turn-on between non-gated battery channels is effectively eliminated, ensuring the accuracy and reliability of voltage sampling. At the same time, the fast turn-off characteristics of each gating circuit can significantly improve the overall channel switching frequency of the multiplexer, meeting the requirements of next-generation battery management systems for high-frequency, real-time voltage monitoring, and possessing the technical advantages of high isolation, high switching speed, and high stability.

[0086] Since the processing and functions implemented by the multiplexer in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned gating circuit, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0087] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gating circuit, characterized in that, It includes a first switch module, a second switch module, a voltage generating module, a first current generating module, and a second current generating module. The second switch module is electrically connected to the first switch module, the voltage generating module, the first current generating module, and the second current generating module. The voltage generating module is electrically connected to the first current generating module and the second current generating module. Both the first switch module and the second switch module are used to be electrically connected to the positive terminal of the battery. The first switch module is used to be electrically connected to the battery output bus, and the second switch module is used to be electrically connected to the switch common bus. The first current generating module is used to receive a first clock signal, and the second current generating module is used to receive a second clock signal. When the first clock signal is a first level signal and the second clock signal is a second level signal, the first current generating module is used to generate a first current according to the first level signal, and the voltage generating module is used to generate a first voltage according to the first current, and transmit the first voltage to a common node, where the common node is the connection point between the first switching module and the second switching module. Both the first switching module and the second switching module are used to conduct voltage according to the common node, so that the voltage output by the battery is transmitted to the battery output bus and the switch common bus. When the first clock signal is a third-level signal and the second clock signal is a fourth-level signal, the second current generation module is used to generate a second current according to the second clock signal to increase the rising slope of the voltage of the common node. Both the first switch module and the second switch module are used to turn off according to the voltage of the common node.

2. The gating circuit according to claim 1, characterized in that, The first switching module includes a first switching transistor and a second switching transistor. The gates of the first switching transistor and the second switching transistor are electrically connected to the second switching module, the voltage generation module, and the first current generation module, respectively. The drain of the first switching transistor is electrically connected to the positive terminal of the battery, the source of the first switching transistor is electrically connected to the source of the second switching transistor, and the drain of the second switching transistor is electrically connected to the battery output bus.

3. The gating circuit according to claim 1, characterized in that, The second switching module includes a third switching transistor and a fourth switching transistor. The gates of the third switching transistor and the fourth switching transistor are electrically connected to the first switching module, the voltage generation module, and the first current generation module, respectively. The drain of the third switching transistor is electrically connected to the positive terminal of the battery. The source of the third switching transistor is electrically connected to the source of the fourth switching transistor and the voltage generation module, respectively. The drain of the fourth switching transistor is electrically connected to the switch common bus. When the voltage of the selected battery cell is greater than the voltage of the non-selected battery cell, the voltage of the common bus in the selection circuit corresponding to the selected battery cell is transmitted to the source of the fourth switch and the common node through the body diode of the fourth switch in the selection circuit corresponding to the non-selected battery cell, thereby pulling up the voltage of the common node and turning off the first switch module in the selection circuit corresponding to the non-selected battery cell.

4. The gating circuit according to claim 1, characterized in that, The voltage generating module includes a first transistor, a second transistor, and a third transistor. The source of the first transistor is electrically connected to the second switching module. The gate of the first transistor is electrically connected to the drain of the first transistor and the source of the second transistor. The source of the third transistor is electrically connected to the drain of the second transistor and the gate of the second transistor. The drain of the third transistor is electrically connected to the first current generating module and the second current generating module.

5. The gating circuit according to claim 4, characterized in that, The voltage generation module further includes a first resistor, a first end of which is electrically connected to the source of the first transistor, and a second end of which is electrically connected to the drain of the third transistor.

6. The gating circuit according to claim 1, characterized in that, The first current generating module includes a fifth switching transistor and a first current source. The gate of the fifth switching transistor is used to receive the first clock signal. The drain of the fifth switching transistor is electrically connected to the voltage generating module, the first switching module, and the second switching module, respectively. The source of the fifth switching transistor is electrically connected to the first terminal of the first current source, and the second terminal of the first current source is grounded.

7. The gating circuit according to claim 1, characterized in that, The second current generating module includes a current generating unit and a current mirror unit, wherein the current mirror unit is electrically connected to the current generating unit, the voltage generating module, the first switching module, the second switching module and the first current generating module respectively; The current generating unit is used to generate a reference current when the second clock signal is a fourth level signal, and the current mirror unit is used to generate the second current according to the reference current.

8. The gating circuit according to claim 7, characterized in that, The current generating unit includes a sixth switching transistor and a second current source. The gate of the sixth switching transistor is used to receive the second clock signal. The drain of the sixth switching transistor is electrically connected to the current mirror unit. The source of the sixth switching transistor is electrically connected to the first terminal of the second current source. The second terminal of the second current source is grounded.

9. The gating circuit according to claim 7, characterized in that, The current mirror unit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is electrically connected to the gate of the fifth transistor, the drain of the fourth transistor, and the current generating unit. The source of the fourth transistor and the source of the fifth transistor are both electrically connected to the second switching module and the voltage generating module, respectively. The drain of the fifth transistor is electrically connected to the voltage generating module, the first switching module, the second switching module, and the first current generating module, respectively.

10. A multiplexer, characterized in that, The system includes multiple gating circuits as described in any one of claims 1-9, wherein the first switch module and the second switch module in each gating circuit are electrically connected to the positive terminal of the corresponding battery and serve as multiple input terminals of the multiplexer, and each first switch module is electrically connected to the battery output bus and serves as the output terminal of the multiplexer.

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