Level conversion circuit

Abstract

The invention discloses a level conversion circuit, which belongs to the technical field of level conversion, and comprises an input module for accessing a control voltage and a power supply voltage; the first conversion module is connected with a power supply voltage and a target negative voltage, a third end is connected with a third end of the input module, a fourth end is connected with a control voltage, and a voltage stabilizing unit for clamping high and low levels is arranged in the first conversion module; the second conversion module is connected with a target positive voltage and a target negative voltage, the third end of the second conversion module is connected with the fifth end of the first conversion module, the fourth end of the second conversion module is connected with the sixth end of the first conversion module, and when the control voltage is a high level, the fifth end of the first conversion module outputs a first clamping negative voltage based on the high level; and when the control voltage is at the low level, the sixth end of the first conversion module outputs the second clamping negative voltage based on the low level, and the second conversion module outputs the target negative voltage based on the second clamping negative voltage, so that the functionality of the level conversion circuit is improved.

Description

Technical Field

[0001] This application relates to the field of level conversion technology, and more particularly to level conversion circuits. Background Technology

[0002] With the increasing demand for high and low levels of various amplitudes, users are also placing higher demands on level conversion circuits.

[0003] Traditional level conversion circuits typically use a specific level conversion circuit for drive control to achieve level conversion. However, this type of level conversion circuit has a significant drawback: the amplitude of the conversion level is limited by the operating voltage range of the transistor (for example, the transistor's operating voltage range VGH-VGL≤45V, meaning that it can normally only achieve high-low level conversion with a phase difference of 45V, while high-low level conversion exceeding 45V will damage the transistor). In other words, this type of level conversion circuit suffers from limited functionality due to the limitation of the conversion level amplitude by the transistor's operating voltage range.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide a level conversion circuit, which aims to solve the technical problem of low functionality of level conversion circuits.

[0006] To achieve the above objectives, this application provides a level conversion circuit, the level conversion circuit comprising: An input module, wherein a control voltage is connected to the first terminal of the input module and a power supply voltage is connected to the second terminal of the input module; A first conversion module has a first terminal connected to the power supply voltage, a second terminal connected to the target negative voltage, a third terminal connected to the third terminal of the input module, and a fourth terminal connected to the control voltage. The first conversion module includes a voltage regulation unit to clamp high and low voltage levels. The second conversion module has a first terminal connected to the target positive voltage, a second terminal connected to the target negative voltage, a third terminal connected to the fifth terminal of the first conversion module, and a fourth terminal connected to the sixth terminal of the first conversion module. When the control voltage is high, the fifth terminal of the first conversion module outputs a first clamping negative voltage based on the high level, and the second conversion module outputs the target positive voltage based on the first clamping negative voltage. When the control voltage is low, the sixth terminal of the first conversion module outputs a second clamping negative voltage based on the low level, and the second conversion module outputs the target negative voltage based on the second clamping negative voltage.

[0007] In one embodiment, the input module includes: A first transistor, the control terminal of the first transistor is connected to the control voltage, and the second terminal of the first transistor is grounded; A first resistor, the first end of which is connected to the power supply voltage, and the second end of which is connected to the first end of the first transistor and the third end of the first conversion module.

[0008] In one embodiment, the first conversion module includes: The second transistor has its control terminal connected to the control voltage and its second terminal connected to the power supply voltage. The third transistor has its control terminal connected to the second terminal of the first resistor in the input module, and the second terminal of the third transistor is connected to the power supply voltage. The second resistor has its first end connected to the first end of the third transistor, and its second end connected to the first end of the voltage regulator unit. A third resistor, wherein the first end of the third resistor is connected to the first end of the third transistor; A fourth resistor, the first end of which is connected to the first end of the second transistor, and the second end of which is connected to the second end of the voltage regulator unit; The fifth resistor, the first end of which is connected to the first end of the second transistor; The fourth transistor, the first terminal of which is connected to the second terminal of the fifth resistor, and the second terminal of the fourth transistor is connected to the target negative voltage; The sixth resistor has its first end connected to the control terminal of the fourth transistor, and its second end connected to the first end of the second resistor. The fifth transistor has its first terminal connected to the second terminal of the third resistor, and the second terminal of the fifth transistor is connected to the target negative voltage. The seventh resistor has its first end connected to the control terminal of the fifth transistor, and its second end connected to the second end of the fourth resistor. The eighth resistor has its first end connected to the first end of the second resistor and its second end connected to the third end of the second conversion module. The ninth resistor has its first end connected to the second end of the fourth resistor, and its second end connected to the fourth end of the second conversion module.

[0009] In one embodiment, the voltage regulator unit includes: The first Zener diode has its cathode connected to the second terminal of the second resistor, and its anode connected to the target negative voltage. The second Zener diode has its cathode connected to the second terminal of the fourth resistor, and its anode connected to the target negative voltage.

[0010] In one embodiment, the first conversion module further includes: A first diode, wherein the anode of the first diode is connected to the second terminal of the second resistor, and the cathode of the first diode is connected to the first terminal of the second resistor; The second diode has its anode connected to the second terminal of the fourth resistor, and its cathode connected to the first terminal of the fourth resistor.

[0011] In one embodiment, the second conversion module includes: A level shifting unit, wherein the first end of the level shifting unit is connected to the target positive voltage, the second end of the level shifting unit is connected to the target negative voltage, and the third end of the level shifting unit is connected to the second end of the eighth resistor in the first conversion module; A complementary output unit, wherein the first terminal of the complementary output unit is connected to the target positive voltage, the second terminal of the complementary output unit is connected to the target negative voltage, the third terminal of the complementary output unit is connected to the second terminal of the ninth resistor in the first conversion module, and the fourth terminal of the complementary output unit is connected to the fourth terminal of the level shifting unit.

[0012] In one embodiment, the level shifting unit includes: The tenth resistor, the first end of which is connected to the target positive voltage; The eleventh resistor, wherein the first end of the eleventh resistor is connected to the second end of the tenth resistor; The first transistor has its first terminal connected to the second terminal of the eleventh resistor, and its third terminal connected to the second terminal of the eighth resistor. The twelfth resistor has its first end connected to the second end of the first transistor, and its second end is connected to the target negative voltage. The thirteenth resistor, wherein the first end of the thirteenth resistor is connected to the second end of the tenth resistor; The second transistor has its first terminal connected to the target positive voltage, and its third terminal connected to the second terminal of the thirteenth resistor. The third transistor, the second terminal of which is connected to the second terminal of the second transistor, and the third terminal of which is connected to the second terminal of the thirteenth resistor; The fourteenth resistor, the first end of which is connected to the second end of the second transistor, and the second end of which is connected to the fourth end of the complementary output unit; The fifteenth resistor has its first end connected to the first end of the third transistor, and its second end connected to the target negative voltage.

[0013] In one embodiment, the complementary output unit includes: The sixth transistor, the control terminal of which is connected to the second terminal of the fourteenth resistor in the level shifting unit, and the second terminal of the sixth transistor is connected to the target positive voltage; The seventh transistor has its first terminal serving as the output terminal of the complementary output unit and connected to the first terminal of the sixth transistor. The second terminal of the seventh transistor is connected to the target negative voltage, and the control terminal of the seventh transistor is connected to the second terminal of the ninth resistor.

[0014] In one embodiment, the complementary output unit further includes: The third diode has its anode connected to the control terminal of the sixth transistor, and its cathode connected to the target positive voltage.

[0015] In one embodiment, the complementary output unit further includes: The fourth diode has its anode connected to the second terminal of the ninth resistor and its cathode connected to the control terminal of the seventh transistor. The fourth transistor has its second terminal connected to the target negative voltage, its second terminal connected to the cathode of the fourth diode, and its third terminal connected to the anode of the fourth diode.

[0016] This application proposes a level conversion circuit, which optimizes the circuit to provide a level conversion circuit comprising: an input module, a first conversion module, and a second conversion module. A voltage regulator unit is included in the first conversion module to clamp high and low levels, preventing the amplitude of the conversion level from being limited by the transistor's operating voltage range. Specifically, by combining the above modules, when the control voltage is high, the fifth terminal of the first conversion module outputs a first clamping negative voltage based on the high level, and the second conversion module outputs a target positive voltage based on the first clamping negative voltage. When the control voltage is low, the sixth terminal of the first conversion module outputs a second clamping negative voltage based on the low level, and the second conversion module outputs a target negative voltage based on the second clamping negative voltage. In this way, the first and second clamping negative voltages reduce the actual operating voltage of the transistor, avoiding the problem of the transistor's operating voltage range affecting the amplitude of the conversion level, thereby improving the functionality of the level conversion circuit. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a functional module diagram of an embodiment of the level conversion circuit of this application; Figure 2 This is a circuit connection diagram of a level conversion circuit; Figure 3 This is a circuit connection diagram of the first embodiment of the level conversion circuit of this application; Figure 4 This is a control schematic diagram of an embodiment of the level conversion circuit of this application; Figure 5 This is a control schematic diagram of yet another embodiment of the level conversion circuit of this application; Figure 6 This is a circuit connection diagram of the second embodiment of the level conversion circuit of this application; Figure 7 This is a waveform diagram of the first embodiment of the level conversion circuit of this application; Figure 8This is yet another waveform diagram of the first embodiment of the level conversion circuit of this application; Figure 9 This is a waveform diagram of a second embodiment of the level conversion circuit of this application; Figure 10 This is a circuit connection diagram of a third embodiment of the level conversion circuit of this application; Figure 11 This is another circuit connection diagram of the third embodiment of the level conversion circuit of this application; Figure 12 This is a waveform diagram of the third embodiment of the level conversion circuit of this application; Figure 13 This is a schematic diagram of the structure of the liquid crystal display panel involved in the embodiments of this application.

[0019] Explanation of icon numbers: VIN, Control Voltage; V0, Output Voltage; VDD, Power Supply Voltage; 10, Input Module; 20, First Conversion Module; 30, Second Conversion Module; VGH, Target Positive Voltage; VGL, Target Negative Voltage; R1, First Resistor; M1, First Transistor; M2, Second Transistor; M3, Third Transistor; M4, Fourth Transistor; M5, Fifth Transistor; R2, Second Resistor; R3, Third Resistor; R4, Fourth Resistor; R5, Fifth Resistor; R6, Sixth Resistor; R7, Seventh Resistor; R8, Eighth Resistor; R9, Ninth Resistor; 21, Voltage Regulator Unit; D1, First Zener Diode; D2 1. Second Zener diode; R10. Tenth resistor; R11. Eleventh resistor; R12. Twelfth resistor; R13. Thirteenth resistor; R14. Fourteenth resistor; R15. Fifteenth resistor; Q1. First transistor; Q2. Second transistor; Q3. Third transistor; M6. Sixth transistor; M7. Seventh transistor; RL. Output resistor; CL. Output capacitor; D3. First diode; D4. Second diode; D5. Third diode; Q4. Fourth transistor; D6. Fourth diode; 31. Level shifting unit; 32. Complementary output unit; M8. Eighth transistor; M9. Ninth transistor.

[0020] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0022] This application provides a level conversion circuit, referring to... Figure 1 , Figure 1 This is a functional module diagram of an embodiment of a level conversion circuit according to this application.

[0023] In this embodiment, the level conversion circuit includes: Input module 10, the first terminal of input module 10 is connected to control voltage VIN, and the second terminal of input module 10 is connected to power supply voltage VDD; The first conversion module 20 has a first terminal connected to the power supply voltage VDD, a second terminal connected to the target negative voltage VGL, a third terminal connected to the third terminal of the input module 10, and a fourth terminal connected to the control voltage VIN. The first conversion module 20 is equipped with a voltage regulator unit 21 to clamp the high and low levels. The second conversion module 30 has a first terminal connected to the target positive voltage VGH, a second terminal connected to the target negative voltage VGL, a third terminal connected to the fifth terminal of the first conversion module 20, and a fourth terminal connected to the sixth terminal of the first conversion module 20. When the control voltage VIN is high, the fifth terminal of the first conversion module 20 outputs a first clamping negative voltage based on the high level, and the second conversion module 30 outputs the target positive voltage VGH based on the first clamping negative voltage. When the control voltage VIN is low, the sixth terminal of the first conversion module 20 outputs a second clamping negative voltage based on the low level, and the second conversion module 30 outputs the target negative voltage VGL based on the second clamping negative voltage.

[0024] It should be noted that, taking the level conversion circuit in a traditional LCD (Liquid Crystal Display) driver as an example, the commonly used high and low levels of the GOA (Gateon Array) signal are approximately 25V / -6V, and the operating voltage range of common level conversion chips is VGH-VGL≤45V. However, taking electronic paper drivers, which require high-voltage driving, as an example, since they need to drive electrophoretic particles, the GOA signal voltage typically needs to reach ±40V. Because there are no readily available chips supporting this voltage range (the amplitude of the conversion level is limited by the operating voltage range of the transistor), it is necessary to use discrete components to build a high-voltage level conversion circuit, or to perform level conversion based on transistors with an increased operating voltage range. This increases costs. Further details can be found in... Figure 2 , Figure 2This is a circuit connection diagram of a level conversion circuit. An example is given for a scenario requiring an output swing as high as 80V, although 90V, 85V, 75V, etc., are also possible. In this case, the transistor's Vgs may exceed the device's safe range (generally ±20V), leading to breakdown and damage. As shown in the diagram, the existing level conversion circuit mainly consists of three modules. The power supply voltage VDD can be set to a 3.3V square wave, the target positive voltage VGH can be set to 40V, and the target negative voltage VGL can be set to -40V. The circuit works by receiving the input square wave signal (i.e., the control signal VIN, actually a 0V and 3.3V square wave) to control the second transistor M2, and simultaneously generating a signal with opposite phase to control the third transistor M3. The first conversion module 10 converts the low level of the square wave signal from 0V to -40V, and the second conversion module 20 converts the high level of the square wave signal from 3.3V to 40V. The following section will discuss... Figure 2 The high and low level control of the square wave signal is explained in stages.

[0025] Phase 1: When the control signal VIN is high, it controls the second transistor M2 to turn off and the third transistor M3 to turn on. Point B is high (3.3V), which in turn controls the fourth transistor M4 to turn on, and point A is low (i.e., -40V of the target negative voltage VGL). Simultaneously, the high level at point B controls the eighth transistor M8 to turn on, and the low level at point C (i.e., -40V of the target negative voltage VGL) in turn controls the seventh transistor M7 to turn on, resulting in a high output voltage Vo (40V). Simultaneously, the output voltage Vo controls the sixth transistor M6 to turn off, and the low level at point A controls the ninth transistor M9 to turn off, preventing both transistors from turning on simultaneously. Further analysis of the gate-source voltage and operating state of each transistor is shown in Table 1 below, where the Vgs (gate-source) voltage of M4 / M7 / M8 is relatively large.

[0026]

[0027] Table 1 Among them, the Vgs of M4 is 3.3 - (-40) = 43.3, the Vgs of M7 is -40 - 40 = -80, and the Vgs of M8 is 3.3 - (-40) = 43.3.

[0028] Phase Two: When the control signal VIN is low, it turns on the second transistor M2, making point A high (i.e., 3.3V of the power supply voltage VDD). This, in turn, turns on the fifth transistor M5, making point B low (i.e., -40V of the target negative voltage VGL), which in turn turns off the eighth transistor M8. Point A also simultaneously turns on the ninth transistor M9, resulting in a low output voltage Vo (-40V). Simultaneously, the output voltage Vo also controls the sixth transistor M6 to turn on, and point C high (40V) controls the seventh transistor M7 to turn off, preventing both transistors from turning on simultaneously. Further analysis of the gate-source voltage and operating state of each transistor is shown in Table 2 below. The Vgs voltages of M5 / M6 / M9 are relatively large.

[0029]

[0030] Table 2 Among them, the Vgs of M5 is 3.3 - (-40) = 43.3, the Vgs of M6 is -40 - 40 = -80, and the Vgs of M9 is 3.3 - (-40) = 43.3. Because the gate insulating layer of the transistors is relatively thin, they are easily damaged if subjected to high voltage. As analyzed above, transistors M4 / M5 / M6 / M7 / M8 / M9 all withstand high voltages and are easily damaged. Therefore, it is necessary to optimize the circuit structure, reduce the Vgs voltage of the transistors, and improve the stability of the circuit.

[0031] In this embodiment, the circuit based on the above embodiments is optimized to reduce the voltage across transistors M4 / M5 / M6 / M7 / M8 / M9 at different stages, thereby ensuring the normal operation of the entire circuit and achieving higher voltage level conversion. For example, a voltage regulator unit 21 can be set in the first conversion module 20 to clamp high and low levels; simply put, it clamps the transistor's Vgs, thereby reducing the transistor's voltage and simultaneously achieving higher voltage level conversion. For example, the voltage regulator unit 21 can clamp the transistor's Vgs within the operating voltage range. Simultaneously, when the control voltage VIN is high, the fifth terminal of the first conversion module 20 outputs a first clamping negative voltage based on a high level, and the second conversion module 30 outputs a target positive voltage VGH based on the first clamping negative voltage. Conversely, when the control voltage VIN is low, the sixth terminal of the first conversion module 20 outputs a second clamping negative voltage based on a low level, and the second conversion module 30 outputs a target negative voltage VGL based on the second clamping negative voltage. The first clamping negative voltage and the second clamping negative voltage refer to the output voltage after clamping by the voltage regulator unit 21. The specific output voltage value is related to the parameters of the relevant components inside the voltage regulator unit 21. The entire level conversion circuit can clamp high and low levels (mainly the original high and low levels of the driving transistor, such as -80, 43.3, etc. in the above embodiment) based on the voltage regulator unit 21, thereby avoiding damage to the transistor and realizing the conversion of higher levels, thus improving the functionality of the level conversion circuit.

[0032] Furthermore, referring to Figure 3 , Figure 3 This is a circuit connection diagram of the first embodiment of the level conversion circuit of this application.

[0033] like Figure 3 As shown, in some feasible embodiments, the input module 10 includes: The first transistor M1 has its control terminal connected to the control voltage VIN, and its second terminal is grounded. The first resistor R1 has its first end connected to the power supply voltage VDD, and its second end is connected to the first end of the first transistor M1 and the third end of the first conversion module 20.

[0034] In this embodiment, the input module 10 consists of a first transistor M1 and a first resistor R1. The first resistor R1 mainly provides a pull-up resistor, and the first transistor M1 mainly enables the input module 10 to output the opposite level to the first conversion module 20 under the control of the control voltage VIN. That is, the first conversion module 20 outputs the opposite level based on the conduction and cutoff of the first transistor M1. Of course, the first transistor M1 can also be other devices, such as transistors, switches, etc. For example, refer to... Figure 4 , Figure 4 This is a control schematic diagram of an embodiment of the level conversion circuit of this application. When the input module 10 is designed with the first transistor M1, if a high level is supplied to the control terminal of the first transistor M1, then the second terminal of the first resistor R1 is grounded, which is also the third terminal of the first conversion module 20 is grounded. Since one terminal of the first conversion module 20 is directly connected to the control voltage VIN, this achieves the opposite output level to the first conversion module 20. For example, refer to... Figure 5 , Figure 5 This is a control diagram of another embodiment of the level conversion circuit of this application. If a low level is supplied to the control terminal of the first transistor M1, the second terminal of the first resistor R1 is connected to the power supply voltage VDD, which means the third terminal of the first conversion module 20 is also connected to the power supply voltage VDD. One terminal of the first conversion module 20 is directly connected to the control voltage VIN, thus achieving an opposite output level. Furthermore, the first conversion module 20 is controlled based on each given opposite level. Because the first conversion module 20 is equipped with a voltage regulator unit 21 to clamp the high and low levels, it can achieve the output of a target negative voltage VGL or a target positive voltage VGH while limiting the gate-source voltage of the transistor. This ensures the overall lifespan of the circuit while expanding its functionality in high-level conversion scenarios.

[0035] Furthermore, in some feasible embodiments, the first conversion module 20 includes: The second transistor M2 has its control terminal connected to the control voltage VIN and its second terminal connected to the power supply voltage VDD. The control terminal of the third transistor M3 is connected to the second terminal of the first resistor R1 in the input module 10, and the second terminal of the third transistor M3 is connected to the power supply voltage VDD. The second resistor R2 has its first end connected to the first end of the third transistor M3 and its second end connected to the first end of the voltage regulator unit 21. The third resistor R3, the first end of which is connected to the first end of the third transistor M3; The fourth resistor R4 has its first end connected to the first end of the second transistor M2, and its second end connected to the second end of the voltage regulator unit 21. The fifth resistor R5, the first terminal of the fifth resistor R5 is connected to the first terminal of the second transistor M2; The fourth transistor M4 has its first terminal connected to the second terminal of the fifth resistor R5, and the second terminal of the fourth transistor M4 is connected to the target negative voltage VGL. The sixth resistor R6 has its first end connected to the control terminal of the fourth transistor M4, and its second end connected to the first end of the second resistor R2. The fifth transistor M5 has its first terminal connected to the second terminal of the third resistor R3, and its second terminal is connected to the target negative voltage VGL. The seventh resistor R7 has its first end connected to the control terminal of the fifth transistor M5, and its second end connected to the second end of the fourth resistor R4. The eighth resistor R8 has its first end connected to the first end of the second resistor R2, and its second end connected to the third end of the second conversion module 30. The ninth resistor R9 has its first end connected to the second end of the fourth resistor R4, and its second end connected to the fourth end of the second conversion module 30.

[0036] Furthermore, the voltage regulator unit 21 includes: The first Zener diode D1 has its cathode connected to the second terminal of the second resistor R2, and its anode connected to the target negative voltage VGL. The second Zener diode D2 has its cathode connected to the second terminal of the fourth resistor R4, and its anode connected to the target negative voltage VGL.

[0037] In this embodiment, the first conversion module 20 can be configured as described above. Of course, other equivalent devices can be used to replace the above-described components, such as directly replacing the transistor with a switch, or replacing the resistor with an adjustable resistor. Alternatively, current-limiting or voltage-limiting protection devices or circuits can be added to the connection circuit between the resistor and the transistor to protect the transistor. For example, the voltage regulator unit 21 includes two Zener diodes, which can clamp the voltage of the two transistors to protect them. Other voltage-limiting or clamping instruments can also be used, and are not limited here. For example, refer to... Figure 3 By adding Zener diodes and current-limiting resistors at critical nodes (such as points A and B), high and low voltage levels are clamped, significantly reducing the stress on the driver transistor Vgs and preventing high-voltage breakdown. Figure 3As shown, the voltage regulator unit 21 consists of a first Zener diode D1, a second Zener diode D2, and current-limiting resistors R2 and R4. This clamps the high-level voltage at points A and B to approximately -32V (assuming the first Zener diode D1 and the second Zener diode D2 are selected based on a clamping voltage of 8V), thereby reducing the Vgs voltage when the fourth transistor M4, fifth transistor M5, and seventh transistor M7 are turned on. Therefore, during level transitions, the high-level voltage at points A and B can be clamped to approximately -32V to reduce the Vgs voltage when the fourth transistor M4 and fifth transistor M5 are turned on, ensuring the lifespan of the transistors. This allows for high-level switching functionality to be achieved with low-cost transistor usage.

[0038] In one embodiment, reference is made to Figure 7 , Figure 7 This is a circuit connection diagram of the second embodiment of the level conversion circuit of this application. The first conversion module 20 further includes: The first diode D3 has its anode connected to the second terminal of the second resistor R2, and its cathode connected to the first terminal of the second resistor R2. The anode of the second diode D4 is connected to the second terminal of the fourth resistor R4, and the cathode of the second diode D4 is connected to the first terminal of the fourth resistor R4.

[0039] In this embodiment, based on the level conversion circuit of the above embodiment, a first diode D3 and a second diode D4 can be added to connect the two diodes in parallel with the second resistor R2 and the fourth resistor R4, respectively. This can accelerate the discharge at points A and B. In practice, the two diodes can be considered equivalent to a single wire, thereby speeding up the discharge process and further optimizing the voltage waveforms at points A and B. For example, refer to... Figure 8 , Figure 8 This is another waveform diagram of the first embodiment of the level conversion circuit of this application. The vertical dashed line in the diagram represents the rising edge delay time. The rising edge delay time of the output signal waveform, relative to the input signal, is 400ns. Further details can be found in... Figure 9 , Figure 9 This is a waveform diagram of a second embodiment of the level conversion circuit of this application. The vertical dashed line represents the rising edge delay time. In the diagram, the rising edge delay time of the output signal waveform is 260ns compared to the input signal, a reduction of approximately 140ns. Furthermore, by connecting a fast discharge path (such as the first diode D3 and the second diode D4 or a transistor auxiliary discharge circuit) in parallel with the output node and intermediate nodes, the falling edge response is effectively improved, the delay is reduced by approximately 30-40%, and the level switching speed is increased.

[0040] Furthermore, in some feasible embodiments, the second conversion module 30 includes: The level shifting unit 31 has a first terminal connected to the target positive voltage VGH, a second terminal connected to the target negative voltage VGL, and a third terminal connected to the second terminal of the eighth resistor R8 in the first conversion module 20. The complementary output unit 32 has a first terminal connected to the target positive voltage VGH, a second terminal connected to the target negative voltage VGL, a third terminal connected to the second terminal of the ninth resistor R9 in the first conversion module 20, and a fourth terminal connected to the fourth terminal of the level shifting unit 31.

[0041] In this embodiment, the second conversion module 30 mainly consists of a level shifting unit 31 and a complementary output unit 32. The level shifting unit 31 primarily utilizes a transistor voltage divider network to shift the PMOS gate level, ensuring stable on / off operation of the high-side driver within a ±40V operating range, thus improving voltage symmetry and response speed. The complementary output unit 32 employs a symmetrical CMOS structure to output a ±40V square wave signal, guaranteeing waveform stability and symmetry. Of course, other protection units or other functional units can also be designed, which will not be described in detail here.

[0042] In some feasible embodiments, the level shifting unit 31 includes: The tenth resistor R10 has its first terminal connected to the target positive voltage VGH. The eleventh resistor R11 is connected to the second end of the tenth resistor R10. The first transistor Q1 has its first terminal connected to the second terminal of the eleventh resistor R11, and its third terminal connected to the second terminal of the eighth resistor R8. The twelfth resistor R12 has its first end connected to the second end of the first transistor Q1, and its second end connected to the target negative voltage VGL. The thirteenth resistor R13 is connected at its first end to the second end of the tenth resistor R10. The second transistor Q2 has its first terminal connected to the target positive voltage VGH, and its third terminal connected to the second terminal of the thirteenth resistor R13. The third transistor Q3 has its second terminal connected to the second terminal of the second transistor Q2, and its third terminal connected to the second terminal of the thirteenth resistor R13. The fourteenth resistor R14 has its first end connected to the second end of the second transistor Q2, and its second end connected to the fourth end of the complementary output unit 32. The fifteenth resistor R15 has its first end connected to the first end of the third transistor Q3, and its second end connected to the target negative voltage VGL.

[0043] In this embodiment, the level shifting unit 31 can be composed of a first transistor Q1, a second transistor Q2, a third transistor Q3, and a voltage divider network consisting of a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12. This controls the low-level voltage at point C to approximately 32V, thereby reducing the Vgs voltage when the sixth transistor M6 is turned on. Other configurations are also possible, as long as their respective functions are implemented. For example, based on the above connections and configuration, the Vgs voltage of the sixth transistor M6 can be reduced by level shifting to achieve high-level conversion.

[0044] In one embodiment, the complementary output unit 32 includes: The control terminal of the sixth transistor M6 is connected to the second terminal of the fourteenth resistor R14 in the level shifting unit 31, and the second terminal of the sixth transistor M6 is connected to the target positive voltage VGH. The seventh transistor M7 has its first terminal serving as the output terminal of the complementary output unit 32 and connected to the first terminal of the sixth transistor M6. The second terminal of the seventh transistor M7 is connected to the target negative voltage VGL. The control terminal of the seventh transistor M7 is connected to the second terminal of the ninth resistor R9.

[0045] In this embodiment, the complementary output unit 32 is composed of a sixth transistor M6 and a seventh transistor M7, and outputs a ±40V square wave signal based on a symmetrical CMOS structure to ensure waveform stability and symmetry. Of course, it can also be composed of other components, such as transistors or switches.

[0046] In one embodiment, based on the level conversion circuit of the above embodiment, the entire conversion process is analyzed as follows: When the control signal VIN is high, the second transistor M2 is turned off, and the third transistor M3 is turned on. Current flows from the power supply voltage VDD through the third transistor M3, the second resistor R2, and the first Zener diode D1. Due to the presence of the first Zener diode D1, the voltage at point A is clamped to -32V. At this time, the Vgs voltage of the fourth transistor M4 is -32 - (-40) = 8V, and the fourth transistor M4 is turned on. Point B is pulled down to a low level (i.e., -40V of the target negative voltage VGL), and the fifth transistor M5 and the sixth transistor M7 are turned off. In level shifting unit 31, a high level at point A controls the first transistor Q1 to conduct. The voltage at the upper end of the eleventh resistor R11 is obtained by voltage division using the tenth resistor R10, the eleventh resistor R11, and the twelfth resistor R12 (i.e., different output voltages can be achieved by setting the resistance value). Assuming the voltage after division is 32V, the third transistor Q3 conducts, and the voltage at point C is approximately 32V. The Vgs of the sixth transistor M6 is 32-40=-8V, so the sixth transistor M6 conducts, and the output voltage Vo is high (40V). The third transistor Q3 conducts because the diode inside Q3 creates a voltage difference between its base and emitter. Furthermore, the operating state and Vgs voltage of each transistor in this stage are shown in Table 3 below. The third transistor M3, the fourth transistor M4, and the sixth transistor M6 are conducting, but their Vgs are significantly reduced.

[0047]

[0048] Table 3 When the control signal VIN is low, the third transistor M3 is turned off, and the second transistor M2 is turned on. Current flows from the power supply voltage VDD through the second transistor M2, the fourth resistor R4, and the second Zener diode D2. Due to the presence of the second Zener diode D2, the voltage at point B is clamped to -32V. At this time, the Vgs voltage of the fifth transistor M5 is -32 - (-40) = 8V, and the fifth transistor M5 is turned on, pulling point A down to a low level (i.e., -40V of the target negative voltage VGL). In level shifting unit 31, a low level at point A controls the first transistor Q1 to be cut off, and a high level (-32V) at point B controls the seventh transistor M7 to be turned on, resulting in a low output voltage Vo (-40V). Simultaneously, due to the cutoff of the first transistor Q1, the voltage across the eleventh resistor R11 is VGH (40V), causing the second transistor Q2 to be turned on. The voltage at point C is approximately 40V, and the sixth transistor M6 has a Vgs of 40 - 40 = 0V, thus cutting off M6. The second transistor Q2 is turned on because the diode inside Q2 creates a voltage difference between its base and emitter. Furthermore, the operating state and Vgs voltage of each transistor in this stage are shown in Table 4 below. The fifth transistor M5 and the eighth transistor M8 are turned on, but their Vgs are significantly reduced.

[0049]

[0050] Table 4 Further details can be found by referring to... Figure 6 , Figure 6 This is a waveform diagram of the first embodiment of the level conversion circuit of this application. When the input is a 200kHz square wave signal, the high level is 40V and the low level is -40V, resulting in the following output waveform. It can be seen that the above circuit can achieve a higher level conversion without damaging the transistor. Furthermore, based on a circuit architecture combining graded voltage limiting and level shifting, the gate-source voltage range of the transistor device can be effectively limited by clamped Zener diodes, voltage divider networks, and bipolar transistor auxiliary drive, so that it still maintains Vgs<10V under ±40V output conditions, avoiding device failure and expanding the functionality of the level conversion circuit.

[0051] It should be noted that the transistors used in all embodiments of this application can be TFTs (Thin Film Transistors), field-effect transistors, MOS (Metal-Oxide-Semiconductors), or other devices with similar characteristics. Since the second terminal and drain of the transistors used here are symmetrical, their source and drain terminals are interchangeable. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source, and the other is called the drain. Figure 3 In the first transistor M1, the characteristics of each port can be determined by its G, D, and S terminals, where G (control terminal) is the control terminal of M1, S is the second terminal of M1, and D is the first terminal of M1. The characteristics of the remaining transistors can be determined based on... Figure 3 The configuration of the transistors is defined as follows: the middle terminal of each transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the transistors used in the embodiments of this application may include both P-type and N-type transistors. P-type transistors conduct when the gate is low and are cut off when the gate is high, while N-type transistors conduct when the gate is high and are cut off when the gate is low. The conduction modes of the corresponding N-type and P-type transistors are different, and the corresponding control methods also differ. The specific control depends on the actual transistor and is not limited here.

[0052] Furthermore, in some feasible embodiments, the first transistor M1 to the ninth transistor M9 can be a low-temperature polycrystalline silicon transistor, an oxide semiconductor transistor, or an amorphous silicon transistor. The transistors in the driving circuit provided in this application are all made of the same material, thereby avoiding the impact of differences between transistors of different materials on the driving circuit.

[0053] Furthermore, in one embodiment, referring to Figure 10 , Figure 10This is a circuit connection diagram of a third embodiment of the level conversion circuit of this application. The complementary output unit 32 further includes: The anode of the third diode D5 is connected to the control terminal of the sixth transistor M6, and the cathode of the third diode D5 is connected to the target positive voltage VGH.

[0054] In one embodiment, reference is made to Figure 11 , Figure 11 This is another circuit connection diagram of the third embodiment of the level conversion circuit of this application. The complementary output unit 32 further includes: The anode of the fourth diode D6 is connected to the second terminal of the ninth resistor R9, and the cathode of the fourth diode D6 is connected to the control terminal of the seventh transistor M7. The fourth transistor Q4 has its second terminal connected to the target negative voltage VGL, and its second terminal is connected to the cathode of the fourth diode D6. The third terminal of the fourth transistor Q4 is connected to the anode of the fourth diode D6.

[0055] In this embodiment, based on the circuit diagram of the above embodiment, a third diode D5 is added to further suppress the voltage spike at point C, reducing the impact and damage to the sixth transistor M6. Simultaneously, EMI can be further optimized. Further details can be found in... Figure 12 , Figure 12 This is a waveform diagram of the third embodiment of the level conversion circuit of this application. Due to the effect of the third diode D5 (a Zener diode), the voltage spike at point C is significantly suppressed to protect the sixth transistor M6. For example, a fourth diode D6 can also be added to accelerate the discharge at point D. In practice, the two diodes can be equivalent to a single wire, thereby accelerating the discharge process and further optimizing the voltage waveform at point D.

[0056] In one embodiment, transistors can be selected based on their on-state level. For example, the first transistor M1, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are N-type transistors; the second transistor M2, the third transistor M3, and the sixth transistor M6 are P-type transistors; the first transistor Q1 and the second transistor Q2 are NPN type; and the third transistor Q3 and the fourth transistor Q4 are PNP type.

[0057] Furthermore, this application also proposes a liquid crystal display panel (which can also be other devices requiring higher voltage conversion). The liquid crystal display panel includes at least a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes a level conversion circuit. The liquid crystal display panel may also include the level conversion circuit described above, see reference... Figure 13 , Figure 13This is a schematic diagram of the structure of the liquid crystal display panel involved in the embodiments of this application.

[0058] like Figure 13 As shown, the liquid crystal display panel may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0059] Those skilled in the art will understand that Figure 13 The structure shown does not constitute a limitation on the liquid crystal display panel and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0060] like Figure 13 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a data storage module, a network communication module, a user interface module, and computer programs.

[0061] exist Figure 13 In the liquid crystal display panel shown, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in this embodiment can be set in the liquid crystal display panel. The liquid crystal display panel calls the computer program stored in the memory 1005 through the processor 1001 and controls the above-mentioned level conversion circuit.

[0062] The various embodiments of the liquid crystal display panel of this application can be referred to the various embodiments of the level conversion circuit of this application, and will not be repeated here.

[0063] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0064] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0065] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods of the various embodiments of this application.

[0066] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A level shifting circuit, characterized by, The level conversion circuit comprises: an input module, a first end of the input module being connected to a control voltage, and a second end of the input module being connected to a power supply voltage; a first conversion module, a first end of the first conversion module being connected to the power supply voltage, a second end of the first conversion module being connected to a target negative voltage, a third end of the first conversion module being connected to a third end of the input module, and a fourth end of the first conversion module being connected to the control voltage, wherein a voltage stabilizing unit is arranged in the first conversion module to clamp high and low levels; a second conversion module, a first end of the second conversion module being connected to a target positive voltage, a second end of the second conversion module being connected to the target negative voltage, a third end of the second conversion module being connected to a fifth end of the first conversion module, and a fourth end of the second conversion module being connected to a sixth end of the first conversion module, wherein when the control voltage is at a high level, the fifth end of the first conversion module outputs a first clamped negative voltage based on the high level, and the second conversion module outputs the target positive voltage based on the first clamped negative voltage, and when the control voltage is at a low level, the sixth end of the first conversion module outputs a second clamped negative voltage based on the low level, and the second conversion module outputs the target negative voltage based on the second clamped negative voltage.

2. The level shifting circuit of claim 1, wherein, The input module comprises: a first transistor, a control end of the first transistor being connected to the control voltage, and a second end of the first transistor being grounded; a first resistor, a first end of the first resistor being connected to the power supply voltage, and a second end of the first resistor being connected to a first end of the first transistor and a third end of the first conversion module.

3. The level shifting circuit of claim 1, wherein, The first conversion module comprises: a second transistor, a control end of the second transistor being connected to the control voltage, and a second end of the second transistor being connected to the power supply voltage; a third transistor, a control end of the third transistor being connected to the second end of the first resistor in the input module, and a second end of the third transistor being connected to the power supply voltage; a second resistor, a first end of the second resistor being connected to the first end of the third transistor, and a second end of the second resistor being connected to a first end of the voltage stabilizing unit; a third resistor, a first end of the third resistor being connected to the first end of the third transistor; a fourth resistor, a first end of the fourth resistor being connected to the first end of the second transistor, and a second end of the fourth resistor being connected to a second end of the voltage stabilizing unit; a fifth resistor, a first end of the fifth resistor being connected to the first end of the second transistor; a fourth transistor, a first end of the fourth transistor being connected to a second end of the fifth resistor, and a second end of the fourth transistor being connected to the target negative voltage; a sixth resistor, a first end of the sixth resistor being connected to the control end of the fourth transistor, and a second end of the sixth resistor being connected to the first end of the second resistor; a fifth transistor, a first end of the fifth transistor being connected to a second end of the third resistor, and a second end of the fifth transistor being connected to the target negative voltage; A seventh resistor, a first end of the seventh resistor is connected with the control end of the fifth transistor, and a second end of the seventh resistor is connected with the second end of the fourth resistor; An eighth resistor, a first end of the eighth resistor is connected with the first end of the second resistor, and a second end of the eighth resistor is connected with the third end of the second conversion module; A ninth resistor, a first end of the ninth resistor is connected with the second end of the fourth resistor, and a second end of the ninth resistor is connected with the fourth end of the second conversion module.

4. The level shifting circuit of claim 3, wherein, The voltage stabilizing unit comprises: A first voltage stabilizing diode, a cathode of the first voltage stabilizing diode is connected with the second end of the second resistor, and an anode of the first voltage stabilizing diode is connected with the target negative voltage; A second voltage stabilizing diode, a cathode of the second voltage stabilizing diode is connected with the second end of the fourth resistor, and an anode of the second voltage stabilizing diode is connected with the target negative voltage.

5. The level shifting circuit of claim 3, wherein, The first conversion module further comprises: A first diode, an anode of the first diode is connected with the second end of the second resistor, and a cathode of the first diode is connected with the first end of the second resistor; A second diode, an anode of the second diode is connected with the second end of the fourth resistor, and a cathode of the second diode is connected with the first end of the fourth resistor.

6. The level shifting circuit of claim 1, wherein, The second conversion module comprises: A level shift unit, a first end of the level shift unit is connected with the target positive voltage, a second end of the level shift unit is connected with the target negative voltage, and a third end of the level shift unit is connected with the second end of the eighth resistor in the first conversion module; A complementary output unit, a first end of the complementary output unit is connected with the target positive voltage, a second end of the complementary output unit is connected with the target negative voltage, a third end of the complementary output unit is connected with the second end of the ninth resistor in the first conversion module, and a fourth end of the complementary output unit is connected with a fourth end of the level shift unit.

7. The level shifting circuit of claim 6, wherein, The level shift unit comprises: A tenth resistor, a first end of the tenth resistor is connected with the target positive voltage; An eleventh resistor, a first end of the eleventh resistor is connected with a second end of the tenth resistor; A first triode, a first end of the first triode is connected with a second end of the eleventh resistor, and a third end of the first triode is connected with the second end of the eighth resistor; A twelfth resistor, a first end of the twelfth resistor is connected with a second end of the first triode, and a second end of the twelfth resistor is connected with the target negative voltage; A thirteenth resistor, a first end of the thirteenth resistor is connected with a second end of the tenth resistor; A second triode, a first end of the second triode is connected with the target positive voltage, and a third end of the second triode is connected with a second end of the thirteenth resistor; A third triode, a second end of the third triode is connected with a second end of the second triode, and a third end of the third triode is connected with a second end of the thirteenth resistor; A fourteenth resistor, a first end of the fourteenth resistor is connected with a second end of the second triode, and a second end of the fourteenth resistor is connected with a fourth end of the complementary output unit; A fifteenth resistor, a first end of the fifteenth resistor is connected with the first end of the third triode, and a second end of the fifteenth resistor is connected with the target negative voltage.

8. The level shifting circuit of claim 6, wherein, The complementary output unit comprises: A sixth transistor, a control end of the sixth transistor is connected with a second end of a fourteenth resistor in the level shift unit, and a second end of the sixth transistor is connected with the target positive voltage; A seventh transistor, a first end of the seventh transistor is connected with a first end of the sixth transistor, and a second end of the seventh transistor is connected with the target negative voltage, and a control end of the seventh transistor is connected with a second end of the ninth resistor.

9. The level shifting circuit of claim 8, wherein, The complementary output unit further comprises: A third diode, an anode of the third diode is connected with the control end of the sixth transistor, and a cathode of the third diode is connected with the target positive voltage.

10. The level shifting circuit of claim 8, wherein, The complementary output unit further comprises: A fourth diode, an anode of the fourth diode is connected with the second end of the ninth resistor, and a cathode of the fourth diode is connected with the control end of the seventh transistor; A fourth triode, a second end of the fourth triode is connected with the target negative voltage, a second end of the fourth triode is connected with the cathode of the fourth diode, and a third end of the fourth triode is connected with the anode of the fourth diode.

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