Data conversion tracking of received data

Abstract

The invention relates to data conversion tracking of received data. The signal conditioning circuitry (400) includes logic circuitry (402), a low pass filter (404), and comparator circuitry (406). The logic circuitry (402) is configured to compare data units from a sequence of data units to previous data units and provide a logic output signal. The low pass filter (404) is coupled to the logic circuitry (402), and the low pass filter (404) is configured to provide a data conversion density measurement of the sequence of data units based on the logic output signal. The comparator circuitry (406) is coupled to the low pass filter (404), and the comparator circuitry (406) is configured to compare the data conversion density measurements to a threshold value, and to indicate a destructive pattern in the sequence of data units based on the comparison to the threshold value.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on September 14, 2021, with application number 202180054477.6 and invention title "Data Conversion Tracking After Receiving Data". Technical Field

[0003] This disclosure generally relates to data transmission, and more specifically to data transformation tracking of received data. Background Technology

[0004] When a transmitter transmits a signal containing data (referred to herein as a data signal or signal) (e.g., a high-speed data (HSD) signal) across a communication channel, the signal leaving the channel may be distorted relative to the signal entering the channel. A distortion compensation circuitry system (e.g., an equalizer or clock and data recovery (CDR) circuitry) can receive the signal leaving the channel and perform distortion compensation on the signal before providing it to the receiver. Summary of the Invention

[0005] In some cases, such as in the presence of destructive data patterns, some or all of the distortion compensation circuitry may fail to reliably perform its intended function. As used herein, a destructive data pattern is a sequence of data units (e.g., a sequence of data bits) having a pattern of values, amplitudes, or magnitudes that could cause the circuit to operate in a manner that leads to failure to meet performance or operational standards, or that could cause the circuit to fail completely. In this sense, a destructive data pattern can be considered a “pathological” data sequence or “pathological” mode of the distortion compensation circuitry. When the distortion compensation circuitry is adaptive or performs adaptive operation (also known as adaptive tuning) (for example, the circuitry periodically tunes according to changing channel conditions, temperature, supply voltage, or other variations), operating the distortion compensation circuitry (e.g., adaptive) during a destructive data pattern or pathological mode can cause the circuitry to deviate from its preferred tuning.

[0006] The described examples can be used to monitor changes or transitions in data and detect destructive data patterns in a sequence of data units. Therefore, one or more of the distortion compensation circuits can be gated in the presence of a destructive data pattern, for example, pausing or restarting the adaptive circuitry, and allowed to operate fully in the absence of a destructive data pattern, for example, resuming adaptive operation. Without one or more of the described examples, in addition to the problems mentioned above, the channel coverage extension provided by the distortion compensation circuitry system, when including equalizer and CDR circuitry, can be degraded by nearly 50% or more. One or more of the described examples can reduce or eliminate this coverage extension loss. Furthermore, one or more of the described examples can prevent equalizer and / or CDR circuitry system failure, thereby maintaining the integrity of the data signal in the presence of destructive data patterns.

[0007] In one example, the signal conditioning circuitry system includes a logic circuitry system, a low-pass filter, and a comparator circuitry system. The logic circuitry system is configured to compare data units from a data unit sequence with previous data units and provide a logic output signal. The low-pass filter is coupled to the logic circuitry system and configured to provide a data conversion density measurement of the data unit sequence based on the logic output signal. The comparator circuitry system is coupled to the low-pass filter and configured to compare the data conversion density measurement with a threshold and, based on the comparison with the threshold, indicate a destructive mode in the data unit sequence. The indication of a destructive mode can be provided to distortion compensation circuitry such that at least one aspect or portion of the distortion compensation circuitry (e.g., adaptive) can operate in the absence of a destructive mode and pause or reset (generally referred to herein as "gated" or "gated") in the presence of a destructive mode.

[0008] In another example, the signal conditioning circuitry includes a data conversion tracking circuitry and an equalizer. The data conversion tracking circuitry includes an XOR gate, a low-pass filter coupled to the XOR gate, and a comparator circuitry coupled to the low-pass filter. The comparator circuitry is configured to compare a data conversion density measurement with a threshold and, based on the comparison, indicate a destructive pattern in the data unit sequence. The equalizer is coupled to the comparator circuitry and configured to gate adaptive operation in response to the indication.

[0009] In another example, a method includes comparing data cells from a data cell sequence with previous data cells and providing a logic output signal. The method further includes generating a time-averaged signal based on the logic output signal. The method also includes comparing the time-averaged signal with a threshold and, based on the comparison with the threshold, indicating a destructive pattern in the data cell sequence. The method further includes gating a distortion compensation circuit system adaptively in response to the indication of the destructive pattern. Attached Figure Description

[0010] Figure 1 Describe an example communication system with a data conversion and tracking circuit system.

[0011] Figure 2 Depicting can be Figure 1 The system shown is an example of a distortion compensation circuit system implemented in the system.

[0012] Figure 3 Depicting Figure 1 The signal conditioning circuit system shown in the image is part of an example data conversion and tracking circuit system.

[0013] Figure 4 Describe an example signal conditioning circuit system with a data conversion and tracking circuit system.

[0014] Figure 5 Description Figure 4 The timing diagram of the signal conditioning circuit system shown in the figure illustrates its operation.

[0015] Figure 6 Drawing operations Figure 2 and 4 The simulation results of the signal conditioning circuit system shown in the figure.

[0016] Figure 7 Drawing operations Figure 2 and 4 The simulation results of the signal conditioning circuit system shown in the figure.

[0017] Figure 8 Describe an example signal conditioning circuit system with a data conversion and tracking circuit system.

[0018] Figure 9 Drawing operations Figure 2 and 8 The simulation results of the signal conditioning circuit system shown in the figure.

[0019] Figure 10 Describe an example signal conditioning circuit system with a data conversion and tracking circuit system.

[0020] Figure 11Describe an example signal conditioning circuit system with a data conversion and tracking circuit system.

[0021] Figure 12 Describe an example signal conditioning circuit system with a data conversion and tracking circuit system.

[0022] Figure 13 Describe a flowchart illustrating an example method for operating a data conversion and tracking circuit system. Detailed Implementation

[0023] In the drawings, similar reference element symbols refer to similar elements throughout, and the individual features are not necessarily drawn to scale. In the specification and claims, the terms "comprising" and "having" and their variations are inclusive in a manner similar to the term "comprising," unless otherwise stated. Additionally, the term "coupled" means indirect or direct electrical or mechanical connection.

[0024] First refer to Figure 1 This describes an example communication system 100 with a data conversion tracking circuitry system 124 according to the present teaching. System 100 includes a transmitter 102, a signal conditioning circuitry system 106, and a receiver 108 coupled as described. Within the communication system 100, the transmitter 102 can transmit data signals to the receiver 108 using channel 104. The signal conditioning circuitry system 106 includes a distortion compensation circuitry system 112, a data unit extraction circuitry system 120, a data unit delay circuitry system 122, and a data conversion tracking circuitry system 124. The distortion compensation circuitry system 112 includes an equalizer 116, for example, in the case of a re-driver circuit. In another example embodiment, the distortion compensation circuitry system 112 also includes a CDR 118, for example, in the case of a re-timer circuit.

[0025] As illustrated, the signal conditioning circuitry 106 is separate from the receiver 108. For example, the signal conditioning circuitry 106 is contained on a separate chip or die from one or more chips or dies containing the receiver 108. However, the chip containing the signal conditioning circuitry 106 and one or more chips containing the receiver 108 may share (e.g., be mounted to) a common printed circuit board (PCB). Alternatively, the signal conditioning circuitry 106 may be integrated into the receiver 110, as illustrated by the dashed box representing the receiver 110. For example, the signal conditioning circuitry 106 and the receiver 110 circuitry are contained on the same chip.

[0026] Furthermore, although depicted as unidirectional communication, as illustrated by the arrows, channel 104 can be used for bidirectional communication. Therefore, transmitter 102 and receiver 108 are each included in a transceiver (not shown). Moreover, in an example of bidirectional communication, signal conditioning circuitry system 106 may also be included on the transmitter 102 side of channel 104.

[0027] During the operation of system 100, transmitter 102 uses channel 104 to transmit data signal TX. OUT Channel 104 can enable TX during transmission. OUT The distorted "lossy" channel causes the output signal CHAN from channel 104 to be distorted. OUT Figure 126 depicts TX OUT The example eye diagram, and Figure 128 depicts a CHAN. OUT Example eye diagram. As illustrated by the eye diagram, the transitions in the data (e.g., 130 and 132) shown in eye diagram 126 are undetectable in eye diagram 128 and can be difficult to distinguish from noise. Distortion compensation circuit system 112 receives CHAN OUT It also corrects for distortion in the signal to provide receiver 108 with a less distorted signal RX. IN .

[0028] In one example, the data signal TX OUT This is a high-speed serial data stream represented as voltage, where "high-speed" can correspond to a speed of 1 gigabits per second (Gbps) or higher. For example, 0 can be approximately -500 millivolts (mV), and 1 can be approximately 500 mV. In a specific instance, the data signal TX... OUT This is a broadband 4K or higher resolution digital video signal transmitted at 10 Gbps or higher and with frequency content ranging from Nyquist to much lower frequencies. Therefore, transmitter 102 can be a camera that outputs the video signal. Channel 104 can be a coaxial cable with an associated connector coupled between transmitter 102 and receiver 108 for transmitting the video signal to receiver 108. Receiver 108 performs digital signal processing on the received signal and outputs the video content to an output device (not shown), such as a television screen or monitor.

[0029] However, the implementation is not limited to these examples. That is, transmitter 102 and receiver 108 can be any two endpoints for transmitting a data signal via the physical medium represented by channel 104. For example, in another example, transmitter 102 is a microcontroller or central processing unit that transmits TX signals to receiver 108 via channel 104. OUTReceiver 108 is a storage device or graphics controller, and channel 104 is a trace on a PCB, such as a motherboard or daughter card. In other instances, channel 104 is an HDMI cable, USB cable, or fiber optic link. In yet another instance, channel 104 is a wireless medium, where TX... OUT The signal is a modulated signal and / or an analog signal, and both transmitter 102 and receiver 108 have wireless capabilities. In the case of wireless transmission, a demodulation circuitry (not shown) can be coupled to channel 104 to receive and demodulate the CHAN. OUT It also provides a demodulated signal to the signal conditioning circuit system 106.

[0030] When a high-speed broadband signal propagates, channel 104 can attenuate the higher frequency content of the signal according to the frequency, thus effectively acting as a low-pass filter. The signal CHAN output from channel 104... OUT It may also include amplitude and / or timing (time) noise, referred to as jitter. Distortion compensation circuitry 112 removes CHAN... OUT At least some distortion, and output closer to TX. OUT RX IN The signal is thus allowed to be recovered in the receiver circuitry 108. Specifically, the equalizer 116 acts as a high-pass filter to compensate for frequency dependence losses in channel 104 by adding the gain back to the higher frequency content attenuated by channel 104. The CDR 118 retims the equalized signal to remove jitter and CHAN. OUT At least some distortion. The equalization and / or retiming signal is the distortion compensation signal RX provided to the receiver 108. IN and the signal CTRL provided to the data unit delay circuit system 122 IN It contains data units. When CDR 118 is not used, the output of equalizer 116 can be provided to data unit extraction circuitry 120 (e.g., decision circuitry) to provide CTRL. IN Although not shown for simplicity, the distortion compensation circuitry 112 may also include an output driver to drive the channel between the distortion compensation circuitry 112 and the receiver 108, such as a cable, link, or trace on a PCB.

[0031] Figure 2 Depicting can be Figure 1 The system shown implements an example distortion compensation circuit system 112. More specifically, Figure 2This illustrates an example of a retimer circuit implementation. In this example, the distortion compensation circuit system 112 includes both an equalizer 116 and a CDR 118. The distortion compensation circuit system also includes, as described, an input termination circuit 200, an equalization (EQ) adaptive control circuit system 204, and a decision circuit 206 coupled as described. In this example, the CDR 118 is implemented as a phase-locked loop (PLL) and includes, as described, a phase-frequency detector 210, a charge pump 212, a low-pass filter 214, and a voltage-controlled oscillator (VCO) 216 coupled as described. The low-pass filter includes, as described, a resistor 226, a capacitor 228, and a capacitor 232 coupled between the output of the charge pump 212 and a reference voltage 230 (e.g., ground).

[0032] In another implementation, PLL 118 includes a divide-by-N block 218 that divides the frequency of VCO 216 by a factor of N. Therefore, block 218 is also referred to herein as frequency divider 218. Furthermore, as shown, CDR 118 uses a locally generated clock from VCO 216 to retime the signal from equalizer 116 to generate a retimed signal RX. IN .

[0033] As illustrated, CDR 118 is implemented using a second-order analog PLL, and is therefore also referred to herein as PLL 118. Alternatively, CDR 118 may be implemented using a digital PLL or a delay-locked loop (DLL). In another example implementation, CDR is based on a phase interpolator, which uses a PLL or DLL to implement a reference loop that accepts an input reference clock signal and generates a set of high-speed clock signals to serve as reference phases. These reference paths are fed into the CDR ring, which contains circuitry for selecting reference phase pairs and interpolating between them to provide a clock for recovering data from the data signal. Moreover, for simplicity, the illustrated distortion compensation circuitry 112 shows the equalizer 116, decision circuitry 206, and phase-frequency detector 210 as separate circuit blocks. However, there may be some overlap between the circuitry of these blocks.

[0034] During the operation of the distortion compensation circuit system 112, CHAN OUT (As shown in eye diagram 128) is received into input termination circuitry system 200. In one example, input termination circuitry system 200 includes one or more resistors that, in order to receive CHAN... OUT Impedance matching is performed when the signal is transmitted to equalizer 116. As previously mentioned, equalizer 116 is used to compensate for CHAN. OUT A high-pass filter with frequency-dependent loss in the signal is used to generate an equalized signal (EQ). OUT202. The equalization signal 202 is represented by eye diagram 222. As can be seen in eye diagram 222, the transitions in the data are detectable. However, as can also be seen in eye diagram 222, some noise and jitter are still present in the equalization signal 202.

[0035] Equalizer 116 may comprise a continuous-time linear equalizer (CTLE), a feedforward equalizer (FFE) with one or more taps, a decision feedback equalizer (DFE) with one or more taps and also including decision circuitry as part of a feedback loop, or a combination thereof. The EQ adaptive control circuitry system 204 allows equalizer 116 to adaptively tune or adjust its settings (e.g., gain and transfer function) based on conditions in channel 104 or other conditions or changes in the system (e.g., changes in temperature and / or supply voltage). The EQ adaptive control circuitry system 204 may be implemented as a hardware controller and memory, or as a combination of sequential and combinational logic.

[0036] In one implementation, prior to CDR lockout, the EQ adaptive control circuitry 204 may search or “scan” equalizer settings to establish initial settings for CDR lockout. Upon CDR lockout, the frequency and phase of the clock signal are adjusted so that the clock edges are aligned with the equalizer signal 202. These initial equalizer settings may correspond to, for example, the length of channel 104 (e.g., the length of a cable) and the associated attenuation of channel 204, which are unknown a priori. Subsequently, as temperature and / or supply voltage change slowly over time, these initial equalizer settings (e.g., the gain and transfer function of equalizer 116) may be incrementally adjusted under the control of the EQ adaptive control circuitry 204.

[0037] exist Figure 2 In the illustrated example of a retimer circuit implementation, the equalization signal 202 is fed to the decision circuit 206 and the PLL 118. In the absence of the PLL 118, for example in a redrive circuit implementation, the equalization signal 202 is fed to the decision circuit 206, and may also be fed directly to the receiver 108 (not shown). In both the retimer and redrive examples, the decision circuit 206 determines at a given time whether the data in the equalization signal 202 is 0 (low) or 1 (high). In this sense, the decision circuit acts as a data unit extraction circuit system.

[0038] In one example of a heavy-drive circuit implementation, decision circuit 206 is a limiting or clipping amplifier that attempts to slice the equalized eye (e.g., element 236 shown in Figure 222) at zero volts or at the center of eye 236. If the slicer output is greater than 0 (or at the center of the equalized eye), the amplifier amplifies the signal 202 until it is clipped in the positive direction. However, if the slicer output is less than 0 (or at the center of the equalized eye), the amplifier amplifies the signal until it is clipped in the negative direction. In this way, decision circuit 206 can reduce some voltage noise, but it does not address the timing noise (jitter) associated with the equalized eye 236. Decision circuit 206 then makes a decision as a CTRL. IN (It contains a sequence of data units) and is provided to the data unit delay circuit system 122.

[0039] exist Figure 2 In the illustrated example timer circuit implementation, PLL 118 receives the equalization signal 202 into phase-frequency detector 210. When divider 218 is implemented, phase-frequency detector 210 monitors the phase error in signal 202 relative to the frequency of VCO 216, or a small fraction of the frequency of VCO 216. Based on the phase error, PLL 118 uses charge pump 212 and low-pass filter 214 to adjust the frequency and phase of the VCO 216 output (clock signal 208) to the center of the timing noise distribution.

[0040] A clock signal 208 with adjusted phase and frequency from the VCO is provided to the feedback loop of the decision circuit 206 and the PLL 118. The decision circuit 206 uses the clock signal 208 to re-timing the equalization signal 202 to eliminate timing alignment errors, thereby generating a re-timing signal RX. IN and the retiming signal CTRL IN RX IN As shown in eye diagram 224, it is greater than CHAN OUT Or the equalizer signal 202 is closer to TX. OUT That is, the decision circuit 206 makes a decision about whether the equalization signal 202 is 1 or 0 at a given clock edge of the clock signal 208 (i.e., for each bit). To this end, the decision circuit 206 is designed to sample the clock signal 208 at the center of the open eye 236 of the equalization signal 202 with phase / frequency aligned to determine whether the sample is 1 or 0. This results in a reduction in both the amplitude noise and timing noise of the signal 202.

[0041] The decision circuit 206 may also include a lock detection circuitry (not shown), which may include one or more registers and flip-flops. The lock detection circuitry determines when the CDR has locked onto the equalizer signal 202 by comparing the frequency and phase of the equalizer signal 202 with the frequency and phase of the clock signal 208. In a particular implementation, before locking the CDR, the decision circuit 206 uses the retimed equalizer signal 202 as the CTRL. IN Provided to the data unit delay circuit system 122. However, initially there was no RX. IN A signal is provided to receiver 108 because the signal may have an error rate exceeding an acceptable threshold, such as a bit error rate. After CDR locking, decision circuit 206 will re-timing CTRL. IN Provided to the data unit delay circuit system 122, and the retiming RX IN Provided to receiver 108.

[0042] PLL 118 is also adaptive. More specifically, after the CDR has achieved lock-on to the equalizer signal 202, PLL 118 maintains alignment of the clock signal 208 from VCO 216 with the equalizer signal 202 in the presence of noise (whether caused by channel 104 or circuitry 112). When the clock signal 208 deviates from its ideal alignment due to noise or temperature / supply voltage variations (also known as “search jitter”), phase-frequency detector 210 detects the alignment deviation or search jitter. PLL 118 then uses charge pump 212 and low-pass filter 214 to pull the clock signal 208 back into alignment with the equalizer signal 202, thereby reducing search jitter.

[0043] The problem with the distortion compensation circuit system 112 is that one or both of the equalizer 116 and CDR 118 may malfunction or operate unreliably in the presence of certain data sequences or patterns. For example, both equalizer 116 and CDR 118 are designed to operate reliably in the presence of random or pseudo-random (e.g., scrambled) data. Therefore, for equalizer 116 and / or CDR 118, ill-conditioned or destructive patterns in the data cell sequence (e.g., bit sequence) contain data that is no longer random or pseudo-random. For example, an ill-conditioned pattern that could disrupt the operation of equalizer 116 or CDR 118 is a sequence of consecutive identical digits (CIDs), such as a sequence of consecutive 1s or consecutive 0s, or some other repeating pattern, such as an alternating sequence of 1s and 0s.

[0044] An example of an ill-conditioned pattern is data from a clock signal or analog clock signal that has an alternating pattern of 1s and 0s. In digital video applications, an example ill-conditioned pattern might be a single 0 followed by 19 ones, or a single 1 followed by 19 zeros, which could represent, for example, the color magenta. In other applications, different data sequences can lead to ill-conditioned patterns in distortion compensation circuitry systems.

[0045] Ill-conditioning can cause any number of problems in the operation of equalizer 116 and CDR 118. For example, ill-conditioning can cause increased search jitter, which causes CDR 118 to lose lock, thus preventing data recovery. In another instance, ill-conditioning causes equalizer 116 to lose its current and preferred settings, which introduces noise and errors into the recovered data. In yet another instance, ill-conditioning causes equalizer 116 to malfunction, which also prevents data recovery.

[0046] One solution is to reduce the bandwidth of CDR 118, which reduces its response time skew in data clock alignment. Another solution is to over-engineer receiver 108 with sufficient margin to tolerate increased search jitter and / or suboptimal equalizer settings. However, these solutions may result in one or more performance parameters of the overall receiver system being sacrificed, a more expensive receiver due to increased power consumption and circuit complexity, and / or failure of other specifications of the receiver system.

[0047] The solution described herein is to detect ill-conditioned patterns in the data and, in the presence of such patterns, to gating "operation." This may include gating the adaptive behavior of one or more of the distortion compensation circuitry (e.g., equalizer 116 and / or CDR 118). Specifically, the data conversion tracking circuitry can be used to track data conversion density (DTD) measurements of a sequence of data cells (e.g., bit sequences), and, for example, when a DTD measurement indicates the presence of an ill-conditioned pattern in the data stream, to pause the adaptation of equalizer 116 and pause or reset the phase / frequency tracking of CDR 118. Once the ill-conditioned pattern is no longer detected, at least a portion or aspect of the operation (e.g., adaptive) of equalizer 116 and CDR 118 can be degated or allowed to operate and tune their respective blocks.

[0048] "Data Transition Density" or "DTD" is the ratio of data unit transitions to the total number of data units over a period of time. For example, DTD is the ratio of the number of transitions (e.g., transitions from 0 to 1 or 1 to 0) in a data stream over a given time period to the total number of unit intervals in the data stream (e.g., the number of bits recovered). For some application scenarios, the DTD of a high-speed digital data stream tends to 0.5 for random or pseudo-random data, and tends to 0 or 1 in the presence of ill-conditioned patterns. Therefore, the DTD can be compared to one or more thresholds to detect the presence of ill-conditioned patterns. Once detected, the data transition tracking circuitry can output or provide a strobe signal (referred to herein as G). TRIG ), to enable adaptive selection of distortion compensation circuit system.

[0049] Using one or more of the example implementations described herein may have one or more advantages or benefits. An example advantage is the ability of the gating distortion compensation circuitry system to be adaptive in order to prevent it from failing or becoming unreliable in the presence of a sick mode. For retimer circuitry, gating may include resetting the CDR before it locks in the presence of a sick mode to prevent synchronization of the equalization scan and to prevent erroneous locking of the CDR, which could prevent data recovery. Another example advantage is that at least some of the circuitry used for data transition tracking is simpler than that used for over-engineered receivers. Another example advantage is the prevention of loss of preferred adaptive equalization settings in the presence of a sick mode. In the context of retimer circuitry, yet another example advantage is the ability to detect sick modes even before data can be reliably recovered, for example, even before the CDR locks. This is because the data transition tracking circuitry system can be designed to allow repeating patterns with long CID sequences to be detected even before the CTRL is re-tied. IN It was detectable before.

[0050] Refer again Figure 1 and 2 The distortion compensation circuit system 112 further includes switches 220 and 234. Switch 220 is coupled between the EQ adaptive control circuit system 204 and the equalizer 116. Switch 234 is coupled between the VCO 216 and the low-pass filter 214. When the distortion compensation circuit system 112 is operated in the presence of random or pseudo-random data, switches 220 and 234 are closed. However, in the presence of a detected ill-conditioned pattern, the distortion compensation circuit system 112 receives G from the data conversion tracking circuit system 124. TRIG .

[0051] Upon receiving G TRIGThen, switch 220 is disconnected, thereby activating the EQ adaptive control circuitry 204. This effectively freezes or maintains the equalizer settings until no more sick mode is detected, at which point switch 220 closes, thus reactivating the EQ adaptive control circuitry 204. Upon receiving G... TRIG Then, switch 234 is also disconnected, thereby enabling the phase and frequency tracking capability of PLL 118. This keeps the frequency of VCO 216 constant until ill-conditioned modes are no longer detected, where switch 234 is closed, thus allowing phase and frequency tracking and adaptive correlation of the phase and frequency of VCO 216. G can be used... TRIG Perform other gating. In another instance, a lock detection circuit system (not shown) for detecting CDR lockout is gating in addition to or instead of disconnecting switch 234.

[0052] Figure 3 Depicting Figure 1 A portion 300 of the signal conditioning circuit system 106 includes an example data conversion tracking circuit system 124. More specifically, circuit 300 further includes a data unit extraction circuit system 120 and a data unit delay circuit system 122. Data conversion includes the data unit extraction circuit system 120, the data unit delay circuit system 122, and the data conversion tracking circuit system 124. The data conversion tracking circuit system 124 includes a logic circuit system 302, a low-pass filter 304, and a comparator circuit system 306 coupled as described.

[0053] The data unit extraction circuit system 120 extracts and outputs a sequence of data units (e.g., data bits) from the signal received from the signal conditioning circuit system. The signal may be a CHANNEL from channel 104. OUT Or it could be the output EQ of an equalizer. OUT However, in the following description, we will refer to the signal entering the data unit extraction circuit system 120 as EQ. OUT The data unit extraction circuit system 120 is provided as a CTRL. IN Data unit, CTRL IN It can be the output of the decision circuit within a re-timer or re-driver circuit, and is RX. IN The digital equivalent. In the retimer implementation, the data unit extraction circuit system 120 also receives a clock signal from the clock generator 330. For example, the clock generator 330 is a phase-aligned clock signal output from the CDR, such as clock signal 208 from the CDR 118.

[0054] In one example implementation, for instance when using a retimer, the data unit extraction circuitry 120 includes a sampler that receives EQ. OUTand clock signal, at each clock edge, EQ OUT The sampler performs sampling and outputs the resulting bits as data units. A sampler can be implemented using a buffer amplifier, an operational amplifier (op amp), a switch (e.g., a field-effect transistor) coupled between the output of the buffer amplifier and the input of the operational amplifier, and a capacitor coupled to the input of the operational amplifier. The sampler will EQ... OUT In the buffer amplifier, the switch can open and close on the clock edge to sample and output a voltage corresponding to the charging state of the capacitor, the charging state being represented by the EQ. OUT 1 or 0 sampling bits.

[0055] In another implementation example, for instance when using a heavy driver, the data unit extraction circuitry 120 includes a slicer that receives EQ. OUT The obtained bits are then output as data units. This can be achieved using EQ. OUT The slicer is implemented using an analog comparator that compares the slice to a threshold. If EQ OUT If the threshold is exceeded, the comparator output goes high, indicating 1. If RX IN EQ OUT If the value is below the threshold, the comparator output goes low, indicating 0.

[0056] Data unit delay circuit system 122 receives a data unit and generates one or more preceding data units. In a digital circuit example, data unit delay circuit system 122 includes a deserializer that generates multiple parallel bits and preceding bits. In an analog or mixed analog / digital example, data unit delay circuit system 122 includes a flip-flop, a delay line, or some other analog delay circuit system that delays the current data unit (e.g., a bit) by one unit interval period.

[0057] The logic circuit system 302 (e.g., one or more XOR gates) receives one or more data units from the data unit sequence, compares them with one or more previous data units, and generates a logic output signal (e.g., LOGIC) based on the comparison. OUT The low-pass filter 304 provides a time-averaged DTD measurement of the data unit sequence based on a logic output signal. The comparator circuitry 306 compares the DTD measurement with at least one threshold (e.g., TH1) and, based on the comparison, indicates whether a destructive (ill-conditioned) pattern exists in the data unit sequence. This indication is represented by signal G. TRIG .

[0058] In one instance, such as when using a rectifier, the comparator circuit system 306 compares the DTD measurement to a single threshold TH1, which is also referred to herein as an upper limit threshold. When the DTD measurement exceeds the threshold, G... TRIGIndicating an ill-conditioned pattern. In another instance, comparator circuitry 306 compares the DTD measurement with thresholds TH1 and TH2, which are also referred to herein as lower thresholds. When the DTD measurement is outside either threshold, for example above threshold TH1 or below threshold TH2, it is determined by G. TRIG Indicates pathological patterns.

[0059] In this example, the low-pass filter 304 has a sufficiently low cutoff frequency, such that G... TRIG Transient offsets in the data (e.g., short bursts of CID) do not indicate ill-conditioning patterns. Furthermore, the time constant of the data conversion tracking circuitry system 124 is smaller than that using G... TRIG The time constant of other control logic (e.g., for adaptive equalizer 116) that gates DTD measurements. This allows the data conversion tracking circuitry 124 to react faster than other adaptive circuitry systems, pausing or resetting the adaptive circuitry before ill-conditioning modes can distort the adaptation. In a specific instance, the time constant of the low-pass filter 304 is longer than that of the one using G. TRIG The time constant of the gating adaptive control circuit system is about an order of magnitude smaller. Therefore, the response speed of the switching tracking circuit system 124 will be 10 times that of other adaptive circuit systems in the system.

[0060] Figure 4 , 8 And 10 to 12 depict signal conditioning circuit systems comprising data conversion and tracking circuit systems according to this description. Specifically, Figure 4 An example signal conditioning circuit system 400 with an example digital implementation of a data conversion tracking circuit system is described. That is, the circuit system 400 includes a sampler or slicer 420 as a data unit extraction circuit system, a deserializer 422 as a data unit delay circuit system, and a data conversion tracking circuit system 424 coupled as described.

[0061] In one example implementation, circuit system 400, together with a retimer circuit, is used as a distortion compensation circuit system, wherein block 420 is for receiving the equalization signal EQ. OUT Both 456 and the phase-aligned clock signal 432 from clock generator 430 are used to generate a sampler for a data unit sequence 434 (in this case, a bit sequence). For example, clock generator 430 is a local VCO within the CDR of a retimer circuit. Sampler 420 may be referenced as above. Figure 3 The circuit system 400 is implemented as described in block 120. In another example implementation, the circuit system 400, together with the re-driver circuit, is used as a distortion compensation circuit system, wherein block 420 is only received by the EQ. OUTSignal 456 is used by a slicer to generate bit sequence 434. Slicer 420 can be referenced as above. Figure 3 Implemented as described in block 120. In both the retimer and redriver implementations, the remaining circuitry 422 and 424 are identical. Therefore, refer to... Figure 4 and related Figures 5 to 7 Only one implementation scheme is described (in this case, the retimer circuit implementation scheme).

[0062] In a specific instance, the EQ containing the data OUT The signal is provided at approximately 10 Gb / s. Therefore, every 100 picoseconds (e.g., one unit interval (UI) or one cycle of 10 Gb data), sampler 420 samples the data center on the rising edge of clock signal 432 to output new data bits. This high-speed serial data stream 434 is provided to deserializer 422. Deserializer 422 parallelizes the serial data stream 434 into multiple (n) slower data streams 436, which are processed in the digital domain by data conversion tracking circuitry system 424. In other instances, the data rate may be different, for example from 270 Mb / s to 12 Gb / s, or even higher data rates, such as 50 Gb / s, 100 Gb / s, or higher.

[0063] In an example implementation, deserializer 122 includes multiple shift registers configured for serial input parallel output (SIPO). In example applications, such as digital video, n = 64. However, n can be other values, such as 32. Therefore, deserializer 422 receives 64 sequential bits (1, 2, 3, ... n) from serial data stream 434 and outputs them to 64 corresponding (separate) lines. A high-speed sampling clock signal 432 is also fed to deserializer 422, which is divided (e.g., segmented) by n, and the n parallel output bits 436 are timed to n. Therefore, the speed of each of the 64 lines with n parallel bits 436 provided to the data conversion tracking circuitry system 424 is 1 / 64th of the serial data stream 434.

[0064] The data conversion tracking circuit system 424 includes a digital logic circuit system with an XOR group 402 having multiple XOR gates (one of which is labeled 406) coupled as shown, a low-pass filter 404, and a comparator circuit system 406. The low-pass filter 404 includes a summer 408 with inputs coupled to the output of the XOR group 402, and an integrator and dump circuit 460 coupled to the output of the summer 408. The low-pass filter 404 may also include a right shifter 418 coupled to the output of the integrator and dump circuit 460. The integrator and dump circuit 460 includes an adder 410 and a z-axis... -1 The accumulator of register 412, where z-1 Indicator register 412 is delayed by one clock cycle. The inputs of adder 410 are coupled to the outputs of summer 408 and register 412 (forming a feedback loop). The output of adder 410 is coupled to the input of register 412. Integrator and dump circuit 460 also includes switch 416, one terminal of which is coupled to the output of register 412, and the other terminal is coupled to the input of right shifter 418 (if used in the circuit) or the input of comparator circuit system 406.

[0065] The comparator circuit system 406 includes two digital comparators 454 and 426 and an AND gate 428. One input of comparator 454 and one input of comparator 426 are coupled to a terminal of switch 416 or the output of right shifter 418. Another input of comparator 454 is coupled to receive an upper threshold TH1. Another input of comparator 426 is coupled to receive a lower threshold TH2. Thresholds TH1 and TH2 can be programmed into registers coupled to comparators 454 and 426 or some other memory device (not shown). The outputs of comparators 454 and 426 are coupled to the input of AND gate 428, and a G is provided at the output of AND gate 428. TRIG Signal 452.

[0066] n parallel bits 436 are input to multiple (e.g., 63) XOR gates 406, where each bit is XORed with the previous bit. Therefore, for the 64 incoming signals 436, we have (n-1)63 signals 438 emerging from the XOR group 402. A summer 408 combines (e.g., adds) the 63 signals 438 into a single integer value 440, each signal 440 having log2(n) bits, or 6 bits in this example. In this example, the minimum value of the single signal 440 can be 0, and the maximum value can be 63. The integer value of signal 440 is updated at 1 / 64 of the original data rate at each deserializer clock edge.

[0067] Signal 440 is provided to integration and dump circuit 460, which provides a time-averaged DTD signal or measurement 446. If used, right shifter 418 truncates the least significant bit (LSB) to remove noise from signal 446. That is, the sum of signal 440 from the output of summer 408 and signal 442 from the register output are accumulated in register 412 until a clear and dump clock edge or pulse 444 is provided to register 412 and switch 416. Pulse 444 closes switch 416, causing the current accumulation sum 442 to be output from integration and dump circuit 460 as DTD measurement 446, and clearing register 412. Then, switch 416 is opened again to restart the accumulator until another clock edge or pulse 444 is provided. Switch 416 is used in this example. However, in an alternative example, there is no switch 416, and the low-pass filter 404 is designed to monitor the slope or rate of change of the signal 440.

[0068] Comparator 454 compares the DTD measurement 446 with TH1, and when signal 446 is less than TH1, it asserts, for example, providing a high signal 450 (1). Otherwise, comparator 454 is deasserted, thus providing a low signal 450 (0). Comparator 426 compares the DTD measurement 446 with TH2, and when signal 446 is greater than TH2, it asserts, for example, providing a high signal 448 (1). Otherwise, comparator 426 is deasserted, thus providing a low signal 448 (0).

[0069] When both signals 450 and 448 are high, AND gate 428 asserts, for example, that a high G is provided. TRIG Signal 452 (1) indicates "good" data, meaning the data type that allows the distortion compensation circuit system to operate correctly and adaptively. Therefore, high G... TRIG Signal 452 signals the distortion compensation circuit system to continue operating in a continuously adaptive manner. In one instance, good data is fully randomized data. Conversely, when one or both of signals 450 and 448 are low, AND gate 428 is deasserted, thereby providing low G. TRIG Signal 452 (0). Low G TRIG Signal 452 indicates the ill-conditioning mode, thus allowing the distortion compensation circuitry system to adaptively select.

[0070] TH1 and TH2 are application-specific and implementation-specific. In one example, TH1 and TH2 are designed based on the value of n and the design of the integration and dump circuit 460. That is, the register 412 accumulates the signal 440 for several cycles of a clock signal divided by n, and its output signal 446 can be represented as a multi-bit number. The size of the accumulator depth (total number of bits) and the frequency of the read and clear clock or pulse determine the averaging level provided by the integration and dump circuit. Therefore, the thresholds TH1 and TH2 can be determined by the amount of averaging performed by the integration and dump circuit 460, the frequency at which the DTD 446 measurement is provided, and the number of output signals 438 from the XOR group 402.

[0071] In the example where n is 64, when the data 434 is random or pseudo-random, the output signal 438 from the summer 408 is expected to be in the middle of the extreme values, for example, approximately 31.5, which is between 0 and 63. If the data 434 contains an ill-conditioned pattern, then the output signal 438 from the summer 408 will skew toward the maximum value (63) or the minimum value (0) for a sufficiently long period of time, such that the time-averaged DTD measurement signal 446 triggers the AND gate 428 to deassert and indicate the presence of the ill-conditioned pattern. In the example where n=64, thresholds TH1 and TH2 can be set to 400 and 275, respectively, to deassert the AND gate 428 when the DTD measurement 446 exceeds the thresholds.

[0072] Figure 5 Description Figure 4 The timing diagram shown illustrates the operation of the signal conditioning circuit system 400 without the right shifter 418. Specifically, the waveforms 440, 442, 444, 446, 448, 450, and 452 for the three time periods 500, 502, and 504 represent... Figure 4 The corresponding signals with the same component symbols are shown in the diagram. The signal 440, which is represented by lowercase letters indicating a series of integer values, is provided by the summer 408 to the integrator and dump circuit 406. As a result of the feedback, the sum 442 is represented by a series of uppercase letters indicating a series of integer values.

[0073] At the beginning of the timing diagram, it is assumed that register 412 has just been cleared, as indicated by the 0 at the beginning of waveform 442 and the absence of a value in waveform 446. Throughout time period 500, no clear and dump pulse 444 is provided, and waveforms 448, 450, and 452 are depicted as low (0). For the first subsequent clock edge (at time t1), the accumulated signal 442 has a value Z, which is the sum of the previous value 0 fed back and the current value z from signal 440. As further explained, since z... -1 A clock delay at register 412, the accumulated signal 442 is delayed by one clock edge from the value represented by waveform 440.

[0074] For the next clock edge (at time t2), the accumulation signal 442 has a value Y, which is the sum of the previous value Z fed back and the current value y from signal 440. For the next clock edge (at time t3), the accumulation signal 442 has a value X, which is the sum of the previous value Y fed back and the current value x from signal 440. This accumulation continues until a clear and dump pulse 444 is provided to the integration and dump circuit 460 at time t5 during time period 502. The final accumulation before pulse 444 occurs at time t4, where the accumulation signal 442 has a value S. S is the sum of the previous value T fed back and the current value s from signal 440. In an alternative embodiment, the clear and dump signal 444 is a clock signal instead of a pulse.

[0075] At the rising edge of the clear and dump pulse 444, switch 416 closes and the value of register 412 (currently S) is provided as the DTD measurement value 446 from the integration and dump circuit 460. Then, switch 416 opens and register 412 is cleared, as indicated by 0 in waveform 442, causing accumulation to start again and continue (as shown) until the clear and dump pulse 444 is provided to the integration and dump circuit 460 at time t6 during time period 504.

[0076] The accumulated signal 442, preceding pulse 444 at time t6, has a value J. J is the sum of the previous value K fed back and the current value j from signal 440. At the rising edge of the clear and dump pulse 444, switch 416 closes and the value of register 412 (currently J) is provided as the DTD measurement 446 from the integration and dump circuit 460. Then, switch 416 opens, register 412 is cleared, as indicated by 0 in waveform 442 during time period 504, causing accumulation to resume.

[0077] During time period 502, assume that the DTD value 446 of S supplied to comparators 454 and 426 is greater than TH1 and greater than TH2. This causes the output signal 448 of comparator 426 to go high, while the output signal 450 of comparator 454 remains low. Therefore, the G output from AND gate 428... TRIG Signal 452 remains low, indicating the ill-conditioned mode, which can be used for gate distortion compensation circuit system adaptation. However, during time period 504, it is assumed that the DTD value 446 of J supplied to comparators 454 and 426 is less than TH1 and greater than TH2. This causes the output signal 448 of comparator 426 to remain high, and the output signal 450 of comparator 454 to change from low to high. Therefore, the G output from AND gate 428... TRIG Signal 452 goes high, indicating good data, and sends a signal to the distortion compensation circuit system to restore adaptive operation.

[0078] Figure 6 and 7 Describing common operations Figure 2 and 4 The simulation results of the signal conditioning circuit systems 112 and 400 shown in the figure. Figure 6 Figure 600 illustrates the waveform 604 of the control voltage of VCO 216, plotted relative to time. Figure 6 Figure 602 also illustrates the waveform of the DTD measurement signal 446 plotted over time. The lines superimposed on the waveform 446 illustrate the upper threshold TH1 of 400 and the lower threshold TH2 of 274. Figure 7 The diagram in Figure 700 illustrates the adaptive waveform 706 of the CTLE of equalizer 116, plotted relative to time. Figure 7 Waveforms 702, 704, and 708 are also described, depicting the adaptation produced for the three tap coefficients of the DFE of the equalizer 116 plotted relative to time.

[0079] In the example simulation, and as illustrated by waveform 604, CDR 118 acquires lock on equalization signal 202 at time t2 with an offset of 500 ppm. Before CDR lock, CTLE (waveform 706) starts with minimum enhancement and increments by 3 after a timeout if CDR 118 fails to lock. If a CTLE timeout occurs before CDR lock is detected, VCO control voltage 604 is reset. VCO control voltage 604 is also reset if DTD measurement 446 changes from indicating a sick mode to indicating random or pseudo-random data. For example, this reset is indicated when DTD measurement 446 changes from less than TH2 to between TH1 and TH2 during the time frame between t1 and t2. Therefore, DTD measurement 446 can indicate a sick mode prior to CDR lock. Moreover, waveforms 702 to 708 illustrate the pause of equalization adaptation before and after CDR lock (which occurs at time t2). When the DTD measurement 446 is outside of TH1 or TH2, the paused equalization is depicted by the horizontal portion of waveforms 702 to 708, for example, at the beginning of times t1, t3, and t4.

[0080] Figure 8 An example signal conditioning circuit system 800 with a data conversion tracking circuit system is described. Specifically, the circuit system 800 includes a sampler 820 as a data unit extraction circuit system, a UI delay circuit system 822 as a data unit delay circuit system, and a data conversion tracking circuit system 824. In this example embodiment, the circuit system 800, together with a retimer circuit, serves as a distortion compensation circuit system, wherein the sampler 820 receives an equalization signal EQ containing data. OUTBoth the phase-aligned clock signal from clock generator 830 and the clock signal from clock generator 830 are used to generate a sequence of data cells (in this case, a bit sequence). For example, clock generator 830 is a local VCO within the CDR of a retimer circuit. Sampler 820 can be referenced as above. Figure 3 Implemented as described in block 120.

[0081] Therefore, every UI or every data cycle, sampler 820 samples the data center on the rising edge of the clock signal to output the recovered data bits. This high-speed serial data stream is provided to delay circuit system 822 and data conversion tracking circuit system 824. Delay circuit system 822 delays each bit in the serial data stream by 1 UI. Delay circuit system 822 outputs the delayed data bits as the previous data unit to data conversion tracking circuit system 824. In one example, delay circuit system 822 is implemented using D flip-flops.

[0082] The data conversion tracking circuit system 824 is an analog circuit system comprising an XOR gate 802, a low-pass filter 804, and a comparator circuit system 806. The low-pass filter 804 may be implemented as an RC circuit having at least one resistor and one capacitor. The comparator circuit system 806 includes an analog comparator 808, an analog comparator 810, and an inverting OR gate 812 at an input corresponding to the output of the TH2 comparator 810.

[0083] As illustrated, one input of XOR gate 802 is coupled to the output of sampler 820. The other input of XOR gate 802 is coupled to the output of delay circuit system 822. The output of XOR gate 802 is coupled to the input of low-pass filter 804. The output of low-pass filter 804 is coupled to one input of comparator 808 and one input of comparator 810. The other input of comparator 808 is coupled to receive the upper threshold TH1. The other input of comparator 810 is coupled to receive the lower threshold TH2. Thresholds TH1 and TH2 can be programmed into registers coupled to comparators 808 and 810 or some other memory device (not shown). The outputs of comparators 808 and 810 are coupled to the input of OR gate 812, and G is provided at the output of OR gate 812. TRIG Signal.

[0084] The XOR gate 802 performs an XOR operation between each bit and the previous bit, and provides the result XOR. OUT Signal. Low-pass filter 804 based on the time constant of low-pass filter 804 for XOR. OUTThe signals are time-averaged to generate a DTD signal or measurement value 814. Comparator 808 compares the DTD measurement value 814 with TH1, and asserts, for example, providing a high signal when signal 814 is less than TH1. Otherwise, comparator 808 is deasserted, thus providing a low signal. Comparator 810 compares the DTD measurement value 814 with TH2, and asserts, for example, providing a high signal when signal 814 is greater than TH2. Otherwise, comparator 810 is deasserted, thus providing an inverted low signal. When the signals from both comparators 808 and 810 are high, OR gate 812 deassertes, for example, providing a low G. TRIG The signal indicates good data to the distortion compensation circuit system. Otherwise, the OR gate 812 asserts, thus providing a high G signal indicating the ill-conditioned mode. TRIG The signal is used to select the distortion compensation circuit system. In this example, relative to... Figure 4 The examples given in the text make G TRIG The polarity reversal.

[0085] Figure 9 Describing common operations Figure 2 and 8 The simulation results of the signal conditioning circuit systems 112 and 800 are shown in Figure 800. Figure 800 shows a waveform 814 representing the DTD measurement signal 814 plotted over time. In this particular example, the lines superimposed on the waveform 814 illustrate an upper threshold of 50 mV TH1 and a lower threshold of -50 mV TH2. However, TH1 and TH2 can be programmed for specific applications and ill-conditioning modes. Furthermore, in this example, an ill-conditioning mode is detected when the DTD measurement value 814 drops to approximately -75 mV. However, good data is detected when the DTD measurement value 814 has an average value of approximately 0 V.

[0086] Figure 10 An example signal conditioning circuit system 1000 with a data conversion tracking circuit system is depicted as another example of an analog implementation. Specifically, circuit 1000 includes a slicer 1020 as a data unit extraction circuit system, a delay line 1022 as a data unit delay circuit system, and a data conversion tracking circuit system 824 (as referenced above). Figure 8 (As described). In this example implementation, circuit system 1000, together with the re-driver circuit, serves as a distortion compensation circuit system, wherein slicer 1020 receives an equalization signal EQ containing data. OUT This is used to generate a sequence of data units (in this case, a bit sequence). The slicer 1020 can be referenced as above. Figure 3 Implemented as described in block 120.

[0087] Slicer 1020 Amplification and Clipping EQ OUTThe "recovered" data bits are output. This high-speed serial data stream is provided to delay line 1022 and data conversion tracking circuit system 824. Delay line 1022 delays each bit in the serial data stream by 1 UI. Delay line 1022 outputs the delayed data bit as the previous data unit to data conversion tracking circuit system 824. Data conversion tracking circuit system 824 is referenced above. Figure 8 The data stream and the delayed data stream are processed as described to indicate good data or pathological patterns in G. TRIG The signal is output to the distortion compensation circuit system. In this example, relative to... Figure 4 The examples given in the text make G TRIG The polarity reversal.

[0088] Figure 11 An example signal conditioning circuit system 1100 with a data conversion tracking circuit system is described as another example simulation implementation. Specifically, circuit system 1100 includes a sampler 1120 as a data unit extraction circuit system, a UI delay circuit system 1122 as a data unit delay circuit system, and a data conversion tracking circuit system 1124. In this example implementation, circuit system 1100, together with a retimer circuit, serves as a distortion compensation circuit system, wherein sampler 1120 receives an equalization signal EQ containing data. OUT Both the phase-aligned clock signal from clock generator 1130 and the clock signal from clock generator 1130 are used to generate a sequence of data cells (in this case, a bit sequence). For example, clock generator 1130 is a local VCO within the CDR of a retimer circuit. Sampler 1120 can be referenced as above. Figure 3 Implemented as described in block 120.

[0089] Therefore, every UI or every data cycle, sampler 1120 samples the data center on the rising edge of the phase-aligned clock signal to output a new data bit. This high-speed serial data stream is provided to delay circuit system 1122 and data conversion tracking circuit system 1124. Delay circuit system 1122 delays each bit in the serial data stream by 1 UI. Delay circuit system 1122 outputs the delayed data bit as the previous data unit to data conversion tracking circuit system 1124. In one example, delay circuit system 1122 is implemented using D flip-flops.

[0090] The data conversion tracking circuit system 1124 comprises an analog circuit system including an XOR gate 1102, a low-pass filter 1104, and a comparator circuit system 1106. The low-pass filter 1104 may be implemented as an RC circuit having at least one resistor and one capacitor. The comparator circuit system 1106 includes a full-wave (FW) rectifier 1108 and an analog comparator 1110.

[0091] As illustrated, one input of XOR gate 1102 is coupled to the output of sampler 1120. The other input of XOR gate 1102 is coupled to the output of delay circuit system 1122. The output of XOR gate 1102 is coupled to the input of low-pass filter 1104. The output of low-pass filter 1104 is coupled to the input of low-FW rectifier 1108. The output of FW rectifier 1108 is coupled to one input of comparator 1110. The other input of comparator 1110 is coupled to receive an upper threshold TH1. Threshold TH1 can be programmed into a register coupled to comparator 1110 or some other memory device (not shown). G is provided at the output of comparator 1110. TRIG Signal.

[0092] XOR gate 1102 performs an XOR operation between each bit and the previous bit, and provides the resulting XOR. OUT Signal. Low-pass filter 1104 based on the time constant of low-pass filter 1104 for XOR. OUT The signal is time-averaged to generate a time-averaged signal. FW rectifier 1108 rectifies any negative voltage in the time-averaged signal to a positive voltage to generate the DTD measurement. Comparator 1110 compares the DTD measurement with TH1, and asserts, for example, that a high G is provided when the DTD measurement is greater than TH1. TRIG Signal. Otherwise, comparator 1110 is deasserted, thus providing low G. TRIG Signal. Low G TRIG The signal indicates good data to the distortion compensation circuit system. High G TRIG The signal indicates the ill-conditioned mode to gating the distortion compensation circuitry system for adaptation. In this example, relative to... Figure 4 The examples given in the text make G TRIG The polarity reversal.

[0093] Figure 12 An example signal conditioning circuit system 1200 with a data conversion tracking circuit system is described as an example of a mixed analog and digital implementation. Specifically, the circuit system 1200 includes a sampler 1220 as a data unit extraction circuit system, a UI delay circuit system 1222 as a data unit delay circuit system, and a data conversion tracking circuit system 1224. In this example implementation, the circuit system 1200, together with a retimer circuit, serves as a distortion compensation circuit system, wherein the sampler 1220 receives an equalization signal EQ containing data. OUT Both the phase-aligned clock signal from clock generator 1230 and the clock signal from clock generator 1230 are used to generate a sequence of data cells (in this case, a bit sequence). For example, clock generator 1230 is a local VCO within the CDR of a retimer circuit. Sampler 1220 can be referenced as above. Figure 3 Implemented as described in block 120.

[0094] Therefore, every UI or every data cycle, sampler 1220 samples the data center on the rising edge of the phase-aligned clock signal to output a new data bit. This high-speed serial data stream is provided to delay circuit system 1222 and data conversion tracking circuit system 1224. Delay circuit system 1222 delays each bit in the serial data stream by 1 UI. Delay circuit system 1222 outputs the delayed data bit as the previous data unit to data conversion tracking circuit system 1224. In one example, delay circuit system 1222 is implemented using D flip-flops.

[0095] The data conversion tracking circuit system 1224 comprises an analog circuit system including an XOR gate 1202, a low-pass filter 1204, and a digital comparator circuit system 1206. The low-pass filter 1204 is implemented as a high-speed counter, providing an interface between the high-speed analog domain and the low-speed digital domain. The comparator circuit system 1206 includes two digital comparators 1208 and 1210, and an AND gate 1212.

[0096] As illustrated, one input of XOR gate 1202 is coupled to the output of sampler 1220. The other input of XOR gate 1202 is coupled to the output of delay circuit system 1222. The output of XOR gate 1202 is coupled to the input of counter 1204. The output of counter 1204 is coupled to one input of comparator 1208 and one input of comparator 1210. The other input of comparator 1208 is coupled to receive the upper threshold TH1. The other input of comparator 1210 is coupled to receive the lower threshold TH2. Thresholds TH1 and TH2 can be programmed into registers coupled to comparators 1208 and 1210 or some other memory device (not shown). The outputs of comparators 1208 and 1210 are coupled to the input of AND gate 1212, and a G is provided at the output of AND gate 1212. TRIG Signal.

[0097] XOR gate 1202 performs an XOR operation between each bit and the previous bit, and provides the result XOR. OUT Signal. Counter 1204 is based on the time constant of counter 1204 for XOR. OUT Time averaging is performed to generate a DTD signal or measurement value. That is, XOR. OUT The signal is accumulated in counter 1204 until a read and clear signal is provided to counter 1204. The read and clear signal causes the current accumulation to be output from counter 1204 as the DTD measurement value 446, and clears counter 1204.

[0098] Comparator 1208 compares the DTD measurement value with TH1, and when the DTD measurement is less than TH1, it asserts, for example, by providing a high signal (1). Otherwise, comparator 1208 is deasserted, thus providing a low signal (0). Comparator 1210 compares the DTD measurement value with TH2, and when the DTD measurement value is greater than TH2, it asserts, for example, by providing a high signal (1). Otherwise, comparator 1210 is deasserted, thus providing a low signal (0).

[0099] When the output signals of both comparators are high, AND gate 1212 asserts, for example, by providing high G. TRIG Signal (1), indicating "good" data, means the data type that allows the distortion compensation circuit system to operate correctly and adaptively. Therefore, high G... TRIG The signal sends a signal to the distortion compensation circuit system to continue operating in an adaptive manner. Conversely, when one or both of the output signals from the comparator are low, AND gate 1212 is de-asserted, thereby providing a low G. TRIG Signal (0). Low G TRIG The signals indicate the ill-conditioned mode and thus allow the distortion compensation circuitry system to be selected. TH1 and TH2 are application-specific and implementation-specific. In one example, TH1 and TH2 are determined by the amount of averaging performed by counter 1204.

[0100] Figure 13 A flowchart illustrating an example method 1300, which includes a data conversion and tracking circuit system and a signal conditioning circuit system, is provided. For example, method 1300 can be implemented in... Figures 1 to 4 Implemented in one or more of the circuit systems (or portions thereof) shown in 8 and 10 to 12.

[0101] According to method 1300, in blocks 1302 and 1304, a circuit system (e.g., a distortion compensation circuit system) receives a signal and extracts a sequence of data units from the signal. For example, the data unit extraction circuit system receives an equalization signal EQ. OUT The data units are extracted using the sampler in the re-timer implementation or the slicer in the re-driver implementation. The data units can be used as CTRL. IN Provided to the data unit delay circuit system and the data conversion and tracking circuit system.

[0102] In box 1306, the data cell delay circuitry system generates the preceding data cells. In one instance, a flip-flop or delay line generates a delayed data stream. In another instance, a deserializer generates multiple parallel data streams.

[0103] In block 1308, a logic circuit system compares one or more data units with one or more preceding data units and provides one or more logic outputs. In one instance, a single XOR gate compares a data unit with preceding data units from a data stream and a single delayed data stream to produce a single XOR output. In another instance, a group of XOR gates compares data units with preceding data units from a parallel data stream and outputs multiple XOR outputs.

[0104] In block 1310, the low-pass filter generates a time-averaged signal (DTD measurement) based on one or more logic output signals. In one example, the low-pass filter is an analog circuit, such as an RC circuit or a counter, that receives a single XOR output and provides a time-averaged signal. In another example, the low-pass filter is a digital circuit that includes a summer and integrator and dump circuitry, which receives multiple XOR outputs and provides a time-averaged signal.

[0105] In block 1312, the comparator circuitry compares the time-averaged signal with a single threshold, wherein the comparator circuitry includes an FW rectifier, and based on the comparison, indicates a destructive pattern in the data unit sequence. For example, the indication is G. TRIG The signal. In another example, the comparator circuit system compares the time-averaged signal with two thresholds to produce G. TRIG The comparator circuit system can be a digital or analog circuit.

[0106] In box 1314, in response to an indication of a destructive mode (e.g., G... TRIG Select at least a portion of the distortion compensation circuitry system (e.g., distortion compensation circuitry system adaptive). For example, suspend EQ adaptive control, suspend phase-frequency adaptation in the CDR circuit, and / or reset the CDR circuit.

[0107] The foregoing examples illustrate several possible embodiments of various aspects of this disclosure, wherein equivalent changes and / or modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A circuit comprising: an equalizer having an input and an output; a slicer having an input coupled to the output of the equalizer and having an output; a delay line having an input coupled to the output of the slicer and having an output; an exclusive OR gate having a first input coupled to the output of the slicer, having a second input coupled to the output of the delay line, and having an output; a low pass filter having an input coupled to the output of the exclusive OR gate and having an output, the low pass filter configured to provide a data transition density measure of a sequence of data units at the output of the slicer; and comparator circuitry having an input coupled to the output of the low pass filter and having an output coupled to the input of the equalizer, the comparator circuitry configured to compare the data transition density measure to a threshold and to indicate a disruptive pattern in the sequence of data units.

2. The circuit of claim 1, wherein the comparator circuitry comprises: a first comparator having an input coupled to the output of the low pass filter and having an output; a second comparator having an input coupled to the output of the low pass filter and having an output; and a logic gate having a first input coupled to the output of the first comparator and having a second input coupled to the output of the second comparator.

3. The circuit of claim 2, wherein the logic gate is an OR gate.

4. A circuit comprising: an equalizer having an input and an output; a sampler or slicer having an input coupled to the output of the equalizer and having an output; a deserializer having an input coupled to the output of the sampler or slicer and having an output; an exclusive OR gate having an input coupled to the output of the deserializer and having an output; a digital low pass filter having an input coupled to the output of the exclusive OR gate and having an output, the low pass filter configured to provide a data transition density measure of a sequence of data units at the output of the sampler or slicer; and comparator circuitry having an input coupled to the output of the low pass filter and having an output coupled to the input of the equalizer, the comparator circuitry configured to compare the data transition density measure to a threshold and to indicate a disruptive pattern in the sequence of data units.

5. The circuit of claim 4, wherein the digital low pass filter comprises: a summer circuit coupled to the output of the logic circuitry and having an output; and an accumulator having an input coupled to the output of the summer circuit.

6. The circuit of claim 5, wherein the digital low pass filter comprises a switch coupling the accumulator to the input of the comparator circuitry.

7. The circuit of claim 6, wherein the digital low pass filter comprises a right shifter coupled between the accumulator output and the input of the comparator circuitry.

8. The circuit of claim 7, wherein the logic gate is an AND gate.

9. The circuit of claim 4, wherein the comparator circuitry comprises: a first comparator having an input coupled to the output of the digital low pass filter and having an output; a second comparator having an input coupled to the output of the digital low pass filter and having an output; and a logic gate having a first input coupled to the output of the first comparator and having a second input coupled to the output of the second comparator.

10. A circuit comprising: an equalizer having an input and an output; a sampler having an input coupled to the output of the equalizer and having an output; delay circuitry having an input coupled to the output of the sampler and having an output; an exclusive OR gate having a first input coupled to the output of the sampler, having a second input coupled to the output of the delay circuitry, and having an output; a low pass filter having an input coupled to the output of the exclusive OR gate and having an output, the low pass filter configured to provide a data transition density measure of a sequence of data units at the output of the sampler; and comparator circuitry having an input coupled to the output of the low pass filter and having an output coupled to the input of the equalizer, the comparator circuitry configured to compare the data transition density measure to a threshold and to indicate a disruptive pattern in the sequence of data units.

11. The circuit of claim 10, wherein the delay circuitry comprises 1 UI of delay circuitry.

12. The circuit of claim 10, wherein the comparator circuitry comprises: a first comparator having an input coupled to the output of the low pass filter and having an output; a second comparator having an input coupled to the output of the low pass filter and having an output; and a logic gate having a first input coupled to the output of the first comparator and having a second input coupled to the output of the second comparator.

13. The circuit of claim 12, wherein the logic gate is an OR gate.

14. The circuit of claim 12, wherein the logic gate is an AND gate.

15. The circuit of claim 14, wherein the low pass filter comprises a counter.

16. The circuit of claim 15, wherein the low pass filter is an analog circuit and the comparator circuitry is digital circuitry.

17. The circuit of claim 10, wherein the comparator circuitry comprises: a comparator having an input; and a rectifier circuit coupled between the output of the low pass filter and the input of the comparator. ​ ​ ​

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