A depletion-mode GaN chip with internally integrated diodes and its cascaded device

Abstract

This invention belongs to the field of semiconductor technology, specifically disclosing a depletion-mode GaN chip with an internally integrated diode and a cascaded device. The GaN chip includes a GaN body structure and a diode structure. The GaN body structure has a source electrode, a drain electrode, and a gate electrode. The gate electrode of the GaN body structure is connected to the positive or negative electrode of the diode structure. The diode structure includes a cathode ohmic metal and an anode metal. The anode metal includes an anode Schottky metal, or the anode metal includes multiple anode Schottky metals and anode ohmic metals arranged alternately and at intervals along the same horizontal direction. The forward conduction resistance of the diode structure is less than the reverse conduction resistance of the diode structure. The turn-on speed and turn-off speed of the cascaded device obtained by cascading the depletion-mode GaN chip of this invention with an enhancement-mode MOS chip can be adjusted separately.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a depletion-mode GaN chip with an internally integrated reverse high leakage diode and a cascaded device including the depletion-mode GaN chip. Background Technology

[0002] Currently, cascaded GaN power devices are widely used in various switching power supplies, especially in industrial and automotive applications, where they offer certain advantages. However, because the gate electrode of depletion-mode GaN is often directly wire-connected to the source electrode in the package, cascaded devices are difficult to adjust. In application, the switching speed is only adjusted by the gate drive resistor of the low-voltage enhancement-mode device, resulting in weak regulation capability. Therefore, cascaded devices often exhibit excessively fast switching speeds, leading to difficulties in electromagnetic interference (EMI) regulation, and in severe cases, waveform oscillation or even device failure. To address this issue, some industry experts have proposed designing a drive resistor at the GaN gate to reduce the switching speed; others have designed a dual-parallel configuration, with one path consisting of a diode and a relatively low resistor in series, and the other a relatively high resistor, to achieve separate adjustment of the GaN turn-on and turn-off speeds.

[0003] However, designing a drive resistor solely at the gate of GaN cannot meet the requirement of individually adjusting the switching speed. In the dual-parallel scheme, a low-resistance series diode is used as one branch, and a relatively high-resistance diode is used as another branch. The diode structure in this scheme is not easy to implement on D-mode GaN chips, and there are certain process incompatibilities, making the manufacturing process more cumbersome and complicated. Summary of the Invention

[0004] In view of this, in order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a depletion-mode GaN chip with an internally integrated diode and a cascaded device, wherein the turn-on speed and turn-off speed of the cascaded device can be adjusted separately.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] This invention provides a depletion-mode GaN chip with an internally integrated diode, comprising a GaN body structure and a diode structure. The GaN body structure has a source electrode, a drain electrode, and a gate electrode. The gate electrode of the GaN body structure is connected to the positive or negative electrode of the diode structure. The diode structure includes a cathode ohmic metal and an anode metal. The anode metal includes an anode Schottky metal, or the anode metal includes multiple anode Schottky metals and multiple anode ohmic metals arranged alternately and at intervals along the same horizontal direction. The forward conduction resistance of the diode structure is less than the reverse conduction resistance of the diode structure, and the reverse leakage current of the diode structure when reverse conduction is 0.0005-10A.

[0007] This invention integrates a diode structure with high reverse leakage current (0.0005-10A) within a depletion-mode GaN chip. This leakage current is higher than that of the existing dual-parallel design where a low-resistance series diode is used as one branch. The diode structure exhibits low resistance during forward conduction and high leakage current during reverse conduction (i.e., it also exhibits a certain range of resistance during reverse conduction). One electrode of the diode structure is connected to the gate electrode of the GaN main structure, and the other electrode is connected to the gate electrode of the cascaded device formed after packaging. This allows for separate adjustment of the turn-on and turn-off speeds of the cascaded device, thereby improving electromagnetic radiation in practical applications and effectively controlling power loss.

[0008] According to some preferred embodiments of the present invention, the reverse voltage of the diode structure during reverse conduction is 0-100V, and the ratio of the reverse conduction resistance to the forward conduction resistance of the diode structure is 5-1000:1. In some embodiments of the present invention, the ratio of the reverse conduction resistance to the forward conduction resistance of the diode structure is preferably 20-100:1.

[0009] According to some preferred embodiments of the present invention, the substrate, the stacked structure, the first dielectric layer, the second dielectric layer and the third dielectric layer are arranged sequentially from bottom to top. The stacked structure includes at least a channel layer and a barrier layer arranged sequentially from bottom to top. The cathode ohmic metal is located in the stacked structure and the first dielectric layer. The anode metal is at least partially located in the stacked structure, the first dielectric layer and the second dielectric layer. An anode hole is formed in the stacked structure along its thickness direction. The bottom of the anode metal is located in the anode hole.

[0010] According to some preferred embodiments of the present invention, when the anode metal comprises an anode Schottky metal, the anode Schottky metal is entirely located in the stacked structure, the first dielectric layer, and the second dielectric layer.

[0011] According to some preferred embodiments of the present invention, when the anode metal comprises a plurality of anode Schottky metals and a plurality of anode ohmic metals, the anode ohmic metals are located in the stacked structure and the first dielectric layer, the anode Schottky metals are located in the stacked structure, the first dielectric layer and the second dielectric layer, and the area of ​​the orthogonal projection of the anode ohmic metals on the substrate is smaller than the area of ​​the orthogonal projection of the anode Schottky metals on the substrate.

[0012] According to some preferred embodiments of the present invention, the area of ​​the orthographic projection of the anode ohmic metal onto the substrate accounts for 0.01% to 50% of the total area of ​​the orthographic projection of the anode metal onto the substrate.

[0013] According to some preferred embodiments of the present invention, the portion of the anode Schottky metal located in the anode hole is in direct contact with the sidewall of the anode hole, such that the width of the contact area between the anode Schottky metal and the underlying channel layer is equal to the width of the anode hole. In some embodiments of the present invention, the positive electrode of the diode structure adopts a large-area Schottky contact, that is, the anode metal of the diode structure only includes the anode Schottky metal. Since there is no dielectric layer on the sidewall of the anode hole corresponding to the anode Schottky contact area in this scheme, the area of ​​the Schottky contact (the Schottky contact formed between the anode Schottky metal and the underlying channel layer) is larger, thereby enabling the diode structure to exhibit low resistance characteristics during forward conduction and high leakage current during reverse conduction; it can also increase the reverse leakage current of the Schottky contact area, making the leakage current distribution during reverse conduction of the diode structure relatively uniform, thereby improving the power handling capability of the device.

[0014] According to some preferred embodiments of the present invention, the sidewall of the anode hole is filled with a first dielectric layer, and the portion of the anode Schottky metal located in the anode hole contacts the first dielectric layer in the anode hole, such that the width of the contact area between the anode Schottky metal and the underlying channel layer is smaller than the width of the anode hole. In other embodiments of the present invention, the positive electrode of the diode structure employs a combination of partial ohmic contact and partial Schottky contact instead of purely Schottky contact; that is, the anode metal of the diode structure includes alternating and spaced anode ohmic metal and anode Schottky metal. This allows the diode structure to exhibit low resistance during forward conduction and high leakage current during reverse conduction. The structural design of the anode metal in this scheme ensures that almost all the leakage current during reverse conduction flows through the anode ohmic contact area, resulting in more precise control of the leakage current during reverse conduction.

[0015] According to some preferred embodiments of the present invention, the diode structure is provided with a first metal connection portion and a second metal connection portion;

[0016] The bottom ends of the first metal connection are respectively connected to the top of the gate electrode of the GaN main structure and one end of the top of the cathode ohmic metal of the diode structure, and the bottom of the second metal connection is connected to the top of the anode metal of the diode structure; or, the bottom ends of the first metal connection are respectively connected to the top of the gate electrode of the GaN main structure and the top of the anode metal of the diode structure, and the bottom of the second metal connection is connected to one end of the top of the cathode ohmic metal of the diode structure. In this invention, the source electrode of the GaN main structure is the source electrode of the entire GaN chip, and the drain electrode of the GaN main structure is the drain electrode of the entire GaN chip. The introduction of the diode structure in the GaN chip is equivalent to connecting a diode in series on the gate electrode of the GaN main structure. The setting of the first metal connection part allows one of the positive and negative electrodes of the diode structure to be connected to the gate electrode of the GaN main structure, so that the other electrode of the diode structure that is not connected to the gate electrode of the GaN main structure becomes the gate electrode of the entire GaN chip. By setting a second metal connection part connected to this electrode, the second metal connection part becomes equivalent to the gate electrode of the entire GaN chip. It is mainly used to control the turn-on and turn-off of the entire GaN chip. Finally, when the cascaded device is packaged, the second metal connection part will be connected to the source electrode of the cascaded device.

[0017] The present invention also provides a cascaded device, including the depletion-mode GaN chip as described above. The cascaded device is obtained by cascading and packaging the depletion-mode GaN chip and the enhancement-mode MOS chip. One of the positive and negative electrodes of the diode structure in the depletion-mode GaN chip is connected to the gate electrode of the GaN body structure, and the other electrode of the diode structure is connected to the source electrode of the cascaded device.

[0018] Compared with the prior art, the advantages of this invention due to the adoption of the above technical solutions are as follows: The depletion-mode GaN chip and cascaded device with an internally integrated diode of this invention, by integrating a diode structure inside the depletion-mode GaN chip, and through the cooperation of the diode structure and the GaN main body structure, enables the diode structure of this invention to exhibit low resistance during forward conduction and high leakage current during reverse conduction; furthermore, after cascading and packaging the depletion-mode GaN chip of this invention with an enhancement-mode MOS chip, the turn-on speed and turn-off speed of the resulting cascaded device can be adjusted separately, thereby improving electromagnetic radiation in practical applications, and also reasonably controlling the power loss of the device. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a top view of the depletion-type GaN chip in Embodiment 1 of the present invention;

[0021] Figure 2 This is a top view of the depletion-type GaN chip in Embodiment 2 of the present invention;

[0022] Figure 3 This is a top view of the depletion-type GaN chip in Embodiment 3 of the present invention;

[0023] Figure 4 This is a top view of the depletion-type GaN chip in Embodiment 4 of the present invention;

[0024] Figure 5 for Figure 1 A schematic diagram of the cross-section along the direction of the dashed line A;

[0025] Figure 6 for Figure 1 A schematic diagram of the cross-section along the direction of the dashed line B;

[0026] Figure 7 for Figure 1 A schematic diagram of the cross-section along the direction of the dashed line C;

[0027] Figure 8 for Figure 2 A schematic diagram of the cross-section along the direction of the dashed line D;

[0028] Figure 9 for Figure 3 A schematic diagram of the cross-section along the direction of the dashed line E;

[0029] Figure 10 for Figure 4 A schematic diagram of the cross-section along the direction of the dashed line F;

[0030] Figure 11 When preparing the depletion-type GaN chip in Example 1 using the preparation method of Example 5, after completing step 3... Figure 1 A cross-sectional diagram along the direction of the dashed line A in the diagram;

[0031] Figure 12 When preparing the depletion-type GaN chip in Example 1 using the preparation method of Example 5, after completing step 3... Figure 1 A cross-sectional diagram along the direction of the dashed line B in the diagram;

[0032] Figure 13 When preparing the depletion-type GaN chip in Example 1 using the preparation method of Example 5, after completing step 4 of depositing the first dielectric layer, along... Figure 1 A cross-sectional diagram along the direction of the dashed line A in the diagram;

[0033] Figure 14 When preparing the depletion-type GaN chip in Example 1 using the preparation method of Example 5, after completing step 4 of forming the first via and gate trench, the... Figure 1 A cross-sectional diagram along the direction of the dashed line A in the diagram;

[0034] Figure 15 When preparing the depletion-type GaN chip in Example 1 using the preparation method of Example 5, after completing step 5... Figure 1 A cross-sectional diagram along the direction of the dashed line A in the diagram;

[0035] Figure 16 This is a schematic diagram of the current distribution when the diode structure is forward-biased in Embodiment 1 of the present invention;

[0036] Figure 17 This is a schematic diagram of the current distribution when the diode structure is reverse-biased in Embodiment 1 of the present invention;

[0037] Figure 18 This is a schematic diagram of the current distribution when the diode structure is forward-biased in Embodiment 3 of the present invention;

[0038] Figure 19 This is a schematic diagram of the current distribution when the diode structure is reverse-biased in Embodiment 3 of the present invention;

[0039] Figure 20 The diagram shows the IV curves of the diode structure in Embodiment 1 of the present invention during forward conduction (first quadrant) and reverse conduction (third quadrant).

[0040] Figure 21 The image shows the IV curves of the diode structure in Embodiment 3 of the present invention during forward conduction (first quadrant) and reverse conduction (third quadrant).

[0041] The attached figures are labeled as follows:

[0042] GaN main structure - 100, diode structure - 200, active region - 300, source electrode - 1, drain electrode - 2, gate electrode - 3, gate and first field plate - 4, gate connection - 5, source electrode ohmic metal - 6, drain electrode ohmic metal - 7, second field plate - 8, first metal connecting strip - 9, second metal connecting strip - 10, substrate - 11, channel layer - 12, barrier layer - 13, capping layer - 14, first dielectric layer - 15, second dielectric layer - 16, third dielectric layer - 17, cathode ohmic metal - 18, anode Schottky metal - 19, anode ohmic metal - 20, first connection body - 21, first connection branch - 22, second connection branch - 23, second connection body - 24, third connection branch - 25, anode hole - 26, first through hole - 27, gate trench - 28. Detailed Implementation

[0043] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0044] Example 1: This example provides a cascaded device, which is obtained by cascading and packaging a depletion-mode GaN chip and an enhancement-mode MOS chip. Wherein, as... Figure 1 As shown, the depletion-mode GaN chip includes a GaN main structure 100 and a diode structure 200 both located in the active region 300. The diode structure 200 is integrated inside the GaN chip and works in conjunction with the GaN main structure 100 to achieve separate adjustment of the turn-on speed and turn-off speed of the cascaded devices.

[0045] Further, the GaN main structure 100 of this embodiment includes a source electrode 1, a drain electrode 2, a gate module, a source electrode ohmic metal 6, a drain electrode ohmic metal 7, a second field plate 8, a first metal connecting strip 9, a second metal connecting strip 10, and a substrate 11, a stacked structure, a first dielectric layer 15, a second dielectric layer 16, and a third dielectric layer 17 arranged sequentially from bottom to top. The gate module includes a gate and a first field plate 4, a gate connection portion 5, and a gate electrode 3. Multiple gates and first field plates 4 are provided. The gate connection portion 5 is used to connect all the gates and the first field plate 4. The gate electrode 3 is connected to the end of the gate connection portion 5 away from the gate and the first field plate 4. The first metal connecting strip 9 is used to connect the source electrode 1 and the source electrode ohmic metal 6, and the second metal connecting strip 10 is used to connect the drain electrode 2 and the drain electrode ohmic metal 7.

[0046] Specifically, the stacked structure of this embodiment includes a channel layer 12, a barrier layer 13, and a capping layer 14 arranged sequentially from bottom to top. The source electrode 1 and drain electrode 2 are both located on the side of the third dielectric layer 17 away from the second dielectric layer 16. The source electrode 1 is located above the source electrode ohmic metal 6, and the drain electrode 2 is located above the drain electrode ohmic metal 7. Both the source electrode ohmic metal 6 and the drain electrode ohmic metal 7 are located within the barrier layer 13, the capping layer 14, and the first dielectric layer 15. The first metal connecting strip 9 and the second metal connecting strip 10 both penetrate the thickness direction of the first dielectric layer 15, the second dielectric layer 16, and the third dielectric layer 17. The two ends of the first metal connecting strip 9 are respectively connected to the bottom of the source electrode 1 and the top of the source electrode ohmic metal 6, and the two ends of the second metal connecting strip 10 are respectively connected to the bottom of the drain electrode 2 and the top of the drain electrode ohmic metal 7. The gate and the first field plate 4 are located within the first dielectric layer 15 and the second dielectric layer 16, and the second field plate 8 is located within the second dielectric layer 16 and the third dielectric layer 17.

[0047] Furthermore, such as Figure 1 , Figure 5 and Figure 6 As shown, the diode structure 200 includes a cathode ohmic metal 18 and an anode metal. In this embodiment, the anode metal includes multiple anode Schottky metals 19 and multiple anode ohmic metals 20, which are arranged alternately and at intervals along the same horizontal direction parallel to the length of the substrate 11. The cathode ohmic metal 18 is located in the barrier layer 13, the capping layer 14, and the first dielectric layer 15; the anode ohmic metal 20 is located in the barrier layer 13, the capping layer 14, and the first dielectric layer 15; and the anode Schottky metal 19 is located in the barrier layer 13, the capping layer 14, the first dielectric layer 15, and the second dielectric layer 16.

[0048] A first metal connection is provided between the gate electrode 3 of the GaN main structure 100 and one end of the diode structure 200. A second metal connection is also provided on the diode structure 200. An anode Schottky metal 19 is connected to an adjacent anode Ohmic metal 20 through the second metal connection. Specifically, as... Figure 1 and Figure 7As shown, the first metal connection portion includes a first connection portion body 21 and a first connection branch 22 and a second connection branch 23 disposed at both ends of the bottom surface of the first connection portion body 21; the second metal connection portion includes a second connection portion body 24 and a plurality of third connection branches 25 disposed on the bottom surface of the second connection portion body 24. The plurality of third connection branches 25 are disposed corresponding to the anode Schottky metal 19 and the anode ohmic metal 20. The first connection portion body 21 is located on the side of the third dielectric layer 17 away from the second dielectric layer 16, and the orthographic projection of the first connection portion body 21 on the substrate 11 coincides with the orthographic projection of the gate electrode 3 and the cathode ohmic metal 18 of the GaN main structure 100 on the substrate 11. The bottom of the first connecting branch 22 is connected to the top of the gate electrode 3 of the GaN main structure 100, and the bottom of the second connecting branch 23 is connected to one end of the top of the cathode ohmic metal 18. The second connecting body 24 is located on the side of the third dielectric layer 17 away from the second dielectric layer 16. The bottom of the third connecting branch 25 corresponding to the anode Schottky metal 19 is connected to the top of the anode Schottky metal 19, and the bottom of the third connecting branch 25 corresponding to the anode ohmic metal 20 is connected to the top of the anode ohmic metal 20. The top of the second connecting body 24 is connected to the source electrode of the cascaded device. In this embodiment, the second connecting body 24 is mainly used to control the turn-on and turn-off of the entire GaN chip. It is equivalent to the gate electrode of the entire GaN chip. The source electrode 1 of the GaN main structure 100 is equivalent to the source electrode of the entire GaN chip, and the drain electrode 2 of the GaN main structure 100 is equivalent to the drain electrode of the entire GaN chip.

[0049] Specifically, in this embodiment, the diode structure 200 is positively connected to the GaN main structure 100, that is, the negative terminal of the diode structure 200 is connected to the gate electrode 3 of the GaN main structure 100, and the positive terminal of the diode structure 200 is connected to the source electrode of the cascaded device. For example... Figure 16 As shown, when diode structure 200 is forward-biased, some current flows from the anode Schottky metal 19 to the cathode Ohm metal 18, and some current flows from the anode Ohm metal 20 to the cathode Ohm metal 18; as Figure 17As shown, during reverse conduction, the current flowing from the negative terminal to the positive terminal is mainly from the cathode ohmic metal 18 to the anode ohmic metal 20, while the current flowing from the cathode ohmic metal 18 to the anode Schottky metal 19 is very small. In this embodiment, the forward conduction resistance of diode structure 200 is 10Ω, the reverse conduction resistance of diode structure 200 is 200Ω, the reverse leakage current of diode structure 200 during reverse conduction is 0.25A, and the reverse voltage of diode structure 200 during reverse conduction is 50V. By connecting diode structure 200 in the forward direction, the voltage division control of low-voltage MOS devices can be achieved within a safe range, while extending the turn-on time of cascaded devices and shortening the turn-off time. When the device is turned on, the drive current flows into the positive terminal and out the negative terminal of diode structure 200, and when the device is turned off, the drive current flows into the negative terminal and out the positive terminal of diode structure 200, which helps to make the device turn on faster and is more suitable for high-power half-bridge circuits.

[0050] Furthermore, in this embodiment, the area of ​​the orthogonal projection of the anode ohmic metal 20 onto the substrate 11 of the diode structure 200 is smaller than the area of ​​the orthogonal projection of the anode Schottky metal 19 onto the substrate 11, and the percentage of the orthogonal projection area of ​​the anode ohmic metal 20 onto the substrate 11 to the total orthogonal projection area of ​​the anode metal onto the substrate 11 is 2%. In the stacked structure, an anode hole 26 penetrating the thickness of the barrier layer 13 and the capping layer 14 is formed along its thickness direction. In this embodiment, the sidewall of the anode hole 26 is filled with a first dielectric layer 15, such as... Figure 5 As shown, the bottoms of the anode ohmic metal 20 and the anode Schottky metal 19 are both located in the anode hole 26, and the portion of the anode Schottky metal 19 located in the anode hole 26 is in contact with the first dielectric layer 15 in the anode hole 26, such that the width of the contact area between the anode Schottky metal 19 and the channel layer 12 below is smaller than the width of the anode hole 26.

[0051] In this embodiment, the positive electrode of the diode structure 200 adopts a combination of local ohmic and local Schottky contacts, which allows the diode structure 200 to exhibit low resistance during forward conduction and high leakage current during reverse conduction. Figure 20 As shown, the IV curve in the first quadrant corresponds to the forward conduction of diode structure 200, and the IV curve in the third quadrant corresponds to the reverse conduction of diode structure 200. Figure 20 This confirms that the diode structure 200 of this embodiment can conduct in reverse, and it can also exhibit a certain range of resistance values ​​when reverse-biased. By setting the width of the contact area between the anode Schottky metal 19 and the underlying channel layer 12 to be smaller than the width of the anode hole 26, the reverse leakage current of the Schottky contact area can be reduced. This allows the leakage current of the diode structure 200 when reverse-biased to almost entirely flow through the anode ohmic contact area, making the leakage current control during reverse conduction more precise.

[0052] Example 2: This example provides a cascaded device, which is obtained by cascading and packaging a depletion-mode GaN chip and an enhancement-mode MOS chip. The cascaded device in this example is basically the same as the cascaded device in Example 1, except that the diode structure 200 in this example is reverse-connected in the GaN main body structure 100, that is, the positive terminal of the diode structure 200 is connected to the gate electrode 3 of the GaN main body structure 100, and the negative terminal of the diode structure 200 is connected to the source electrode of the cascaded device. In addition, the first metal connection part and the second metal connection part in this example are different from those in Example 1. The first metal connection part in this example is located on the gate electrode 3 of the GaN main body structure 100 and the anode metal of the diode structure 200, and the second metal connection part is located at one end of the cathode ohmic metal 18 of the diode structure 200. An anode Schottky metal 19 is connected to an adjacent anode ohmic metal 20 through the first metal connection part.

[0053] Specifically, such as Figure 2 and Figure 8 As shown, the first metal connection portion of this embodiment includes a first connection portion body 21, a first connection branch 22 disposed on the bottom surface of the first connection portion body 21, and a plurality of second connection branches 23. The plurality of second connection branches 23 are disposed corresponding to the anode Schottky metal 19 and the anode ohmic metal 20. The second metal connection portion includes a second connection portion body 24 and a third connection branch 25 disposed in the middle of the bottom surface of the second connection portion body 24. The orthographic projection of the first connection portion body 21 on the substrate 11 of the first metal connection portion partially overlaps with the gate electrode 3 of the GaN main structure 100 and covers the orthographic projection of the anode metal on the substrate 11. The bottom of the first connection branch 22 is connected to the top of the gate electrode 3 of the GaN main structure 100. The bottom of the second connection branch 23 corresponding to the anode Schottky metal 19 is connected to the top of the anode Schottky metal 19. The bottom of the second connection branch 23 corresponding to the anode ohmic metal 20 is connected to the top of the anode ohmic metal 20. The bottom of the third connection branch 25 is connected to the top of the cathode ohmic metal 18.

[0054] In this embodiment, by reversing the diode structure 200, the voltage division control of the low-voltage MOS device can be controlled to a safe range, while extending the turn-on time of the cascaded device and shortening the turn-off time. Furthermore, when reversed, the drive current when the device is turned on flows into the negative terminal of the diode and flows out from the positive terminal, while the drive current when the device is turned off flows into the positive terminal of the diode structure 200 and flows out from the negative terminal, which can make the turn-off speed faster and more suitable for flyback applications.

[0055] Example 3: This example provides a cascaded device, which is obtained by cascading and packaging a depletion-mode GaN chip and an enhancement-mode MOS chip. Wherein, as... Figure 3As shown, the depletion-mode GaN chip includes a GaN main structure 100 and a diode structure 200 both located in the active region 300. The diode structure 200 is integrated inside the GaN chip and works in conjunction with the GaN main structure 100 to achieve separate adjustment of the turn-on speed and turn-off speed of the cascaded devices.

[0056] Further, the GaN main structure 100 of this embodiment includes a source electrode 1, a drain electrode 2, a gate module, a source electrode ohmic metal 6, a drain electrode ohmic metal 7, a second field plate 8, a first metal connecting strip 9, a second metal connecting strip 10, and a substrate 11, a stacked structure, a first dielectric layer 15, a second dielectric layer 16, and a third dielectric layer 17 arranged sequentially from bottom to top. The gate module includes a gate and a first field plate 4, a gate connection portion 5, and a gate electrode 3. Multiple gates and first field plates 4 are provided. The gate connection portion 5 is used to connect all the gates and the first field plate 4. The gate electrode 3 is connected to the end of the gate connection portion 5 away from the gate and the first field plate 4. The first metal connecting strip 9 is used to connect the source electrode 1 and the source electrode ohmic metal 6, and the second metal connecting strip 10 is used to connect the drain electrode 2 and the drain electrode ohmic metal 7.

[0057] Specifically, the stacked structure of this embodiment includes a channel layer 12, a barrier layer 13, and a capping layer 14 arranged sequentially from bottom to top. The source electrode 1 and drain electrode 2 are both located on the side of the third dielectric layer 17 away from the second dielectric layer 16. The source electrode 1 is located above the source electrode ohmic metal 6, and the drain electrode 2 is located above the drain electrode ohmic metal 7. Both the source electrode ohmic metal 6 and the drain electrode ohmic metal 7 are located within the barrier layer 13, the capping layer 14, and the first dielectric layer 15. The first metal connecting strip 9 and the second metal connecting strip 10 both penetrate the thickness direction of the first dielectric layer 15, the second dielectric layer 16, and the third dielectric layer 17. The two ends of the first metal connecting strip 9 are respectively connected to the bottom of the source electrode 1 and the top of the source electrode ohmic metal 6, and the two ends of the second metal connecting strip 10 are respectively connected to the bottom of the drain electrode 2 and the top of the drain electrode ohmic metal 7. The gate and the first field plate 4 are located within the first dielectric layer 15 and the second dielectric layer 16, and the second field plate 8 is located within the second dielectric layer 16 and the third dielectric layer 17.

[0058] Furthermore, the diode structure 200 includes a cathode ohmic metal 18 and an anode metal. In this embodiment, the anode metal only includes an anode Schottky metal 19. The cathode ohmic metal 18 is located in the barrier layer 13, the capping layer 14, and the first dielectric layer 15, while the anode Schottky metal 19 is located in the barrier layer 13, the capping layer 14, the first dielectric layer 15, and the second dielectric layer 16. A first metal connection is provided between the gate electrode 3 of the GaN main structure 100 and one end of the diode structure 200, and a second metal connection is provided at the other end of the diode structure 200. Specifically, as... Figure 3As shown, the first metal connection includes a first connection body 21 and a first connection branch 22 and a second connection branch 23 disposed at both ends of the bottom surface of the first connection body 21; the second metal connection includes a second connection body 24 and a third connection branch 25 disposed in the middle of the bottom surface of the second connection body 24. The first connection body 21 is located on the side of the third dielectric layer 17 away from the second dielectric layer 16, and the orthographic projection of the first connection body 21 on the substrate 11 coincides with the orthographic projection of the gate electrode 3 and the cathode ohmic metal 18 of the GaN main structure 100 on the substrate 11. The bottom of the first connection branch 22 is connected to the top of the gate electrode 3 of the GaN main structure 100, and the bottom of the second connection branch 23 is connected to one end of the top of the cathode ohmic metal 18; the second connection body 24 is located on the side of the third dielectric layer 17 away from the second dielectric layer 16, the bottom of the third connection branch 25 is connected to one end of the top of the anode Schottky metal 19, and the top of the second connection body 24 is connected to the source electrode of the cascaded device. In this embodiment, the second connection body 24 is mainly used to control the opening and closing of the entire GaN chip. It is equivalent to the gate electrode of the entire GaN chip. The source electrode 1 of the GaN main body structure 100 is equivalent to the source electrode of the entire GaN chip, and the drain electrode 2 of the GaN main body structure 100 is equivalent to the drain electrode of the entire GaN chip.

[0059] Specifically, in this embodiment, the diode structure 200 is also positively connected to the GaN main structure 100, that is, the negative terminal of the diode structure 200 is connected to the gate electrode 3 of the GaN main structure 100, and the positive terminal of the diode structure 200 is connected to the source electrode of the cascaded device. For example... Figure 18 As shown, when the diode structure 200 is forward-biased, the current flows uniformly from the anode Schottky metal 19 to the cathode Ohmic metal 18; Figure 19 As shown, during reverse conduction, the current flows uniformly from the cathode ohmic metal 18 to the anode Schottky metal 19. In this embodiment, the forward conduction resistance of diode structure 200 is 15Ω, the reverse conduction resistance of diode structure 200 is 400Ω, the reverse leakage current of diode structure 200 during reverse conduction is 0.125A, and the reverse voltage of diode structure 200 during reverse conduction is 50V. By connecting diode structure 200 in the forward direction, the voltage division control of low-voltage MOS devices can be achieved within a safe range, while extending the turn-on time of cascaded devices and shortening the turn-off time. When the device is turned on, the drive current flows into the positive terminal and out the negative terminal of diode structure 200; when the device is turned off, the drive current flows into the negative terminal and out the positive terminal of diode structure 200, which helps to make the device turn-on faster and is more suitable for high-power half-bridge circuits.

[0060] Furthermore, an anode hole 26 is formed along the thickness direction of the stacked structure, penetrating the thickness of the barrier layer 13 and the capping layer 14. In this embodiment, the sidewall of the anode hole 26 does not have a first dielectric layer 15, such as... Figure 9 As shown, the portion of the anode Schottky metal 19 located in the anode hole 26 is in direct contact with the sidewall of the anode hole 26, such that the width of the contact area between the anode Schottky metal 19 and the underlying channel layer 12 is equal to the width of the anode hole 26. In this embodiment, the positive electrode of the diode structure 200 adopts a large-area Schottky contact, meaning the anode metal of the diode structure 200 only includes the anode Schottky metal 19. Since the sidewall of the anode hole 26 corresponding to the anode Schottky contact area in this scheme has no dielectric layer, the area of ​​the Schottky contact (the Schottky contact formed between the anode Schottky metal 19 and the underlying channel layer 12) is larger, thus enabling the diode structure 200 to exhibit low resistance during forward conduction and high leakage current during reverse conduction. Figure 21 As shown, the IV curve in the first quadrant corresponds to the forward conduction of diode structure 200, and the IV curve in the third quadrant corresponds to the reverse conduction of diode structure 200. Figure 21 This confirms that the diode structure 200 of this embodiment can also conduct in reverse, and it can exhibit a certain range of resistance values ​​when reverse-biased. Furthermore, by setting the width of the contact area between the anode Schottky metal 19 and the underlying channel layer 12 to be equal to the width of the anode hole 26, the reverse leakage current of the Schottky contact area can be relatively increased, making the leakage current distribution of the diode structure 200 relatively uniform when reverse-biased, thereby improving the power handling capability of the device.

[0061] Example 4: This example provides a cascaded device, which is obtained by cascading and packaging a depletion-mode GaN chip and an enhancement-mode MOS chip. The cascaded device in this example is basically the same as the cascaded device in Example 3, except that the diode structure 200 in this example is reversed in the GaN main body structure 100, that is, the positive terminal of the diode structure 200 is connected to the gate electrode 3 of the GaN main body structure 100, and the negative terminal of the diode structure 200 is connected to the source electrode of the cascaded device. Specifically, as shown... Figure 4 and Figure 10 As shown, in this embodiment, the orthographic projection of the first connecting body 21 of the first metal connecting portion on the substrate 11 coincides with the orthographic projection of the gate electrode 3 and the anode Schottky metal 19 of the GaN main structure 100 on the substrate 11. The bottom of the first connecting branch 22 is connected to the top of the gate electrode 3 of the GaN main structure 100. The bottom of the second connecting branch 23 is connected to one end of the top of the anode Schottky metal 19. The bottom of the third connecting branch 25 is connected to the top of the cathode ohmic metal 18.

[0062] In this embodiment, by reversing the diode structure 200, the voltage division control of the low-voltage MOS device can be controlled to a safe range, while extending the turn-on time of the cascaded device and shortening the turn-off time. Furthermore, when reversed, the drive current when the device is turned on flows into the negative terminal of the diode and flows out from the positive terminal, while the drive current when the device is turned off flows into the positive terminal of the diode structure 200 and flows out from the negative terminal, which can make the turn-off speed faster and more suitable for flyback applications.

[0063] Example 5: This example provides a method for fabricating a depletion-type GaN chip. The depletion-type GaN chips in Examples 1 and 2 above were all fabricated using the method described in this example, specifically including the following steps:

[0064] Step 1: Nitride epitaxial growth is performed on substrate 11 to sequentially form a channel layer 12, a barrier layer 13, and a capping layer 14. The materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The channel layer 12, barrier layer 13, and capping layer 14 form a stacked structure, thereby constituting a complete semiconductor epitaxial layer structure. A high concentration of two-dimensional electron gas can be formed at the heterojunction interface between the channel layer 12 and the barrier layer 13, generating a conductive channel.

[0065] Step 2: Etch source electrode ohmic holes, drain electrode ohmic holes, cathode holes and anode holes 26 from the top surface of capping layer 14 downwards. Source electrode ohmic holes, drain electrode ohmic holes, cathode holes and anode holes 26 all penetrate the thickness of barrier layer 13 and capping layer 14.

[0066] Step 3: As Figure 11 and Figure 2 As shown, metal is filled into the source electrode ohmic hole, drain electrode ohmic hole, and cathode hole to form source electrode ohmic metal 6, drain electrode ohmic metal 7, and cathode ohmic metal 18, respectively. Metal is also partially filled into the anode hole 26 to form anode ohmic metal 20. The bottom area of ​​the region in the anode hole 26 filled with anode ohmic metal 20 accounts for 2% of the bottom area of ​​the entire anode hole 26. Annealing is then performed so that the source electrode ohmic metal 6, drain electrode ohmic metal 7, cathode ohmic metal 18, and anode ohmic metal 20 form ohmic contacts with the epitaxial material below them.

[0067] Step 4: As Figure 13 As shown, a first dielectric layer 15 is deposited above the capping layer 14, and wet etching is used to etch specific areas of the first dielectric layer 15 to form first vias 27 and gate trenches 28, respectively. Figure 14 As shown, the first through hole 27 is located within the range of the anode hole 26 in step 2, and the grid groove 28 is located between the source electrode ohmic metal 6 and the drain electrode ohmic metal 7.

[0068] Step 5: After growing metal above the first dielectric layer 15 and patterning it, the anode Schottky metal 19 and the gate module are formed, as shown below. Figure 15 As shown, the anode Schottky metal 19 is located in the first through hole 27, which forms a Schottky contact with the two-dimensional electron gas below; the gate and the first field plate 4 in the gate module are located in the gate trench 28.

[0069] Step 6: Perform N-type ion implantation in the channel layer 12 between the cathode ohmic metal 18 and the anode Schottky metal 19 to form a partially implanted isolation region.

[0070] By using region injection isolation, the reverse resistance formed by the ohmic contact between the positive and negative terminals of the diode structure 200 can be increased. This reduces the reverse leakage current when the diode structure 200 is reverse-conducting, thus providing a method for adjusting the reverse leakage current of the diode structure 200. This allows the cascaded device of the present invention to better improve electromagnetic radiation and reasonably control power loss.

[0071] Step 7: Deposit a second dielectric layer 16 above the first dielectric layer 15, and perform area etching from the top surface of the second dielectric layer 16 downwards to form a gate via. Then fill the gate via with metal and form a second field plate 8 after patterning. The bottom of the second field plate 8 is connected to the top of the gate and the first field plate 4.

[0072] Step 8: Deposit a third dielectric layer 17 above the second dielectric layer 16, and perform regional etching from the top surface of the third dielectric layer 17 downwards to form source vias, drain vias, second vias, third vias and fourth vias. Then, grow metal above the third dielectric layer 17 and perform patterned etching to form source electrode 1, drain electrode 2, first metal connector 9, second metal connector 10, first metal connector and second metal connector. The first metal connecting strip 9 and the second metal connecting strip 10 are located in the source via and the drain via, respectively. The first metal connecting part includes a first connecting part body 21 and a first connecting branch 22 and a second connecting branch 23 disposed on the bottom surface of the first connecting part body 21. The second metal connecting part includes a second connecting part body 24 and a third connecting branch 25 disposed on the bottom surface of the second connecting part body 24. The first connecting part body 21 and the second connecting part body 24 are both located on the side of the third dielectric layer 17 away from the second dielectric layer 16. The first connecting branch 22 and the second connecting branch 23 are located in the second via and the third via, respectively. The third connecting branch 25 is located in the fourth via.

[0073] Example 6: This example provides a method for fabricating a depletion-type GaN chip. The depletion-type GaN chips in Examples 3 and 4 above were all fabricated using the method described in this example, specifically including the following steps:

[0074] Step 1: Nitride epitaxial growth is performed on substrate 11 to sequentially form a channel layer 12, a barrier layer 13, and a capping layer 14. The materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The channel layer 12, barrier layer 13, and capping layer 14 form a stacked structure, thereby constituting a complete semiconductor epitaxial layer structure. A high concentration of two-dimensional electron gas can be formed at the heterojunction interface between the channel layer 12 and the barrier layer 13, generating a conductive channel.

[0075] Step 2: Etch source electrode ohmic holes, drain electrode ohmic holes, cathode holes and anode holes 26 from the top surface of capping layer 14 downwards. Source electrode ohmic holes, drain electrode ohmic holes, cathode holes and anode holes 26 all penetrate the thickness of barrier layer 13 and capping layer 14.

[0076] Step 3: Fill the source electrode ohmic hole, drain electrode ohmic hole and cathode hole with metal to form source electrode ohmic metal 6, drain electrode ohmic metal 7 and cathode ohmic metal 18 respectively, and perform annealing treatment so that source electrode ohmic metal 6, drain electrode ohmic metal 7 and cathode ohmic metal 18 form ohmic contacts with the epitaxial material below them respectively.

[0077] Step 4: Deposit a first dielectric layer 15 above the capping layer 14, and perform wet etching on the first dielectric layer 15 to completely expose the anode hole 26 in step 2, while forming a gate trench 28, which is located between the source electrode ohmic metal 6 and the drain electrode ohmic metal 7.

[0078] Step 5: After growing metal above the first dielectric layer 15 and patterning it, an anode Schottky metal 19 and a gate module are formed respectively. The anode Schottky metal 19 is entirely located in the anode hole 26, and it forms a Schottky contact with the two-dimensional electron gas below. The gate in the gate module is located in the gate trench 28 with the first field plate 4.

[0079] Step 6: Deposit a second dielectric layer 16 above the first dielectric layer 15, and perform area etching from the top surface of the second dielectric layer 16 downwards to form a gate via. Then fill the gate via with metal and form a second field plate 8 after patterning. The bottom of the second field plate 8 is connected to the top of the gate and the first field plate 4.

[0080] Step 7: Deposit a third dielectric layer 17 above the second dielectric layer 16, and perform regional etching from the top surface of the third dielectric layer 17 downwards to form source vias, drain vias, second vias, third vias and fourth vias. Then, grow metal above the third dielectric layer 17 and perform patterned etching to form source electrode 1, drain electrode 2, first metal connector 9, second metal connector 10, first metal connector and second metal connector. The first metal connecting strip 9 and the second metal connecting strip 10 are located in the source via and the drain via, respectively. The first metal connecting part includes a first connecting part body 21 and a first connecting branch 22 and a second connecting branch 23 disposed at both ends of the bottom surface of the first connecting part body 21. The second metal connecting part includes a second connecting part body 24 and a third connecting branch 25 disposed in the middle of the bottom surface of the second connecting part body 24. The first connecting part body 21 and the second connecting part body 24 are both located on the side of the third dielectric layer 17 away from the second dielectric layer 16. The first connecting branch 22 and the second connecting branch 23 are located in the second via and the third via, respectively. The third connecting branch 25 is located in the fourth via.

[0081] The depletion-mode GaN chip of the present invention integrates a diode structure 200 inside the depletion-mode GaN chip and the cooperation between the diode structure 200 and the GaN main structure 100, so that the diode structure 200 of the present invention can exhibit low resistance when forward conduction and high leakage current when reverse conduction; and the turn-on speed and turn-off speed of the cascaded device obtained by cascading the depletion-mode GaN chip of the present invention with an enhancement-mode MOS chip can be adjusted separately.

[0082] The above embodiments of the present invention are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A depletion-mode GaN chip with an internally integrated diode, characterized in that, The device includes a GaN host structure and a diode structure. The GaN host structure has a source electrode, a drain electrode, and a gate electrode. The gate electrode of the GaN host structure is connected to the positive or negative electrode of the diode structure. The diode structure includes a cathode ohmic metal and an anode metal. The anode metal includes multiple anode Schottky metals and multiple anode ohmic metals, which are arranged alternately and at intervals along the same horizontal direction to improve the reverse leakage current when the diode structure is reverse-biased. The forward conduction resistance of the diode structure is less than the reverse conduction resistance of the diode structure, and the reverse leakage current when the diode structure is reverse-biased is 0.0005-10A. When the anode metal includes multiple anode Schottky metals and multiple anode ohmic metals, when the diode structure is forward-biased, part of the current flows from the anode Schottky metal to the cathode ohmic metal, and part of the current flows from the anode ohmic metal to the cathode ohmic metal; when reverse-biased, the current flows from the cathode ohmic metal to the anode ohmic metal and the anode Schottky metal, respectively.

2. The depletion-mode GaN chip according to claim 1, characterized in that, The reverse voltage of the diode structure when it is reverse-conducting is 0-100V, and the ratio of the reverse conduction resistance of the diode structure to the forward conduction resistance of the diode structure is 5-1000:

1.

3. The depletion-mode GaN chip according to claim 1, characterized in that, It also includes a substrate, a stacked structure, a first dielectric layer, a second dielectric layer and a third dielectric layer arranged from bottom to top, wherein the stacked structure includes at least a channel layer and a barrier layer arranged from bottom to top, wherein the cathode ohmic metal is located in the stacked structure and the first dielectric layer, and the anode metal is at least partially located in the stacked structure, the first dielectric layer and the second dielectric layer; The stacked structure has anode holes along its thickness direction, and the bottom of the anode metal is located in the anode holes.

4. The depletion-mode GaN chip according to claim 3, characterized in that, When the anode metal includes anode Schottky metal, the anode Schottky metal is entirely located in the stacked structure, the first dielectric layer, and the second dielectric layer.

5. The depletion-mode GaN chip according to claim 3, characterized in that, When the anode metal includes multiple anode Schottky metals and multiple anode ohmic metals, the anode ohmic metals are located in the stacked structure and the first dielectric layer, the anode Schottky metals are located in the stacked structure, the first dielectric layer and the second dielectric layer, and the area of ​​the orthogonal projection of the anode ohmic metals on the substrate is smaller than the area of ​​the orthogonal projection of the anode Schottky metals on the substrate.

6. The depletion-mode GaN chip according to claim 5, characterized in that, The area of ​​the orthogonal projection of the anode ohmic metal onto the substrate accounts for 0.01% to 50% of the total area of ​​the orthogonal projection of the anode metal onto the substrate.

7. The depletion-type GaN chip according to claim 4, characterized in that, The portion of the anode Schottky metal located in the anode hole is in direct contact with the sidewall of the anode hole, such that the width of the contact area between the anode Schottky metal and the underlying channel layer is equal to the width of the anode hole.

8. The depletion-mode GaN chip according to claim 5, characterized in that, The sidewall of the anode hole is filled with a first dielectric layer, and the portion of the anode Schottky metal located in the anode hole is in contact with the first dielectric layer in the anode hole, such that the width of the contact area between the anode Schottky metal and the underlying channel layer is smaller than the width of the anode hole.

9. The depletion-mode GaN chip according to claim 1, characterized in that, The diode structure is provided with a first metal connection portion and a second metal connection portion; the two ends of the bottom of the first metal connection portion are respectively connected to the top of the gate electrode of the GaN main body structure and one end of the top of the cathode ohmic metal of the diode structure, and the bottom of the second metal connection portion is connected to the top of the anode metal of the diode structure; or, the two ends of the bottom of the first metal connection portion are respectively connected to the top of the gate electrode of the GaN main body structure and the top of the anode metal of the diode structure, and the bottom of the second metal connection portion is connected to one end of the top of the cathode ohmic metal of the diode structure.

10. A cascaded device, characterized in that, The device includes the depletion-mode GaN chip as described in any one of claims 1-9, wherein the cascaded device is obtained by cascading and packaging the depletion-mode GaN chip and the enhancement-mode MOS chip, wherein one of the positive and negative electrodes of the diode structure in the depletion-mode GaN chip is connected to the gate electrode of the GaN body structure, and the other electrode of the positive and negative electrodes of the diode structure is connected to the source electrode of the cascaded device.

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