Quantum chip processing equipment and quantum chip uniformity control method

Abstract

The invention discloses quantum chip processing equipment and a quantum chip uniformity control method. The method comprises the following steps: providing a wafer; sequentially preparing and forming a first photoresist layer and a second photoresist layer on the surface of one side of the wafer; forming a first metal layer on one side, deviating from the wafer, of the second photoresist layer, and determining the distance and the thickness from the first metal layer to the center of the wafer; forming an oxide layer on the surface of one side, deviating from the wafer, of the first metal layer; forming a second metal layer on the surface of one side, deviating from the wafer, of the oxide layer to form a Josephson junction, and determining the width of the second metal layer; determining the area of the Josephson junction according to the distance from the first metal layer to the center of the wafer, the thickness of the first metal layer and the width of the second metal layer; and according to the area of the Josephson junction, determining the non-uniformity compensation amount of the quantum chip, and compensating the quantum chip processing equipment to obtain the quantum chip with good uniformity. By means of the method, compensation optimization of non-uniformity in the machining process is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum chip processing, and in particular to a quantum chip processing device and a quantum chip uniformity control method. BACKGROUND

[0002] At present, the preparation of superconducting quantum chips is carried out through a semiconductor process. The Josephson junction, which is the core element of the superconducting quantum chip, is generally realized through electron beam exposure and thin film deposition. Specifically, double-angle deposition is the most mature technical solution for preparing Josephson junctions at present. It has the advantages of simple process and compatibility with semiconductor processes, but also brings the problem of obvious in-plane distribution non-uniformity. This non-uniformity will bring great trouble to the bit control signal calibration work and affect the practicability of the quantum chip. The thin film prepared in this way has natural thickness (out-of-plane) and size (in-plane) non-uniformity, resulting in in-chip non-uniformity of the quantum chip performance, and this non-uniformity will become more obvious as the size of the quantum chip, such as the size of the wafer, increases.

[0003] In view of the above non-uniformity, the most representative technical solution in the prior art is the laser annealing technology. The basic principle of this technology is to perform laser annealing on the bits after the bit processing is completed to adjust the frequency performance of the bits. However, this method is a kind of post-processing performance, which is an additional process after the bit processing is completed, and is not conducive to the optimization of large-scale quantum bits. SUMMARY

[0004] The present application provides a quantum chip processing device and a quantum chip uniformity control method to compensate and optimize the in-plane non-uniformity during the Josephson junction processing, reduce the risk of contamination in the additional processing process, and improve the processing purity and the processing accuracy of the quantum chip.

[0005] In a first aspect, the present application provides a quantum chip uniformity control method, comprising:

[0006] providing a wafer; sequentially preparing and forming a first photoresist layer and a second photoresist layer on one side surface of the wafer; the first photoresist layer comprises a first opening, and the second photoresist layer comprises a second opening; the orthographic projection of the first opening on the wafer covers the orthographic projection of the second opening on the wafer;

[0007] forming a first metal layer on the side of the second photoresist layer away from the wafer, and determining the distance from the first metal layer to the center of the wafer and the thickness of the first metal layer;

[0008] forming an oxidation layer on the surface of the side of the first metal layer away from the wafer;

[0009] forming a second metal layer on a surface of the oxide layer away from the wafer to form a Josephson junction and determining a width of the second metal layer;

[0010] determining an area of the Josephson junction according to the distance of the first metal layer to the center of the wafer and the thickness of the first metal layer and the width of the second metal layer;

[0011] determining a compensation amount of non-uniformity of the quantum chip according to the area of the Josephson junction and compensating the quantum chip processing equipment to obtain a quantum chip with good uniformity.

[0012] Optionally, the first metal layer is formed on a surface of the second photoresist layer away from the wafer, and the distance of the first metal layer to the center of the wafer and the thickness of the first metal layer are determined, comprising:

[0013] The first metal layer is deposited on a surface of the second photoresist layer away from the wafer by using a double-angle deposition process;

[0014] The distance of the first metal layer to the center of the wafer is determined according to the designed width of the first metal layer;

[0015] The thickness of the first metal layer is determined according to the initial deposition thickness of the center of the wafer.

[0016] Optionally, the distance of the first metal layer to the center of the wafer is determined according to the designed width of the first metal layer, comprising:

[0017] The distance of the first metal layer to the center of the wafer is determined according to the designed width of the first metal layer based on a first calculation formula; the first calculation formula is: ; wherein, is the distance of the first metal layer to the center of the wafer after actual deposition at a target position x on the wafer, is the designed width of the first metal layer, δ is a widening deviation caused by proximity effect, H is the thickness of the second photoresist layer, and D is the distance from the projection of the crucible on the wafer plane to the surface of the second photoresist layer.

[0018] Optionally, the thickness of the first metal layer is determined according to the initial deposition thickness of the center of the wafer, comprising:

[0019] The thickness of the first metal layer is determined according to the initial deposition thickness of the center of the wafer based on a second calculation formula; the second calculation formula is: ; wherein, Ts is the thickness of the first metal layer, Tc is the initial deposition thickness of the center of the wafer, D' is the vertical distance from the crucible to the wafer surface, is the distance between any point on the wafer and the crucible, and R is the distance between the center of the sample table and the center of the wafer.

[0020] Optionally, the first metal layer is located on the surface of the second photoresist layer away from the wafer and the second photoresist layer close to the inner wall of the second opening;

[0021] The second metal layer is formed on the surface of the oxide layer away from the wafer to form a Josephson junction, and the width of the second metal layer is determined, comprising:

[0022] The wafer is rotated by a preset angle about a first rotation axis, and the second metal layer is formed on the surface of the oxide layer away from the wafer by using a double-angle deposition process to form a Josephson junction; the first rotation axis is parallel to the thickness direction of the wafer;

[0023] The width of the second metal layer is determined according to the initial width of the second metal layer.

[0024] Optionally, the width of the second metal layer is determined according to the initial width of the second metal layer, comprising:

[0025] When the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the thickness of the first metal layer;

[0026] When the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer.

[0027] Optionally, when the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer, comprising:

[0028] When the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer according to a third calculation formula;

[0029] The third calculation formula is: ; wherein, W is the width of the second metal layer actually deposited at a target position y on the wafer, W 2d is the initial width of the second metal layer, δ is the spread deviation caused by proximity effect, H is the thickness of the second photoresist layer, Ts is the thickness of the first metal layer, D is the distance from the projection of the crucible on the wafer plane to the surface of the second photoresist layer, is the distance of the current position point on the wafer from the origin, W Lip is the width of the first metal layer located on the inner wall of the second photoresist layer.

[0030] Optionally, when the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the thickness of the first metal layer, comprising:

[0031] When the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the thickness of the first metal layer, based on a fourth calculation formula;

[0032] The fourth calculation formula is: , wherein, W is the width of the second metal layer actually deposited at the target position y on the wafer, 2d W0 is the initial width of the second metal layer, δ is the spread deviation caused by proximity effect, H is the thickness of the second photoresist layer, Ts is the thickness of the first metal layer, and D is the distance from the projection of the crucible on the wafer plane to the surface of the second photoresist layer, is the distance of the current position point on the wafer from the origin.

[0033] Optionally, the area of the Josephson junction is determined according to the distance of the first metal layer to the center of the wafer and the thickness of the first metal layer, and the width of the second metal layer, comprising:

[0034] The area of the Josephson junction is determined according to the distance of the first metal layer to the center of the wafer and the thickness of the first metal layer, and the width of the second metal layer, based on a fifth calculation formula;

[0035] The fifth calculation formula is: , wherein, is the area of the Josephson junction, is the distance of the first metal layer to the center of the wafer, and Ts is the thickness of the first metal layer, is the width of the second metal layer.

[0036] Optionally, the compensation amount of the non-uniformity of the quantum chip is determined according to the area of the Josephson junction, comprising:

[0037] The compensation amount of the non-uniformity of the quantum chip is determined according to the area of the Josephson junction, based on a sixth calculation formula;

[0038] The sixth calculation formula is: , wherein F is the compensation amount, is the area of the Josephson junction.

[0039] In a second aspect, the present application provides a quantum chip processing device, comprising a sample table, a crucible and a control unit; the sample table is used for placing and rotating a quantum chip, the crucible is used for generating a beam to the surface of the quantum chip; the control unit is used for executing the above-mentioned quantum chip uniformity control method.

[0040] The technical scheme of the embodiment of the present application provides a wafer; a first photoresist layer and a second photoresist layer are sequentially prepared on one side surface of the wafer; the first photoresist layer comprises a first opening, and the second photoresist layer comprises a second opening; a normal projection of the first opening on the wafer covers a normal projection of the second opening on the wafer; a first metal layer is formed on a side of the second photoresist layer away from the wafer, and a distance from the first metal layer to the center of the wafer and a thickness of the first metal layer are determined; an oxidation layer is formed on a surface of the first metal layer away from the wafer; a second metal layer is formed on a surface of the oxidation layer away from the wafer to form a Josephson junction, and a width of the second metal layer is determined; the area of the Josephson junction is determined according to the distance from the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer; the compensation amount of the non-uniformity of the quantum chip is determined according to the area of the Josephson junction, and the quantum chip processing equipment is compensated to obtain a quantum chip with good uniformity. By using the above method, the in-plane non-uniformity is compensated and optimized in the processing of the Josephson junction, the risk of pollution in the additional processing process is reduced, and the processing purity and the processing precision of the quantum chip are improved.

[0041] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0043] Figure 1 is a flow chart of a quantum chip uniformity control method provided by the embodiment of the present application;

[0044] Figure 2 is a coordinate system diagram established on a wafer provided by the embodiment of the present application;

[0045] Figure 3 is a flow chart of another quantum chip uniformity control method provided by the embodiment of the present application;

[0046] Figure 4 is a structure diagram before a first metal layer is deposited on a wafer provided by the embodiment of the present application;

[0047] Figure 5 is a structure diagram after a first metal layer is formed on a wafer provided by the embodiment of the present application;

[0048] Figure 6 A structure schematic diagram when a first metal layer inner wall influences deposition of a second metal layer is provided for an embodiment of the present application.

[0049] Figure 7 A structure schematic diagram when a first metal layer inner wall does not influence deposition of a second metal layer is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiment of the present application will be described clearly and completely below in combination with the drawings in the embodiment of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application.

[0051] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0052] In an embodiment, Figure 1 is a flowchart of a method for controlling uniformity of a quantum chip provided by an embodiment of the present application, Figure 2 is a schematic diagram of a coordinate system established on a wafer, which can be applicable to compensation and optimization of in-plane non-uniformity in a Josephson junction processing process, improve processing purity and processing precision of a quantum chip, and the method can be configured in a quantum chip processing device. The quantum chip processing device includes a sample table and a crucible; the sample table is used to place and rotate a quantum chip, and the crucible is used to generate a beam to the surface of the quantum chip; as shown in Figure 1 and Figure 2 The method comprises the following steps:

[0053] S110, providing a wafer; sequentially preparing and forming a first photoresist layer and a second photoresist layer on one side surface of the wafer.

[0054] The first photoresist layer includes a first opening, and the second photoresist layer includes a second opening, and a normal projection of the first opening on the wafer covers a normal projection of the second opening on the wafer.

[0055] The wafer is a basic material in semiconductor manufacturing, which is a circular sheet made of high-purity single crystal silicon (or other semiconductor materials such as gallium arsenide, silicon carbide, etc.), used to provide mechanical support and electrical isolation of the sample table, to produce devices on its surface through a series of micro-nano processing processes such as lithography, etching, deposition, and doping. The first photoresist layer and the second photoresist layer are etch-resistant film materials whose solubility changes through irradiation or radiation of ultraviolet light, electron beams, ion beams, or X-rays. The first photoresist layer and the second photoresist layer can be formed by coating, for example, and the material of the first photoresist layer can include but is not limited to polymethyl methacrylate (PMMA), and the material of the second photoresist layer can include but is not limited to methacrylic acid (MAA).

[0056] Specifically, before preparing the Josephson junction, a wafer is provided, and the wafer is cleaned to remove particles and organic contaminants on the surface of the wafer. Then, a first photoresist layer is formed on one side of the wafer by spin coating or deposition process, and the first photoresist layer is baked. Then, a second photoresist layer is formed on the side of the first photoresist layer away from the wafer by spin coating or deposition process, and is baked. After baking, the first photoresist layer and the second photoresist layer are patterned and etched by electron beam exposure process, that is, exposed and developed according to a predetermined pattern, to remove the exposed part of the first photoresist layer and the second photoresist layer, and form a structure including a first opening and a second opening. In this embodiment, the first photoresist layer includes the first opening, and the second photoresist layer includes the second opening. The first opening and the second opening are both located at the middle position of the photoresist layer, and the normal projection of the first photoresist layer on the wafer covers the normal projection of the second photoresist layer on the wafer. That is, the width of the first photoresist layer obtained after etching is smaller than the width of the second photoresist layer, and the photoresist layer on the wafer surface presents a shape of "wide at the top and narrow at the bottom".

[0057] S120, forming a first metal layer on the side of the second photoresist layer away from the wafer, and determining the distance from the first metal layer to the center of the wafer and the thickness of the first metal layer.

[0058] The first metal layer is usually a superconducting material and is an electrode of the Josephson junction. The material of the first metal layer can include but is not limited to aluminum.

[0059] Specifically, after the second photoresist layer is formed, a coordinate system can be established on the wafer, and the distance from the center of the wafer to the first metal layer can be determined by referring to the coordinate system. Figure 2As shown, O is the center of the wafer, the gray arrow, i.e. the deposition direction, represents the direction of the beam center line emitted by the crucible, a is the included angle between the positive direction of the z axis and the beam center line, and β is the included angle between the projection (i.e. the dashed line) of the beam center line on the xoy plane and the positive direction of the x axis. In addition, considering that the distance between the target (i.e. the crucible) of the deposition device and the wafer sample is much greater than the shape of the crucible, the embodiment approximates the crucible as a point and considers that the beam is radiated from the target crucible in a spherical field. In the embodiment, when the first metal layer is prepared, the angles of a and β can be preset based on the coordinate system, so as to determine the sputtering direction, wherein the specific values of the angles of a and β can be set according to actual conditions, and are not limited herein. For example, β1=90° and a1=45°. Then, a first metal layer with a certain thickness and width is deposited on the surface of the second photoresist layer away from the wafer based on the preset deposition parameters of the first metal layer by using a preset deposition process, including but not limited to a double-angle deposition process. It should be noted that since the deposition is not vertical, the area covered by the first metal layer can include the upper part and the sidewall of the second photoresist layer.

[0060] After the deposition is completed, the actual width and thickness of the first metal layer can be determined according to the preset deposition parameters. The preset deposition parameters can include but are not limited to the design width and the design thickness of the first metal layer. In addition, the distance from the first metal layer to the center of the wafer and the thickness of the first metal layer can also be directly determined by a scanning electron microscope, an atomic force microscope or a four-probe method, and the specific determination method can be set according to actual conditions, and is not limited herein.

[0061] S130, forming an oxide layer on the surface of the first metal layer away from the wafer.

[0062] The oxide layer is a thin film layer located in the middle of the Josephson junction. The material of the oxide layer can include but is not limited to aluminum oxide.

[0063] Specifically, after the first metal layer is prepared, the surface of the first metal layer away from the wafer needs to be oxidized. The oxidation can be completed in an oxidation chamber, or the wafer can be directly exposed to dry air. By controlling the pressure, time and temperature of oxygen, a thin oxide layer can be formed on the surface of the first metal layer after the oxidation is completed.

[0064] S140, forming a second metal layer on the surface of the oxide layer away from the wafer to form a Josephson junction and determining the width of the second metal layer.

[0065] The second metal layer has the same meaning as the first metal layer and is usually a superconducting material, which is another electrode of the Josephson junction. The material of the second metal layer can include but is not limited to aluminum.

[0066] Specifically, after forming the oxide layer, a third layer structure of the Josephson junction, i.e., the second metal layer, needs to be prepared on the surface of the oxide layer away from the wafer. In the embodiment, when the wafer returns to the evaporation chamber from the oxidation chamber, the wafer still maintains the state in the first evaporation, and the second metal layer formed in the second evaporation is located in a different direction from the first metal layer formed in the first evaporation. Therefore, to ensure the normal conduction of the Josephson junction, the wafer needs to be rotated first when the second metal layer is formed on the oxide layer. Referring to the coordinate system shown in FIG. 6, it can be understood that the angles α2 and β2 change, which means that the sputtering direction changes. The specific values of the angles α2 and β2 can be set according to actual conditions, which are not limited herein. For example, α2 = 45° and β2 = 180°. Figure 2

[0067] In addition, after the second metal layer is formed on the surface of the oxide layer away from the wafer, the structure of the Josephson junction is formed. Since the first metal layer has a height and is deposited on the sidewall of the second photoresist layer, a shadow effect will occur when the second metal layer is deposited, resulting in a reduction in the effective width. In the embodiment, the actual width of the second metal layer can be obtained by performing logical operation or data processing on the preset deposition parameters according to the preset deposition parameters of the second metal layer. The preset deposition parameters can include but are not limited to the design width of the second metal layer. In addition, the width of the second metal layer can also be directly determined by a scanning electron microscope, an atomic force microscope, or a four-probe method. The specific determination method can be set according to actual conditions, which is not limited herein.

[0068] S150, determining the area of the Josephson junction according to the distance of the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer.

[0069] Specifically, when the Josephson junction is prepared, the first metal layer and the second metal layer will have an overlapping part, and therefore the area of the Josephson junction can be understood as the projected area of the overlapping region of the first metal layer and the second metal layer on the wafer. Due to factors such as deposition angle, photoresist topography, and metal step coverage, the actual area of the overlapping region is not the same as the calculated area of the overlapping region. In the embodiment, after the distance of the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer are determined, the area of the Josephson junction after actual production can be obtained by performing logical operation or other data processing on the above-mentioned parameters. In addition, the area of the Josephson junction can also be obtained by inversely deducing the critical current flowing through the Josephson junction. The specific method can be determined according to actual conditions, which is not limited herein.

[0070] ​S160, determine the compensation amount of the non-uniformity of the quantum chip according to the area of the Josephson junction, and compensate the quantum chip processing equipment to obtain a quantum chip with good uniformity.

[0071] Specifically, after the area of the Josephson junction is determined, the compensation amount of the non-uniformity can be obtained according to the area of the Josephson junction. In this embodiment, the compensation amount of the non-uniformity of the quantum chip can be obtained by preset logical operation according to the area of the Josephson junction, or electrical testing (IC) or topography measurement (SEM) can be performed on multiple Josephson junctions on each wafer to calculate indicators such as area standard deviation and mean deviation, so as to obtain the compensation amount. Of course, other determination methods can also be used, which are not limited herein. After the compensation amount of the non-uniformity of the quantum chip is determined, the compensation amount is set in the quantum chip processing equipment to compensate the quantum chip processing equipment, so that the uniformity of the quantum chip prepared subsequently can reach the preset uniformity range, and the preparation yield and efficiency of the quantum chip are improved.

[0072] The technical scheme of the embodiment of the present application provides a wafer; a first photoresist layer and a second photoresist layer are sequentially prepared on one side surface of the wafer; the first photoresist layer comprises a first opening, and the second photoresist layer comprises a second opening; a projection of the first opening on the wafer covers a projection of the second opening on the wafer; a first metal layer is formed on a side of the second photoresist layer away from the wafer, and a distance from the first metal layer to the center of the wafer and a thickness of the first metal layer are determined; an oxidation layer is formed on a surface of the first metal layer away from the wafer; a second metal layer is formed on a surface of the oxidation layer away from the wafer to form a Josephson junction, and a width of the second metal layer is determined; the area of the Josephson junction is determined according to the distance from the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer; and the compensation amount of the non-uniformity of the quantum chip is determined according to the area of the Josephson junction, and the quantum chip processing equipment is compensated to obtain a quantum chip with good uniformity. By using the above method, the in-plane non-uniformity is compensated and optimized in the Josephson junction processing process, the risk of contamination in the additional processing process is reduced, and the processing purity and the processing precision of the quantum chip are improved.

[0073] In another specific embodiment, optionally, Figure 3 A flowchart of another method for controlling the uniformity of a quantum chip provided by the embodiment of the present application is shown in FIG. 6. Figure 4 A structure schematic diagram before a first metal layer is deposited on a wafer provided by the embodiment of the present application is shown in FIG. 2. Figure 5 A structure schematic diagram after a first metal layer is formed on a wafer provided by the embodiment of the present application is shown in FIG. 3. The specific implementation of S120 in the above embodiment, that is, forming a first metal layer on a side of the second photoresist layer away from the wafer and determining the distance from the first metal layer to the center of the wafer and the thickness of the first metal layer, is refined as follows:

[0074] The first metal layer is formed on the side of the second photoresist layer away from the wafer by a double-angle deposition process;

[0075] The distance from the first metal layer to the center of the wafer is determined according to the designed width of the first metal layer;

[0076] The thickness of the first metal layer is determined according to the initial deposition thickness at the center of the wafer.

[0077] Further, the first metal layer is located on the surface of the second photoresist layer away from the wafer and the second photoresist layer close to the inner wall of the second opening. The specific implementation of S140 in the above embodiment, forming the second metal layer on the surface of the oxidation layer away from the wafer to form the Josephson junction and determining the width of the second metal layer, is refined as:

[0078] The wafer is rotated by a preset angle about the first rotation axis, and the second metal layer is formed on the surface of the oxidation layer away from the wafer by a double-angle deposition process to form the Josephson junction. The first rotation axis is parallel to the thickness direction of the wafer;

[0079] The width of the second metal layer is determined according to the initial width of the second metal layer.

[0080] Further, the specific implementation of S150, determining the area of the Josephson junction according to the distance from the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer, is refined as:

[0081] The area of the Josephson junction is determined according to the distance from the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer based on the fifth calculation formula;

[0082] The fifth calculation formula is: ; wherein, the area of the Josephson junction, the distance from the first metal layer to the center of the wafer, and Ts is the thickness of the first metal layer, the width of the second metal layer.

[0083] Further, the specific implementation of S160, determining the compensation amount of the non-uniformity of the quantum chip according to the area of the Josephson junction, is refined as:

[0084] The compensation amount of the non-uniformity of the quantum chip is determined according to the area of the Josephson junction based on the sixth calculation formula;

[0085] The sixth calculation formula is: , wherein F is the compensation amount, the area of the Josephson junction.

[0086] The details of the embodiment not yet described can refer to the above embodiments, which will not be described here.

[0087] Reference is made to Figure 2 to Figure 5 The method comprises the following steps:

[0088] S210, providing a wafer; sequentially preparing a first photoresist layer and a second photoresist layer on one side surface of the wafer.

[0089] Reference is made to Figure 4 .

[0090] S220, using a double-angle deposition process to deposit a first metal layer on the side of the second photoresist layer away from the wafer.

[0091] The first metal layer is located on the side surface of the second photoresist layer away from the wafer and the inner wall of the second photoresist layer close to the second opening.

[0092] The double-angle deposition process (DAD) is a key technology for preparing Josephson junctions or other nano-scale "bridge" or "suspended" structures in micro-nano processing. Double-angle deposition forms two partially overlapping metal layers on the photoresist pattern by evaporating metal at two different incident angles, with an ultra-thin oxide layer in between, thereby naturally forming a nano-scale cross-type Josephson junction without the need for high-precision alignment.

[0093] Specifically, in the actual preparation process, the wafer is fixed on a sample stage in a quantum chip processing device, and usually the center of the wafer is aligned with the center of the sample stage. Combined with the wafer coordinate system shown in Figure 2 , by rotating the sample stage, α and β are rotated to the preset angle position, β1=90°, α1=45°, and at this angle, the crucible generates a beam to the surface of the second photoresist layer to form a first metal layer with a certain thickness and width on the side surface of the second photoresist layer away from the wafer and the inner wall of the second photoresist layer close to the second opening, as shown in Figure 5 .

[0094] S230, according to the design width of the first metal layer, determining the distance of the first metal layer to the center of the wafer.

[0095] The step can be further refined as follows: according to the design width of the first metal layer, based on the first calculation formula, the distance of the first metal layer to the center of the wafer is determined; the first calculation formula is: ; wherein, is the actual distance of the first metal layer to the center of the wafer at the target position x on the wafer after deposition, is the designed width of the first metal layer, δ is the width deviation caused by proximity effect, H is the thickness of the second photoresist layer, and D is the distance from the projection of the crucible on the wafer plane to the surface of the second photoresist layer.

[0096] Specifically, referring to Figure 4 and Figure 5 , the lowermost dark gray long strip represents a wafer, the slightly lighter gray in the middle is a first photoresist layer, and the lightest gray at the top is a second photoresist layer. After forming the first metal layer, the actual width of the first metal layer needs to be determined. In this embodiment, according to the designed width of the first metal layer, based on a first calculation formula, , wherein is the distance from the first metal layer to the center of the wafer after actual deposition at a target position x on the wafer, is the designed width of the first metal layer, δ is the width deviation caused by proximity effect, H is the thickness of the second photoresist layer, and D is the distance from the projection of the crucible (C) on the wafer plane to the surface of the second photoresist layer, D = D' x cos α1 - R, wherein D' is the distance between the axis of the sample table and the crucible (C), which is generally related to the design of the equipment manufacturer and can be obtained in advance, α1 is the included angle between the positive direction of the z-axis and the center line of the beam, and α1 can be 45°, and R is the distance between the center (O') of the sample table and the center (O) of the surface of the wafer away from the sample table, which can also be obtained in advance. By substituting D', α1 and R into the above formula, D can be calculated. Therefore, according to the above formula, , δ, H and D can be obtained in advance, therefore, by substituting the known , δ, H and D into the first calculation formula, the distance from the first metal layer to the center of the wafer can be obtained by calculation.

[0097] It should be noted that δ is the width deviation caused by proximity effect, which is generally greater than 0, and δ is generally related to the beam size and deposition voltage direction. This parameter has different description models, and can be determined by using a constant, a square root function, a linear function or a polynomial function. The specific determination can be made according to the actual situation, which is not limited here.

[0098] S240, determining the thickness of the first metal layer according to the initial deposition thickness of the center of the wafer.

[0099] wherein this step can be further refined as: determining the thickness of the first metal layer according to the initial deposition thickness of the center of the wafer based on a second calculation formula; the second calculation formula is: ; wherein Ts is the thickness of the first metal layer, Tc is the initial deposition thickness of the center of the wafer, D' is the vertical distance from the crucible to the surface of the wafer, is the distance between any point on the wafer and the crucible, and R is the distance between the center of the sample table and the center of the wafer.

[0100] Specifically, in the calculation of the thickness of the first metal layer, the thickness at the O point in the initial deposition thickness of the wafer center, i.e. Figure 4 and Figure 5 may be obtained based on the thickness. In the embodiment, according to the second calculation formula, , wherein Ts is the thickness of the first metal layer, Tc is the initial deposition thickness of the wafer center, D' is the vertical distance from the crucible to the wafer surface, is the distance between any point on the wafer and the crucible, and R is the distance between the center of the sample table and the center of the wafer. In the above formula, Tc, D', and R can be obtained by direct measurement, calculation, etc. Therefore, after substituting the known Tc, D', and R into the second calculation formula, the actual thickness Ts of the first metal layer can be calculated.

[0101] S250, forming an oxide layer on the surface of the first metal layer away from the wafer.

[0102] S260, rotating the wafer by a preset angle about the first rotation axis, and forming a second metal layer on the surface of the oxide layer away from the wafer by using a double-angle deposition process to form a Josephson junction; the first rotation axis is parallel to the thickness direction of the wafer.

[0103] Specifically, referring to Figure 5 , the first metal layer formed by the first deposition is represented by the hatched part, and the remaining structures are the same as Figure 4 . When depositing the second metal layer, the wafer needs to be rotated because the deposition angles of the first and second depositions are different, i.e., rotating the wafer by a preset angle about the first rotation axis to reach the target angle of the second metal layer deposition. For example, the angle of the second deposition is α2=45°, β2=180°, which can be understood as rotating counterclockwise by 90° about the first rotation axis compared with the first deposition angle. The second metal layer is formed by using a double-angle deposition process at the target angle.

[0104] S270, determining the width of the second metal layer according to the initial width of the second metal layer.

[0105] The step can be further refined as follows: when the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, determining the width of the second metal layer according to the initial width of the second metal layer and the thickness of the first metal layer; when the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, determining the width of the second metal layer according to the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer.

[0106] ​​Specifically, after the second metal layer is formed, the second deposition is performed on the basis of the first deposition, so the second deposition is affected by the first deposition. In other words, due to the oblique deposition, a certain thickness and width of the first metal layer, referred to as lip, is deposited on the sidewall of the second photoresist. The height of the lip is related to the angle of deposition. As shown in FIG. 7, due to the blocking effect of the lip, there are two cases of the lip part of the first metal layer affecting and not affecting the deposition of the second metal layer. Figure 5

[0107] When the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, that is, the width of the lip part of the inner wall of the first metal layer is very small, the beam current during the deposition of the second metal layer does not contact the lip area. At this time, the width of the second metal layer can be determined according to the initial width of the second metal layer and the thickness of the first metal layer through logical operation or other calculation methods.

[0108] When the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, that is, the width of the lip part of the inner wall of the first metal layer is very large, the beam current during the deposition of the second metal layer will contact the lip area, thereby affecting the deposition thickness and deposition area of the second metal layer. At this time, the width of the second metal layer can be determined according to the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer through logical operation or other calculation methods.

[0109] S280, determining the area of the Josephson junction based on a fifth calculation formula according to the distance of the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer.

[0110] The fifth calculation formula is: ; wherein, is the area of the Josephson junction, is the distance of the first metal layer to the center of the wafer, and Ts is the thickness of the first metal layer, is the width of the second metal layer.

[0111] Specifically, in determining the area of the Josephson junction, the area of the Josephson junction can be determined according to the distance of the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer according to the fifth calculation formula, , wherein, is the distance of the first metal layer to the center of the wafer, and Ts is the thickness of the first metal layer, is the width of the second metal layer, by substituting , Ts and into the fifth calculation formula, the area of the Josephson junction after the actual production is completed can be finally obtained.

[0112] ​S290, determining the compensation amount of the non-uniformity of the quantum chip based on the sixth calculation formula according to the area of the Josephson junction.

[0113] wherein the sixth calculation formula is: wherein F is the compensation amount, is the area of the Josephson junction.

[0114] Specifically, after the area of the Josephson junction is determined, the compensation amount of the non-uniformity can be obtained according to the area of the Josephson junction. In this embodiment, the compensation amount of the non-uniformity of the quantum chip can be determined according to the area of the Josephson junction based on the sixth calculation formula: by calculating the reciprocal of the area of the Josephson junction. After the compensation amount of the non-uniformity of the quantum chip is determined, the compensation amount is set in the quantum chip processing equipment to compensate the quantum chip processing equipment, so that the uniformity of the quantum chip prepared subsequently can reach the preset uniformity range, and the preparation yield and efficiency of the quantum chip are improved.

[0115] The technical scheme of the embodiment of the application, by adopting the double-angle deposition process, a first metal layer is deposited on the side of the second photoresist layer away from the wafer; the distance from the first metal layer to the center of the wafer is determined according to the designed width of the first metal layer; the thickness of the first metal layer is determined according to the initial deposition thickness of the center of the wafer; the wafer is rotated by a preset angle about a first rotation axis, and a second metal layer is formed on the surface of the oxide layer away from the wafer by using the double-angle deposition process to form a Josephson junction; the first rotation axis is parallel to the thickness direction of the wafer; the width of the second metal layer is determined according to the initial width of the second metal layer; the area of the Josephson junction is determined based on the fifth calculation formula according to the distance from the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer; and the compensation amount of the non-uniformity of the quantum chip is determined based on the sixth calculation formula according to the area of the Josephson junction. By using the above method, the area of the Josephson junction is gradually determined, and the compensation amount is determined based on the area of the Josephson junction, so that the compensation of the quantum chip in the processing process is realized, and the cost is reduced.

[0116] Figure 6 is a structural schematic view of the first metal layer inner wall affecting the deposition of the second metal layer provided by the embodiment of the application, Figure 7 is a structural schematic view of the first metal layer inner wall not affecting the deposition of the second metal layer provided by the embodiment of the application, for reference Figure 6 and Figure 7As shown, optionally, when the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer, comprising: when the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer according to a third calculation formula; the third calculation formula is: ; wherein, is the width of the second metal layer actually deposited at the target position y on the wafer, W 2d is the initial width of the second metal layer, δ is the spread deviation caused by proximity effect, H is the thickness of the second photoresist layer, Ts is the thickness of the first metal layer, D is the distance from the projection of the crucible on the wafer plane to the surface of the second photoresist layer, is the distance of the current position point on the wafer from the origin, W Lip is the width of the first metal layer located on the inner wall of the second photoresist layer.

[0117] Specifically, referring to Figure 6 , when the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, that is, the lip of the first metal layer will block the second metal layer, so that the second metal layer is deposited in the lip area and cannot reach the wafer surface in the first opening, at this time it belongs to the stage of "lip acting", when calculating the width of the second metal layer in this case, the third calculation formula can be used, to calculate, wherein, W 2d is the initial width of the second metal layer, δ is the spread deviation caused by proximity effect, H is the thickness of the second photoresist layer, Ts is the thickness of the first metal layer, D is the distance from the projection of the crucible on the wafer plane to the surface of the second photoresist layer, is the distance of the current position point on the wafer from the origin, W Lip is the width of the first metal layer located on the inner wall of the second photoresist layer. , wherein Tc is the initial deposition thickness of the wafer center, D' is the vertical distance from the crucible to the wafer surface, is the distance between any point on the wafer and the crucible, R is the distance between the center of the sample table and the center of the wafer, α1 is the included angle between the positive direction of the z axis and the central line of the beam, α1 = 45°, y is the target position of the wafer, and the above parameters are substituted into W Lip calculation formula to obtain W Lip . Finally, W 2d , δ, H, Ts, D, |y| and W Lip are substituted into the third calculation formula to obtain the final width of the second metal layer .

[0118] With reference back to Figure 6 , a brief description is given to the derivation process of the third calculation formula, AB is the width of the first opening, CD is the width of the second metal layer when the lip does not block the second metal layer, MN is the width of the second opening, and EF is the width of the second metal layer deposition beam that can finally pass through the second opening under the influence of the lip. It can be seen that the width of the second metal layer when the lip does not block should be CD, but actually it is EF, and EF=CD-CE-DF, EF=E'F'=MN-MF'-NE', , MF'=(|y| / D)×(H+Ts), NE'=W lip -(|y| / D)×(H+H lip , therefore, it can be calculated that , wherein, .

[0119] It should be noted that the O point of Figure 5 is y=0, Figure 6 only exemplarily shows the calculation method of the width of the second metal layer when y is less than 0, and for the area where y is greater than 0, it is the lip “acting” area, and the calculation method is the same as that shown in Figure 6 , and specific reference can be made to the above content, which will not be repeated here.

[0120] Optionally, with reference to Figure 7 , when the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the thickness of the first metal layer, comprising: when the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the thickness of the first metal layer based on a fourth calculation formula; the fourth calculation formula is: , wherein, is the width of the second metal layer actually deposited at the target position y on the wafer, W 2d is the initial width of the second metal layer, δ is the spread deviation caused by proximity effect, H is the thickness of the second photoresist layer, Ts is the thickness of the first metal layer, D is the distance from the projection of the crucible on the wafer plane to the surface of the second photoresist layer, is the distance of the current position point on the wafer from the origin.

[0121] Specifically, when the first metal layer in the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, i.e., the lip of the first metal layer does not block the second metal layer from passing, so that the second metal layer is not deposited in the lip area and sputters onto the wafer surface in the first opening, this is the stage of the lip "not working", and the deposition width of the metal layer at this time is still the CD. In this case, the width of the second metal layer can be calculated according to the fourth calculation formula, The calculation is performed, where W 2d is the initial width of the second metal layer, δ is the spread deviation caused by proximity effect, H is the thickness of the second photoresist layer, Ts is the thickness of the first metal layer, D is the distance from the projection of the crucible on the wafer plane to the surface of the second photoresist layer, is the distance of the current position point on the wafer from the origin. Substituting the known W 2d , δ, H, Ts, D and |y| into the fourth calculation formula, the final width of the second metal layer .

[0122] Based on the same inventive concept, the present application provides a quantum chip processing device, comprising a sample table, a crucible and a control unit; the sample table is used for placing and rotating a quantum chip, the crucible is used for generating a beam to the surface of the quantum chip; the control unit is used for executing the above-mentioned quantum chip uniformity control method. The functional modules and beneficial effects of the execution method are the same.

[0123] It should be understood that various forms of flow shown above can be used to reorder, add or delete steps. For example, each step described in the present application can be executed in parallel, sequentially or in different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0124] The above specific embodiments do not constitute a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for controlling the uniformity of a quantum chip, characterized in that, include: Provide wafers; A first photoresist layer and a second photoresist layer are sequentially formed on one side surface of the wafer; the first photoresist layer includes a first opening, the second photoresist layer includes a second opening, and the orthographic projection of the first opening on the wafer covers the orthographic projection of the second opening on the wafer. A first metal layer is formed on the side of the second photoresist layer away from the wafer, and the distance from the first metal layer to the center of the wafer and the thickness of the first metal layer are determined. An oxide layer is formed on the surface of the first metal layer opposite to the wafer. A second metal layer is formed on the surface of the oxide layer opposite to the wafer to form a Josephson junction, and the width of the second metal layer is determined. The area of ​​the Josephson junction is determined based on the distance from the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer; Based on the area of ​​the Josephson junction, the compensation amount for the non-uniformity of the quantum chip is determined, and the quantum chip processing equipment is compensated to obtain the quantum chip with good uniformity.

2. The control method according to claim 1, characterized in that, A first metal layer is formed on the side of the second photoresist layer opposite to the wafer, and the distance from the first metal layer to the center of the wafer and the thickness of the first metal layer are determined, including: The first metal layer is formed by depositing the second photoresist layer on the side of the wafer opposite to the wafer using a dual-angle deposition process. The distance from the first metal layer to the center of the wafer is determined based on the designed width of the first metal layer; The thickness of the first metal layer is determined based on the initial deposition thickness at the center of the wafer.

3. The control method according to claim 2, characterized in that, Based on the designed width of the first metal layer, the distance from the first metal layer to the center of the wafer is determined, including: Based on the designed width of the first metal layer and using a first calculation formula, the distance from the first metal layer to the center of the wafer is determined; the first calculation formula is: ;in, The distance from the center of the wafer to the first metal layer after actual deposition at the target location x on the wafer. δ is the design width of the first metal layer, H is the widening deviation caused by proximity effect, D is the thickness of the second photoresist layer, and D is the distance from the projection of the crucible onto the wafer plane to the surface of the second photoresist layer.

4. The control method according to claim 2, characterized in that, The thickness of the first metal layer is determined based on the initial deposition thickness at the center of the wafer, including: Based on the initial deposition thickness at the wafer center, the thickness of the first metal layer is determined using a second calculation formula; the second calculation formula is: Where Ts is the thickness of the first metal layer, Tc is the initial deposition thickness at the center of the wafer, and D' is the vertical distance from the crucible to the wafer surface. R is the distance between any point on the wafer and the crucible, and R is the distance between the center of the sample stage and the center of the wafer.

5. The control method according to claim 1, characterized in that, The first metal layer is located on the surface of the second photoresist layer away from the wafer and on the inner wall of the second opening of the second photoresist layer; A second metal layer is formed on the surface of the oxide layer opposite to the wafer to form a Josephson junction, and the width of the second metal layer is determined, including: The wafer is rotated at a preset angle around a first rotation axis, and a second metal layer is formed on the surface of the oxide layer facing away from the wafer using a dual-angle deposition process to form the Josephson junction; the first rotation axis is parallel to the thickness direction of the wafer. The width of the second metal layer is determined based on the initial width of the second metal layer.

6. The control method according to claim 5, characterized in that, Determining the width of the second metal layer based on its initial width includes: When the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, the width of the second metal layer is determined based on the initial width of the second metal layer and the thickness of the first metal layer; When the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, the width of the second metal layer is determined based on the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer.

7. The control method according to claim 6, characterized in that, When the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, the width of the second metal layer is determined based on the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer, including: When the first metal layer on the inner wall of the second photoresist layer affects the deposition of the second metal layer, the width of the second metal layer is determined according to the initial width of the second metal layer and the width of the first metal layer on the inner wall of the second photoresist layer, based on the third calculation formula. The third calculation formula is: ;in, W represents the width of the second metal layer actually deposited at the target location y on the wafer. 2d δ is the initial width of the second metal layer, δ is the widening deviation caused by the proximity effect, H is the thickness of the second photoresist layer, Ts is the thickness of the first metal layer, and D is the distance from the projection of the crucible onto the wafer plane to the surface of the second photoresist layer. W is the distance of the current position point on the wafer relative to the origin. Lip The width of the first metal layer located on the inner wall of the second photoresist layer.

8. The control method according to claim 6, characterized in that, When the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, the width of the second metal layer is determined based on the initial width of the second metal layer and the thickness of the first metal layer, including: When the first metal layer on the inner wall of the second photoresist layer does not affect the deposition of the second metal layer, the width of the second metal layer is determined based on the initial width of the second metal layer and the thickness of the first metal layer, according to the fourth calculation formula. The fourth calculation formula is: ,in, W represents the width of the second metal layer actually deposited at the target location y on the wafer. 2d δ is the initial width of the second metal layer, δ is the widening deviation caused by the proximity effect, H is the thickness of the second photoresist layer, Ts is the thickness of the first metal layer, and D is the distance from the projection of the crucible onto the wafer plane to the surface of the second photoresist layer. The distance of the current position point on the wafer relative to the origin.

9. The control method according to claim 1, characterized in that, The area of ​​the Josephson junction is determined based on the distance from the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer, including: The area of ​​the Josephson junction is determined based on the distance from the first metal layer to the center of the wafer, the thickness of the first metal layer, and the width of the second metal layer, using the fifth calculation formula. The fifth calculation formula is: ;in, Let the area be the Josephson knot. Ts is the distance from the first metal layer to the center of the wafer, and Ts is the thickness of the first metal layer. The width of the second metal layer.

10. The control method according to claim 1, characterized in that, Based on the area of ​​the Josephson junction, the compensation amount for the non-uniformity of the quantum chip is determined, including: Based on the area of ​​the Josephson junction, the compensation amount for the non-uniformity of the quantum chip is determined according to the sixth calculation formula. The sixth calculation formula is: Where F is the compensation amount. Let be the area of ​​the Josephson knot.

11. A quantum chip processing device, characterized in that, The device includes a sample stage, a crucible, and a control unit; the sample stage is used to place and rotate the quantum chip, the crucible is used to generate a beam to the surface of the quantum chip, and the control unit is used to execute the quantum chip uniformity control method according to any one of claims 1-10.

Images