Laminated structure and preparation method thereof

Abstract

The invention provides a laminated structure and a preparation method thereof, the laminated structure comprises a silicon substrate, a silicon nitride layer and a polycrystalline silicon layer, the silicon nitride layer is located between the silicon substrate and the polycrystalline silicon layer, and the polycrystalline silicon layer is located between the silicon substrate and the polycrystalline silicon layer. The ratio of nitrogen element to silicon element in the silicon nitride layer at the first end, close to the silicon substrate, of the silicon nitride layer is larger than that at the second end, away from the silicon substrate, of the silicon nitride layer. The compression stress generated by the silicon nitride layer is used for balancing or compensating the inherent tensile stress of the polycrystalline silicon layer, so that the problem of wafer warping caused by polycrystalline silicon film deposition is solved, and the overall flatness and physical stability of the wafer are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor materials, and in particular to a layer stack and a method for manufacturing the same. BACKGROUND

[0002] In the field of semiconductor technology, polycrystalline silicon thin film is a basic and key material, which is widely used in the manufacturing process of various microelectronic devices due to its excellent electrical properties and process compatibility.

[0003] However, in the existing polycrystalline silicon thin film deposition process, one technical problem to be solved is that the flatness of the wafer carrying the thin film may be deteriorated after the process is completed. For example, the wafer may have physical deformation such as overall warping, edge deformation, or central area depression. Such deformation poses a challenge to the compatibility of subsequent photolithography, etching, and other high-precision patterning processes, as well as the yield and stability of the final device. SUMMARY

[0004] The present application provides a layer stack and a method for manufacturing the same. The layer stack sets a layer of silicon nitride with a specific composition gradient from nitrogen-rich to silicon-rich between the silicon substrate and the polycrystalline silicon layer, uses the compressive stress generated by the silicon nitride layer to balance or compensate for the inherent tensile stress of the polycrystalline silicon layer, thereby improving the wafer warping problem caused by polycrystalline silicon thin film deposition and improving the overall flatness and physical stability of the wafer.

[0005] The technical solution of the present application is implemented as follows: In a first aspect, the present application provides a layer stack. The layer stack can include a silicon substrate, a silicon nitride layer, and a polycrystalline silicon layer.

[0006] The silicon nitride layer can be located between the silicon substrate and the polycrystalline silicon layer, and The ratio of nitrogen elements to silicon elements in the silicon nitride layer can be greater at a first end of the silicon nitride layer closer to the silicon substrate than at a second end of the silicon nitride layer farther from the silicon substrate.

[0007] In some examples, the ratio of nitrogen elements to silicon elements in the silicon nitride layer can gradually decrease from the first end to the second end.

[0008] In some examples, at the first end, the ratio of nitrogen elements to silicon elements in the silicon nitride layer can be greater than 1.33.

[0009] In some examples, the polycrystalline silicon layer includes a seed layer and a bulk growth layer arranged in sequence, the seed layer being in contact with the silicon nitride layer, and the bulk growth layer being configured to perform epitaxial growth on the basis of the crystal grains provided by the seed layer.

[0010] In some examples, the silicon nitride layer contains silicon elements originating from the silicon substrate at the first end.

[0011] In some examples, the silicon nitride layer comprises at least one same constituent element as the polysilicon layer at an interface between the silicon nitride layer and the polysilicon layer.

[0012] In some examples, the silicon nitride layer has a compressive stress, and the polysilicon layer has a tensile stress.

[0013] In some examples, a product of an absolute value of the compressive stress and a thickness of the silicon nitride layer is within a predetermined range of a difference between a product of an absolute value of the tensile stress and a thickness of the polysilicon layer.

[0014] In some examples, the absolute value of the compressive stress is within a range of 300 Mpa to 800 Mpa, and the absolute value of the tensile stress is within a range of 200 Mpa to 600 Mpa.

[0015] In some examples, the thickness of the silicon nitride layer is within a range of 50 nm to 500 nm.

[0016] In some examples, the warpage of the laminated structure is less than 50 μm.

[0017] In some examples, the laminated structure further comprises a silicon dioxide layer between the silicon nitride layer and the polysilicon layer.

[0018] In a second aspect, the present application provides a method for manufacturing a laminated structure, which can be used to manufacture the laminated structure according to the first aspect, and can comprise: forming a silicon nitride layer on a silicon substrate, such that in the silicon nitride layer, a ratio of nitrogen element to silicon element is greater at a first end of the silicon nitride layer close to the silicon substrate than at a second end of the silicon nitride layer away from the silicon substrate; and forming a polysilicon layer on the silicon nitride layer to obtain the laminated structure.

[0019] In some examples, forming the silicon nitride layer on the silicon substrate comprises gradually decreasing the ratio of nitrogen element to silicon element in the silicon nitride layer from the first end to the second end.

[0020] In some examples, forming the silicon nitride layer on the silicon substrate comprises forming the silicon nitride layer by a low pressure chemical vapor deposition method.

[0021] In some examples, forming the silicon nitride layer on the silicon substrate comprises: forming the first end with ammonia as a main reaction gas; forming the second end with dichlorosilane as the main reaction gas.

[0022] In some examples, forming the polysilicon layer on the silicon nitride layer comprises: depositing a seed layer on the silicon nitride layer at a first temperature; and depositing a bulk growth layer on the seed layer at a second temperature higher than the first temperature, such that the bulk growth layer epitaxially grows on the seed layer-provided grain base.

[0023] In some examples, the step of forming the polysilicon layer further comprises: monitoring in real time a difference in thermal radiation between an edge and a center of the silicon substrate and the silicon nitride layer; and dynamically adjusting a process pressure used to form the polysilicon layer according to the difference.

[0024] In some examples, the method of manufacturing further comprises forming a silicon dioxide layer between the silicon nitride layer and the polysilicon layer.

[0025] The present application provides a layer stack and a method of manufacturing the same. The layer stack includes a specially designed silicon nitride layer with gradient composition disposed between a silicon substrate and a polysilicon layer. Specifically, the silicon nitride layer contains a higher proportion of nitrogen element at one end close to the silicon substrate than at the other end away from the silicon substrate. With this structural design, the silicon nitride layer can have a specific compressive stress, thereby helping to balance or offset the inherent tensile stress of the overlying polysilicon layer. As a result, the warpage of the entire wafer can be reduced through effective management and offset of the internal stress, thereby improving the flatness and physical stability of the semiconductor wafer, providing support for the yield and reliability of subsequent high-precision photolithography and other manufacturing processes. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A schematic diagram of a wafer that has developed saddle-shaped warpage.

[0027] Figure 2 A schematic diagram of a wafer that has developed bowl-shaped deformation.

[0028] Figure 3 A schematic cross-sectional view of a layer stack provided by an embodiment of the present application.

[0029] Figure 4 A schematic cross-sectional view of a layer stack provided by another embodiment of the present application.

[0030] Figure 5 A schematic cross-sectional view of a layer stack provided by yet another embodiment of the present application.

[0031] Figure 6 A flowchart of a method of manufacturing a layer stack provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the purposes, technical solutions and beneficial effects of the present application more clear and explicit, the present application will be further described in detail below with reference to the accompanying drawings.

[0033] In the research of polysilicon thin film deposition process in semiconductor manufacturing, it is noticed that the physical morphology of wafers prepared by chemical vapor deposition (CVD) process often shows undesirable changes after the process is completed. Through observation and analysis of a large number of samples, it is found that the wafer after deposition shows a complex deformation mode, for example, see Figure 1 , the "saddle-shaped" warping formed by concave and convex bending along different axial directions, or see Figure 2 , the "bowl-shaped" deformation of the whole bending towards one side. In order to accurately describe these deformations, their geometric shapes can be defined in advance here. The side on which the functional thin film (such as the silicon nitride layer and the polysilicon layer to be described later) is deposited is defined as the "front side" of the wafer or the stacked structure, and the opposite side is defined as the "back side". Accordingly, "concave bending" refers to the shape in which the central part of the wafer is displaced towards its back side, while the edge part is displaced towards its front side. "Convex bending" refers to the shape in which the central part of the wafer is displaced towards its front side, while the edge part is displaced towards its back side.

[0034] Based on this definition, "bowl-shaped" deformation usually refers to the overall wafer showing a single concave or convex bending; while "saddle-shaped" warping is a more complex shape, which refers to the wafer showing concave bending in one axial direction, and convex bending in the other axial direction perpendicular to it. These structural distortions significantly affect the flatness of the wafer, and pose potential challenges to subsequent high-precision patterning, etching and packaging processes.

[0035] In order to explore the root cause of such deformations, the physical mechanism in the deposition process is analyzed in depth. It can be recognized that one of the root causes of the problem lies in the inherent physical properties of the material itself. For example, under high-temperature deposition conditions, there is a significant difference in the coefficient of thermal expansion (CTE) between the polysilicon thin film and the single crystal silicon as the substrate. Specifically, the CTE of polysilicon is about 4.2×10 -6 / °C, while the CTE of single crystal silicon is about 2.6×10 -6 / °C. This mismatch leads to inconsistent shrinkage of the two during cooling from the high-temperature deposition state to room temperature, thus inevitably generating and accumulating significant thermal stress within the film layer system, which is finally manifested in the form of wafer macroscopic warping.

[0036] On this basis, through further experiments and observation, it is found that some typical deposition processes have certain limitations in their inherent process design and control strategies in dealing with this thermodynamic challenge.

[0037] From the perspective of stress control mechanism, the conventional deposition process tends to pay less attention to the introduction of active stress management strategies in the process path. For example, the deposition process lacks the design of pre-applied compensatory stress, nor does it build structures that can offset stress. This makes the tensile stress generated by the polycrystalline silicon thin film during the cooling process almost entirely borne by the single crystal silicon substrate alone, resulting in the entire wafer being in a state of passive strain in structure for a long time.

[0038] From the perspective of interface structure, the microstructure of the polycrystalline silicon thin film is composed of a large number of grains with different orientations, which is directly grown on the single crystal silicon substrate with highly regular atomic arrangement. There is a natural mismatch in the continuity of the lattice between the two. This makes the interface formed by the two mechanically weak and prone to stress concentration. When subjected to thermal cycling, this concentrated stress can induce micro-cracks, delamination or local peeling, etc., thereby affecting the reliability of the entire structure.

[0039] In addition, from the flexibility of process control, the conventional method tends to use a single-stage deposition process at a constant temperature. Although this way of operation is relatively simple, it also makes it lose the opportunity to implement differentiated thermal parameter management in the initial nucleation stage and the subsequent grain growth stage of thin film formation. Due to the lack of such dynamic control means, the microstructure of the thin film is difficult to adjust according to the needs of stress optimization, which may eventually lead to a higher level of residual stress in the system.

[0040] In view of the analysis and understanding of the above problems, a technical path for systematic optimization of polycrystalline silicon deposition stress is considered. This path can be carried out from multiple dimensions such as deposition structure design, interface transition construction and dynamic regulation of process parameters, in order to more effectively regulate and balance the internal stress generated during the deposition process, and thus improve the morphological stability of the wafer and the compatibility of subsequent processes.

[0041] It should be understood that the term "layered structure" used in this application has a specific meaning. In the context of this application, "layered structure" refers to a combination of a silicon substrate and functional film layers formed thereon for stress regulation. Specifically, the layered structure of the present application can itself constitute a complete semiconductor wafer product, for example, it can be used as a stress-optimized substrate; or it can constitute a key component of a more complex semiconductor wafer containing other circuits or components. The following description will describe the layered structure in detail.

[0042] Referring to Figure 3 The embodiments of the present application provide a layered structure 100.

[0043] For example, the layered structure 100 can include a silicon substrate 20. The silicon substrate 20 can serve as a base portion of the layered structure 100. Specifically, in applications, the silicon substrate 20 can be a single-crystal silicon wafer in the semiconductor industry, which serves as a base for the growth of subsequent functional film layers and provides overall mechanical support. Before the deposition of the film layers, the silicon substrate 20 can undergo a series of conventional cleaning steps, such as the RCA cleaning method, to remove organic matter, metal ions, and native oxide layers on the surface, in order to obtain a clean, undamaged initial surface. For the selection of the silicon substrate, for example, its preparation by the Czochralski method or the Float-Zone method, its doping type (P-type or N-type), crystal orientation (such as <100> or <111>), diameter size (such as 8 inches, 12 inches, etc.), thickness, and specific resistivity, etc. can be routinely selected or adjusted by those skilled in the art according to the performance requirements of downstream devices and the compatibility of the process platform, and these parameters themselves do not constitute a particular limitation on the implementation of the present application.

[0044] On the silicon substrate 20, an intermediate film layer can be formed. In some embodiments, this intermediate film layer can be a silicon nitride layer 40. The silicon nitride layer 40 itself can have an intrinsic compressive stress. The presence of this compressive stress enables the silicon nitride layer to play a role in stress adjustment in the entire layered structure.

[0045] The physical origin of the compressive stress possessed by the silicon nitride layer 40 can be understood from multiple aspects. When forming a silicon nitride thin film by chemical vapor deposition (CVD) or other methods, the internal stress is usually the result of the combined action of intrinsic stress and thermal stress. Among them, the intrinsic stress often plays a dominant role, which is closely related to the microstructure and chemical composition of the film. For example, when using hydrogen-containing precursors such as silane and ammonia for deposition, the silicon nitride layer 40 formed will inevitably contain a certain amount of hydrogen elements in the form of Si-H or N-H bonds in the amorphous network. The presence of these hydrogen-containing groups and their behavior in subsequent thermal processes, such as outgassing and network rearrangement, is considered an important reason for the generation of intrinsic compressive stress. In addition, changes in deposition process parameters such as temperature, pressure, gas flow ratio, etc. will directly affect the atomic density, bonding state, and hydrogen content of the film layer, thus providing the possibility for the regulation of the compressive stress size. At the same time, the difference in the thermal expansion coefficient between the silicon nitride layer 40 and the silicon substrate 20 will also contribute a part of the thermal stress during the cooling process. Based on the understanding of these stress sources, a silicon nitride layer 40 with a specific compressive stress value can be obtained by setting the formation conditions, for the subsequent overall stress balance.

[0046] Further, to enhance the structural stability and functional adaptability of the silicon nitride layer 40, its internal chemical composition can exhibit a distribution characteristic varying along its thickness direction. For example, the relative proportion of nitrogen element and silicon element in the silicon nitride layer 40 can not be constant. The silicon nitride layer 40 at its one end close to the silicon substrate 20, i.e., the first end 402, can have a relatively high nitrogen element content, presenting a "nitrogen-rich" composition state. While the silicon nitride layer 40 at its other end away from the silicon substrate 20, i.e., the second end 404, can have a relatively high silicon element content, presenting a "silicon-rich" composition state.

[0047] Such a composition variation along the thickness direction can bring a series of associated influences on the overall mechanics and interface characteristics of the stacked structure 100. At the first end 402 of the silicon nitride layer 40, the presence of the nitrogen-rich composition helps to form a unique interface region in terms of physical and chemical properties between the silicon nitride layer 40 and the silicon substrate 20. For example, when deposited by a low-pressure chemical vapor deposition (LPCVD) process, a nitrogen-containing gas (such as ammonia, NH3) can be introduced for a short time in a reaction environment at about 700°C~850°C, so that the surface of the silicon substrate 20 is subjected to a certain degree of nitridation, thereby forming an atomic-level, dense nitrogen-rich interface. The nitrogen-rich interface forms a dense Si-N network structure with a bond length of about 1.73Å, a bond energy of about 4.5eV, and a Young's modulus of up to 280GPa, which is significantly higher than the 170GPa of pure silicon, thereby effectively suppressing the lateral shrinkage deformation of the polysilicon during cooling. Such an interface region is usually accompanied by stronger interface bonding. At the second end 404 of the silicon nitride layer 40, the silicon-rich composition makes the surface properties of the silicon nitride layer 40 closer to those of silicon material, providing a more compatible surface environment for the subsequent nucleation and growth of polysilicon.

[0048] On the silicon nitride layer 40, a polysilicon layer 60 can be further formed. The polysilicon layer 60 plays a key electrical function role in many semiconductor devices, such as the gate of a transistor. However, from the perspective of physical mechanics, the polysilicon layer deposited by a high-temperature process, such as in an LPCVD reactor at a temperature range of 580°C~650°C and a pressure range of 0.1 Torr~1 Torr, using a precursor such as silane (SiH4) or disilane (Si2H6) for thermal decomposition, usually remains a significant tensile stress, e.g., +200MPa~+600MPa, after cooling from the high-temperature deposition state to room temperature.

[0049] Thus, the overall synergy of the layer stack 100 provided by the embodiments of the present application is exhibited. A polysilicon layer 60 with intrinsic tensile stress and a silicon nitride layer 40 with intrinsic compressive stress are integrated by a specific stacking sequence. Due to the opposite directions of the two kinds of stress, the compressive stress of the silicon nitride layer can effectively counterbalance and weaken the tensile stress of the polysilicon layer inside the layer stack. The mutual counterbalance of the internal stress makes the net stress applied on the entire silicon substrate significantly reduced, thereby helping to suppress the warping deformation of the wafer and improve the overall flatness thereof.

[0050] It can be understood that any specific parameters, materials or process steps described herein are illustrative only and not restrictive. For example, in some embodiments, a silicon dioxide layer can be additionally provided between the silicon nitride layer 40 and the polysilicon layer 60, which can further improve the interface bonding energy or play other roles. Similarly, the deposition process of the polysilicon layer can also include more complex steps, such as depositing a thin seed layer first, then depositing the main layer, and adjusting the grain structure by two-stage temperature rising, etc. These additional or alternative technical means for optimizing the overall effect can be used by those skilled in the art based on the core idea disclosed in the present application. Various modifications and combinations can be made by those skilled in the art based on the core idea disclosed in the present application, and these embodiments not listed one by one should be considered as included in the protection scope of the present application.

[0051] In summary, the present application provides a layer stack 100. The layer stack 100 includes a specially designed silicon nitride layer 40 with gradient composition provided between a silicon substrate 20 and a polysilicon layer 60. Specifically, the silicon nitride layer 40 contains a higher proportion of nitrogen element at one end close to the silicon substrate 20 than at the other end away from the silicon substrate 20. With this structural design, the silicon nitride layer can have a specific compressive stress, thereby helping to balance or compensate for the inherent tensile stress of the overlying polysilicon layer. Thus, by effectively managing and offsetting the internal stress, the warpage of the entire wafer can be reduced, thereby improving the flatness and physical stability of the semiconductor wafer, providing support for the yield and reliability of subsequent high-precision photolithography and other manufacturing processes.

[0052] For the silicon nitride layer 40, a region connecting the first end 402 and the second end 404 thereof can be, for example, a compositionally smooth transition region. More specifically, the ratio of nitrogen element to silicon element in the silicon nitride layer 40 can exhibit a gradually decreasing trend from the first end 402 to the second end 404. This "gradual decrease" can be a continuous, smooth change rather than a stepwise mutation. In comparison with an interface of composition mutation, a compositionally graded bulk structure has its physical properties such as lattice parameters and thermal expansion coefficients gradually transitioned as well. This design helps to evenly distribute the stress gradient within the layer in the thickness direction of the film, thereby avoiding the formation of a stress concentration region at a specific depth, which is beneficial to improving the structural integrity of the silicon nitride layer 40 itself and its reliability when subjected to tests such as thermal shock.

[0053] Further, the "nitrogen-rich" state of the silicon nitride layer 40 at the first end 402 can be more precisely defined. For example, at the first end 402, the atomic ratio of nitrogen element to silicon element in the silicon nitride layer 40 can be greater than 1.33.

[0054] Since the stoichiometric ratio of ideal silicon nitride (Si3N4) is 4:3, i.e., approximately equal to 1.33, a ratio greater than 1.33 means that an ultra-stoichiometric, extremely nitrogen-rich thin layer is formed at the interface close to the silicon substrate 20. This extremely nitrogen-rich composition state helps to form a dense-bonded, more structurally rigid interface layer in the initial stage of contact with the silicon substrate 20, thereby maximizing the interfacial adhesion and helping to generate a higher compressive stress value in the initial layer, providing a stronger foundation for the stress compensation ability of the entire layer structure 100.

[0055] For the polysilicon layer 60, it can itself have a more fine internal structure. For example, referring to Figure 4 The polysilicon layer 60 can include a seed layer 602 and a main growth layer 604 arranged in sequence. The seed layer 602 can be located between the silicon nitride layer 40 and the main growth layer 604, and the seed layer 602 is in contact with the silicon nitride layer 40.

[0056] The dual-layer structure with different grain sizes can be achieved by a two-step deposition process. Specifically, a seed layer 602 with a thickness of 5-10 nm and a grain size of 20-50 nm can be first deposited at a relatively low first temperature, e.g., 600 °C, to provide a high density of uniformly distributed nucleation sites on the silicon nitride layer 40. Subsequently, a bulk growth layer 604 can be deposited at a relatively high second temperature, e.g., 650 °C. The second temperature is set to be relatively higher than the first temperature to increase the rate of epitaxial growth. Since the seed layer 602 has provided a uniform nucleation template, the bulk growth layer 604 will be epitaxially grown on the basis of the grains provided by the template, thereby configured to quickly form a polycrystalline silicon with small and uniform grain sizes. By such a two-stage process of seed layer induced growth, the micro-uniformity of the polycrystalline silicon layer 60 can be improved, e.g., the standard deviation of the grain size distribution of the polycrystalline silicon layer 60 can be less than ±20 nm. In some examples, the standard deviation of the grain size distribution of the polycrystalline silicon layer 60 can be reduced from about ±35 nm of a conventional process to about ±12 nm, which not only helps to ensure good adhesion of the polycrystalline silicon layer 60 to the silicon nitride layer 40, but also improves the electrical properties of the film layer.

[0057] Further, according to some embodiments of the present application, the silicon nitride layer 40 can contain silicon elements originating from the silicon substrate 20 in its first end 402 close to the silicon substrate 20. This can occur naturally during the initial deposition stage of the silicon nitride layer 40, especially when a surface pre-nitridation process is performed, high temperature can drive some silicon atoms on the surface of the silicon substrate 20 to react with the nitrogen-containing reactive gas, or to migrate upward and diffuse into the initially formed few atomic layers of silicon nitride, thereby forming an atomic-level, compositionally interpenetrating interface transition zone between the silicon substrate 20 and the silicon nitride layer 40.

[0058] In response, according to some other embodiments of the present application, the silicon nitride layer 40 naturally contains the same constituent element, silicon, as the overlying polycrystalline silicon layer 60 at its interface with the polycrystalline silicon layer 60, i.e., at the second end 404, due to its own design as a "silicon-rich" state. By forming such compositionally continuous transition or interpenetrating regions at the upper and lower interfaces of the stacked structure, the sharp physical interface caused by material discontinuity can be effectively eliminated, and replaced by a more "blurred" and "gradual" transition zone. This design can greatly enhance the bonding force between adjacent film layers, thereby significantly improving the anti-delamination and anti-cracking ability of the entire stacked structure 100 when subjected to thermal cycling or mechanical stress.

[0059] In addition, the layer stack 100 is physically characterized by the fact that the silicon nitride layer 40 therein has a net compressive stress, while the polysilicon layer 60 has a net tensile stress. This clear opposition in stress properties is the physical basis for the stress counterbalancing and weakening effects described above. This clear feature of the technology makes it possible for a self-regulating mechanical system to exist within the layer stack, thereby enabling stable and controllable influence on the warping of the wafer as a whole.

[0060] In order to describe this mechanical principle more specifically and quantitatively, the parameter “stress-thickness product” can be introduced, which refers to the product of the stress value and the thickness of the film, and is used to represent the contribution of a single film to the overall bending of the layer stack 100.

[0061] Based on the above definition of the direction of deformation, the mechanical model in the layer stack 100 can be understood as follows: the tensile stress of the polysilicon layer 60 tends to cause the layer stack 100 to bend concavely; while the compressive stress of the silicon nitride layer 40 tends to cause the structure to bend convexly in the opposite direction. The ideal state in which these two forces cancel each other out can be conceptually expressed by the following formula: σ SiN ×t SiN +σ Poly ×t Poly ≈0.

[0062] Here, σ SiN represents the compressive stress of the silicon nitride layer 40, t SiN represents the thickness of the silicon nitride layer 40; σ Poly represents the tensile stress of the polysilicon layer 60, t Poly represents the thickness of the polysilicon layer 60. Here, the positive and negative of the stress are used to represent its physical direction: generally, the tensile stress that tends to cause concave bending is positive, while the compressive stress that tends to cause convex bending is negative. Based on this convention, σ Poly is usually positive, while σ SiN is usually negative.

[0063] In specific engineering practice, the above idealized model is transformed into a more operational criterion, which is to control the difference between the product of the absolute value of the compressive stress of the silicon nitride layer 40 and its thickness (|σ SiN |×t SiN ) and the product of the absolute value of the tensile stress of the polysilicon layer 60 and its thickness (|σ Poly |×t Poly ) within a “predetermined range”.

[0064] The "predetermined range" here is an engineered concept. It is not simply to pursue the above difference to be zero, but to set an acceptable tolerance window according to the application requirements of the final product and the compatibility of subsequent processes. For example, in order to ensure that the final warpage of the wafer can meet the requirements (for example, less than 50 μm) of a certain process (such as high-precision photolithography), the range that the net stress thickness product must meet can be calculated in advance through a mechanical model. This calculated range, that is, the "predetermined range" here. In other application scenarios, the range can even be intentionally set as an interval that does not contain zero (for example, a slight net compressive stress range) to pre-compensate for the tensile stress that may be introduced in subsequent process steps.

[0065] The stress values in the laminated structure 100 can be controlled through the deposition process so that they fall within a specific range that is conducive to achieving balance. For example, the absolute value of the compressive stress of the silicon nitride layer 40 can be in the range of 300 Mpa~800 Mpa, and the absolute value of the tensile stress of the polysilicon layer 60 can be in the range of 200 Mpa~600 Mpa. These numerical ranges are typical stress values that can be stably achieved through reasonable control of process parameters under standard semiconductor manufacturing processes (such as LPCVD).

[0066] The thickness of the silicon nitride layer 40 as a stress compensation layer, that is, t SiN It can also be in the range of 50 nm~500 nm. This range is set to balance the effectiveness of stress compensation and the efficiency of manufacturing costs.

[0067] By adopting one or more combinations of the above structural features, the laminated structure 100 can exhibit excellent morphological stability. For example, the warpage of the entire laminated structure 100 can be controlled to be less than 50 μm. This index has important practical significance for semiconductor manufacturing, ensuring the accuracy of pattern transfer and the final yield of devices. In a specific experiment, it has been confirmed that the wafer warpage can be reduced from 140 μm of the traditional process to 23.8 μm by using the technical solution of the present application, which has a significant effect.

[0068] The laminated structure 100 can also be fine-tuned in structure. For example, referring to Figure 5 A silicon dioxide layer 50 can be additionally provided between the silicon nitride layer 40 and the polysilicon layer 60. The silicon dioxide layer 50 can be formed by thermal oxidation or chemical vapor deposition, for example. Moreover, the silicon dioxide layer 50 can play multiple beneficial roles, such as serving as an excellent adhesion layer to increase the interfacial binding energy, or as an electrical isolation layer or diffusion barrier layer.

[0069] Referring to Figure 6Some embodiments of the present application also provide a method for preparing the layer structure 100. The method can include steps S02-S04.

[0070] In step S02, a silicon nitride layer 40 is formed on the silicon substrate 20, such that in the silicon nitride layer 40, the ratio of nitrogen element to silicon element is greater at a first end of the silicon nitride layer 40 close to the silicon substrate 20 than at a second end of the silicon nitride layer 40 away from the silicon substrate 20.

[0071] In step S04, a polysilicon layer 60 is formed on the silicon nitride layer 40 to obtain the layer structure 100.

[0072] By performing step S02, a thin film of silicon nitride (Si x N y ) is formed on the silicon substrate, i.e. the silicon nitride layer 40. The silicon nitride layer 40 can be prepared by chemical vapor deposition (CVD) or the like, for example, by a low pressure chemical vapor deposition (LPCVD) process. The thickness of the silicon nitride layer 40 can be selected in the range of 50-500 nm, for example, to match the stress generated by the polysilicon layer of different thickness.

[0073] Step S02 can be designed to gradually change the composition of the silicon nitride layer 40, so that the formed silicon nitride layer 40 not only generates compressive stress, but also forms a good interface with the silicon substrate 20 and the polysilicon layer 60 to be formed subsequently on the silicon nitride layer 40. Specifically, during deposition, by precisely controlling the flow ratio of nitrogen-containing gas such as ammonia (NH3) to silicon-containing gas such as dichlorosilane (SiH2Cl2), the formed silicon nitride layer 40 presents a smooth transition from the nitrogen-rich region close to the silicon substrate, i.e. the first end 402, to the silicon-rich region away from the silicon substrate, i.e. the second end 404, along its thickness direction.

[0074] For example, in the initial stage of deposition, a higher proportion of nitrogen-containing gas can be introduced first to form a nitrogen-rich interface with a nitrogen-silicon atomic ratio (N / Si) greater than the stoichiometric ratio of 1.33 on the surface of the silicon substrate 20 to enhance adhesion and introduce initial compressive stress. Subsequently, during the deposition process, the flow rate of silicon-containing gas is gradually increased or the flow rate of nitrogen-containing gas is gradually reduced until a silicon-rich state is formed on the top surface of the silicon nitride layer 40, providing a more compatible growth interface for the subsequent deposition of the polysilicon layer. This composition gradient design avoids stress concentration caused by sudden changes in physical properties between different materials, forming an excellent stress buffer layer.

[0075] Those skilled in the art can understand that the specific deposition temperature, reaction chamber pressure, gas flow rate, composition gradient rate and other process parameters can be adjusted according to the equipment used, the size and thickness of the silicon substrate, and the magnitude of the stress to be compensated, to obtain a silicon nitride layer 40 with a specific compressive stress value, for example, -300 MPa ~ -800 MPa.

[0076] After the deposition of the silicon nitride layer 40 in step S02 is completed, the deposition of the target polysilicon layer 60 on the silicon nitride layer 40 is continued, i.e., step S04 is performed. Step S04 can also use a chemical vapor deposition process, which is carried out at a conventional deposition temperature of polysilicon, for example, 600 ℃ ~ 650 ℃.

[0077] Due to the presence of the silicon nitride layer 40 with gradient compressive stress in step S02, when cooling from the high-temperature deposition environment to room temperature, the tensile stress generated by the polysilicon layer 60 can be effectively compensated by the compressive stress of the silicon nitride layer 40. This balance of internal stress significantly reduces the net stress of the entire laminated structure, thereby greatly inhibiting the occurrence of warping deformation.

[0078] In some embodiments, in order to further optimize the electrical properties and stress state of the polysilicon layer 60, step S04 can also use a multi-stage deposition process. For example, a fine-grained polysilicon seed layer can be first deposited at a relatively low temperature, which ensures the uniformity of nucleation and provides a high density of nucleation sites for subsequent growth; then, a main growth layer is deposited at a relatively high temperature. The higher temperature here can increase the crystal growth rate. Since the growth is induced based on the seed layer, it is possible to achieve a polysilicon layer 60 with small and uniform grain size, i.e., high and uniform grain boundary density, at a high deposition rate.

[0079] During the formation of the polysilicon layer 60, dynamic control means can also be introduced. For example, the difference in thermal radiation between the edge and center of the silicon substrate can be monitored in real time, which can reflect the actual temperature and growth rate of different regions of the wafer. According to the monitored difference, the process pressure can be dynamically adjusted, for example, within ±0.03 Torr to compensate, to ensure that the final polysilicon layer 60 has a high degree of thickness uniformity, for example, within ±2%.

[0080] In the entire preparation method, the step of forming the silicon nitride layer is designed to have compressive stress, and the step of forming the polysilicon layer is designed to have tensile stress, so that after the structure preparation is completed, the internal stress can reach the expected balanced state.

[0081] Further, between step S02 and step S04, the preparation method can further comprise step S03, i.e. after forming the silicon nitride layer 40 and before forming the polysilicon layer 60, a silicon dioxide layer 50 is formed on the silicon nitride layer 40.

[0082] The technical solutions of the present application are further described in detail below through specific examples, but these examples should not be understood as limiting the scope of protection of the present application.

[0083] Embodiment 1 The present embodiment provides a preparation method of a layer structure.

[0084] In step S02, the silicon nitride layer 40 is formed by using the LPCVD process. First, the temperature of the reaction chamber is set to 800℃, ammonia (NH3) is introduced and the pressure is maintained at 0.3Torr to form a nitrogen-rich interface on the surface of the silicon substrate, at which time the N / Si ratio is greater than 1.33. Subsequently, dichlorosilane (SiH2Cl2) is introduced into the reaction chamber as a silicon source gas while maintaining the total gas pressure at 0.3Torr~1.0Torr, and the introduction rate is gradually increased at a rate of 1.0sccm / min until the flow ratio of ammonia to dichlorosilane reaches 1 / 10, forming a silicon nitride layer 40 with a thickness of 200nm, which transitions from nitrogen-rich to silicon-rich.

[0085] In step S04, the polysilicon layer with a thickness of 1000nm is deposited on the silicon nitride layer 40 by continuing to use the LPCVD process at a temperature of 620℃.

[0086] Embodiment 2 The method provided in the present embodiment is basically the same as that in Embodiment 1, and the difference lies in the composition gradient rate and the final thickness of the silicon nitride layer 40.

[0087] In step S02, the introduction rate of dichlorosilane (SiH2Cl2) is gradually increased at a rate of 2.0sccm / min until a silicon nitride layer 40 with a thickness of 400nm is formed. The remaining steps and parameters are the same as those in Embodiment 1. The present embodiment is suitable for scenarios where a thicker or higher tensile stress polysilicon layer needs to be compensated.

[0088] Embodiment 3 The method provided in the present embodiment is basically the same as that in Embodiment 1, and the difference lies in the silicon source gas used in step S02 and the deposition temperature.

[0089] In step S02, the temperature of the reaction chamber is set to 780℃, and dichlorosilane (SiH2Cl2) is used as the silicon source gas, and the remaining parameters are the same as those in Embodiment 1. The present embodiment shows that the technical solutions of the present application can be implemented using different precursors and process windows.

[0090] Example 4 This embodiment further optimizes step S04 based on embodiment 1.

[0091] In step S04, a two-stage method is used to deposit the polycrystalline silicon layer 60. First, a fine-grained polycrystalline silicon seed layer with a thickness of 10 nm is deposited at 600 °C. Then, the temperature is increased to 650 °C, and a main growth layer with a thickness of 990 nm is deposited. During the deposition of the main growth layer, the difference in thermal radiation between the wafer edge and center is monitored in real time using an in-situ thermal radiation sensor, and the chamber pressure is dynamically adjusted within ±0.03 Torr based on this difference to ensure high uniformity of film thickness. The seed layer is formed at a lower deposition temperature to obtain a dense polycrystalline silicon structure. This structure has a high density of grain boundaries, which on the one hand enhances the interfacial bonding with the underlying silicon nitride layer and prevents film delamination; on the other hand, it provides a high density of nucleation sites for the subsequent growth of the main layer, which is beneficial for forming a polycrystalline silicon layer 60 with smaller grain size, higher grain boundary density, and better electrical performance.

[0092] Example 5 Based on Example 4, this embodiment adds a silicon dioxide layer 50 between the silicon nitride layer 40 and the polysilicon layer 60.

[0093] Specifically, after step S02 and before step S04, step S03 is added: forming a silicon dioxide layer 50 on the silicon nitride layer 40. A silicon dioxide layer 50 with a thickness of 20 nm is deposited on the silicon-rich surface of the silicon nitride layer 40 using a chemical vapor deposition process. This silicon dioxide layer 50 can serve as an adhesive layer to further enhance interfacial bonding energy, and can also serve as an electrical isolation layer or a diffusion barrier layer. Subsequently, the same step S04 as in Example 4 is performed.

[0094] Example 6 The method provided in this embodiment is basically the same as that in Embodiment 4, except that the deposition time of the main growth layer in step S04 is extended to obtain a polycrystalline silicon layer 60 with a thickness of 2.1 μm. This embodiment is used to verify the stress improvement effect of this application on thick film deposition.

[0095] Comparative Example 1 This comparative example simulates a conventional single-layer polycrystalline silicon deposition process. The same silicon substrate as in Example 1 was cleaned and placed directly into the LPCVD reaction chamber. The reaction chamber temperature was set to 620°C, and silane gas was introduced to deposit a 1000nm thick polycrystalline silicon layer on the silicon substrate.

[0096] Comparative Example 2 This comparative example is used to verify the necessity of the "gradient composition" technical feature of the silicon nitride layer in this application. After cleaning, the same silicon substrate as in Example 1 was placed in an LPCVD reaction chamber. First, at 800°C, dichlorosilane and ammonia were simultaneously introduced to deposit a stoichiometric silicon nitride (Si3N4) layer with a thickness of 200 nm and uniform chemical composition on the surface of the silicon substrate. Then, the same polycrystalline silicon layer deposition steps as in Comparative Example 1 were performed.

[0097] Comparative Example 3 Based on Comparative Example 1, the thickness of the polycrystalline silicon layer was increased to 2.1 micrometers for direct comparison with Example 6, to verify the effect of this application in the thick film deposition scenario.

[0098] Effect verification The laminated structures 100 prepared in each Example 1 and the comparative example were tested. The maximum warpage value of the surface of each laminated structure 100 was measured using a laser scanning flatness tester; the thickness uniformity of the film was measured using a four-probe stage; and the presence of cracks at the interface between the polycrystalline silicon layer and the underlying silicon nitride layer was observed using a scanning electron microscope. The test results are shown in Table 1.

[0099] Table 1

[0100] The data in Table 1 clearly show that, compared with Comparative Example 1 which directly deposited polycrystalline silicon, Comparative Example 2, which used a uniform silicon nitride layer, improved warpage to some extent, but the effect was limited, and there was a risk of microcracks caused by excessive interfacial stress.

[0101] However, in Example 1 of this application, the maximum warpage value is significantly lower than that of Comparative Examples 1, 2, and 3 by employing a gradient silicon nitride layer 40. Furthermore, Example 2 optimizes warpage by introducing more prestress, achieving the lowest warpage value (23.8 μm) while ensuring minimal decrease in film uniformity. Examples 4 and 5 achieve optimal film thickness uniformity through two-step polysilicon deposition while maintaining a warpage value <40 μm. This demonstrates that there is a synergistic effect between the gradient nitride layer and the two-step deposition process in the stacked structure 100 provided by the embodiments of this application, successfully solving the long-standing wafer warpage problem in the prior art.

[0102] It should be noted that the technical solutions described in this application can be combined arbitrarily without conflict.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A layered structure, characterized by The laminated structure comprises a silicon substrate, a silicon nitride layer and a polysilicon layer, wherein, The silicon nitride layer is located between the silicon substrate and the polysilicon layer, and The ratio of nitrogen element to silicon element in the silicon nitride layer is greater at a first end of the silicon nitride layer close to the silicon substrate than at a second end of the silicon nitride layer away from the silicon substrate.

2. The laminate structure according to claim 1, characterized in that, The ratio of nitrogen element to silicon element in the silicon nitride layer gradually decreases from the first end to the second end.

3. The laminate structure according to claim 2, characterized in that At the first end, the ratio of nitrogen element to silicon element in the silicon nitride layer is greater than 1.

33.

4. The laminate structure according to claim 1, wherein The polysilicon layer comprises a seed layer and a bulk growth layer arranged in sequence, the seed layer being in contact with the silicon nitride layer, wherein the bulk growth layer is configured to epitaxially grow on the basis of crystal grains provided by the seed layer.

5. The laminate structure according to claim 1, wherein The silicon nitride layer contains silicon element from the silicon substrate in the first end.

6. The laminate structure according to claim 5, characterized in that The silicon nitride layer contains at least one constituent element same as the polysilicon layer at the interface between the silicon nitride layer and the polysilicon layer.

7. The laminate structure according to any one of claims 1 to 6, characterized in that, The silicon nitride layer has compressive stress, and the polysilicon layer has tensile stress.

8. The laminate structure according to claim 7, characterized in that The difference between the product of the absolute value of the compressive stress and the thickness of the silicon nitride layer and the product of the absolute value of the tensile stress and the thickness of the polysilicon layer is within a predetermined range.

9. The laminate structure according to claim 7, wherein The absolute value of the compressive stress is within the range of 300Mpa-800Mpa, and the absolute value of the tensile stress is within the range of 200Mpa-600Mpa.

10. The laminate structure according to any one of claims 1 to 6, characterized in that, The thickness of the silicon nitride layer is within the range of 50nm-500nm.

11. The laminate structure according to any one of claims 1 to 6, characterized in that, The warpage of the laminated structure is less than 50μm.

12. The laminate structure according to any one of claims 1 to 6, characterized in that, The laminated structure further comprises a silicon dioxide layer between the silicon nitride layer and the polysilicon layer.

13. A method for producing a layered structure, characterized by The preparation method is used for preparing the laminated structure according to any one of claims 1-12, and comprises: forming a silicon nitride layer on a silicon substrate, so that in the silicon nitride layer, the ratio of nitrogen element to silicon element is greater at a first end of the silicon nitride layer close to the silicon substrate than at a second end of the silicon nitride layer away from the silicon substrate; and forming a polysilicon layer on the silicon nitride layer to obtain a laminated structure.

14. The method of claim 13, wherein The forming of the silicon nitride layer on the silicon substrate comprises gradually decreasing the ratio of nitrogen element to silicon element in the silicon nitride layer from the first end to the second end.

15. The method of claim 14, wherein the method further comprises: The forming of the silicon nitride layer on the silicon substrate comprises forming the silicon nitride layer by using a low-pressure chemical vapor deposition method.

16. The method of claim 14, wherein The forming of the silicon nitride layer on the silicon substrate comprises: forming the first end by using ammonia as the main reaction gas; and forming the second end by using dichlorosilane as the main reaction gas.

17. The method of producing a layered structure according to claim 13, characterized by, The forming of the polysilicon layer on the silicon nitride layer comprises: depositing a seed layer on the silicon nitride layer at a first temperature; and depositing a bulk growth layer on the seed layer at a second temperature higher than the first temperature, so that the bulk growth layer epitaxially grows on the basis of crystal grains provided by the seed layer.

18. The method for producing a layered structure according to claim 13, characterized by, The forming of the polysilicon layer further comprises: real-time monitoring the difference in thermal radiation between the edge and the center of the silicon substrate and the silicon nitride layer; and dynamically adjusting a process pressure used to form the polysilicon layer based on the difference.

19. The method of producing a laminated structure according to any one of claims 13 to 18, characterized in that, The method for manufacturing further includes forming a silicon dioxide layer between the silicon nitride layer and the polysilicon layer.

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