Method of forming semiconductor device

Abstract

The method includes forming a first layer over a second layer; performing a laser treatment process on the first layer, where the laser treatment process includes directing a laser beam into the first layer, where the laser beam modifies the first layer; and after performing the laser treatment process on the first layer, performing a planarization process on the first layer to remove the first layer, where the planarization process exposes the second layer. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to methods of forming semiconductor devices. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor layers over a semiconductor substrate, and patterning each material layer using photolithography to form electrical circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more components to be integrated into a given area. During the formation of higher density semiconductor devices, uneven topography of layers can impact yield and device performance. Accordingly, improved techniques to improve planarity of layers are desired. SUMMARY

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first layer over a second layer; performing a laser treatment process on the first layer, wherein the laser treatment process comprises directing a laser beam into the first layer, wherein the laser beam modifies the first layer; and after performing the laser treatment process on the first layer, performing a planarization process on the first layer to remove the first layer, wherein the planarization process exposes the second layer.

[0005] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: depositing a first layer over a substrate, wherein the first layer is a first material; and removing an upper portion of the first layer, comprising: scanning a laser beam across a top surface of the first layer, wherein, after scanning the laser beam, the upper portion of the first layer has different physical properties than an underlying lower region of the first layer; and polishing the upper portion of the first layer to expose the lower region of the first layer.

[0006] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first bonding layer over a first substrate; forming a second bonding layer over a second substrate; bonding the first bonding layer to the second bonding layer using a fusion bonding process; heating the first substrate using a first laser; and removing the first substrate using a first mechanical planarization process. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the present disclosure embodiments can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to common practice, the various drawings are not to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 illustrate intermediate stages in the implementation of a planarization process including a laser treatment process according to some embodiments.

[0009] Figure 7 , Figure 8 , Figure 9 and Figure 10 illustrate intermediate stages in the implementation of a planarization process including a laser treatment process according to some embodiments.

[0010] Figure 11 illustrates a three-dimensional view of an exemplary complementary field effect transistor (CFET) according to some embodiments.

[0011] Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 and Figure 27 are various views of intermediate stages in the manufacture of a CFET according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing various aspects of the present disclosure. Although each of the examples described below is particularly useful for implementing the present disclosure, the following description is not intended to limit the scope of the present disclosure to these examples alone, but rather is intended to cover all alternatives, modifications and equivalents. For example, in the following description, forming a first component over or on a second component can include embodiments in which the first component and the second component are in direct contact, and can also include embodiments in which additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. Furthermore, the present disclosure can refer to a number of reference numerals in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatial or directional terms, such as "below", "under", "lower", "above", "upper" and the like, can be used herein for ease of describing the illustrated examples. The spatial and directional terms should be understood in the context of the orientation of the device as shown in the figures. The device can be oriented in other manners (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein interpreted accordingly.

[0014] Various representative embodiments are described in relation to implementing a planarization process to remove material or to planarize a surface of a layer. Embodiments described herein include implementing a laser treatment process on the material prior to removal by the planarization process. The laser treatment process modifies the material, allowing the material to be more easily removed by the planarization process. This can allow for more precise material removal, and can allow for improved planarity of the resulting planarized surface. For example, implementing a laser treatment process can reduce the impact of initial surface topography on the planarization process, allowing for improved uniformity, reduced dishing, and improved planarity of the resulting planarized surface. Embodiments described herein are intended as illustrative and non-limiting examples, and all suitable changes, materials, applications, manufacturing steps, devices or structures are contemplated as within the scope of the present disclosure.

[0015] Figures 1 to 6 An intermediate step in a planarization process including a laser treatment process is shown, according to some embodiments. Figure 1 A cross-sectional view of an upper layer 20 over a lower layer 10 is shown, according to some embodiments. A subsequently implemented planarization process removes the upper layer 20 to expose the lower layer 10. As Figure 1As shown, the upper layer 20 has an uneven top surface. For example, the top surface of the upper layer 20 may have an uneven topography including roughness, protrusions, depressions, grooves, or any other deviation from flatness. The lower layer 10 and the upper layer 20 may be any suitable material, such as silicon or other semiconductor materials, oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), polymers, sealants, prepregs, other dielectric materials, or other suitable materials or combinations of materials. The lower layer 10 or the upper layer 20 may include a variety of materials or multiple components. The lower layer 10 or the upper layer 20 may be, for example, a wafer or other suitable substrate. All suitable layers or materials are considered to be within the scope of embodiments of this disclosure.

[0016] Figure 2 and Figure 3 A laser processing process is illustrated for an upper layer 20 according to some embodiments. During the laser processing process, a laser source 30 directs a laser beam 32 into the upper layer 20 to modify portions of the upper layer 20. For example, the laser source 30 may generate the laser beam 32 and focus it onto the material of the upper layer 20. During the laser processing process, energy from the laser beam 32 is absorbed by regions of the upper layer 20 located near the laser beam 32, modifying the material of the upper layer 20 in these regions. For example, the energy from the laser beam 32 may heat the material of the upper layer 20 near the laser beam 32, causing the material near the laser beam 32 to expand or undergo other chemical or structural changes. In some cases, the laser beam 32 causes the material to expand, which increases internal stress and may cause cracks, fractures, or deformations in the material. Therefore, after the laser processing process, the modified material is structurally weaker than the unmodified material. In this way, regions of the upper layer 20 are modified by the energy of the laser beam 32, forming modified regions 20' of the upper layer 20.

[0017] During the laser processing, the laser beam 32 can translate across the upper layer 20, extending the modified region 20'. For example, Figure 2 A laser source 30 is shown at a first location above the upper layer 20, and Figure 3 The laser source 30 is shown in a second position, having been translated over the upper layer 20. As the laser beam 32 translates across the upper layer 20, the energy from the laser beam 32 continuously modifies the material of the upper layer 20, extending the modified region 20' across the upper layer 20. In some embodiments, the laser processing can be performed over the entire upper layer 20, modifying the entire upper layer 20. In this way, the modified region 20' can cover the entire upper layer 20, and in such a case, the upper layer 20 can be referred to as the modified upper layer 20' (e.g., see...). Figure 4). Thus, in some cases, a modified upper layer 20' can be formed after the laser processing procedure is completed. The modified upper layer 20' can be formed, for example, by translating the laser beam 32 along a path that covers some or all of the regions of the upper layer 20 in a suitable pattern, such as a path having a raster pattern, a spiral pattern, a grid pattern, or any other suitable pattern. The laser beam 32 can be moved continuously (e.g., scanned) across portions of the upper layer 20, or the laser beam 32 can be moved across portions of the upper layer 20 in one or more discrete steps. In some cases, the laser source 30 can remain stationary while the laser beam 32 is on or while the laser beam 32 is applied to the upper layer 20. In some cases, the laser beam 32 can be turned off periodically or occasionally during the laser processing procedure. Other configurations, applications, movements, or operations of the laser source 30 are possible during the laser processing procedure. In some embodiments, the upper layer 20 can be modified using more than one "pass" of the laser beam 32, such as by performing multiple laser processing procedures along interleaved paths, etc. In some embodiments, multiple laser processing procedures can be performed on the same regions of the upper layer 20. For example, a laser processing procedure can be performed on a previously formed modified region 20' or modified upper layer 20'. In some embodiments, multiple modified regions 20' can be formed, or only portions of the upper layer 20 can be modified using the laser processing procedure.

[0018] In some embodiments, the laser processing procedure modifies the upper layer 20 into a modified upper layer 20' to enable easier and / or more uniform removal of the upper layer 20 using a planarization process. The planarization process can include a chemical mechanical polishing (CMP) process, a lapping process, or another suitable planarization process. In some cases, the laser processing procedure can structurally weaken the upper layer 20 through laser-induced heating, laser-induced damage, or laser-induced chemical changes. For example, heating the material of the upper layer 20 using the laser beam 32 can cause the material of the upper layer 20 to expand, modify the material of the upper layer 20 to have more structural defects, broken bonds, etc. In some cases, the modified upper layer 20' can have a greater volume than the unmodified upper layer 20. This is an example, the laser processing procedure can form the modified upper layer 20' by otherwise modifying a property of the upper layer 20. Forming the modified upper layer 20' that is structurally weaker than the unmodified upper layer 20 can allow the modified upper layer 20' to be removed more easily using the planarization process. For example, the modified upper layer 20' can have a greater removal rate during the planarization process than the unmodified upper layer 20 or than an underlying unmodified layer (e.g., the lower layer 10). In some cases, the modified upper layer 20' can be more chemically active or have a greater etch rate during the planarization process than the unmodified upper layer 20. In this way, performing a laser processing procedure on a layer as described herein can thus reduce the time, material, or cost of planarizing the layer.

[0019] The laser source 30 can include a laser diode or any suitable laser emitting source configured to generate the laser beam 32, with appropriate optics, lenses, optical fibers, etc. In some embodiments, the laser beam 32 has a wavelength in a range of about 300 nm to about 1500 nm, although other wavelengths are possible. The laser source 30 can generate the laser beam 32 with a pulse dwell time in a range of about 1 femtosecond (fs) to about 1000 nanoseconds (ns), and can generate the laser beam 32 with a pulse energy in a range of about 1 microjoule (pJ) to about 1000 millijoules (mJ), although other laser characteristics are possible. The particular wavelength or laser power used in the laser processing procedure can depend on the characteristics of the upper layer 20 and / or the lower layer 10. In some embodiments, the laser beam 32 can be applied continuously to the upper layer 20 during at least a portion of the laser processing procedure. In other embodiments, the laser beam 32 can be pulsed during at least a portion of the laser processing procedure. In some embodiments, the power or other characteristics of the laser beam 32 can be controlled or adjusted to control the amount or depth of modification. For example, the characteristics of the laser beam 32 can be adjusted according to portions of the lower layer 10 and / or the upper layer 20 that have different compositions.

[0020] In some embodiments, the laser beam 32 can be a focused beam, with a focal point 33 of the laser beam 32 located within the upper layer 20. In other embodiments, the laser beam 32 can be focused at or near the top surface of the upper layer 20 or at or near the bottom surface of the upper layer 20. In some embodiments, the focal point 33 of the laser beam 32 is located above the bottom surface of the upper layer 20. For example, the focal point 33 of the laser beam 32 can be located at a distance Dl above the lower layer 10 (e.g., a distance Dl above the bottom surface of the upper layer 20). The distance Dl can be in a range from about 1 pm to about 100 pm, although other distances are possible. In some cases, a target removal surface within the structure can be represented by a dashed line indicating the distance Dl. The distance Dl can depend on the properties of the upper layer 20 and / or the lower layer 10. For example, energy (e.g., heating) from the laser beam 32 can propagate outward from the laser beam 32, causing a bottom portion of the upper layer 20 to be modified by the laser beam 32 even if the laser beam 32 is not focused on the bottom portion of the upper layer 20. The focal point 33 of the laser beam 32 can be separated (e.g., by the distance Dl) from the lower layer 10 to reduce or minimize modification of the lower layer 10 by the laser beam 32. In some cases, a region of the upper layer 20 at or near the focal point 33 of the laser beam 32 can experience a greater amount of modification than a region farther from the focal point 33, or can experience modification at a greater rate than a region farther from the focal point 33. For example, in some cases, heating of the upper layer 20 can be greatest at the focal point 33. In this way, in some cases, a region of the upper layer 20 at or near the top surface of the upper layer 20 can be less modified than a region of the upper layer 20 at or near the bottom surface of the upper layer 20. In some cases, controlling the focal point 33 to be at or near a constant distance (e.g., the distance Dl) above the lower layer 10 can improve the planarity of the resulting top surface of the lower layer 10 after planarization. In some embodiments, the depth of the focal point 33 can be controlled or adjusted to control the depth of the modified upper layer 20'.

[0021] Turning to Figure 4 , according to some embodiments, the upper layer 20 is shown after the laser processing procedure is complete. In this example, the entire upper layer 20 has been modified by the laser processing procedure, forming a modified upper layer 20'. In other embodiments, only a portion of the upper layer 20 is modified by the laser processing procedure, thus forming one or more modified regions 20' in the upper layer 20, rather than forming a completely modified upper layer 20'. In some cases, an upper portion of the lower layer 10 can also be modified by the laser processing procedure. Figure 4

[0022] In Figures 5 to 6 , according to some embodiments, a planarization process is implemented to remove the modified upper layer 20'. Figure 5 ​A modified upper layer 20' is illustratively shown during a planarization process, and Figure 6 A lower layer 10 is shown after the modified upper layer 20' is removed by a planarization process. Figure 5 A planarization tool 40 is shown as it removes portions of the modified upper layer 20'. Figure 5 The planarization tool 40 in FIG. 4 represents any suitable CMP tool, lapping tool, or the like. For example, the planarization process can be a CMP process or the like, in which the planarization tool 40 can include a polishing pad or the like. In some cases, a slurry can be used during the planarization process. As previously described, the modified upper layer 20' can be more easily removed than the unmodified upper layer 20 using the planarization tool 40. Thus, in some cases, the conditions, materials (e.g., slurry, polishing pad, or the like), or parameters (e.g., pressure, rotational speed, or the like) used by the planarization tool 40 can be different for removing the modified upper layer 20' than for removing the unmodified upper layer 20. In some cases, because the modified upper layer 20' is more easily removed, the material of the polishing tool 40 can need to be replaced less frequently.

[0023] In some cases, using a laser processing process as described herein can allow for improved planarity after a planarization process is implemented. For example, the top surface of the lower layer 10 after the planarization process can be more planar if the upper layer 20 is modified into a modified upper layer 20 by the laser processing process than if the upper layer 20 is not modified. In some cases, the improved planarity of the lower layer 10 can be due to the modified upper layer 20' being more easily removed relative to the unmodified lower layer 10. Further, controlling the focal point 33 of the laser beam 32 to be about a contact distance (e.g., distance Dl) above the lower layer 10 can result in more uniform planarization. In this way, the techniques described herein can reduce the sensitivity of planarization to surface topography, and can reduce uneven topography, dishing, roughness, bumping, or other deviations from planarity in a planarized layer.

[0024] Figures 7 to 10 Intermediate steps in a planarization process including a laser processing process are shown according to some embodiments. For example, Figures 7 to 10 The planarization process described is similar to the planarization process previously described for Figures 1 to 6 The planarization process described, except that instead of removing a separate upper layer and leaving a remaining lower layer, the planarization process removes an upper portion of a layer and leaves a remaining lower portion of the same layer. For example, according to some embodiments, Figure 7A cross-sectional view of layer 10 is shown. A subsequent planarization process removes upper region 10B of layer 10, leaving lower region 10A of layer 10 unchanged. After the planarization process, lower region 10A of layer 10 has a planarized top surface. The techniques described herein can improve the planarity and uniformity of lower region 10A. In other embodiments, the planarization process can remove an upper portion of the first layer and a portion of the first layer that overlies the second layer. In such embodiments, the planarization process can expose a top surface of the first layer and a top surface of the second layer.

[0025] Figure 8 and Figure 9 A laser treatment process is shown being performed on layer 10 according to some embodiments. During the laser treatment process, laser source 30 directs laser beam 32 into layer 10 to modify upper region 10B of layer 10. For example, laser source 30 can generate laser beam 32 and focus laser beam 32 into the material of layer 10. In this way, portions of upper region 10B are modified by laser beam 32 into modified upper region 10B', as shown in Figure 8 In some embodiments, focal point 33 of laser beam 32 is positioned above the bottom surface of lower region 10A. For example, focal point 33 of laser beam 32 can be positioned at a distance D2 above lower region 10A (e.g., a distance D2 above the bottom of upper region 10B). Distance D2 can be in a range from about 1 pm to about 100 pm, although other distances are possible. In some embodiments, the depth of focal point 33 into layer 10 can be controlled or adjusted to control the depth of modified upper region 10B'. In some embodiments, the power or other characteristics of laser beam 32 can be controlled or adjusted to control the amount or depth of modification. For example, the characteristics of laser beam 32 can be adjusted according to portions of layer 10 having different compositions. Shifting focal point 33 relative to lower region 10A can reduce modification of lower region 10A. Laser beam 32 can be translated across layer 10 during the laser treatment process, extending modified upper region 10B'.

[0026] In Figure 9 , layer 10 is shown after the laser treatment process is complete according to some embodiments. In the example of Figure 9 , the entire upper region 10B has been modified by the laser treatment process, forming modified upper region 10B'. In other embodiments, only portions of upper region 10B are modified by the laser treatment process, thus forming one or more modified upper regions 10B' in layer 10. In some cases, an upper portion of lower region 10A can also be modified by the laser treatment process.

[0027] In Figure 10In some cases, a planarization process is implemented to remove the modified upper region 10B'. The planarization process can be a CMP process or the like, and can be similar to the planarization process previously described for Figure 5 As previously described, the modified upper region 10B' can be more easily removed than the unmodified upper region 10B using the planarization process. The modified upper region 10B' can also be more easily removed than the lower (unmodified) region 10A. In some cases, using the laser treatment process as described herein can allow for improved planarity after the planarization process is implemented to remove the upper region of the layer. For example, the top surface of the lower region 10A after the planarization process can be more planar if the upper region 10B is modified into the modified upper region 10B' by the laser treatment process than if the upper region 10B is unmodified. In some cases, the improved planarity of the lower layer 10 can be due to the modified upper layer 20' being more easily removed than the unmodified lower layer 10. In this way, the techniques described herein can result in a more planar and more uniform planarized surface.

[0028] As an example of using the laser treatment process in the planarization process, Figures 11 to 27 An intermediate stage in the formation of a stacked transistor structure is shown in accordance with some embodiments. In some cases, the stacked transistor structure can be a complementary field effect transistor (CFET) structure. Figures 11 to 27 Embodiments are intended as illustrative examples, and the techniques described herein can be used as part of any suitable process, and can be used to form any suitable device or structure. For example, the techniques described herein can be used to form a fin field effect transistor (FinFET) structure, a planar FET structure, a nanostructure FET structure, other CFET structures, a package, a chip, a die, or other type of device or other type of structure. Any planarization process can also include a laser treatment process when appropriate or desired.

[0029] Figure 11 An example of a stacked transistor 110 (including FETs (transistors) 110U and 110L) is shown in accordance with some embodiments. Figure 11is a three-dimensional view, and some components of the stacked transistor are omitted for clarity. The stacked transistor 110 includes multiple vertically stacked FETs. For example, the stacked transistor can include a lower nanosheet FET 110L of a first device type (e.g., n-type / p-type) and an upper nanosheet FET 110U of a second device type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second device type of the upper nanosheet FET 110U is opposite the first device type of the lower nanosheet FET 110L. The nanosheet FETs 110U and 110L include semiconductor nanosheets 126 (including lower semiconductor nanosheets 126L and upper semiconductor nanosheets 126U), where the semiconductor nanosheets 126 function as channel regions for the nanosheet FETs. The lower semiconductor nanosheets 126L are for the lower nanosheet FET 110L, and the upper semiconductor nanosheets 126U are for the upper nanosheet FET 110U. In other embodiments, the stacked transistor can also be adapted for other types of transistors (e.g., FinFETs, etc.).

[0030] A gate dielectric 178 surrounds the respective semiconductor nanosheet 126. A gate electrode 180 (including a lower gate electrode 180L and an upper gate electrode 180U) is located above the gate dielectric 178. Source / drain regions 162 (including lower source / drain regions 162L and upper source / drain regions 162U) are disposed on opposite sides of the gate dielectric 178 and respective gate electrode 180. Each of the source / drain regions 162 can refer to either a source or a drain, alone or collectively depending on context. Isolation components (not shown) can be formed to separate desired source / drain regions 162 and / or desired gate electrodes 180.

[0031] Figure 11 Reference cross-sections used in later figures are also shown. Cross-section A-A’ is a vertical cross-section parallel to the longitudinal axis of the semiconductor nanosheet 126 of the stacked transistor and in the direction of current flow between, for example, the source / drain regions 162 of the stacked transistor. Cross-section B-B’ is a vertical cross-section perpendicular to cross-section A-A’ and along the longitudinal axis of the gate electrode 180 of the CFET. Cross-section C-C’ is a vertical cross-section parallel to cross-section B-B’ and extending through the source / drain regions 162 of the stacked transistor. For clarity, later figures can refer to these reference cross-sections.

[0032] Figures 12 to 27 Views of intermediate stages in the formation of a stacked transistor (as Figure 11 schematically represented in FIG. 1) are shown in accordance with some embodiments. Figures 12 to 22 Cross-sectional views, Figure 23 three-dimensional views are shown, and Figures 24 to 27A cross-sectional view is shown. In the following discussion, unless otherwise noted, cross-sectional views are along a vertical reference cross-section A-A’ similar to that in Figure 11

[0033] In Figures 12 to 13 In accordance with some embodiments, the lower wafer 123L is bonded to the upper wafer 123U. Figure 12 The wafers 123L / 123U before bonding are shown, and Figure 13 The wafers 123L / 123U after bonding are shown. The lower wafer 123L includes a multilayer stack 122L on a substrate 120, and the upper wafer 123U includes a multilayer stack 122U on a substrate 121. The substrates 120 / 121 can be semiconductor substrates, such as bulk semiconductors, which can be doped (e.g., with p-type or n-type dopants) or undoped. Other substrates, such as multilayer or graded substrates, can also be used. In some embodiments, the semiconductor material of the substrates 120 / 121 can include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; or the like or combinations thereof.

[0034] The multilayer stack 122L of the lower wafer 123L includes a dummy layer 124L, a semiconductor layer 126L, and a bonding layer 127L, and the multilayer stack 122U of the upper wafer 123U includes a dummy layer 124U, a semiconductor layer 126U, and a bonding layer 127U. The multilayer stacks 122L / 122U can be formed of another number of layers than shown. In some embodiments, the dummy layers 124L / 124U are formed of a first semiconductor material, the semiconductor layers 126L / 126U are formed of a second semiconductor material, and the bonding layers 127L / 127U are formed of a dielectric material. The first and second semiconductor materials can be selected from the candidate semiconductor materials of the substrates 120 / 121. The semiconductor layer 126L and the semiconductor layer 126U can be formed of the same second semiconductor material, or can be formed of different semiconductor materials. The first and second semiconductor materials have a high etch selectivity to each other. Thus, the dummy layers 124L / 124U can be selectively removed in subsequent process steps without significantly removing the semiconductor layers 126L / 126U.

[0035] ​In some embodiments, the dummy layers 124L / 124U are formed of or include silicon germanium, and the semiconductor layers 126L / 126U are formed of silicon. To form the multilayer stacks 122L and 122U, layers of first and second semiconductor materials can be deposited over the respective substrates 120 and 121, arranged as shown and described above. The layers of first and second semiconductor materials can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited using processes such as chemical vapor deposition (CVD) processes or atomic layer deposition (ALD) processes, and the like.

[0036] In some embodiments, the bonding layers 127L / 127U are formed of or include a dielectric material suitable for direct bonding (e.g., fusion bonding, dielectric-to-dielectric bonding, oxide-to-oxide bonding, and the like). For example, the bonding layers 127L / 127U can include silicon oxide, silicon oxynitride, and the like. The bonding layers 127L and 127U can be similar materials or different materials. In some embodiments, the bonding layers 127L / 127U can be a material that has a high etch selectivity to the first and / or second semiconductor materials, and thus can be removed at a faster rate than the first and / or second semiconductor materials in subsequent processes. In other embodiments, the bonding layers 127L / 127U are formed of a semiconductor material.

[0037] In Figure 13 , the structure after bonding the bonding layer 127U of the upper wafer 123U to the bonding layer 127L of the lower wafer 123L is shown. The bonding layer 127U can be bonded to the bonding layer 127L using a suitable direct bonding process. For example, the surfaces of the bonding layers 127L / 127U can be treated using a surface preparation process, and then the bonding layer 127U can be pressed against the bonding layer 127L. In some cases, a thermal treatment such as an anneal can be implemented. Other bonding processes are also possible. The bonding layers 127L and 127U collectively form an isolation layer 127 that separates the upper multilayer stack 122U from the lower multilayer stack 122L. The upper multilayer stack 122U and the lower multilayer stack 122L collectively form a single multilayer stack 122 between the substrates 120 and 121.

[0038] In Figure 14 , a laser treatment process is implemented on the substrate 121 to modify the material of the substrate 121. The laser treatment process can be similar to the laser treatment process previously described with respect to Figures 2 to 3The laser processing procedure is described. For example, the laser source 30 can generate a laser beam 32 that penetrates the substrate 121, modifies the material of the substrate 121, and forms a modified region 121' of the substrate 121. The laser source 30 can be scanned across the substrate 121 to extend the modified region 121'. In some cases, layers of the multi-layer stack 122 underneath the substrate 121 (e.g., the semiconductor layer 126U) can have little or no modification. Figure 15 The structure is shown after the laser processing procedure has been implemented, and the entire substrate 121 is modified. In other words, the modified region 121' of the substrate 121 extends across the substrate 121.

[0039] In Figure 16 In some embodiments, a planarization procedure is implemented to remove the substrate 121. The planarization procedure can include, for example, a CMP procedure, a lapping procedure, etc. Removing the substrate 121 exposes a surface of the layers of the multi-layer stack 122. For example, in Figure 16 In some embodiments, removing the substrate 121 exposes a surface of the topmost semiconductor layer 126U. In some cases, implementing the laser processing procedure on the substrate 121 prior to the substrate 121 being removed can result in a flatter and more uniform planarization surface (e.g., the surface of the topmost semiconductor layer 126U).

[0040] Although Figures 12 to 16 The multi-layer stack 122 is shown as being formed on the substrate 120 using bonding and planarization techniques, the multi-layer stack 122 can be formed using other techniques. For example, in other embodiments, all of the individual layers of the multi-layer stack 122 can be grown or deposited on the substrate 120. In such embodiments, the individual layers of the multi-layer stack 122 can be formed using techniques similar to those used to form the multi-layer stack 122L / 122U. The following procedure steps can be implemented on similar structures formed using any suitable technique.

[0041] In Figure 17 In some embodiments, the multi-layer stack 122 and the substrate 120 are patterned to form semiconductor strips 128. The semiconductor strips 128 are formed to extend upward from the substrate 120. Each of the semiconductor strips 128 includes a semiconductor strip 120' (a patterned portion of the substrate 120, also referred to as a fin 120') and a portion of the multi-layer stack 122 (also referred to as a multi-layer stack 122). The individual layers of the multi-layer stack 122 are referred to hereinafter as nanostructures. In particular, the multi-layer stack 122 includes a pseudo-nanostructure 124L, a pseudo-nanostructure 124U, a lower semiconductor nanostructure 126L, and an upper semiconductor nanostructure 126U. The pseudo-nanostructure 124L and the pseudo-nanostructure 124U are subsequently referred to collectively as the pseudo-nanostructures 124. The lower semiconductor nanostructure 126L and the upper semiconductor nanostructure 126U are subsequently referred to collectively as the semiconductor nanostructures 126.

[0042] The lower semiconductor nanostructures 126L provide channel regions for lower nanostructure FETs of subsequently formed CFETs. The upper semiconductor nanostructures 126U provide channel regions for upper nanostructure FETs of subsequently formed CFETs. Semiconductor nanostructures 126 directly above or below (e.g., in contact with) the isolation layer 127 can be used for isolation and can or can not be used as channel regions for CFETs. The isolation layer 127 is subsequently replaced with isolation structures that define boundaries of the lower and upper nanostructure FETs.

[0043] The patterning process can be applied to the layers of first and second semiconductor materials, the dielectric material, and the substrate 120 to define the semiconductor strips 128, including the fins 120', the dummy nanostructures 124, the isolation layer 127, and the semiconductor nanostructures 126. The fins 120', the isolation layer 127, and the nanostructures 124 / 126 can be patterned by any suitable technique. For example, the patterning process can include one or more photolithography processes, including a double patterning or multiple patterning process. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, smaller pitch than is obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as etch masks for the patterning process to etch various underlying layers and the substrate 120. The etching can be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. The etching can be anisotropic.

[0044] In Figure 18 In accordance with some embodiments, a dielectric material 132 is deposited over the semiconductor strips 128. A shallow trench isolation (STI) region 133 is subsequently formed from the dielectric material 132. As shown in Figure 18 The dielectric material 132 is formed over the substrate 120 and between adjacent semiconductor strips 128. In some embodiments, the dielectric material 132 includes a dielectric liner and a dielectric fill material over the dielectric liner. Each of the dielectric liner and the dielectric fill material can include an oxide, such as silicon oxide, a nitride, such as silicon nitride, etc., or combinations thereof. The dielectric material 132 can be deposited using a suitable deposition process, such as ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or combinations thereof. In some embodiments, the dielectric material 132 includes silicon oxide formed by a FCVD process and a subsequent anneal process.

[0045] exist Figure 19 In this process, a laser processing technique is applied to the dielectric material 132 to modify the upper region of the dielectric material 132. The laser processing technique can be similar to that previously applied to... Figures 2 to 3 The laser processing process is described. For example, laser source 30 can generate a laser beam 32 that penetrates dielectric material 132, modifying an upper region of dielectric material 132 and forming a modified region 132' of dielectric material 132. The modified upper region of dielectric material 132 can extend over semiconductor strips 128. In some cases, the entire upper region of dielectric material 132 can be modified. In some embodiments, modifying the entire upper region of dielectric material 132 can allow improved flatness and reduce loading effects, for example, due to different densities or different spacings of semiconductor strips 128 in different regions of substrate 120. In other embodiments, the modified upper region may only include a portion of the upper region of dielectric material 132 covering or near a group of semiconductor strips 128. In some embodiments, the location, area, depth, or amount of modification of dielectric material 132 in different regions can be selected to compensate for loading effects, thus allowing improved flatness and uniformity. Laser source 30 can scan across dielectric material 132 to extend the modified region 132'. Figure 19 As shown, the laser processing technique can modify the portion of the dielectric material 132 located above the semiconductor strip 128. Therefore, the bottom of the modified region 132' can be approximately flush with the top surface of the semiconductor strip 128. In other embodiments, the bottom of the modified region 132' can be located above or below the top surface of the semiconductor strip 128. In some cases, the upper portion of the topmost layer of the semiconductor strip 128 can be modified using a laser processing technique.

[0046] Figure 20 The structure after laser processing has been performed is shown, and the entire upper portion of the dielectric material 132 above the semiconductor strip 128 has been modified. In other words, the modified region 132' of the dielectric material 132 extends above the semiconductor strip 128 and extends above the dielectric material 132 between the semiconductor strips 128.

[0047] exist Figure 21 In some embodiments, a planarization process is performed to remove the modified region 132' of the dielectric material 132. The planarization process may include, for example, a CMP process, a polishing process, etc. Removing the modified region 132' exposes the semiconductor strip 128. For example, in... Figure 20 In this embodiment, the modified region 132' is removed to expose the surface of the topmost semiconductor layer 126U. After the planarization process is performed, the top surfaces of the dielectric material 132 and the semiconductor strip 128 can be flush. In some cases, performing a laser processing process on the dielectric material 132 prior to planarization can produce a flatter and more uniform planarized surface.

[0048] In Figure 22 which the dielectric material 132 is recessed, with the remaining portions of the dielectric material 132 forming STI regions 133. The dielectric material 132 can be recessed using an etching process, which can include a wet etching process and / or a dry etching process. The dielectric material 132 can be recessed such that the upper portions of the semiconductor strips 128, including the multilayer stacks 122, protrude above the remaining STI regions 133. The top surface of the STI regions 133 can be higher, lower, or about the same height as the top surface of the fins 120’.

[0049] In Figure 23 which the dielectric material 132 is recessed, with the remaining portions of the dielectric material 132 forming STI regions 133. The dielectric material 132 can be recessed using an etching process, which can include a wet etching process and / or a dry etching process. The dielectric material 132 can be recessed such that the upper portions of the semiconductor strips 128, including the multilayer stacks 122, protrude above the remaining STI regions 133. The top surface of the STI regions 133 can be higher, lower, or about the same height as the top surface of the fins 120’.

[0050] In Figure 24 which the dielectric material 132 is recessed, with the remaining portions of the dielectric material 132 forming STI regions 133. The dielectric material 132 can be recessed using an etching process, which can include a wet etching process and / or a dry etching process. The dielectric material 132 can be recessed such that the upper portions of the semiconductor strips 128, including the multilayer stacks 122, protrude above the remaining STI regions 133. The top surface of the STI regions 133 can be higher, lower, or about the same height as the top surface of the fins 120’.

[0051] Subsequently, source / drain recesses 146 are formed in the semiconductor strips 128. The source / drain recesses 146 are formed by etching and can extend through the multi-layer stack 122 and into the fins 120'. The floor of the source / drain recesses 146 can be at a level above, below, or flush with the top surface of the STI regions 133. In the etching process, the gate spacers 144 and the dummy gate stacks 142 mask some portions of the semiconductor strips 128. The etching can include a single etching process or multiple etching processes. The etching of the source / drain recesses 146 can be stopped using a timed etching process when the source / drain recesses 146 reach a desired depth.

[0052] In Figure 25 , the interior spacers 154 and the dielectric isolation layers 156 are formed. Forming the interior spacers 154 can include an etching process that laterally etches the dummy nanostructures 124, recessing the sidewalls of the dummy nanostructures 124. The isolation layers 127 can also be removed using an etching process. The etching process can be isotropic and can be selective to the material being etched. In this way, the isolation layers 127 can be completely removed from between the lower semiconductor nanostructures 126L (collectively) and the upper semiconductor nanostructures 126U (collectively) without completely removing the dummy nanostructures 124. Because the dummy gate stacks 142 wrap the sidewalls of the semiconductor nanostructures 126 (see Figure 23 ), the dummy gate stacks 142 can support the upper semiconductor nanostructures 126U such that the upper semiconductor nanostructures 126U do not collapse when the isolation layers 127 are removed. Further, while the sidewalls of the dummy nanostructures 124 are shown as being straight after etching, the sidewalls can be recessed or convex.

[0053] The interior spacers 154 are formed on the recessed sidewalls of the dummy nanostructures 124 and the dielectric isolation layers 156 are formed between the upper semiconductor nanostructures 126U (collectively) and the lower semiconductor nanostructures 126L (collectively). As described in more detail subsequently, source / drain regions will subsequently be formed in the source / drain recesses 146 and the dummy nanostructures 124 will be replaced with corresponding gate structures. The interior spacers 154 function as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structures. Further, the interior spacers 154 can be used to prevent damage to the subsequently formed source / drain regions from subsequent etching processes, such as etching processes used to form the gate structures. On the other hand, the dielectric isolation layers 156 function to isolate the upper semiconductor nanostructures 126U (collectively) from the lower semiconductor nanostructures 126L (collectively). Further, the intermediate semiconductor nanostructures (the semiconductor nanostructures 126 in contact with the dielectric isolation layers 156) and the dielectric isolation layers 156 can define the boundaries of the lower nanostructure FETs and the upper nanostructure FETs.

[0054] The interior spacers 154 and the dielectric isolation layers 156 can be formed by conformally depositing an insulating material in the source / drain recesses 146, on the sidewalls of the dummy nanostructures 124, and between the upper semiconductor nanostructures 126U and the lower semiconductor nanostructures 126L, and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxycarbonitride, silicon oxycarbide, silicon oxynitride, etc. Other low dielectric constant (low-k) materials having a k value less than about 3.5 can be utilized. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material, when etched, has portions that are retained on the sidewalls of the dummy nanostructures 124 (thus forming the interior spacers 154), and has portions that are retained between the upper semiconductor nanostructures 126U and the lower semiconductor nanostructures 126L (thus forming the dielectric isolation layers 156).

[0055] Also as shown, lower epitaxial source / drain regions 162L and upper epitaxial source / drain regions 162U are formed. The lower epitaxial source / drain regions 162L are formed in the lower portions of the source / drain recesses 146. The lower epitaxial source / drain regions 162L are in contact with the lower semiconductor nanostructures 126L, and are not in contact with the upper semiconductor nanostructures 126U. The interior spacers 154 electrically insulate the lower epitaxial source / drain regions 162L from the dummy nanostructures 124L, which will be replaced with replacement gates in subsequent processes. Figure 25

[0056] The lower epitaxial source / drain regions 162L are epitaxially grown, and have a conductivity type appropriate for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain regions 162L are n-type source / drain regions, the corresponding material can include silicon or carbon-doped silicon, which is doped with n-type dopants, such as phosphorus, arsenic, etc. When the lower epitaxial source / drain regions 162L are p-type source / drain regions, the corresponding material can include silicon or silicon germanium, which is doped with p-type dopants, such as boron, indium, etc. The lower epitaxial source / drain regions 162L can be in-situ doped, and can or can not be implanted with corresponding p-type or n-type dopants. During epitaxy of the lower epitaxial source / drain regions 162L, exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructures 126U can be masked to prevent unwanted epitaxial growth on the upper semiconductor nanostructures 126U. After the lower epitaxial source / drain regions 162L are grown, the mask on the upper semiconductor nanostructures 126U can then be removed.

[0057] ​The upper surface of the lower epitaxial source / drain region 162L has facets that laterally extend outward beyond the sidewalls of the multilayer stack 122 as a result of the epitaxial process used to form the lower epitaxial source / drain region 162L. In some embodiments, adjacent lower epitaxial source / drain regions 162L remain separated after the epitaxial process is complete. In other embodiments, the facets cause adjacent lower epitaxial source / drain regions 162L of the same FET to merge.

[0058] A first contact etch stop layer (CESL) 166 and a first ILD 168 are formed over the lower epitaxial source / drain regions 162L. The first CESL 166 can be formed of a dielectric material that has a high etch selectivity with respect to etching of the first ILD 168, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 168 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 168 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0059] The formation process can include depositing a conformal CESL layer, depositing a material for the first ILD 168, and a subsequent planarization process and then an etch back process. In some embodiments, the first ILD 168 is etched first, leaving the first CESL 166 unetched. An anisotropic etch process is then implemented to remove portions of the first CESL 166 that are higher than the recessed first ILD 168. After the recessing, the sidewalls of the upper semiconductor nanostructures 126U are exposed.

[0060] An upper epitaxial source / drain region 162U is then formed in the upper portion of the source / drain recess 146. The upper epitaxial source / drain region 162U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 126U. The material of the upper epitaxial source / drain region 162U can be selected from the same set of candidate materials used to form the lower source / drain region 162L, depending on the desired conductivity type of the upper epitaxial source / drain region 162U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 162U can be opposite that of the lower epitaxial source / drain region 162L. For example, the upper epitaxial source / drain region 162U can be oppositely doped from the lower epitaxial source / drain region 162L. Alternatively, the conductivity type of the upper epitaxial source / drain region 162U and the lower epitaxial source / drain region 162L can be the same. The upper epitaxial source / drain region 162U can be in-situ doped with n-type or p-type dopants and / or can be implanted with n-type or p-type dopants. Adjacent upper source / drain regions 162U can remain separated after the epitaxial process, or can be merged.

[0061] After the epitaxial source / drain region 162U is formed, a second CESL 170 and a second ILD 172 are formed. The materials and formation methods can be similar to those of the first CESL 166 and the first ILD 168, respectively, and are not discussed in detail here. The formation process can include depositing a layer for the CESL 170 and the ILD 172, and performing a planarization process to remove excess portions of the corresponding layer. The planarization process can include a laser treatment process. After the planarization process, the top surfaces of the second ILD 172, the gate spacers 144, and the mask 186 (if present) or the dummy gate 184 are substantially coplanar (within process variation). Thus, the top surface of the mask 140 (if present) or the dummy gate 138 is exposed through the second ILD 172. In the illustrated embodiment, the mask 140 remains after the removal process. In other embodiments, the mask 140 is removed, such that the top surface of the dummy gate 138 is exposed through the second ILD 172.

[0062] Figure 26A replacement gate process is shown that replaces the dummy gate stack 142 and the dummy nanostructures 124 with the gate structure 190. The replacement gate process includes first removing the remaining portions of the dummy gate stack 142 and the dummy nanostructures 124. The dummy gate stack 142 is removed in one or more etching processes, defining recesses between the gate spacers 144, and exposing the upper portions of the semiconductor strips 128. The remaining portions of the dummy nanostructures 124 are then removed by etching, such that the recesses extend between the semiconductor nanostructures 126. In the etching process, the dummy nanostructures 124 are etched at a faster rate than the semiconductor nanostructures 126, the dielectric isolation layers 156, and the interior spacers 154. The etching can be isotropic. For example, when the dummy nanostructures 124 are formed of silicon germanium, and the semiconductor nanostructures 126 are formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0063] The gate dielectric 178 is then deposited in the recesses between the gate spacers 144 and on the exposed semiconductor nanostructures 126. The gate dielectric 178 is conformally formed on the exposed surfaces of the recesses (removed gate stack 142 and dummy nanostructures 124) including the semiconductor nanostructures 126 and the gate spacers 144. In some embodiments, the gate dielectric 178 wraps all (e.g., four) sides of the semiconductor nanostructures 126. Specifically, the gate dielectric 178 can be formed on the top surface of the fin 120'; on the top surface, sidewalls, and bottom surface of the semiconductor nanostructures 126; and on the sidewalls of the gate spacers 144. The gate dielectric 178 can include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multiple layers thereof, or the like. The gate dielectric 178 can include a high dielectric constant (high-k) material having a k value greater than about 7.0, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric 178 can include molecular beam deposition (MBD), ALD, PECVD, or the like, and a subsequent planarization process (e.g., CMP) to remove portions of the gate dielectric 178 that are above the second ILD 172. Although a single layer of gate dielectric 178 is shown, the gate dielectric 178 can include multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0064] A lower gate electrode 180L is formed on the gate dielectric 178 around the lower semiconductor nanostructure 126L. For example, the lower gate electrode 180L wraps around the lower semiconductor nanostructure 126L. The lower gate electrode 180L can be formed of a metal-containing material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, and the like. Although a single layer gate electrode is shown, the lower gate electrode 180L can include any number of work function adjusting layers, any number of barrier layers, any number of glue layers, and fill materials.

[0065] The lower gate electrode 180L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 180L can include one or more work function adjusting layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 180L includes an n-type work function adjusting layer, which can be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. In some embodiments, the lower gate electrode 180L includes a p-type work function adjusting layer, which can be formed of titanium nitride, tantalum nitride, combinations thereof, and the like. Additionally or alternatively, the lower gate electrode 180L can include a dipole inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0066] The lower gate electrode 180L can be formed by: conformally depositing one or more gate electrode layers; and recessing the gate electrode layers. Any acceptable etching process can be implemented, such as dry etching, wet etching, and the like or combinations thereof, to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 180L can expose the upper semiconductor nanostructure 126U.

[0067] In some embodiments, an isolation layer (not explicitly shown) can be optionally formed on the lower gate electrode 180L. The isolation layer serves as an isolation component between the lower gate electrode 180L and a subsequently formed upper gate electrode 180U. The isolation layer can be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, and the like) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 126U.

[0068] Then, an upper gate electrode 180U is formed on the isolation layer (if present) or the lower gate electrode 180L described above. The upper gate electrode 180U is disposed between the upper semiconductor nanostructures 126U. In some embodiments, the upper gate electrode 180U wraps the upper semiconductor nanostructures 126U. The upper gate electrode 180U can be formed from the same candidate materials and candidate processes used to form the lower gate electrode 180L. The upper gate electrode 180U is formed from materials suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 180U can include one or more work function adjusting layers (e.g., n-type work function adjusting layers and / or p-type work function adjusting layers) formed from materials suitable for the device type of the upper nanostructure FET. Although a single layer gate electrode 180U is shown, the upper gate electrode 180U can include any number of work function adjusting layers, any number of barrier layers, any number of glue layers, and fill materials.

[0069] In addition, a removal process is performed to level the top surface of the upper gate electrode 180U and the second ILD 172. The removal process used to form the gate dielectric 178 can be the same removal process used to form the upper gate electrode 180U. In some embodiments, a planarization process such as a CMP process, an etch-back process, a combination thereof, and the like can be utilized. The planarization process can include a laser treatment process. After the planarization process, the top surfaces of the upper gate electrode 180U, the gate dielectric 178, the second ILD 172, and the gate spacers 144 are substantially coplanar (within process variation). Each respective pair of the gate dielectric 178 and the gate electrode 180 (including the upper gate electrode 180U and / or the lower gate electrode 180L) can be collectively referred to as a “gate stack” 190 or a “gate structure” 190 (including an upper gate structure 190U and a lower gate structure 190L). Each gate structure 190 extends along three sides (e.g., a top surface, sidewalls, and a bottom surface) of the channel region of the semiconductor nanostructure 126 (see FIG. 2B). The lower gate structure 190L can also extend along the sidewalls and / or the top surface of the fin 120’. The gate structure 190 can extend between opposing inner spacers 154, and thus the gate structure 190 can have a width that is less than the width of the semiconductor nanostructure 126. In some embodiments, some gate structures 190 can have a height that is greater than the height of the inner spacer 154. In some cases, the gate structure 190 can have curved sidewalls. Figure 11 ) The lower gate structure 190L can also extend along the sidewalls and / or the top surface of the fin 120’. The gate structure 190 can extend between opposing inner spacers 154, and thus the gate structure 190 can have a width that is less than the width of the semiconductor nanostructure 126. In some embodiments, some gate structures 190 can have a height that is greater than the height of the inner spacer 154. In some cases, the gate structure 190 can have curved sidewalls.

[0070] Also as Figure 26A gate mask 192 is formed over the gate stack 142, as shown in FIG. 2. The formation process can include recessing the gate stack 190, filling the resulting recess with a dielectric material such as silicon nitride, silicon carbon nitride, silicon oxynitride, silicon carbon oxynitride, etc., and performing a planarization process to remove excess portions of the dielectric material over the second ILD 172. The planarization process can include a laser treatment process.

[0071] In Figure 27 In the embodiment of FIG. 2, a metal-semiconductor alloy region 194 and an upper source / drain contact 196U are formed through the second ILD 172 to electrically couple to the upper epitaxial source / drain region 162U. As an example of forming the upper source / drain contact 196U, an opening is formed through the second ILD 172 and the second CESL 170 using acceptable photolithography and etching techniques. A liner (not shown separately) and a conductive material such as a diffusion barrier, adhesion layer, etc. are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A removal process can be performed to remove excess material from the gate spacers 144 and the top surface of the second ILD 172. The remaining liner and conductive material form the upper source / drain contact 196U in the opening. In some embodiments, a planarization process such as CMP, an etch-back process, a combination thereof, etc. is utilized. The planarization process can include a laser treatment process. After the planarization process, the top surfaces of the gate spacers 144, the second ILD 172, and the upper source / drain contact 196U are substantially coplanar (within process variations).

[0072] Optionally, a metal-semiconductor alloy region 194 is formed at the interface between the source / drain region 162 and the upper source / drain contact 196U. The metal-semiconductor alloy region 194 can be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicide-germanide region formed of a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 194 can be formed prior to the material of the upper source / drain contact 196U by depositing a metal in the opening for the upper source / drain contact 196U and then performing a thermal anneal process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the source / drain region 162 to form a low resistance-metal semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by a deposition process such as ALD, CVD, PVD, etc. After the thermal anneal process, a cleaning process such as a wet clean can be performed to remove any residual metal from the opening for the upper source / drain contact 196U, such as from the surface of the metal-semiconductor alloy region 194. The material of the upper source / drain contact 196U can then be formed on the metal-semiconductor alloy region 194.

[0073] The ESL 204 and the third ILD 206 are then formed. In some embodiments, the ESL 204 can include a dielectric material having a high etch selectivity with respect to the etching of the third ILD 206, such as aluminum oxide, aluminum nitride, silicon nitride, silicon oxynitride, silicon oxycarbide, etc. The third ILD 206 can be formed using flowable CVD, ALD, etc., and the material can include PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method such as CVD, PECVD, etc.

[0074] Subsequently, upper gate contacts 208 and upper source / drain vias 210 are formed to contact the upper gate electrodes 180U and the upper source / drain contacts 196U, respectively. As an example of forming the upper gate contacts 208 and the upper source / drain vias 210, openings for the upper gate contacts 208 and the upper source / drain vias 210 are formed through the third ILD 206 and the ESL 204. The openings can be formed using acceptable photolithography and etching techniques. Liners (not shown separately), such as diffusion barriers, adhesion layers, and the like, and conductive materials are formed in the openings. The liners can include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The conductive materials can be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, and the like. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the third ILD 206. The planarization process can include a laser treatment process. The remaining liners and conductive materials form the upper gate contacts 208 and the upper source / drain vias 210 in the openings. The upper gate contacts 208 and the upper source / drain vias 210 can be formed in different processes or can be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the upper gate contacts 208 and the upper source / drain vias 210 can be formed in different cross-sections, which can avoid shorting of the contacts. In some cases, the resulting structure can be referred to as a device layer 212.

[0075] Still referring to Figure 27 A front side interconnect structure 214 is formed on the device layer 212. The front side interconnect structure 214 includes layers of dielectric layers 216 and conductive features 218 in the dielectric layers 216. The dielectric layers 216 can include low-k dielectric layers formed of low-k dielectric materials. The dielectric layers 216 can also include passivation layers formed of non-low-k and dense dielectric materials over the low-k dielectric materials, such as undoped silicate glass (USG), silicon oxide, silicon nitride, and the like or combinations thereof. The dielectric layers 216 can also include polymer layers. The conductive features 218 can include wires and vias formed using a damascene process. The conductive features 218 can include metal lines and metal vias that include diffusion barriers and copper-containing materials over the diffusion barriers. Aluminum pads can also be present over and electrically connected to the metal lines and vias. Additional processing can be implemented on the device layer 212, such as forming lower source / drain contacts to the lower source / drain regions 162L, forming a back side interconnect structure, or other processing.

[0076] Embodiments described herein can achieve advantages. By modifying material using a laser processing process as described herein, the modified material can be more easily removed using a planarization process. This can allow for faster planarization and reduced cost. This can also allow for improved uniformity or planarity of the resulting planarized surface. Further, implementing a laser processing process as described herein can reduce surface topography and can reduce the sensitivity of polishing to surface topography. The depth of the modified material can be controlled by controlling the focal point of the laser beam used in the laser processing process. The laser processing process can modify the layer throughout the entire thickness of the layer or can only modify an upper portion of the layer. The techniques described herein can reduce under-polishing, over-polishing, or bonding issues caused by uneven surfaces. Improving a planarization process using a laser processing process as described herein can improve the yield and uniformity of the overall device processing.

[0077] In embodiments, a method includes forming a first layer over a second layer; implementing a laser processing process on the first layer, wherein the laser processing process includes directing a laser beam into the first layer, wherein the laser beam modifies the first layer; and after implementing the laser processing process on the first layer, implementing a planarization process on the first layer to remove the first layer, wherein the planarization process exposes the second layer. In embodiments, a focal point of the laser beam is above a top surface of the second layer. In embodiments, the laser beam has a wavelength in a range of 300 nm to 1500 nm. In embodiments, the method includes forming a nanostructure stack over a substrate, wherein the nanostructure stack includes the second layer, wherein forming the first layer includes depositing the first layer over the nanostructure stack and on sidewalls of nanostructures of the nanostructure stack; and after implementing the planarization process, forming a gate structure between adjacent nanostructures of the nanostructure stack. In embodiments, the first layer is silicon. In embodiments, the first layer and the second layer are the same material. In embodiments, after implementing the laser processing process, the entire first layer is modified. In embodiments, the laser beam modifies the first layer by heating the first layer. In embodiments, the planarization process is a chemical mechanical polishing (CMP) process.

[0078] In an embodiment, a method includes depositing a first layer over a substrate, wherein the first layer is a first material; and removing an upper portion of the first layer, including: scanning a laser beam across a top surface of the first layer, wherein, after scanning the laser beam, the upper portion of the first layer has a different physical property than an underlying lower region of the first layer; and polishing the upper portion of the first layer to expose the lower region of the first layer. In an embodiment, a focus of the laser beam is at a first depth in the first layer, wherein the first depth is less than a first thickness of the first layer. In an embodiment, after scanning the laser beam, a polishing removal rate of the upper region is greater than a polishing removal rate of the lower region. In an embodiment, the first material is an oxide. In an embodiment, the laser beam is pulsed during scanning of the laser beam. In an embodiment, after scanning the laser beam, the upper portion of the first layer has a greater volume than the upper portion of the first layer before scanning the laser beam. In an embodiment, the method includes depositing a second layer over the substrate, wherein the first layer covers the second layer, wherein polishing the upper portion of the first layer also exposes the second layer.

[0079] In an embodiment, a method includes forming a first bonding layer over a first substrate; forming a second bonding layer over a second substrate; bonding the first bonding layer to the second bonding layer using a fusion bonding process; heating the first substrate using a first laser; and removing the first substrate using a first mechanical planarization process. In an embodiment, the first substrate is a silicon wafer. In an embodiment, the method includes forming a dielectric material over the second substrate; heating an upper portion of the dielectric material using a second laser; and removing the upper portion of the dielectric material using a second mechanical planarization process. In an embodiment, the method includes forming a multilayer stack between the first bonding layer and the first substrate, wherein removing the first substrate exposes the multilayer stack.

[0080] Some embodiments of the present application provide a method of forming a semiconductor device, including: forming a first layer over a second layer; performing a laser processing process on the first layer, wherein the laser processing process includes directing a laser beam into the first layer, wherein the laser beam modifies the first layer; and after performing the laser processing process on the first layer, performing a planarization process on the first layer to remove the first layer, wherein the planarization process exposes the second layer.

[0081] In some embodiments, a focus of the laser beam is located above a top surface of the second layer. In some embodiments, the laser beam has a wavelength in a range of 300 nm to 1500 nm. In some embodiments, the method further comprises: forming a nanostructure stack above the substrate, wherein the nanostructure stack comprises the second layer, wherein forming the first layer comprises depositing the first layer over the nanostructure stack and on sidewalls of the nanostructures of the nanostructure stack; and forming a gate structure between adjacent nanostructures of the nanostructure stack after implementing the planarization process. In some embodiments, the first layer is silicon. In some embodiments, the first layer and the second layer are the same material. In some embodiments, the entire first layer is modified after implementing the laser processing process. In some embodiments, the laser beam modifies the first layer by heating the first layer. In some embodiments, the planarization process is a chemical mechanical polishing (CMP) process.

[0082] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: depositing a first layer above a substrate, wherein the first layer is a first material; and removing an upper portion of the first layer, comprising: scanning a laser beam across a top surface of the first layer, wherein, after scanning the laser beam, the upper portion of the first layer has a different physical property than an underlying lower region of the first layer; and polishing the upper portion of the first layer to expose the lower region of the first layer.

[0083] In some embodiments, a focus of the laser beam is located at a first depth in the first layer, wherein the first depth is less than a first thickness of the first layer. In some embodiments, after scanning the laser beam, a polishing removal rate of the upper region is greater than a polishing removal rate of the lower region. In some embodiments, the first material is an oxide. In some embodiments, the laser beam is pulsed during scanning of the laser beam. In some embodiments, after scanning the laser beam, the upper portion of the first layer has a greater volume than the upper portion of the first layer prior to scanning the laser beam. In some embodiments, the method further comprises depositing a second layer above the substrate, wherein the first layer covers the second layer, wherein polishing the upper portion of the first layer also exposes the second layer.

[0084] Still other embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first bonding layer above a first substrate; forming a second bonding layer above a second substrate; bonding the first bonding layer to the second bonding layer using a fusion bonding process; heating the first substrate using a first laser; and removing the first substrate using a first mechanical planarization process.

[0085] In some embodiments, the first substrate is a silicon wafer. In some embodiments, the method further comprises: forming a dielectric material over the second substrate; heating an upper portion of the dielectric material using a second laser; and removing the upper portion of the dielectric material using a second mechanical planarization process. In some embodiments, the method further comprises forming a multilayer stack between the first bonding layer and the first substrate, wherein removing the first substrate exposes the multilayer stack.

[0086] The foregoing overview has outlined rather broadly the features of several embodiments in accordance with this disclosure so as to provide those skilled in the art with a general understanding of the aspects of the disclosure. The disclosure, however, can be practiced with a great variety of modifications, alterations, and permutations of the embodiments described herein. Accordingly, it should be understood that there is no intention to limit the disclosure to the precise conditions, configurations, or the like described herein.

Claims

1. A method of forming a semiconductor device, comprising: forming a first layer over a second layer; performing a laser processing procedure on the first layer, wherein the laser processing procedure comprises directing a laser beam into the first layer, wherein the laser beam modifies the first layer; and after performing the laser processing procedure on the first layer, performing a planarization procedure on the first layer to remove the first layer, wherein the planarization procedure exposes the second layer.

2. The method of claim 1, wherein, a focal point of the laser beam is above a top surface of the second layer.

3. The method of claim 1, wherein, the laser beam has a wavelength in a range of 300 nm to 1500 nm.

4. The method of claim 1, further comprising: forming a nanostructure stack over a substrate, wherein the nanostructure stack comprises the second layer, wherein forming the first layer comprises depositing the first layer over the nanostructure stack and on sidewalls of the nanostructures of the nanostructure stack; and after performing the planarization procedure, forming a gate structure between adjacent nanostructures of the nanostructure stack.

5. The method of claim 1, wherein, the first layer is silicon.

6. The method of claim 1, wherein, the first layer and the second layer are the same material.

7. The method of claim 1, wherein, after performing the laser processing procedure, the entire first layer is modified.

8. The method of claim 1, wherein, the laser beam modifies the first layer by heating the first layer.

9. A method of forming a semiconductor device, comprising: depositing a first layer over a substrate, wherein the first layer is a first material; and removing an upper portion of the first layer, comprising: scanning a laser beam across a top surface of the first layer, wherein, after scanning the laser beam, the upper portion of the first layer has a different physical property than an underlying lower region of the first layer; and polishing the upper portion of the first layer to expose the lower region of the first layer.

10. A method of forming a semiconductor device, comprising: forming a first bonding layer over a first substrate; forming a second bonding layer over a second substrate; bonding the first bonding layer to the second bonding layer using a fusion bonding procedure; heating the first substrate using a first laser; and removing the first substrate using a first mechanical planarization procedure. ​

Images