Method for monitoring charge generation condition in process
By forming a one-time programmable structure on the wafer and performing ultraviolet curing and leakage detection, the problem of unsatisfactory charge monitoring in the wet processing and photolithography-development washing process is solved, realizing effective monitoring of charge generation and improving device performance and production yield.
Patent Information
- Application Number
- CN202511345435.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-19
- Publication Date
- 2026-02-27
AI Technical Summary
In the existing technology, the charge monitoring effect in the wet processing and photolithography development and rinsing processes is not ideal, and the charge sensing sensitivity of the oxide layer control wafer is insufficient, which affects device performance and production yield.
A one-time programmable structure is formed on the wafer, residual charge is removed by ultraviolet curing, and leakage current is detected after the wafer is processed by the target process to determine the charge generation status.
Effective charge monitoring of wafer cleaning and post-lithography development rinsing processes has been achieved, ensuring device performance and production yield.
Smart Images
Figure CN121586447A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for monitoring charge generation in a process. BACKGROUND
[0002] In a semiconductor wafer manufacturing process, the wet treatment process and the post-etching rinsing process are key links for ensuring the cleanliness of the device. The core function of the two processes is to remove the photoresist, etching by-products and particle contaminants on the wafer surface through liquid rinsing, chemical treatment or physical brushing, so as to provide a clean process environment for subsequent device preparation or testing.
[0003] However, in the actual operation process of the above two processes, due to the influence of equipment characteristics and process principles, additional charges are easily generated and introduced, which poses a significant threat to device performance and production yield. At present, the charge monitoring method of some semiconductor manufacturing modules is usually referred to, and an oxide layer control sheet is used as a charge monitoring carrier. The principle is to indirectly judge the charge state of the process environment by detecting the charge accumulation on the surface of the oxide layer control sheet. However, when this scheme is directly applied to the charge monitoring of the wet treatment process and the post-etching rinsing process, the monitoring effect is not ideal due to the insufficient charge sensing sensitivity of the oxide layer control sheet. SUMMARY
[0004] The present application provides a method for monitoring the charge generation condition in a process, which can realize the charge monitoring of the wafer cleaning process or the post-etching rinsing process.
[0005] The present application provides a method for monitoring the charge generation condition in a process, which includes: providing a wafer, a one-time programmable structure for testing is formed on the wafer, and the one-time programmable structure is used to be turned on after capturing charges; pre-treating the wafer to remove residual charges on the wafer; processing the wafer through a target process; detecting the leakage of the wafer to determine the charge generation condition of the target process.
[0006] In some embodiments, the one-time programmable structure includes, from bottom to top, a substrate, an epitaxial layer, and a dielectric layer, a buried layer is formed at the junction of the substrate and the epitaxial layer, a first well region and a lightly doped well region are formed in the epitaxial layer, and a body region, a source region and a drain region are respectively formed on the surface layer of the lightly doped well region; a polysilicon gate is formed on the surface of the epitaxial layer, the polysilicon gate is located between the source region and the drain region, and a self-aligned silicide barrier layer is formed on the polysilicon gate; The medium layer covers the polysilicon gate and the surface of the epitaxial layer, and contact holes are formed in the medium layer and respectively connected to the body region, the source region and the drain region; The surface of the medium layer is formed with a top layer metal corresponding to the contact holes, and the top layer metal is respectively connected to the body region, the source region and the drain region through the corresponding contact holes.
[0007] In some embodiments, the step of pre-treating the wafer to remove residual charges on the wafer comprises: The wafer is subjected to ultraviolet light curing treatment.
[0008] In some embodiments, the duration of the ultraviolet light curing treatment is not less than 200s.
[0009] In some embodiments, the target process includes a wafer cleaning process or a post-etching rinsing process.
[0010] In some embodiments, after the step of detecting the leakage current of the wafer to determine the charge generation condition of the target process, the method further comprises: The wafer is subjected to ultraviolet light curing treatment to remove charges on the wafer; The wafer is recycled.
[0011] In some embodiments, the step of detecting the leakage current of the wafer to determine the charge generation condition of the target process comprises: A negative voltage is applied to the drain region of the one-time programmable structure; The current leakage between the source region and the drain region of the one-time programmable structure is measured; Based on the comparison result of the current leakage and the preset leakage current threshold, the charge generation condition of the target process is determined.
[0012] The technical scheme of the present application has at least the following advantages: 1. By forming a one-time programmable structure with a specific structure in the wafer, and processing the wafer with the target process to be monitored, and then detecting the leakage current of the wafer after the target process, when the leakage current between the source region and the drain region of the one-time programmable structure exceeds the standard, it means that the charge generation of the target process exceeds the standard, thereby effectively monitoring the charge generation of the target process. BRIEF DESCRIPTION OF DRAWINGS
[0013] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0014] Figure 1 This is a flowchart of a method for monitoring charge generation in a process according to an exemplary embodiment of this application; Figure 2 This is a schematic diagram illustrating a one-time programmable structure provided by an exemplary embodiment of this application.
[0015] Explanation of reference numerals in the attached figures: 1. Substrate; 11. Buried layer; 2. Epitaxial layer; 21. First well region; 22. Lightly doped well region; 23. Body region; 24. Source region; 25. Drain region; 26. Metal silicide; 3. Dielectric layer; 4. Polysilicon gate; 5. Self-aligned silicide barrier layer; 6. Sidewall oxide film; 7. Contact hole; 8. Top metal. Detailed Implementation
[0016] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0017] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0018] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0019] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0020] This application provides a method for monitoring charge generation in a process, referring to... Figure 1 The method includes the following steps: S1: Provide a wafer on which a one-time programmable structure for testing is formed, the one-time programmable structure being turned on after a charge is captured.
[0021] For example, a wafer is provided on which a one-time programmable structure (OTP) for testing is formed. When a charge remains on the wafer, the one-time programmable structure can capture the charge and turn on, thereby enabling monitoring of the generated charge.
[0022] Furthermore, refer to Figure 2 The one-time programmable structure comprises, from bottom to top, a substrate 1, an epitaxial layer 2, and a dielectric layer 3. A buried layer 11 is formed at the junction of the substrate 1 and the epitaxial layer 2, and a first well region 21 and a lightly doped well region 22 are formed in the epitaxial layer 2. A body region 23, a source region 24, and a drain region 25 are formed on the surface of the lightly doped well region 22. A polysilicon gate 4 is formed on the surface of the epitaxial layer 2, located between the source region 24 and the drain region 25. A self-aligned silicide barrier layer 5 is formed on the polysilicon gate 4, and sidewall oxide films 6 are formed on both sides of the polysilicon gate 4. The dielectric layer 3 covers the polysilicon gate 4, the self-aligned silicide barrier layer 5, and the surface of the epitaxial layer 2. Contact holes 7 are formed in the dielectric layer 3, respectively connecting to the body region 23, the source region 24, and the drain region 25. Metal silicide 26 is formed at the contact positions between the contact holes 7 and the source region 24 and the drain region 25, thereby reducing contact resistance. A top layer metal 8 is formed on the surface of the dielectric layer 3, corresponding to the contact holes 7. These top layer metals 8 are connected to the body region 23, the source region 24 and the drain region 25 through the corresponding contact holes 7.
[0023] S2: Pre-process the wafer to remove residual charges on the wafer.
[0024] For example, the wafer is pre-processed to remove residual charge and avoid affecting subsequent monitoring results.
[0025] Furthermore, pretreatment of the wafer can be achieved by performing ultraviolet curing.
[0026] Furthermore, the duration of the aforementioned UV curing treatment is set to be no less than 200 seconds. For example, it can be set to 500 seconds to ensure the quality of charge removal.
[0027] S3: Process the wafer using the target process.
[0028] For example, the target process refers to a process that requires charge monitoring. The wafer described above is placed in the corresponding cleaning machine and processed using the target process.
[0029] Furthermore, the target process may include a wafer cleaning process or a post-photolithography development rinsing process.
[0030] S4: Perform leakage current detection on the wafer to determine the charge generation status of the target process.
[0031] For example, after processing a wafer using a target process, if a certain amount of charge is generated in the target process, a one-time programmable structure will be used to turn on after capturing the charge. Taking the one-time programmable structure provided above as an example, the charge generated by the target process will be transferred to the source region 24 and the drain region 25 through the top layer metal 8 and the contact hole 7, and then captured by the polysilicon gate 4, causing the polysilicon gate 4 to become charged, and the one-time programmable structure to turn on. At this time, by performing leakage current detection on the one-time programmable structure in the wafer, the charge generation status of the target process can be determined.
[0032] Furthermore, step S4 may include the following: S41: Apply a negative voltage to the drain region of the one-time programmable structure.
[0033] For example, a negative voltage can be applied to the drain region of a one-time programmable structure using a WAT test instrument.
[0034] S42: Measure the current leakage current between the source and drain regions of a one-time programmable structure.
[0035] For example, the leakage current between the source and drain regions of a one-time programmable structure, i.e., the current leakage current, is measured using a WAT test instrument.
[0036] S43: Based on the comparison between the current leakage current and the preset leakage current threshold, determine the charge generation status of the target process.
[0037] For example, the current leakage current can be compared with a preset leakage current threshold. If the current leakage current is greater than the preset leakage current threshold, it means that too much charge has been generated in the target process, and the charge generation of the target process is poor.
[0038] Furthermore, following step S4 above, the following processing may also be included: S5: Perform UV curing on the wafer to remove the charge on the wafer.
[0039] For example, the wafer is subjected to ultraviolet curing to neutralize residual charges on the wafer, including one-time programmable structures. The duration of this ultraviolet curing step can be set to be no less than 200 seconds, for example, 500 seconds.
[0040] S6: Recycle wafers.
[0041] For example, wafers that have undergone UV curing can be recycled for subsequent reuse.
[0042] The method for monitoring charge generation in the process provided in this application embodiment forms a one-time programmable structure with a specific structure in the wafer, processes the wafer using the target process to be monitored, and then performs leakage current detection on the wafer processed by the target process. When the leakage current between the source region and the drain region of the one-time programmable structure exceeds the standard, it means that the charge generation of the target process exceeds the standard, thereby realizing effective monitoring of the charge generation of the target process.
[0043] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for monitoring charge generation in a process, characterized in that, include: A wafer is provided on which a one-time programmable structure for testing is formed, the one-time programmable structure being activated upon capture of charge; The wafer is pre-treated to remove residual charge on the wafer; The wafer is processed using the target process. Leakage current detection is performed on the wafer to determine the charge generation status of the target process.
2. The method for monitoring charge generation in the process according to claim 1, characterized in that, The one-time programmable structure includes, from bottom to top, a substrate, an epitaxial layer, and a dielectric layer. A buried layer is formed at the junction of the substrate and the epitaxial layer. A first well region and a lightly doped well region are formed in the epitaxial layer. A body region, a source region, and a drain region are formed on the surface of the lightly doped well region, respectively. A polysilicon gate is formed on the surface of the epitaxial layer, the polysilicon gate is located between the source region and the drain region, and a self-aligned silicide barrier layer is formed on the polysilicon gate. The dielectric layer covers the polysilicon gate and the surface of the epitaxial layer, and contact holes are formed in the dielectric layer that are respectively connected to the body region, the source region and the drain region; The surface of the dielectric layer is formed with a top layer metal corresponding to the contact holes, and the top layer metal is connected to the body region, source region and drain region through the corresponding contact holes.
3. The method for monitoring charge generation in the process according to claim 1, characterized in that, The step of pre-processing the wafer to remove residual charge on the wafer includes: The wafer is subjected to ultraviolet light curing treatment.
4. The method for monitoring charge generation in the process according to claim 3, characterized in that, The duration of the ultraviolet curing treatment shall not be less than 200 seconds.
5. The method for monitoring charge generation in the process according to claim 1, characterized in that, The target process includes a wafer cleaning process or a post-photolithography development and rinsing process.
6. The method for monitoring charge generation in the process according to claim 1, characterized in that, After performing leakage current detection on the wafer to determine the charge generation status of the target process, the method further includes: The wafer is subjected to ultraviolet curing to remove the charge on the wafer; The wafers were recycled.
7. The method for monitoring charge generation in the process according to claim 2, characterized in that, The step of performing leakage current detection on the wafer to determine the charge generation status of the target process includes: A negative voltage is applied to the drain region of the one-time programmable structure; Measure the current leakage current between the source and drain regions of the one-time programmable structure; Based on the comparison between the current leakage current and the preset leakage current threshold, the charge generation status of the target process is determined.