Semiconductor test structure and manufacturing method thereof

Abstract

The invention provides a semiconductor test structure and a manufacturing method thereof. The semiconductor test structure comprises a substrate, a dielectric layer arranged on the substrate, gate metal formed in a dielectric layer groove to simulate a gate structure, and a gate via hole arranged on the simulated gate structure and electrically connected with the simulated gate structure. The manufacturing method comprises the following steps: forming a dielectric layer comprising a groove on a substrate, and filling gate metal into the groove to form an analog gate structure; and forming a gate via hole electrically connected with the analog gate structure on the analog gate structure. According to the invention, a test structure capable of truly simulating the contact interface of the gate via hole and the metal gate is constructed in a short-flow process, and the via hole is formed by using an existing mask plate, so that the rapid, low-cost and high-precision verification of the gate via hole resistance in the process that the contact hole passes through the active region gate (COAG) is realized; the problem that an existing testing method is long in period or invalid in feedback is solved, and the process research and development process is accelerated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor test structure and a manufacturing method thereof. BACKGROUND

[0002] In the field of semiconductor manufacturing, with the continuous miniaturization of device critical dimensions, semiconductor technology has developed to very advanced technology nodes. In these advanced nodes, in order to further improve the integration and density of devices, the industry generally adopts the Contact Over Active Gate (COAG) technology. As shown in the layout diagram of a semiconductor device, compared with the traditional layout in which the Gate Contact is arranged outside the gate extending out of the active area, the COAG technology directly arranges the Gate Contact on the gate part above the active area. This optimization in layout can effectively reduce the device area by about 10% to 20%. Figure 1

[0003] However, the application of the COAG technology, while bringing the advantage of device area reduction, also introduces new technical challenges. In order to achieve the above-mentioned compact layout, the size of the gate via is designed to be very small. As shown in the transmission electron microscope (TEM) cross-sectional view of the gate via, the critical dimension of the gate via is extremely small, especially at the interface between the bottom and the underlying metal gate contact, which may further shrink, forming a process bottleneck. This extremely small contact area directly leads to a significant increase in the contact resistance between the gate via and the underlying metal gate. Excessive contact resistance can seriously affect the electrical performance of the device and even reduce the yield of the product. Therefore, it is crucial to develop a process solution that can effectively reduce the contact resistance. Figure 2

[0004] Currently, the evaluation and verification of the contact resistance reduction scheme usually relies on two test processes. The first is the Full-Loop test, which can truly manufacture the device and accurately measure the contact resistance, but its production cycle is very long, which cannot meet the needs of rapid verification and iteration of process solutions in the research and development stage, greatly slowing down the project development progress. The second is the Short-Loop test, which although has a short test cycle, but its traditional test structure has inherent limitations. As shown in the schematic diagram of the traditional short-loop test structure, the test via (V0) is usually directly made on the silicon substrate. This structure does not form the contact interface between the gate via and the metal gate, but forms the contact interface between the via and the silicon substrate. Therefore, this structure cannot truly simulate the key electrical connection interface in the device, cannot effectively feedback the level of contact resistance, and cannot be used to evaluate the effect of process improvement aimed at reducing resistance. Figure 3

[0005] ​​​Therefore, the industry urgently needs a new test method which can quickly and accurately feedback the contact resistance of the gate via in a short time, so as to shorten the learning cycle of process development, thereby accelerating the research and development process of advanced technology nodes. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a semiconductor test structure and a manufacturing method thereof, which can quickly and accurately feedback the contact resistance of the gate via in a short time, so as to overcome the long full-flow test cycle and the defect of the traditional short-flow test which cannot accurately simulate the key interface in the prior art.

[0007] In order to solve the above technical problems, the present application provides a semiconductor test structure, comprising:

[0008] a substrate;

[0009] a dielectric layer disposed on the substrate, wherein a first metal layer groove is formed in the dielectric layer;

[0010] a gate metal filled in the first metal layer groove to form a simulation gate structure; and

[0011] a gate via disposed on the simulation gate structure, wherein the gate via is electrically connected with the simulation gate structure.

[0012] Preferably, the gate metal is a work function metal.

[0013] Preferably, the semiconductor test structure is a Kelvin structure.

[0014] Preferably, the semiconductor test structure further comprises a metal interconnection structure formed on the gate via, wherein the metal interconnection structure is used to lead out an electrical signal to test the contact resistance between the gate via and the simulation gate structure.

[0015] Preferably, the metal interconnection structure comprises a first metal interconnection layer or a second metal interconnection layer, and the first metal interconnection layer or the second metal interconnection layer is electrically connected with the gate via through a jump layer connection.

[0016] In order to solve the above technical problems, the present application further provides a manufacturing method of a semiconductor test structure, comprising the following steps:

[0017] Step 1: forming a dielectric layer comprising a first metal layer groove on a substrate, and filling a gate metal into the first metal layer groove to form a simulation gate structure;

[0018] Step 2: forming a gate via on the simulation gate structure, wherein the gate via is electrically connected with the simulation gate structure.

[0019] Preferably, the manufacturing method is based on a short cycle process flow.

[0020] Preferably, in step one, the gate metal is a work function metal.

[0021] Preferably, in step two, the step of forming the gate via includes: using a mask for forming another via different from the gate via in function or level to form the gate via.

[0022] Preferably, the structure formed by step one and step two is a Kelvin structure.

[0023] Preferably, the manufacturing method further includes: forming a subsequent metal interconnection structure on the gate via to test the contact resistance between the gate via and the analog gate structure through the metal interconnection structure.

[0024] Preferably, in the step of forming the metal interconnection structure, the metal interconnection structure is formed by a jump layer connection, so that the test can be performed on the first metal interconnection layer or the second metal interconnection layer.

[0025] As described above, the semiconductor test structure and the manufacturing method thereof have the following beneficial effects:

[0026] The present application builds a special test structure that can truly simulate the contact interface between the gate via and the metal gate in a short process, and realizes the rapid, low-cost and high-precision monitoring of the resistance of the gate via in the COAG process by using existing process modules and masks. This not only solves the problem of long feedback cycle or invalid test results of traditional test methods, but also effectively shortens the research and development cycle of advanced process nodes. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A schematic diagram showing a semiconductor device layout according to some embodiments of the present application;

[0028] Figure 2 A transmission electron microscope cross-sectional schematic diagram showing a gate via according to the prior art;

[0029] Figure 3 A cross-sectional schematic diagram showing a short process test structure according to the prior art;

[0030] Figure 4 A flowchart showing a semiconductor test structure manufacturing method according to some embodiments of the present application;

[0031] Figure 5 A cross-sectional schematic diagram showing a semiconductor test structure according to some embodiments of the present application. DETAILED DESCRIPTION

[0032] These and other advantages and benefits of the application will become apparent from consideration of the following detailed description and drawings. Other advantages and benefits will also become readily apparent to those skilled in the art on reading the following specification. The application can be implemented or applied in other different embodiments and its details can be modified in various obvious respects without departing from the spirit of the application. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0033] With reference to Figure 5 The present application provides a semiconductor test structure, comprising: a substrate 101; a first dielectric layer 102 disposed on the substrate 101, the first dielectric layer 102 having a trench formed therein; a gate metal filled in the trench to form a dummy gate structure 103; and a gate via 106 disposed on the dummy gate structure 103, wherein the gate via 106 is electrically connected to the dummy gate structure 103. An isolation layer 104 and a second dielectric layer 105 are also shown above the dummy gate structure 103, wherein the gate via 106 passes through the second dielectric layer 105 and the isolation layer 104 to contact the dummy gate structure 103.

[0034] In some embodiments, the substrate 101 provides mechanical support for semiconductor fabrication, and can be a semiconductor substrate such as, but not limited to, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon-germanium substrate, or a group III-V compound semiconductor substrate (e.g., gallium arsenide GaAs). The first dielectric layer 102 and the second dielectric layer 105 are used to provide electrical isolation between conductive features, and can be formed using interlayer dielectric materials commonly used in the art, such as silicon oxide-based materials (e.g., silicon dioxide, fluorine-doped silicate glass FSG), silicon oxynitride, or low-k or ultralow-k materials such as carbon-doped silicon oxide (SiOC), organic silicate glass (OSG), or porous dielectric materials, in order to reduce resistance-capacitance (RC) delay. The isolation layer 104 is typically used as an etch stop layer, and can be a material such as silicon nitride (SiN), silicon carbon nitride (SiCN), or silicon boron nitride (SiBN), the choice of which depends on its etch selectivity with respect to the overlying second dielectric layer 105.

[0035] In some embodiments, the gate metal constituting the dummy gate structure 103 is a work function metal. More specifically, the dummy gate structure 103 can be a composite structure including one or more layers of work function metal and one layer of bulk fill metal. The work function metal can be a P-type work function metal or an N-type work function metal, depending on the type of transistor. For example, the P-type work function metal can include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), etc., and their alloys or multi-layer combinations, while the N-type work function metal can include titanium aluminum alloy (TiAl), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum nitride (TiAlN), lanthanum (La) doped metal, etc., and their multi-layer combinations. The bulk fill metal can be a material with relatively low resistivity, such as tungsten (W), cobalt (Co), molybdenum (Mo), or copper (Cu). By filling the same work function metal and bulk metal as in the real device, the contact interface between the gate via and the metal gate in the device can be accurately simulated, and its electrical and physical properties can be accurately simulated, so that more valuable resistance data can be obtained, and the effectiveness of the test results can be ensured.

[0036] In some embodiments, the semiconductor test structure is a Kelvin structure. Specifically, the test structure of the present application can be grafted on the layout basis of the existing bottommost metal-via (M0V0) Kelvin (Kelvin) direct connection test key (TSK). By using the Kelvin structure for testing, the contact resistance to be measured can be accurately separated by the four-probe measurement method, and the interference of the lead resistance and the probe contact resistance on the measurement results can be effectively eliminated, so that the real contact resistance value between the gate via 106 and the dummy gate structure 103 can be accurately obtained.

[0037] In some embodiments, further comprising: a metal interconnection structure formed on the gate via 106, the metal interconnection structure being used to lead out electrical signals to test the contact resistance between the gate via 106 and the dummy gate structure 103. The metal interconnection structure is part of the back-end-of-line (BEOL) process, and can include one or more metal wiring layers (e.g., M1, M2,..., Mn) and interlayer vias (e.g., V1, V2,..., Vn-1) connecting these metal wiring layers. Each metal wiring layer is embedded in its corresponding interlayer dielectric layer. For example, a simple metal interconnection structure can include: a zeroth-level metal interconnection layer (M0) in direct contact with the gate via 106, a first-level via (V1) connecting the M0 and a first metal interconnection layer (M1), and the first metal interconnection layer (M1). A more complex structure can continue to extend to higher-level metal layers and vias. These metal layers will eventually be connected to test pads on the surface of the chip for contact testing by external probes.

[0038] The metal interconnect structure is usually formed by a single damascene or dual damascene process. Taking the dual damascene process as an example, the method for forming the M1 layer and V1 layer interconnect structure includes: first, depositing an interlayer dielectric material containing the M1 layer and V1 layer on the planarized surface of the gate via 106; then, forming a trench pattern of M1 and a via opening pattern of V1 in the dielectric material by two consecutive or self-aligned photolithography and etching steps; then, depositing a barrier layer and / or a seed layer by conformal deposition, the barrier layer is used to prevent the diffusion of metal (especially copper) into the dielectric material, and the optional material includes tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), ruthenium (Ru) or cobalt (Co), etc., and the seed layer provides nucleation sites for subsequent metal filling; then, filling the main conductive metal by electrochemical deposition (ECD), chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form M1 and V1 at the same time. The main conductive metal can be copper (Cu), which is the current mainstream interconnect material, or a future alternative material such as cobalt (Co), ruthenium (Ru) or an alloy material. Finally, the surface excess metal and barrier layer material are removed by chemical mechanical polishing (CMP) process, thereby completing the manufacture of a layer of metal interconnect structure. This process can be repeated to build a more complex interconnect network layer by layer.

[0039] In some embodiments, the metal interconnect structure includes a first metal interconnect layer (M1) or a second metal interconnect layer (M2) which is electrically connected to the gate via 106 through a jump layer connection. This means that the test signal does not need to be led out at the level immediately adjacent to the gate via, but through a reasonable jump layer connection design, the Kelvin structure signal originally tested at the bottom layer is led out to the metal wire (M1 or M2) at a higher level and then connected to the test pad. This jump layer connection design has high flexibility and can be easily integrated into the existing short flow test layout without the need for large-scale modification of the bottom layer layout, and can also avoid the complex wiring area at the bottom layer, simplifying the overall design of the test chip.

[0040] The present application also provides a method for manufacturing a semiconductor test structure, and the main process flow can refer to Figure 4 , which includes the following steps:

[0041] Step one, forming a dielectric layer containing a first metal layer trench on a substrate, and filling a gate metal into the first metal layer trench to form a simulated gate structure;

[0042] Specifically, referring to Figure 5The structure is formed by first forming a first dielectric layer 102 on a substrate 101. The first dielectric layer 102 can be formed by plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), or spin-on coating, etc. Next, a hard mask layer is deposited, photoresist is coated, and exposed and developed by deep ultraviolet (DUV) or extreme ultraviolet (EUV) lithography technology, and then the photoresist pattern is transferred to the hard mask layer by dry etching processes such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etching. The hard mask layer is used as a mask to form a trench in the first dielectric layer 102. Then, the trench is filled with gate metal, which usually includes forming one or more thin work function metal layers by atomic layer deposition (ALD) or physical vapor deposition (PVD), and then forming a main filling metal by chemical vapor deposition (CVD) or PVD. Subsequently, a chemical mechanical polishing (CMP) process is performed to remove excess metal and planarize the surface using a specific polishing liquid, thereby forming a simulated gate structure 103 embedded in the first dielectric layer 102. This step modifies the existing middle-of-line M0V0 short process: after the trench for forming the zeroth-level metal interconnection layer (M0A) is etched, instead of filling a conventional interconnection metal (such as copper or cobalt), a work function metal (WF) for forming a metal gate (MG) is filled, thereby forming an "M0A gate" structure. The purpose of this structure is to provide a contact interface that is exactly the same as the metal gate in the real device, thereby solving the fundamental problem that the traditional short process cannot simulate this interface.

[0043] In some embodiments, in step one, the gate metal is a work function metal. Selecting the same work function metal as in the full process ensures that the material interface in the test structure remains consistent with the material interface in the real device in terms of physical and chemical properties, which is a prerequisite and guarantee for accurate evaluation of contact resistance.

[0044] Step two, forming a gate via on the simulated gate structure and electrically connected to the simulated gate structure.

[0045] In particular, with reference to Figure 5The structure is formed as follows. After the dummy gate structure 103 is formed, the isolation layer 104 and the second dielectric layer 105 are deposited in sequence. Then, a similar lithography and dry etching process is used to etch the second dielectric layer 105. When the etching reaches the isolation layer 104, the etching gas formula is changed to remove the isolation layer 104 with a high selectivity ratio. Finally, a via opening is formed, which extends downward to expose the surface of the dummy gate structure 103. Before the via opening is filled with a conductive material, a pre-cleaning step, such as an in-situ argon (Ar) sputter cleaning, is usually performed to remove the oxide or residue at the bottom of the opening, ensuring good electrical contact. Finally, the via opening is filled with a conductive material, which is usually also a composite structure, including a thin liner / barrier layer (e.g., Ti / TiN or Ta / TaN) deposited by ALD or PVD, and a bulk metal (e.g., W, Cu, Co, or Ru) filled by CVD or electrochemical deposition (mainly for Cu), and is planarized again by a CMP process, finally forming the gate via 106.

[0046] In some embodiments, the step of forming the gate via in step two includes using a mask used to form another via different from the gate via in function or level to form the gate via. Specifically, the present method uses a mask used to form a via of diffusion contact (VD) in the existing process flow to define the pattern of the gate via. In this way, a "VD" via is formed in the COAG process directly on the "M0A gate" formed in step one. This borrowed "VD" via plays the role of a gate via (VG) here, thereby forming a direct connection test structure for quickly feeding back the contact resistance of the gate via. The method of borrowing a mask has the outstanding advantage of not needing to make and introduce a new lithography mask for this specific test structure. This not only saves the high cost of the lithography mask, but also simplifies the process flow, which is an effective way to achieve quick and low-cost verification.

[0047] The test structure manufactured by the above steps can effectively simulate the contact interface between the gate via and the metal gate in a real device.

[0048] In some embodiments, the manufacturing method is based on a short-cycle process flow. Compared with a full flow that needs to go through dozens or even hundreds of steps, the short-cycle process flow only includes a small number of key steps related to the middle-of-line (MOL). This shortens the manufacturing period of the entire test structure from months to weeks or even shorter, thereby enabling quick feedback of the effect of the process improvement scheme on reducing the contact resistance and accelerating the iteration and development schedule of the research and development project.

[0049] In some embodiments, the structure formed by step one and step two is a Kelvin structure. This ensures the accuracy of the subsequent resistance measurement.

[0050] In some embodiments, the manufacturing method further comprises: forming a subsequent metal interconnection structure on the gate via, to test the contact resistance between the gate via and the analog gate structure through the metal interconnection structure.

[0051] In some embodiments, in the step of forming the metal interconnection structure, the metal interconnection structure is formed by a way of jump layer connection, so that the test can be performed on the first metal interconnection layer (M1) or the second metal interconnection layer (M2). This method makes the design of test points can be flexibly arranged on higher and sparser metal layers, simplifies the layout design of test chip and the execution difficulty of subsequent probe test, and improves the test efficiency.

[0052] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be randomly changed in shape, number and proportion, and the component layout pattern may be more complex.

[0053] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A semiconductor test structure, characterized by, The semiconductor test structure comprises: a substrate; a dielectric layer disposed on the substrate, the dielectric layer having a first metal layer trench formed therein; a gate metal filled in the first metal layer trench to form an analog gate structure; and a gate via disposed on the analog gate structure, wherein the gate via is electrically connected with the analog gate structure. The gate metal is a work function metal.

2. The semiconductor test structure of claim 1, wherein: The semiconductor test structure is a Kelvin structure.

3. The semiconductor test structure of claim 1, wherein: The semiconductor test structure further comprises:

4. The semiconductor test structure of claim 1, wherein: a metal interconnect structure formed on the gate via, the metal interconnect structure being used to lead out an electrical signal to test a contact resistance between the gate via and the analog gate structure. The metal interconnect structure comprises a first metal interconnect layer or a second metal interconnect layer, which is electrically connected with the gate via by a jump layer connection.

5. The semiconductor test structure of claim 4, wherein: The semiconductor test structure comprises:

6. A method of manufacturing a semiconductor test structure, characterized by, a substrate; a dielectric layer disposed on the substrate, the dielectric layer having a first metal layer trench formed therein; a gate metal filled in the first metal layer trench to form an analog gate structure; and 7. The method of claim 6, wherein: a gate via disposed on the analog gate structure, wherein the gate via is electrically connected with the analog gate structure.

8. The method of claim 6, wherein: The gate metal is a work function metal.

9. The method of claim 6, wherein: The semiconductor test structure is a Kelvin structure.

10. The method of claim 6, wherein: The semiconductor test structure further comprises:

11. The method of fabricating a semiconductor test structure of claim 6, wherein: a metal interconnect structure formed on the gate via, the metal interconnect structure being used to lead out an electrical signal to test a contact resistance between the gate via and the analog gate structure.

12. The method of claim 11, wherein: The metal interconnect structure comprises a first metal interconnect layer or a second metal interconnect layer, which is electrically connected with the gate via by a jump layer connection. The semiconductor test structure comprises: a substrate; a dielectric layer disposed on the substrate, the dielectric layer having a first metal layer trench formed therein; a gate metal filled in the first metal layer trench to form an analog gate structure; and a gate via disposed on the analog gate structure, wherein the gate via is electrically connected with the analog gate structure. The gate metal is a work function metal. The semiconductor test structure is a Kelvin structure. The semiconductor test structure further comprises: a metal interconnect structure formed on the gate via, the metal interconnect structure being used to lead out an electrical signal to test a contact resistance between the gate via and the analog gate structure. The metal interconnect structure comprises a first metal interconnect layer or a second metal interconnect layer, which is electrically connected with the gate via by a jump layer connection.

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