Method for monitoring epitaxial doping concentration of FDSOI source / drain region
By forming a mask layer on the insulator and etching away the insulator layer, the problem of the influence of the insulator in SIMS testing is solved, and accurate monitoring of the epitaxial doping concentration of the source/drain regions of FDSOI is achieved.
Patent Information
- Application Number
- CN202511695332.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-02-27
AI Technical Summary
In existing SIMS pads, the presence of a silicon-on-insulator layer affects SIMS test results, making it impossible to accurately monitor the epitaxial doping concentration of the FDSOI source/drain regions.
The influence of the insulator is removed by forming a mask layer on the insulator, etching away the insulator layer, forming the source/drain epitaxial layer, and performing SIMS testing.
Accurate monitoring of the epitaxial doping concentration in the source/drain regions of FDSOI was achieved, and accurate test data was obtained.
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Figure CN121586453A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, in particular to a method for monitoring epitaxial doping concentration of FDSOI source / drain region. BACKGROUND
[0002] In the preparation of fully depleted silicon-on-insulator (FDSOI) devices, SiP / SiGeB layers are epitaxially grown as source / drain regions of NMOS / PMOS. The SiP layer needs to monitor the doping concentration of P, and the SiGeB layer needs to monitor the doping concentration of B and Ge. The above detection is realized by designing a SIMS pad and slicing for SIMS concentration test.
[0003] SIMS (secondary ion mass spectroscopy) is currently the mainstream precision analysis instrument for testing and analyzing trace impurity elements in high-purity semiconductors and other materials. It focuses on a high-energy primary ion beam to bombard the sample surface, and a cascade collision occurs with the sample. The molecules on the sample surface absorb energy and sputter a large number of particle fragments. Only a small part of the particle fragments will be ionized to form secondary ions or ion groups. By loading a certain voltage on the sample surface to form a uniform electric field, the ionized secondary ions or ion groups are extracted into the secondary light path, and finally collected and analyzed by the mass analyzer to obtain the spectrum of the sample surface information.
[0004] For the existing SIMS pad of fully depleted silicon-on-insulator (FDSOI) devices, the SiP / SiGeB layer is formed in the silicon layer on the insulator. Since the insulator is not conductive, the surface charge generated during the SIMS test cannot be promptly discharged, thereby affecting the generation and collection of secondary ions during the test and affecting the SIMS test results. SUMMARY
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for monitoring the epitaxial doping concentration of the source / drain region of FDSOI, which solves the problem that the insulator under the epitaxial layer of the source / drain region in the existing SIMS pad affects the SIMS test results.
[0006] To achieve the above object and other related objects, the present application provides a method for monitoring the epitaxial doping concentration of the source / drain region of FDSOI, comprising:
[0007] Step one, providing a silicon-on-insulator substrate, and forming a mask layer with a SIMS pad pattern on the silicon-on-insulator substrate;
[0008] Step two, using the mask layer as a mask, removing the exposed insulator layer in the silicon-on-insulator substrate by etching;
[0009] Step three, after removing the mask layer, forming source / drain region epitaxial layer, completing the preparation of SIMS pad;
[0010] Step four, SIMS testing is performed on the SIMS pad.
[0011] Preferably, in step one, the mask layer with the SIMS pad pattern is formed by photolithography and etching process.
[0012] Preferably, the size of the SIMS pad pattern is greater than 8 microns*8 microns.
[0013] Preferably, in step two, the etching is dry etching.
[0014] Preferably, in step three, the mask layer is removed by etching or ashing process.
[0015] Preferably, in step three, the source / drain region epitaxial layer is formed by selective epitaxial growth process.
[0016] Preferably, for NMOS, the source / drain region epitaxial layer is SiP layer; for PMOS, the source / drain region epitaxial layer is SiGeB layer.
[0017] As described above, the method for monitoring FDSOI source / drain region epitaxial doping concentration provided by the present application has the following beneficial effects: before forming the source / drain region epitaxial layer, the insulator in the SIMS pad is removed, thereby obtaining accurate FDSOI source / drain region epitaxial doping concentration. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the description of the embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.
[0019] Figure 1 The flowchart of the method for monitoring FDSOI source / drain region epitaxial doping concentration provided by the embodiments of the present application is shown. DETAILED DESCRIPTION
[0020] The embodiments of the present application will be described below through specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied through other different embodiments, and various modifications or changes can be made to the details in the present specification based on different views and applications without departing from the spirit of the present application.
[0021] The technical solutions in the present application will be described clearly and completely in combination with the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present application.
[0022] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0023] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, or it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0024] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict.
[0025] Please refer to Figure 1 , which shows the flowchart of the method for monitoring the epitaxial doping concentration of the FDSOI source / drain region provided by the embodiments of the present application.
[0026] As Figure 1 shown, the method for monitoring the epitaxial doping concentration of the FDSOI source / drain region comprises the following steps:
[0027] Step one, providing a silicon-on-insulator substrate, forming a mask layer with a SIMS pad pattern on the silicon-on-insulator substrate;
[0028] Step two, taking the mask layer as a mask, removing the insulator layer in the exposed silicon-on-insulator substrate by etching;
[0029] Step three, after removing the mask layer, forming a source / drain region epitaxial layer, and completing the preparation of the SIMS pad;
[0030] Step four, SIMS test is performed on the SIMS pad.
[0031] In step one, a mask layer with a SIMS pad pattern is formed by a photolithography and etching process, the size of the SIMS pad pattern is greater than 8 microns*8 microns.
[0032] In step two, the etching is dry etching.
[0033] In step three, the mask layer is removed by an etching or ashing process, and a source / drain region epitaxial layer is formed by a selective epitaxial growth process, for NMOS, the source / drain region epitaxial layer is a SiP layer, and for PMOS, the source / drain region epitaxial layer is a SiGeB layer.
[0034] In step four, a standard sample and the SIMS pad are put into a SIMS device for testing, standard test data of the standard sample and initial test data of the SIMS pad are obtained, and based on the standard test data and the initial test data, SIMS test data of the SIMS pad is generated. Since there is no insulator under the source / drain region epitaxial layer in the SIMS pad, accurate FDSOI source / drain region epitaxial doping concentration can be obtained through the SIMS test data of the SIMS pad.
[0035] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, rather than the number, shape and size of the components when actually implemented. The actual implementation of each component can be arbitrarily changed in terms of type, number and proportion, and the layout type of the components can also be more complex.
[0036] In summary, the method for monitoring FDSOI source / drain region epitaxial doping concentration provided by the present application removes the insulator in the SIMS pad before forming the source / drain region epitaxial layer, so as to obtain accurate FDSOI source / drain region epitaxial doping concentration. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.
[0037] The above embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.
Claims
1. A method of monitoring the epi-doping concentration of FDSOI source / drain regions, characterized by, The method comprises: Step one, providing a silicon-on-insulator substrate, and forming a mask layer with a SIMS pad pattern on the silicon-on-insulator substrate; Step two, removing the exposed insulator layer in the silicon-on-insulator substrate by etching with the mask layer as a mask; Step three, after removing the mask layer, forming a source / drain region epitaxial layer, and completing the preparation of the SIMS pad; Step four, performing SIMS testing on the SIMS pad.
2. The method of claim 1, wherein, In the step one, the mask layer with the SIMS pad pattern is formed by a photolithography and etching process.
3. The method according to claim 1 or 2, characterized in that, The size of the SIMS pad pattern is greater than 8 microns*8 microns.
4. The method of claim 1, wherein, In the step two, the etching is dry etching.
5. The method of claim 1, wherein, In the step three, the mask layer is removed by an etching or ashing process.
6. The method of claim 1, wherein, In the step three, the source / drain region epitaxial layer is formed by a selective epitaxial growth process.
7. The method of claim 6, wherein, For NMOS, the source / drain region epitaxial layer is a SiP layer; for PMOS, the source / drain region epitaxial layer is a SiGeB layer.