Chip packaging structure

Abstract

The chip packaging structure comprises a substrate, a first wiring layer, a chip, a heat conduction piece and a packaging layer, the heat conduction piece comprises a first part located on the side, away from the substrate, of a body part and a second part arranged around the side face of the body part, and the first part is in heat conduction connection with the second part; the packaging layer is arranged around the side face of the second part of the heat conduction piece, and the heat conduction coefficient of the heat conduction piece is larger than that of the chip; the first part is used for being connected with an external radiator, the second part is used for transmitting heat of the function part to the first part, the heat transmission efficiency is improved through the heat conduction piece with the higher heat conduction coefficient, and therefore the heat dissipation capacity of the chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of microelectronic packaging process, in particular to a chip packaging structure. BACKGROUND

[0002] Most chips are connected with the substrate by means of face mounting or flip-chip bonding. The flip-chip bonding makes the back of the chip face up, but the heat conduction efficiency between the back of the chip and the front of the chip is low. When heat is generated on the front of the chip, the heat needs to cross the path on the thickness of the chip to reach the back of the chip. Since the heat conduction performance of the material of the chip is poor, the heat dissipation capacity of the chip is not ideal.

[0003] Therefore, the existing chip packaging structure has the technical problem of poor heat dissipation capacity of the chip. SUMMARY

[0004] The embodiments of the present application provide a chip packaging structure, which can alleviate the technical problem of poor heat dissipation capacity of the chip of the existing chip packaging structure.

[0005] The embodiments of the present application provide a chip packaging structure, which comprises: a substrate; a first wiring layer arranged on one side surface of the substrate; a chip arranged on one side of the first wiring layer away from the substrate, and electrically connected with the first wiring layer; a heat conduction member comprising a first part located on one side of the chip away from the substrate, and a second part arranged around the side surface of the chip, the first part being in thermal conduction connection with the second part, and the heat conduction coefficient of the heat conduction member being greater than the heat conduction coefficient of the chip; a packaging layer arranged around the side surface of the second part of the heat conduction member, and the one side surface of the first part away from the substrate being exposed from the packaging layer.

[0006] Optionally, the first part and the second part are an integral structure.

[0007] Optionally, the upper end surface of the packaging layer is flush with the one side surface of the first part away from the substrate.

[0008] Optionally, the surface of the chip away from the substrate is provided with a groove, and the heat conduction member is arranged in a shape following the groove.

[0009] Optionally, the longitudinal cross-sectional shape of the groove is any one of a triangle, a rectangle, a trapezoid, and a semicircle.

[0010] Optionally, the surface of the chip away from the substrate is provided with a plurality of grooves, and the plurality of grooves are arranged in parallel.

[0011] Optionally, the chip and the substrate are filled with an underfill adhesive, and a preparation material of the underfill adhesive comprises a heat-conductive material.

[0012] Optionally, the second part of the heat-conductive member is in contact with the substrate and is arranged around the side surface of the chip and the underfill adhesive, and the second part is in contact with the side surface of the underfill adhesive.

[0013] Optionally, the chip packaging structure further comprises a second wiring layer arranged on a side surface of the substrate away from the chip, and a connecting hole is formed in the substrate, and the first wiring layer and the second wiring layer are electrically connected through the connecting hole.

[0014] Optionally, the chip packaging structure comprises a plurality of chips, and the plurality of chips are arranged at the same side of the substrate.

[0015] Optionally, a preparation material of the substrate comprises a glass material.

[0016] Embodiments of the present application provide a preparation method of a chip packaging structure, comprising: providing a substrate, and forming a first wiring layer on a side of the substrate; flip-chip mounting a chip on a side of the substrate provided with the first wiring layer, so that the chip is electrically connected with the first wiring layer, and filling a gap between the chip and the substrate with an adhesive material to form an underfill adhesive; forming a heat-conductive member on a side surface and a side of the chip away from the substrate, and a heat-conductivity coefficient of the heat-conductive member is greater than a heat-conductivity coefficient of the chip; forming an encapsulation material layer to encapsulate the chip, and removing the encapsulation material on a side of the chip away from the substrate by grinding, and retaining the encapsulation material on the side of the heat-conductive member, so as to prepare an encapsulation layer arranged around the side of the heat-conductive member.

[0017] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects: The chip packaging structure is provided with a heat-conductive member, the heat-conductive member comprises a first part and a second part in heat-conductive connection, the first part is used for connecting with an external external heat sink, and the second part is used for transmitting heat of a functional part to the first part, and the heat-conductive member with a higher heat-conductivity coefficient enhances the heat transmission efficiency, thereby enhancing the heat dissipation capacity of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0019] Figure 1 is a first cross-sectional schematic view of a chip packaging structure provided by the present application; Figure 2 is a top view schematic view of a chip packaging structure provided by the present application; Figure 3 is Figure 2 is a cross-sectional schematic view of a chip packaging structure provided by the present application at A-A cross section; Figure 4 is a second cross-sectional schematic view of a chip packaging structure provided by the present application; Figure 5 is a first state flow chart of a preparation method of a chip packaging structure provided by the present application; Figure 6 is a second state flow chart of a preparation method of a chip packaging structure provided by the present application; Figure 7 is a third state flow chart of a preparation method of a chip packaging structure provided by the present application; Figure 8 is a fourth state flow chart of a preparation method of a chip packaging structure provided by the present application.

[0020] Explanation of reference signs: 1, substrate; 2, first wiring layer; 21, contact terminal; 3, chip; 31, body part; 32, functional part; 4, heat conduction member; 41, first part; 42, second part; 5, underfill adhesive; 6, packaging layer; 7, second wiring layer; 8, first dielectric layer; 9, second dielectric layer; 10, solder ball; 11, chip packaging structure; 12, groove. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower of the device in the actual use or working state, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device.

[0022] Figure 1 A cross-sectional schematic view of a chip packaging structure 11 provided by the present application is shown in the figure. The two sides of the substrate 1 are respectively provided with a first metal wiring layer 2 and a second wiring layer 7. The second wiring layer 7 is provided with a plurality of solder balls 10 away from one side of the substrate 1. The solder balls 10 are used for soldering connection between the second wiring layer 7 and a PCB board. Figures 5 to 8 A flowchart of a preparation method of the chip packaging structure 11 is shown in the figure. The four stages in the flowchart are used to show the semi-finished state of the chip packaging structure 11 at different process stages.

[0023] Please refer to Figure 1 The chip packaging structure 11 provided by the present application includes a substrate 1, a first wiring layer 2, a chip 3, a heat-conducting member 4, and a packaging layer 6. The first wiring layer 2 is arranged on one side surface of the substrate 1. The chip 3 is arranged on one side of the first wiring layer 2 away from the substrate 1. The heat-conducting member 4 includes a first part 41 located on one side of a body part 31 away from the substrate 1, and a second part 42 arranged around the side surface of the body part 31. The first part 41 is in heat-conducting connection with the second part 42. The packaging layer 6 is arranged around the side surface of the second part 42 of the heat-conducting member 4. One side surface of the first part 41 away from the substrate 1 is exposed from the packaging layer 6. The heat-conducting coefficient of the heat-conducting member 4 is greater than the heat-conducting coefficient of the chip 3.

[0024] The one side surface of the first part 41 away from the substrate 1 is exposed from the packaging layer 6, so as to facilitate heat-conducting connection between the first part 41 and an external heat sink.

[0025] The first wiring layer 2 includes a plurality of contact terminals 21 arranged in insulation with each other. The chip 3 includes a body part 31 and a functional part 32 located on one side of the body part 31 facing the substrate 1. The functional part 32 of one chip 3 is electrically connected with one contact terminal 21.

[0026] The chip 3 in the chip packaging structure 11 is flip-chip soldered, the front surface of the chip 3 is in contact with the substrate, and the front surface of the chip 3 is a side surface on which the functional part 32 is arranged, so that part of the heat generated by the functional part 32 can be directly conducted out of the substrate 1, thereby enhancing the heat dissipation capacity of the chip 3 in the chip packaging structure 11.

[0027] The first wiring layer 2 includes at least one first metal wiring layer, and when the first wiring layer 2 includes two or more first metal wiring layers, a first insulating layer is arranged between adjacent first metal wiring layers.

[0028] It can be understood that the first part 41 of the heat conduction member 4 is exposed and connected to an external heat sink, thereby better conducting the heat transmitted from the functional part 32 out of the chip 3, and the second part 42 of the heat conduction member 4 is arranged around the side surface of the chip 3. Since the thermal conductivity coefficient of the heat conduction member 4 is greater than that of the body part 31, the heat of the functional part 32 can be transmitted to the first part 41 along the body part 31 and the second part, thereby enhancing the transmission efficiency of the heat from the functional part 32 to the first part 41.

[0029] In this embodiment, the heat conduction member 4 is divided into the first part 41 connected to the external heat sink and the second part 42 for transmitting the heat of the functional part 32 to the first part 41. By taking advantage of the higher thermal conductivity coefficient of the heat conduction member 4, the heat conduction efficiency of the heat of the functional part 32 to the first part 41 can be enhanced, thereby better conducting the heat of the chip 3 out of the chip 3 and enhancing the heat dissipation capacity of the chip 3.

[0030] In one embodiment, the first part 41 and the second part 42 are in an integrated structure.

[0031] The heat conduction member 4 can be prepared by casting or forging, so that the first part 41 and the second part 42 of the heat conduction member 4 are in an integrated structure.

[0032] The casting refers to injecting molten material into a mold to obtain the heat conduction member 4 including the first part 41 and the second part 42 after cooling, and the forging refers to forming a metal in a mold by forging to obtain the heat conduction member 4 including the first part 41 and the second part 42.

[0033] The material of the heat conduction member 4 includes at least one of copper, aluminum, silver and alloys thereof, a composite layer structure composed of the above-mentioned materials, a metal matrix composite material, and a high-thermal-conductivity non-metallic material.

[0034] When the heat conduction member 4 is a metal material, the first part 41 and the second part 42 of the heat conduction member 4 in an integrated structure can also be obtained by electroplating or physical vapor deposition process.

[0035] It can be understood that when the thermal conductivity of the metal material still cannot meet the demand, a metal matrix composite material can be used, which refers to adding a high-thermal-conductivity filler to the metal material to obtain better thermal conductivity and improve the comprehensive performance of the heat conduction piece 4. For example, an aluminum-silicon carbide composite material can be used for the heat-conducting glue. The aluminum-silicon carbide composite material has a similar thermal expansion coefficient to the silicon material of the body part 31 of the chip 3, which can reduce the thermal stress between the chip 3 and the heat conduction piece 4, thereby improving the comprehensive performance of the heat conduction piece 4.

[0036] In an embodiment, the first part 41 and the second part 42 are a split combination structure.

[0037] In this form, the first part 41 and the second part 42 of the heat conduction piece 4 are manufactured separately and connected together in some way, including but not limited to welding or mechanical locking.

[0038] Among them, the welding method: the prefabricated first part 41 and the second part 42 are welded together by solder to form an integral heat conduction piece 4.

[0039] Among them, the mechanical locking method: the connecting position of the first part 41 and the second part 42 is designed with a clamping groove or a locking structure, and the first part 41 and the second part 42 are physically buckled together at the connecting position to form a split combination structure.

[0040] Among them, the connecting position of the first part 41 and the second part 42 can be filled with heat-conducting glue to reduce thermal resistance.

[0041] In this embodiment, the first part 41 and the second part 42 are manufactured separately, and individual components in the first part 41 and the second part 42 can be repaired or replaced.

[0042] In an embodiment, heat-conducting glue is filled at the contact interface between the first part 41 and the external heat sink.

[0043] Among them, the preparation material of the heat-conducting glue can be a heat-conducting material, which is filled in the micro gap between the first part 41 and the external heat sink to establish good thermal contact between the first part 41 and the external heat sink.

[0044] Among them, the first part 41 and the external heat sink can be connected by welding, and the heat-conducting glue is the solder filled in the micro gap between the first part 41 and the external heat sink in the molten state during welding.

[0045] It can be understood that, since the first part 41 and the external heat sink are in thermal contact through direct contact, the micro gaps at the contact interface will affect the thermal conductivity. By filling the thermal conductive glue in the micro gaps, the micro gaps that affect the thermal conductivity are removed, and the newly added thermal conductive glue has high thermal conductivity, thereby enhancing the heat dissipation capacity of the chip packaging structure 11.

[0046] In an embodiment, the first part 41 covers the top surface of the chip 3 away from the base 1 (i.e. the back surface), and the second part 42 covers the side wall of the chip 3.

[0047] It can be understood that, by making the heat dissipation member completely cover the top surface and the side wall of the chip 3, on the one hand, the heat dissipation member can increase the heat conduction surface area, facilitating the increase of the contact area with the external heat sink, and on the other hand, the contact area between the heat dissipation member and the chip 3 is larger, increasing the heat exchange efficiency between the functional part 32 of the chip 3 and the heat dissipation member.

[0048] In an embodiment, the external heat sink includes a passive heat sink and an active heat sink.

[0049] The passive heat sink includes any one of a fin heat sink, a uniform temperature plate, and a metal shell. The fin heat sink includes a plurality of fin structures, which can expand the heat dissipation surface area by increasing the fins. The uniform temperature plate is a two-dimensional flat heat pipe, which can quickly and uniformly spread heat to the entire heat dissipation surface. The metal shell can be a shell of a terminal device, which is in direct contact with the heat dissipation member for heat dissipation. The passive heat sink refers to relying entirely on natural convection and radiation heat dissipation without additional power.

[0050] The active heat sink includes any one of a fin heat sink with a fan, a liquid cooling heat sink (which removes heat through flowing liquid), and a semiconductor refrigeration sheet (which is driven by electricity to achieve active refrigeration, and can make the temperature of the chip 3 lower than the ambient temperature).

[0051] It can be understood that the heat dissipation effect of the active heat sink is better than that of the passive heat sink, but the cost is higher. For example, by installing a fan on the fin heat sink, the blowing of the fan greatly enhances the heat dissipation effect.

[0052] In an embodiment, the upper end surface of the packaging layer 6 is flush with the side surface of the first part 41 away from the base 1.

[0053] The packaging layer 6 protects the chip packaging structure 11 from physical damage, vibration and impact, and can also block moisture, dust and ion contaminants in the environment, thereby improving the reliability and life of the chip packaging structure 11.

[0054] It can be understood that the upper end surface of the encapsulation layer 6 flush with the side surface of the first part 41 away from the substrate 1 is conducive to exposing the side surface of the first part 41 away from the substrate 1, facilitating the heat conduction connection with the external heat sink.

[0055] In an embodiment, the surface of the chip 3 away from the substrate 1 is provided with a groove 12, and the heat conduction member 4 is contoured along the groove 12.

[0056] Among them, the heat conduction member 4 is contoured along the inner wall of the groove 12, that is, the heat conduction member 4 is continuously arranged along the inner wall of the groove 12, so as to form the same shape as the inner wall of the groove 12, for example, the heat conduction member 4 can be formed on the inner wall of the groove 12 by electroplating, when the groove 12 is a continuous sawtooth structure, the heat conduction member 4 formed by electroplating is also a continuous sawtooth structure, that is, the heat conduction member 4 is contoured along the groove 12.

[0057] Among them, the inner wall of the groove 12 becomes an effective heat dissipation surface, and the heat conduction member 4 is contoured along the groove 12, which means that the contact area between the heat conduction member 4 and the body part 31 at the groove 12 is increased, thereby increasing the heat dissipation area of the heat conduction member 4 and the chip 3.

[0058] Among them, the heat conduction member 4 can be contoured along the profile of the inner wall of the groove 12 by deposition or electroplating process, so as to cover the back of the chip 3 and the inner wall of the groove 12.

[0059] It can be understood that after the heat conduction material is filled and solidified in the groove 12 to form the heat conduction member 4, the bonding force between the heat conduction member 4 and the body part 31 of the chip 3 is greatly enhanced, avoiding the delamination of the interface between the heat conduction member 4 and the body part 31 under thermal stress or mechanical stress.

[0060] It can be understood that by arranging at least one groove 12 on the side of the body part 31 away from the substrate 1, the first part 41 can be closer to the heat source (i.e. the functional part 32), and the heat can be conducted laterally to the side wall of the nearest groove 12, and then dissipated through the heat conduction member 4, thereby shortening the heat conduction path and improving the heat dissipation efficiency.

[0061] In an embodiment, the longitudinal cross-sectional shape of the groove 12 is any one of a triangle, a rectangle, a trapezoid, and a semicircle.

[0062] Among them, the longitudinal cross-sectional shape of the groove 12 is a triangle, that is, the groove 12 is a V-shaped groove, which can be formed by anisotropic wet etching, or by laser scribing or special tool grinding; when the heat conduction member 4 is subsequently deposited or electroplated, the metal material is more likely to grow uniformly on the inner wall of the slope of the V-shaped groove, achieving good contoured setting, and avoiding the formation of cavities in the heat conduction member 4, which can cause poor heat conduction efficiency.

[0063] In an embodiment, referring to Figure 2 and Figure 3 The chip 3 is provided with a plurality of grooves 12 away from the surface of the substrate 1, and the plurality of grooves 12 are arranged in parallel.

[0064] Among them, the plurality of grooves 12 arranged in parallel can be arranged in a zigzag shape in series.

[0065] Among them, the zigzag shape in series refers to that the surface of the body part 31 of the chip 3 away from the substrate 1 is no longer a plane, but a textured surface composed of a series of peaks (tooth tips between adjacent grooves 12) and valleys (groove bottoms).

[0066] Among them, the zigzag shape in series has a regular periodicity, that is, the size and shape of each groove 12 are the same.

[0067] Among them, the plurality of grooves 12 arranged in a zigzag shape in series can be prepared by etching process or precision mechanical grinding process.

[0068] It can be understood that compared with a plurality of isolated and spaced grooves 12, the grooves 12 arranged in a zigzag shape in series eliminate all “flat zones” on the surface of the body part 31 away from the substrate 1, and maximize the heat dissipation area.

[0069] In some examples, the plurality of grooves 12 can intersect each other in a grid shape to achieve uniform heat dissipation effect.

[0070] In an embodiment, the chip 3 and the substrate 1 are filled with an underfill adhesive 5, and the preparation material of the underfill adhesive includes a heat-conducting material.

[0071] Among them, in the structure of the flip chip 3, the chip 3 is connected with the substrate 1 through a small solder joint, thereby forming a relatively fragile point support. By filling the underfill adhesive 5 between the chip 3 and the substrate 1, the point support at the solder joint becomes a surface support of the underfill adhesive 5, which significantly enhances the overall mechanical strength of the chip packaging structure 11 and prevents the solder joint between the chip 3 and the substrate 1 from being damaged due to physical external force.

[0072] Among them, the thermal conductivity coefficient of the underfill adhesive 5 can be greater than the thermal conductivity coefficient of the body part 31 of the chip 3, thereby enhancing the heat dissipation effect of the chip 3 toward the substrate 1. The underfill adhesive 5 and the heat-conducting member 4 respectively improve the heat dissipation effect of the chip 3 on both sides in the thickness direction.

[0073] Among them, the preparation material of the underfill adhesive 5 can be an epoxy resin-based composite material.

[0074] The composition is as follows: resin matrix (which can be epoxy resin), inorganic filler (which can be fused silica), curing agent and accelerator, functional additives.

[0075] The resin matrix is used to provide fluidity before curing of the underfill adhesive 5 and to form a solid three-dimensional network structure after curing, providing certain mechanical strength, adhesion and chemical stability. The inorganic filler is an amorphous silica ball formed by rapid cooling after high-temperature melting, used to adjust the thermal expansion coefficient of the underfill adhesive 5 and enhance the thermal conductivity of the underfill adhesive 5, so that the thermal expansion coefficients of the underfill adhesive 5 and the substrate 1 tend to be the same, thereby reducing the thermal stress between the underfill adhesive 5 and the substrate 1. The curing agent and accelerator react with the resin matrix to crosslink and cure it from liquid to solid, thereby curing to form the underfill adhesive 5. The functional additives can include coupling agents and stress absorbers. The coupling agents (such as silane coupling agents) can enhance the interfacial bonding force between the underfill adhesive 5 and the substrate 1 or the chip 3, preventing delamination between the underfill adhesive 5 and the chip 3 or the substrate 1. The stress absorbers (such as rubber particles) are used to further reduce the modulus of the underfill adhesive 5, thereby increasing the ability of the underfill adhesive 5 to absorb stress.

[0076] The underfill adhesive 5 fills the front surface of the chip 3 (the side with the functional part 32) and protects the functional part 32 and the solder joints on the front surface of the chip 3. The encapsulation layer 6 wraps and fixes from the outside and protects the back surface of the chip 3. The two work together to make the chip packaging structure 11 have excellent reliability, ensuring that the chip packaging structure 11 can still operate normally in harsh environments.

[0077] It can be understood that the filling of the underfill adhesive 5 not only replaces the air between the chip 3 and the substrate 1, but also provides an effective heat dissipation path for the heat transfer from the functional part 32 of the chip 3 to the substrate 1 below, enhancing the heat dissipation effect of the chip packaging structure 11. At the same time, the underfill adhesive 5 can also absorb thermal stress, reducing the stress at the solder joints between the chip 3 and the substrate 1.

[0078] It can be understood that the underfill adhesive 5 will wrap the functional part 32 and the solder joints of the chip 3, thereby protecting the functional part 32 and the solder joints, isolating the solder joints and the precise circuit interface from the external environment, thereby preventing the functional part 32 and the solder joints from being damaged or corroded.

[0079] In one embodiment, the second portion 42 of the heat-conducting member 4 is in contact with the substrate 1 and is arranged around the side surface of the chip 3 and the underfill adhesive 5, and the second portion 42 is in contact with the side surface of the underfill adhesive 5.

[0080] Compared with the traditional structure, the heat of the functional part 32 of the chip 3 is transmitted upward to the top surface of the chip 3 through the body part 31 of the chip 3 and downward through the substrate 1, and the side surface of the chip 3 does not have good heat dissipation or heat conduction capacity and is not used as a heat transmission path. The heat conduction member 4 of the present application covers the side surface of the chip 3, so that the heat can be transmitted upward from the second part 42 of the heat conduction member 4 on the side surface to the first part 41, thereby increasing the heat transmission path and enhancing the heat dissipation effect.

[0081] The second part 42 is in contact with the side surface of the underfill adhesive 5, and heat exchange is generated between the underfill adhesive 5 and the heat conduction member 4 through direct contact, so that the two upward and downward heat conduction paths of the chip 3 are connected to each other. The heat transmitted downward from the chip 3 can be transmitted upward to the first part 41 through the second part 42 after reaching the underfill adhesive 5 and then be dissipated. Similarly, the heat transmitted upward from the chip 3 can also be transmitted downward to the underfill adhesive 5 through the second part 42 after reaching the second part 42 and then be transmitted to the substrate 1 to dissipate the heat, thereby further enhancing the heat dissipation effect.

[0082] The second part 42 is in contact with the substrate 1, which can form a strong physical or chemical bond, thereby enhancing the bonding strength between the heat conduction member 4, the chip 3, and the underfill adhesive 5 and avoiding separation of the film layers between the heat conduction member 4, the chip 3, and the underfill adhesive 5.

[0083] The bottom surface of the second part 42 can also be in direct contact with the substrate 1 in a surface contact manner, so that the heat can be directly transmitted to the substrate 1 through the second part 42 and then be dissipated.

[0084] The underfill adhesive 5 is located between the chip 3 and the substrate 1 and needs to have a certain heat conductivity to enable the heat to be transmitted downward. In addition, the underfill adhesive 5 can also be used to fill the gap between the chip 3 and the substrate 1. Since the gap will affect the heat conductivity, the heat conductivity of the underfill adhesive 5 needs to be better than that of the gap (air).

[0085] It can be understood that the preparation material of the underfill adhesive 5 includes a heat conduction material. The heat conduction contact between the second part 42 and the side surface of the underfill adhesive 5 can establish a heat transmission path with fast heat conduction. The heat is transmitted to the underfill adhesive 5 through the functional part 32. The underfill adhesive 5 is in contact with the substrate 1 on one side to dissipate heat directly and is transmitted to the first part 41 through the second part 42 on the other side, thereby dissipating heat from the chip 3 more quickly. In the above path, the underfill adhesive 5 and the second part 42 of the heat conduction member 4 are both materials with high heat conductivity (compared with the body part 31 of the chip 3). Since the body part 31 with low heat conductivity is not involved in the path, the transmission efficiency of the heat of the chip 3 through the path is higher.

[0086] It should be noted that since the substrate 1 also has good heat dissipation capacity, the substrate 1 can be regarded as a heat sink, and heat can be dissipated in all directions at the substrate 1. The second part 42 is connected to the side of the underfill adhesive 5, so that part of the heat of the first part 41 is released through the thermal conduction connection with the substrate 1, and the other part is released through the external heat sink, thereby reducing the heat dissipation pressure of the external heat sink and enhancing the overall heat dissipation capacity of the chip packaging structure 11.

[0087] In addition, the second part 42 of the heat conduction member 4 covers the side of the underfill adhesive 5. The material of the second part 42 of the heat conduction member 4 is usually metal and relatively hard, and the underfill adhesive 5 is a resin material. The second part 42 of the heat conduction member 4 can also play a role in protecting the underfill adhesive 5 layer, thereby prolonging the service life of the underfill adhesive 5 layer, preventing the underfill adhesive 5 layer from cracking due to external mechanical stress or material aging, and further ensuring its core function of protecting the solder joints, thereby improving the lifetime reliability of the entire packaging product.

[0088] In an embodiment, the functional part 32 of the chip 3 is welded to the contact terminal 21.

[0089] The functional part 32 refers to a part of the chip 3 where a transistor circuit is provided.

[0090] The functional part 32 refers to a part of the chip 3 where a transistor circuit is provided.

[0091] In an embodiment, the chip packaging structure 11 further comprises a second wiring layer 7, which is arranged on the side surface of the substrate 1 away from the chip 3. The substrate 1 has a connecting hole formed therein, and the first wiring layer 2 and the second wiring layer 7 are electrically connected through the connecting hole.

[0092] The second wiring layer 7 comprises at least one second metal wiring layer. When the second wiring layer 7 comprises two or more second metal wiring layers, a second insulating layer is arranged between adjacent second metal wiring layers.

[0093] The first dielectric layer 8 can be arranged on the side of the substrate 1 facing the chip 3, and the second dielectric layer 9 can be arranged on the side of the second wiring layer 7 away from the substrate 1.

[0094] The second wiring layer 7 is arranged on the side of the substrate 1 away from the chip 3, and the second wiring layer 7 is used to connect with a PCB. The width and spacing of the traces of the second wiring layer 7 can be larger than those of the first wiring layer 2.

[0095] In the chip 3 needs to be connected with the power layer and the ground layer, the second wiring layer 7 can be used to arrange the power layer and the ground layer, and then connected with the corresponding first wiring layer 2 through the connecting hole, and the signal is transmitted to the corresponding chip 3.

[0096] It can be understood that the metal wiring layer has a large area of the power layer and the ground layer, and the power layer and the ground layer are excellent heat conductors. Heat can be conducted from the chip 3 to the power layer and the ground layer of the second wiring layer 7, and finally conducted out or released to the environment through the PCB board.

[0097] It can be understood that the first wiring layer 2 is located on the side of the substrate 1 close to the chip 3, and the first wiring layer 2 is used for fine connection with the chip 3, so the wiring pitch of the first wiring layer 2 is small to adapt to the fine pitch between different solder points on the chip 3, while the second wiring layer 7 matches the PCB board.

[0098] It should be noted that the second wiring layer 7 can be provided with multiple layers, so that signals of different properties can be arranged on different layers, and the pitch between adjacent wires can be increased to effectively reduce the crosstalk between signals.

[0099] In an embodiment, referring to Figure 4 , the chip packaging structure 11 includes a plurality of chips 3, and the plurality of chips 3 are arranged at intervals on the same side of the substrate 1.

[0100] Among them, the adjacent chips 3 are separated by the packaging layer 6.

[0101] Among them, a plurality of chips 3 are arranged at intervals on the same substrate, and the intervals between adjacent chips 3 can be equal.

[0102] Among them, the heat conductors 4 corresponding to the plurality of chips 3 can be in communication with each other and arranged continuously, so that heat can be transmitted between the heat conductors 4 of different chips, avoiding the abnormality caused by heat concentration at a single chip 3.

[0103] It can be understood that the top surfaces of the chips 3 in the chip packaging structure 11 can be flush, that is, the top surfaces of chips 3 of different heights can be ground to be flush with each other by a grinding process when the packaging layer 6 is prepared, and the heat conductors 4 are uniformly prepared on this flush horizontal plane. The top surfaces of the first portions 41 of the plurality of heat conductors 4 are also flush with each other.

[0104] In an embodiment, the preparation material of the substrate 1 includes a glass material.

[0105] The thickness of the glass material substrate 1 is large and the heat conduction performance is poor. When the preparation material of the substrate 1 includes a glass material, the heat dissipation capacity of the chip packaging structure 11 is poor, and it is more necessary to set the heat conductors 4 to enhance the heat dissipation capacity of the chip 3.

[0106] Referring to Figures 5 to 8 The application also provides a preparation method of the chip packaging structure, comprising: Step one: referring to Figure 5 providing a substrate 1, and forming a first wiring layer 2 on one side of the substrate 1; Step two: referring to Figure 6 inverting a chip 3 on the side of the substrate 1 provided with the first wiring layer 2, so that the chip 3 is electrically connected with the first wiring layer 2, and filling a gap between the chip 3 and the substrate 1 with adhesive material to form an underfill adhesive 5; Step three: referring to Figure 7 forming a heat conduction member 4 on the surface and side of the chip 3 away from the substrate 1, the heat conduction coefficient of the heat conduction member 4 being greater than that of the chip 3; Step four: referring to Figure 8 forming a layer of packaging material to encapsulate the chip 3, and removing the packaging material on the side of the chip 3 away from the substrate 1 by grinding, and retaining the packaging material on the side of the heat conduction member 4, to obtain a packaging layer 6 arranged around the side of the heat conduction member 4.

[0107] In step two, a connecting hole is formed on the substrate 1, a second wiring layer 7 is formed on the other side surface of the substrate 1 away from the first wiring layer 2, and the first wiring layer 2 and the second wiring layer 7 are electrically connected through the connecting hole; In step two, the back surface of the chip 3 is directed away from the substrate 1, and is welded with the first wiring layer 2 on the substrate 1, so as to realize the inversion of the chip 3 on the substrate 1, and to fill the underfill adhesive 5 between the chip 3 and the substrate 1; In step three, the heat conduction member 4 is prepared on the surface and side of the body part 31 of the chip 3 away from the substrate 1, so that the heat conduction member 4 comprises a first part 41 covering the back surface of the body part 31 and a second part 42 covering the side surface of the body part 31, and the first part 41 and the second part 42 are in thermal conduction connection.

[0108] In an embodiment, the step of preparing the heat conduction member 4 on the body part 31 of the chip 3 comprises: integrally forming the heat conduction member 4 on the back surface and side of the body part 31 by physical vapor deposition, atomic layer deposition or electroplating process.

[0109] The physical vapor deposition refers to: in a vacuum environment, metal material is bombarded from a target by a physical method (such as sputtering) to fly in an atomic or ionic state and deposit on the surface of the chip 3; the atomic layer deposition refers to: by alternately pulsing a precursor gas into a reaction chamber, chemical adsorption and reaction occur on the surface of the substrate 1, and the thin film is grown layer by layer; the electroplating process refers to: under the action of an electric field, the chip 3 is used as a cathode and is immersed in an electrolyte containing metal ions, so that the metal ions are reduced to metal atoms on the surface of the chip 3 and are continuously deposited and thickened.

[0110] It can be understood that the first part 41 and the second part 42 of the prepared heat conduction piece 4 are integrally formed. Since the heat conduction piece 4 is a continuous whole, there is no contact interface between the first part 41 and the second part 42 of the heat conduction piece 4, thereby completely eliminating the additional thermal resistance (leading to low heat conduction efficiency) caused by poor contact at the contact interface position, and improving the heat conduction efficiency.

[0111] In an embodiment, before the heat conduction piece 4 is prepared, the step of etching or grinding the surface of the body part 31 of the chip 3 away from the substrate 1 is further included to form at least one groove 12; wherein the step of preparing the heat conduction piece 4 includes: the heat conduction piece 4 is profiled along the contour of the groove 12.

[0112] The etching refers to selectively removing materials by chemical or physical-chemical methods. The etching includes wet etching and dry etching. The wet etching is etching using a chemical solution, which is convenient for forming a V-shaped groove. The dry etching is etching using plasma, which is convenient for forming a rectangular groove. The dry etching has the advantages of high precision and good controllability.

[0113] The grinding treatment refers to mechanical processing using physical abrasives (such as diamond grinding wheels).

[0114] It can be understood that the etching has the advantages of high precision and controllable morphology, and the grinding treatment has high efficiency and relatively low cost, and is easy to realize large-area grooves 12, and is more suitable for forming a roughened surface or groove 12 array with certain randomness or without high requirements on the morphology.

[0115] In an embodiment, the step of forming the groove 12 includes: forming a groove 12 with a longitudinal cross-sectional shape of a triangle, a rectangle, a square or a trapezoid; or, forming a plurality of grooves 12 connected head to tail in a continuous zigzag shape.

[0116] In an embodiment, the step of forming the packaging layer 6 includes: using plastic packaging material to perform molding to cover the chip 3 and the side surface of the heat conduction piece 4; and then grinding the packaging layer 6 until the top surface of the side of the heat conduction piece 4 away from the substrate 1 is exposed.

[0117] The process of the first step (molding) is as follows: The semi-finished product composed of the chip 3, the substrate 1, the heat-conducting member 4, etc. is placed in a mold, liquid or semi-solid plastic packaging material is injected into and fills all spaces, and then is heated and solidified, so that the chip 3 and the heat-conducting member 4 and other components are firmly fixed on the substrate 1.

[0118] During molding, the plastic packaging material completely covers the top surface of the heat-conducting member 4, which is a necessary intermediate state to ensure that all gaps on the side surface and the top surface are fully filled.

[0119] The process of the second step (grinding) is as follows: The surface of the solidified packaging layer 6 is quantitatively removed by using a high-precision mechanical grinding machine or a chemical mechanical polishing device, so as to expose the top surface of the heat-conducting member 4. By accurately controlling the grinding amount, the plastic packaging material covering the top surface of the first part 41 of the heat-conducting member 4 is ground off, so that the top surface of the first part 41 of the heat-conducting member 4 is perfectly exposed, and the exposed top surface of the heat-conducting member 4 is flush with the top surface of the surrounding packaging layer 6.

[0120] In an embodiment, a connecting hole is formed on the substrate 1, and before or after the substrate 1 is provided, a step of forming a second wiring layer 7 on the side surface of the substrate 1 away from the chip 3 is further included. The first wiring layer 2 and the second wiring layer 7 are electrically connected through the connecting hole.

[0121] The embodiment of the present application provides a terminal device including the chip packaging structure 11 of any of the above embodiments.

[0122] It can be understood that by loading the chip packaging structure 11 in the terminal device, the excellent heat dissipation performance of the chip packaging structure 11 improves the competitiveness of the product.

[0123] The chip packaging structure 11 provided by the present application includes a substrate 1, a first wiring layer 2, a chip 3, and a heat-conducting member 4. The heat-conducting member 4 includes a first part 41 on the side of the body part 31 away from the substrate 1, and a second part 42 arranged around the side surface of the body part 31. The first part 41 is in thermal contact with the second part 42. The thermal conductivity coefficient of the heat-conducting member 4 is greater than that of the body part 31. The heat-conducting member 4 is divided into the first part 41 connected with an external external heat sink and the second part 42 transmitting the heat of the functional part 32 to the first part 41. By using the advantage of higher thermal conductivity coefficient of the heat-conducting member 4, the heat dissipation efficiency of the functional part 32 to the first part 41 can be enhanced, so that the heat of the chip 3 can be better dissipated, and the heat dissipation capacity of the chip 3 is enhanced.

[0124] In the above embodiments, the description of each embodiment has its own focus. The parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0125] The chip packaging structure 11 and the preparation method thereof provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed, and the above description of the embodiments should not be understood as a limitation of the present application.

Claims

1. A chip package structure, characterized by, The chip package structure comprises: a substrate; a first wiring layer arranged on one side surface of the substrate; a chip arranged on the side of the first wiring layer away from the substrate, the chip being electrically connected with the first wiring layer; a heat conduction member comprising a first part arranged on the side of the chip away from the substrate and a second part arranged around the side surface of the chip, the first part being in thermal conduction connection with the second part, the heat conduction coefficient of the heat conduction member being greater than the heat conduction coefficient of the chip; a packaging layer arranged around the side surface of the second part of the heat conduction member, the side surface of the first part away from the substrate being exposed from the packaging layer.

2. The chip package structure of claim 1, wherein, The first part and the second part are in an integral structure.

3. The chip package structure of claim 2, wherein, The upper end surface of the packaging layer is flush with the side surface of the first part away from the substrate.

4. The chip package structure of claim 1, wherein, The surface of the chip away from the substrate is provided with a groove, and the heat conduction member is arranged in a profile along the groove.

5. The chip package structure of claim 4, wherein, The longitudinal cross-sectional shape of the groove is any one of a triangle, a rectangle, a trapezoid and a semicircle.

6. The chip package structure of claim 4, wherein, The surface of the chip away from the substrate is provided with a plurality of grooves, and the plurality of grooves are arranged in parallel.

7. The chip package structure of claim 1, wherein, The gap between the chip and the substrate is filled with an underfill adhesive, and the preparation material of the underfill adhesive comprises a heat conduction material.

8. The chip package structure of claim 7, wherein, The second part of the heat conduction member is in contact with the substrate and is arranged around the side surface of the chip and the underfill adhesive, and the second part is in contact with the side surface of the underfill adhesive.

9. The chip package structure of any one of claims 1 to 8, wherein, The chip package structure further comprises a second wiring layer arranged on the side surface of the substrate away from the chip, a connecting hole is formed on the substrate, and the first wiring layer and the second wiring layer are electrically connected through the connecting hole.

10. The chip package structure of any one of claims 1 to 8, wherein, The chip package structure comprises a plurality of chips, and the plurality of chips are arranged in parallel on the same surface of the substrate.

11. The chip package structure of any one of claims 1 to 8, wherein, The preparation material of the substrate comprises a glass material.

12. A method for fabricating a chip packaging structure, characterized in that, The chip package structure comprises: providing a substrate, and forming a first wiring layer on one side of the substrate; flip-chip mounting a chip on the side of the substrate provided with the first wiring layer, so that the chip is electrically connected with the first wiring layer, and filling the gap between the chip and the substrate with an adhesive material to form an underfill adhesive; forming a heat conduction member on the side surface of the chip away from the substrate, the heat conduction coefficient of the heat conduction member being greater than the heat conduction coefficient of the chip; forming a layer of packaging material to package the chip, and removing the packaging material on the side of the chip away from the substrate by grinding, and retaining the packaging material on the side surface of the heat conduction member to prepare a packaging layer arranged around the side surface of the heat conduction member.

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