Preparation method of semiconductor through hole, semiconductor interposer and preparation method of semiconductor interposer

Abstract

The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor through hole, a semiconductor interposer and a preparation method of the semiconductor interposer. The invention provides a preparation method of a semiconductor interposer, which comprises the following steps of: forming lattice defects in a preset through hole region of a semiconductor substrate, and growing an epitaxial semiconductor material layer; selectively removing the amorphous or polycrystalline semiconductor material in the preset through hole region through a corrosion process to obtain a semiconductor intermediate layer through hole; filling the through hole with metal to form a conductive through hole; and thinning the second surface of the semiconductor substrate until the conductive through hole penetrates through the remaining semiconductor substrate and the epitaxial semiconductor material layer to form a semiconductor intermediate layer. According to the method, local internal stress generated by deep reactive ion etching or laser through holes is fundamentally avoided, etching damage to the inner walls of the through holes is reduced, the integrity of the semiconductor interposer is remarkably improved, and the risks of warping, internal stress and even breakage of high wafer level or chip level packaging are fundamentally reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor via hole preparation method, a semiconductor interposer and a preparation method thereof. BACKGROUND

[0002] The semiconductor interposer is essentially a sheet-shaped substrate placed between the chip and the packaging substrate, and is a key intermediate layer structure between the chip and the packaging substrate, mainly responsible for high-density interconnection, power distribution and signal transmission, and is one of the core components of advanced packaging technology. Under the background of the rapid development of current packaging technology, the semiconductor interposer is attracting attention due to its significant advantages in improving chip performance (such as bandwidth, energy efficiency) and optimizing cost structure.

[0003] At present, the semiconductor interposer is mainly prepared based on a top-down process route, and the specific process mainly involves deep reactive ion etching or laser via technology. The vertical interconnection via hole penetrating through the semiconductor substrate is formed by top-down etching. However, this process route is easy to introduce local stress in the deep etching process, and the lattice damage caused by etching or laser via itself and the influence on the side wall morphology lead to stress concentration and uneven distribution in the interposer. This stress accumulation not only induces micro-crack initiation during the via etching stage, but also aggravates the structural instability in the subsequent packaging process, thereby increasing the risk of interposer fracture in wafer-level or chip-level packaging. SUMMARY

[0004] In view of the problems existing in the prior art, one object of the present application is to provide a bottom-up semiconductor via hole preparation method; another object of the present application is to provide a semiconductor interposer preparation method with uniform stress distribution; and still another object of the present application is to provide a semiconductor interposer with lower risk of packaging fracture.

[0005] The present application discloses a semiconductor via hole preparation method, which comprises: providing a semiconductor substrate, performing a patterned pretreatment on the first surface of the semiconductor substrate to form lattice defects in a preset via hole region; growing an epitaxial semiconductor material layer on the first surface of the semiconductor substrate after the patterned pretreatment; in the preset via hole region, amorphous or polycrystalline material is obtained, while other regions remain perfect crystals; selectively removing the amorphous or polycrystalline semiconductor material in the preset via hole region by etching process to obtain a semiconductor via hole.

[0006] The preparation method of the semiconductor via hole fundamentally avoids local internal stress generated by deep reactive ion etching or laser via hole technology, avoids etching damage of the inner wall of the via hole, and significantly improves the reliability of the interposer and reduces the risk of warping, internal stress, and even cracking of wafer-level or chip-level packaging.

[0007] Further, the method for forming the lattice defects of the preset via hole region comprises: forming a patterned mask layer on the first surface of the semiconductor substrate and exposing the preset via hole region; inducing the generation of lattice defects in the exposed first surface of the semiconductor substrate by high energy to form the lattice defects of the preset via hole region.

[0008] Further, the method for inducing the generation of lattice defects in the exposed first surface of the semiconductor substrate by high energy comprises: irradiating the preset via hole region by a focused laser beam or a focused ion beam.

[0009] Further, the method for growing the epitaxial semiconductor material layer comprises chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering technology.

[0010] Further, the etching process comprises strong acid etching, strong alkali etching, electrochemical etching, or photoelectrochemical etching.

[0011] Further, the amorphous or polycrystalline semiconductor material in the preset via hole region of the epitaxial semiconductor material layer is selectively removed by the etching process, or the amorphous or polycrystalline semiconductor material in the preset via hole region of the epitaxial semiconductor material layer and the lattice defect material of the first surface of the semiconductor substrate are selectively removed by the etching process.

[0012] The application further discloses a preparation method of a semiconductor interposer, comprising the following steps: obtaining a semiconductor via hole by using the preparation method of the semiconductor via hole as described above; filling the via hole with metal to form a conductive via hole; thinning the second surface of the semiconductor substrate until the conductive via hole penetrates through the remaining semiconductor substrate and the epitaxial semiconductor material layer to form a semiconductor interposer.

[0013] Further, after forming the conductive via hole, a first wiring layer is formed on the first surface of the epitaxial semiconductor material layer, and a second wiring layer is formed on the thinned second surface of the semiconductor substrate.

[0014] Further, the semiconductor substrate is a silicon substrate, and the material of the epitaxial semiconductor material layer is a silicon epitaxial layer; or the semiconductor substrate is a silicon carbide substrate, and the material of the epitaxial semiconductor material layer is a silicon carbide epitaxial layer.

[0015] The application also discloses a semiconductor interposer prepared by the preparation method.

[0016] In conclusion, the application has the following advantages and beneficial effects: The application provides a preparation method of a semiconductor via. First, a lattice defect is formed in a preset via region of a semiconductor substrate, and then an epitaxial semiconductor material layer is grown. Since the lattice defect causes the preset via region to grow an amorphous or polycrystalline epitaxial semiconductor material layer, and other regions grow a single-crystal epitaxial semiconductor material layer. The amorphous or polycrystalline semiconductor material in the preset via region is selectively removed by an etching process to obtain a semiconductor via. The preparation method of the semiconductor via provided by the application fundamentally avoids local internal stress generated by deep reactive ion etching or laser via, reduces etching damage to the inner wall of the via, significantly improves the integrity of the interposer, and fundamentally reduces the risk of warping, internal stress and even cracking of high wafer-level or chip-level packaging. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 FIG. 1 is a structure schematic diagram of a semiconductor substrate after a first surface of the semiconductor substrate is patterned and pretreated in an embodiment of the application; Figure 2 FIG. 2 is a structure schematic diagram of a semiconductor substrate after an epitaxial semiconductor material layer is grown on the semiconductor substrate after the patterned pretreatment is completed in an embodiment of the application; Figure 3 FIG. 3 is a structure schematic diagram of a semiconductor via obtained in an embodiment of the application; Figure 4 FIG. 4 is a structure schematic diagram of a semiconductor interposer prepared in an embodiment of the application.

[0018] Explanation of reference numerals in the drawings: 1, semiconductor substrate; 2, first surface of the semiconductor substrate; 3, preset via region; 4, epitaxial semiconductor material layer; 5, non-preset via region; 6, amorphous or polycrystalline semiconductor material; 7, semiconductor via; 8, second surface of the semiconductor substrate; 9, semiconductor interposer; 10, conductive via. DETAILED DESCRIPTION

[0019] To make the objectives, technical solutions and advantages of the application clearer, the technical solutions of the application will be described below in detail with reference to the specific embodiments of the application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the application.

[0020] Embodiments of the present application are described below in detail, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the drawings are exemplary only, and are used for explanation of the present application, and should not be understood as a limitation of the present application.

[0021] As shown in Figures 1-3 , the present embodiment provides a method for preparing a semiconductor via, specifically comprising steps S1-S3.

[0022] S1, providing a semiconductor substrate 1, performing a patterned pretreatment on the first surface 2 of the semiconductor substrate, and forming a lattice defect in a preset via region 3.

[0023] In an embodiment, the method for forming a lattice defect in a preset via region comprises: forming a patterned mask layer on the first surface 2 of the semiconductor substrate, and exposing the preset via region; using high-energy induction to generate a lattice defect in the exposed first surface 2 of the semiconductor substrate, and forming a lattice defect in the preset via region 3.

[0024] Specifically, the method for using high-energy induction to generate a lattice defect in the exposed first surface 2 of the semiconductor substrate comprises irradiating the preset via region 3 with a focused laser beam or a focused ion beam.

[0025] As shown in Figure 1 , a high-precision physical means such as a focused laser beam or a focused ion beam is used to induce a lattice defect in the preset via region 3, and the initial design of the via topography is completed.

[0026] S2, growing an epitaxial semiconductor material layer 4 on the first surface 2 of the semiconductor substrate after the patterned pretreatment; in the preset via region, amorphous or polycrystalline material is obtained, while other regions remain perfect crystals.

[0027] In an embodiment, as shown in Figure 2 , a chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering technique is used to grow a homoepitaxial epitaxial semiconductor material layer 4 above the first surface 2 of the semiconductor substrate.

[0028] In an embodiment, the semiconductor substrate 1 is a silicon substrate, and the specific material is monocrystalline silicon. The material of the epitaxial semiconductor material layer 4 is a silicon epitaxial layer. Alternatively, the semiconductor substrate is a silicon carbide substrate, and the specific material is monocrystalline silicon carbide. The material of the epitaxial semiconductor material layer is a silicon carbide epitaxial layer.

[0029] As shown in Figure 2As shown, homoepitaxial growth of semiconductor material is performed on the patterned pre-processed semiconductor substrate by chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering techniques. In this process, the pre-defined via region 3 is destroyed in terms of lattice continuity, resulting in amorphous or polycrystalline formation in this region during epitaxial growth; the untreated original substrate region maintains its lattice continuity, achieving high-quality homoepitaxial single crystal growth, and finally forming a composite epitaxial layer structure coexisting with single crystal and amorphous (or polycrystalline). The epitaxial layer of the pre-defined via region 3 is amorphous or polycrystalline, and the non-pre-defined via region 5 is single crystal.

[0030] S3, selectively removing the amorphous or polycrystalline semiconductor material 6 of the pre-defined via region 3 by an etching process, to obtain a semiconductor via 7.

[0031] Due to the large difference in etching rate between single crystal regions and amorphous or polycrystalline regions, the single crystal region is almost not etched, while the amorphous or polycrystalline region has a very fast etching rate due to its structural disorder. By taking advantage of the difference in etching rate between single crystal regions and amorphous or polycrystalline regions, the material of the polycrystalline or amorphous region is selectively removed.

[0032] In an embodiment, as shown in FIG. 2, the semiconductor substrate 1 is first patterned by a pre-processing step, and then the epitaxial semiconductor material layer 4 is grown on the patterned semiconductor substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering techniques. Figure 3 As shown, the amorphous or polycrystalline semiconductor material of the pre-defined via region in the epitaxial semiconductor material layer 4 and the lattice defect material of the first surface 2 of the semiconductor substrate are selectively removed by an etching process. Or the amorphous or polycrystalline semiconductor material of the pre-defined via region in the epitaxial semiconductor material layer 4 is selectively removed by an etching process.

[0033] More specifically, the etching process includes strong acid etching, strong base etching, electrochemical etching or photoelectrochemical etching.

[0034] By using an etching process such as strong acid etching, strong base etching, electrochemical etching or photoelectrochemical etching, the amorphous or polycrystalline region is quickly removed, while the single crystal region structure is completely preserved, obtaining a low-stress, high-reliability vertical interconnection semiconductor via.

[0035] As shown in FIG. 3, the semiconductor via 7 obtained by the method described above is filled with metal to form a conductive via 10. Figures 3-4 As shown in FIG. 4, a semiconductor interposer 9 is formed by thinning the second surface 8 of the semiconductor substrate until the conductive via 10 penetrates through the remaining semiconductor substrate 1 and the epitaxial semiconductor material layer 4. As shown in FIG. 4, a semiconductor interposer 9 is formed by thinning the second surface 8 of the semiconductor substrate until the conductive via 10 penetrates through the remaining semiconductor substrate 1 and the epitaxial semiconductor material layer 4.

[0036] As shown in FIG. 4, a semiconductor interposer 9 is formed by thinning the second surface 8 of the semiconductor substrate until the conductive via 10 penetrates through the remaining semiconductor substrate 1 and the epitaxial semiconductor material layer 4.

[0037] As shown in FIG. 4, a semiconductor interposer 9 is formed by thinning the second surface 8 of the semiconductor substrate until the conductive via 10 penetrates through the remaining semiconductor substrate 1 and the epitaxial semiconductor material layer 4.

[0038] In one embodiment, after forming the conductive via 10, a first wiring layer (not shown in the figure) is formed on the first surface of the epitaxial semiconductor material layer; and a second wiring layer (not shown in the figure) is formed on the second surface of the thinned semiconductor substrate.

[0039] The application also discloses a semiconductor interposer prepared by the preparation method.

[0040] The semiconductor interposer prepared by the preparation method has fundamentally avoided local internal stress generated by deep reactive ion etching or laser via, reduced etching damage of the inner wall of the via, significantly improved the integrity of the interposer, and fundamentally reduced the risk of warping, internal stress, and even cracking of high wafer level or chip level packaging.

[0041] Finally, it should be noted that any modification or equivalent replacement of part or all of the technical features of the technical solutions disclosed in the application and the embodiments described above, as long as the essence does not deviate from the corresponding technical solutions of the application, belongs to the patent range of the device structure and the embodiments described above.

Claims

1. A method for fabricating a semiconductor through-hole, characterized in that, include: A semiconductor substrate is provided, and the first surface of the semiconductor substrate is patterned and pre-processed to form lattice defects in a predetermined via region; An epitaxial semiconductor material layer is grown on the first surface of a semiconductor substrate that has undergone patterning preprocessing. In the pre-defined through-hole area, amorphous or polycrystalline materials are grown, while other areas remain perfect crystals; Semiconductor vias are obtained by selectively removing amorphous or polycrystalline semiconductor material from a predetermined via region through an etching process.

2. The method for preparing a semiconductor through-hole according to claim 1, characterized in that, The method for forming lattice defects in a predetermined through-hole region includes: A patterned mask layer is formed on the first surface of the semiconductor substrate, exposing a predetermined via region; High-energy induction is used to generate lattice defects in the first surface of the exposed semiconductor substrate, forming lattice defects in the predetermined via region.

3. The method for preparing a semiconductor through-hole according to claim 2, characterized in that, The method for generating lattice defects within an exposed first surface of a semiconductor substrate using high-energy induction includes: The pre-defined through-hole area is irradiated with a focused laser beam or a focused ion beam.

4. The method for preparing a semiconductor through-hole according to claim 1, characterized in that, The method for growing an epitaxial semiconductor material layer includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering techniques.

5. The method for preparing a semiconductor through-hole according to claim 1, characterized in that, The corrosion process includes strong acid corrosion, strong alkali corrosion, electrochemical corrosion, or photoelectrochemical corrosion.

6. The method for preparing a semiconductor through-hole according to claim 1, characterized in that, The etching process selectively removes amorphous or polycrystalline semiconductor material from the predetermined via region in the epitaxial semiconductor material layer, or selectively removes amorphous or polycrystalline semiconductor material from the predetermined via region in the epitaxial semiconductor material layer and lattice defect material from the first surface of the semiconductor substrate.

7. A method for preparing a semiconductor interposer, characterized in that, Includes the following steps: Semiconductor vias are obtained by the method for preparing semiconductor vias as described in any one of claims 1-6; The through-hole is filled with metal to form a conductive through-hole; The second surface of the semiconductor substrate is thinned until the conductive via penetrates the remaining semiconductor substrate and the epitaxial semiconductor material layer to form a semiconductor interlayer.

8. The method for preparing a semiconductor interposer according to claim 7, characterized in that, After forming conductive vias, a first wiring layer is formed on the first surface of the epitaxial semiconductor material layer; a second wiring layer is formed on the second surface of the thinned semiconductor substrate.

9. The method for preparing a semiconductor interposer according to claim 7, characterized in that, The semiconductor substrate is a silicon substrate, and the material of the epitaxial semiconductor material layer is a silicon epitaxial layer; or the semiconductor substrate is a silicon carbide substrate, and the material of the epitaxial semiconductor material layer is a silicon carbide epitaxial layer.

10. A semiconductor interposer, characterized in that, It is prepared by the preparation method according to any one of claims 7-9.

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