Packaging substrate and preparation method of chip packaging structure

Abstract

The invention discloses a packaging substrate and a preparation method of a chip packaging structure. The packaging substrate comprises a supporting substrate, a flexible layer, m conductive layers, m-1 insulating layers, a solder mask layer and a conductive bonding pad. The m conductive layers are used as the wiring layers of the packaging carrier plate, so that the wiring space and the wiring number of the packaging carrier plate can be increased, and the problem of poor wiring density of the coreless carrier plate is solved. The conductive bonding pad is used for being welded with the chip so as to fixedly connect the chip to the packaging carrier plate to form the chip packaging structure. The m-1-th insulating layer insulates the mth conductive layer from the m-1-th conductive layer, so that the risk of short circuit between the mth conductive layer and the m-1-th conductive layer is reduced. The flexible layer is supported by adopting the supporting substrate with a relatively large elastic modulus, so that the rigidity and the dimensional stability of the coreless carrier plate in a chip laminating process are ensured, and the laminating precision and the yield of the chip are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a method for preparing a packaging substrate and a chip packaging structure. Background Technology

[0002] The chip carrier board for integrated circuits (ICs), also known as the IC packaging carrier board, is used directly to mount the integrated circuit. It not only provides support and protection for the IC but also enables the connection between the IC and the printed circuit board (PCB). In short, the chip carrier board is a core element that carries the integrated circuit and enables high-speed communication and effective heat dissipation between the IC and the outside world.

[0003] The trend towards thinner electronic products has spurred the development of coreless packaging substrates, which are not only thinner than core-based packaging substrates but also offer superior electrical performance. Packaging substrates are crucial components connecting integrated circuit chips to external PCBs. For chip packaging in mobile portable devices, especially smart wearables such as VR and AR, ultra-thin packaging substrates are needed to reduce chip size and weight, improving the comfort of wearing the device. Simultaneously, the increasing demands of terminals for chip computing power and AI technologies necessitate the development of chip packaging substrates with high wiring density. Coreless substrates can meet these technical requirements.

[0004] However, there are also problems with the poor wiring precision of coreless carrier boards, as well as the poor stability after the thickness of the carrier board is reduced. Summary of the Invention

[0005] This application provides a method for preparing a packaging substrate and a chip packaging structure, aiming to improve the problems of poor wiring precision and poor stability of coreless substrates.

[0006] The first aspect of this application provides a packaging carrier board, comprising: a supporting substrate; a flexible layer located on one side of the supporting substrate, the elastic modulus of the flexible layer being less than that of the supporting substrate; a first conductive layer located on the side of the flexible layer away from the supporting substrate; an m-th conductive layer and an m-1-th insulating layer, sequentially stacked on the side of the first conductive layer away from the supporting substrate, the m-th conductive layer comprising the first conductive layer and the m-th conductive layer, the m-1-th insulating layer comprising the m-1-th insulating layer, the m-th conductive layer located on the side of the m-1-th insulating layer away from the supporting substrate, the conductive layer comprising at least one signal trace, wherein m is an integer greater than or equal to 2; a solder mask layer located on the side of the second conductive layer away from the supporting substrate; and a plurality of conductive pads located on the side of the solder mask layer away from the supporting substrate, the conductive pads being electrically connected to the m-th conductive layer, the heat distortion temperature of the solder mask layer being greater than or equal to 350°C.

[0007] According to an embodiment of the first aspect of this application, the coefficient of thermal expansion of the solder resist layer is less than 10 ppm.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the coefficient of thermal expansion of the solder resist layer is 3ppm to 8ppm.

[0009] According to any of the foregoing embodiments of the first aspect of this application, the material of the conductive layer includes a metallic material.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the material of the insulating layer includes organic materials and / or inorganic materials.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the material of the support substrate includes glass.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the material of the flexible layer includes organic materials.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the material of the flexible layer includes polyimide.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the flexible layer is 2μm to 20μm.

[0015] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the flexible layer is 3μm to 10μm.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the coefficient of thermal expansion of the flexible layer is 3ppm to 20ppm.

[0017] According to any of the foregoing embodiments of the first aspect of this application, the coefficient of thermal expansion of the flexible layer is 3ppm to 10ppm.

[0018] According to any of the foregoing embodiments of the first aspect of this application, the material of the solder resist layer includes organic materials.

[0019] According to any of the foregoing embodiments of the first aspect of this application, the material of the solder resist layer includes polyimide.

[0020] According to any of the foregoing embodiments of the first aspect of this application, the solder mask layer and the flexible layer are made of the same material.

[0021] According to any of the foregoing embodiments of the first aspect of this application, it further includes: an adhesion layer located between the flexible layer and the first conductive layer.

[0022] According to any of the foregoing embodiments of the first aspect of this application, the material of the adhesive layer includes inorganic materials.

[0023] According to any of the foregoing embodiments of the first aspect of this application, the material of the adhesive layer includes at least one of silicon oxide or silicon nitride.

[0024] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the adhesive layer is less than the thickness of the flexible layer.

[0025] According to any of the foregoing embodiments of the first aspect of this application, the m-layer conductive layer includes a second conductive layer, the m-1-layer insulating layer includes a first insulating layer, the first insulating layer is located between the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer are electrically connected.

[0026] According to any of the foregoing embodiments of the first aspect of this application, the first conductive layer includes a plurality of spaced first conductive portions, the second conductive layer includes a plurality of spaced second conductive portions, and the first conductive portions and the second conductive portions are electrically connected to each other.

[0027] According to any of the foregoing embodiments of the first aspect of this application, the first conductive portion includes a first functional layer and a second functional layer stacked along a direction away from the supporting substrate, wherein the thickness of the first functional layer is less than the thickness of the second functional layer.

[0028] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the second functional layer is 2μm to 30μm.

[0029] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the second functional layer is 5μm to 20μm.

[0030] According to any of the foregoing embodiments of the first aspect of this application, the material of the first conductive layer includes a metallic material.

[0031] According to any of the foregoing embodiments of the first aspect of this application, the material of the second conductive layer includes a metallic material.

[0032] According to any of the foregoing embodiments of the first aspect of this application, the material of the second functional layer includes copper.

[0033] According to any of the foregoing embodiments of the first aspect of this application, the material of the first conductive layer and the material of the second conductive layer are the same.

[0034] According to any of the foregoing embodiments of the first aspect of this application, the first functional layer includes a first sublayer and a second sublayer stacked along a direction away from the supporting substrate, and the first sublayer and the second sublayer are made of different materials.

[0035] According to any of the foregoing embodiments of the first aspect of this application, the material of the first sublayer includes titanium.

[0036] According to any of the foregoing embodiments of the first aspect of this application, the material of the second sublayer includes copper.

[0037] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the first sublayer is 10nm to 100nm.

[0038] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the second sublayer is 100nm~2000nm.

[0039] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the second sublayer is greater than the thickness of the first sublayer.

[0040] According to any of the foregoing embodiments of the first aspect of this application, the m-layer conductive layer includes a third conductive layer, the m-1-layer insulating layer includes a second insulating layer, the second insulating layer is located between the second conductive layer and the third conductive layer, the second insulating layer is located on the side of the second conductive layer away from the supporting substrate, and the third conductive layer and the second conductive layer are electrically connected.

[0041] According to any of the foregoing embodiments of the first aspect of this application, the encapsulation substrate further includes: a second insulating layer located between the second conductive layer and the third conductive layer.

[0042] According to any of the foregoing embodiments of the first aspect of this application, the material of the second insulating layer includes organic materials and / or inorganic materials.

[0043] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the second insulating layer is 10 μm to 100 μm.

[0044] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the second insulating layer is 20μm to 80μm.

[0045] According to any of the foregoing embodiments of the first aspect of this application, the second insulating layer and the first insulating layer are made of the same material.

[0046] According to any of the foregoing embodiments of the first aspect of this application, the material of the third conductive layer includes a metallic material.

[0047] According to any of the foregoing embodiments of the first aspect of this application, the third conductive layer and the first conductive layer are made of the same material, and / or the third conductive layer and the second conductive layer are made of the same material.

[0048] According to any of the foregoing embodiments of the first aspect of this application, the material of the first insulating layer includes organic materials and / or inorganic materials.

[0049] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the first insulating layer is 10 μm to 100 μm.

[0050] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the first insulating layer is 20μm to 80μm.

[0051] An embodiment of the second aspect of this application provides a packaging carrier board, comprising: a supporting substrate; a flexible layer located on one side of the supporting substrate, the elastic modulus of the flexible layer being less than that of the supporting substrate; a first conductive layer located on the side of the flexible layer facing away from the supporting substrate; an (n-1)th insulating layer located on the side of the first conductive layer facing away from the supporting substrate; an nth conductive layer located on the side of the first insulating layer facing away from the supporting substrate, a second conductive layer electrically connected to the first conductive layer, where n is greater than or equal to 2 and is a positive integer; a solder resist layer located on the side of the second conductive layer facing away from the supporting substrate; and a plurality of conductive pads located on the side of the solder resist layer facing away from the supporting substrate, the conductive pads being electrically connected to the second conductive layer, the heat distortion temperature of the solder resist layer being greater than or equal to 400°C.

[0052] An embodiment of the third aspect of this application provides a method for fabricating a chip packaging structure, including: The chip is fixedly connected to the conductive pads of the packaging substrate of any of the above embodiments. A sealing layer is prepared on the side of the chip away from the packaging substrate, and the chip is positioned within the orthogonal projection of the sealing layer onto the substrate when projected onto the packaging substrate. Remove the support substrate; The flexible layer is patterned to expose the first conductive layer; Conductive pins are fabricated on the side of the flexible layer opposite to the first conductive layer, and the conductive pins are electrically connected to the first conductive layer.

[0053] According to an embodiment of this application, the packaging carrier includes a supporting substrate, a flexible layer, an m-th conductive layer, an m-1-th insulating layer, a solder resist layer, and conductive pads. The flexible layer of the packaging carrier serves as the bottom layer of the subsequent chip packaging structure, insulating the first conductive layer and other film layers on the side of the flexible layer away from the first conductive layer, reducing the risk of short circuits between the first conductive layer and other film layers. Furthermore, the flexible layer replaces the temporary bonding layer in related technologies, eliminating the need for temporary bonding materials and their processing steps, thus reducing costs. The m-th conductive layer serves as the wiring layer of the packaging carrier, increasing the wiring space and the number of wirings, improving the wiring density difference problem of coreless carriers. The conductive pads are used to solder the chip to fix it to the packaging carrier, forming a chip packaging structure. The m-1-th insulating layer insulates the m-th conductive layer from the (m-1)-th conductive layer, reducing the risk of short circuits between them. A supporting substrate with a high elastic modulus is used to support the flexible layer, ensuring the rigidity and dimensional stability of the coreless carrier during chip bonding, improving chip bonding accuracy and yield. The heat distortion temperature of the solder mask is greater than or equal to 350℃. In the subsequent chip packaging structure preparation process, the solder mask can be directly dry etched. The process is simple, it is easy to control the accuracy of vias, and improves the chip bonding accuracy and yield. It can improve the problem that the low heat distortion temperature of the solder mask makes it easy to damage the solder mask when dry etching, making chip bonding difficult. The only way to etch the solder mask is to use wet etching, which is complicated and has low precision. Attached Figure Description

[0054] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0055] Figure 1 This is a partial cross-sectional view of a packaging carrier provided in an embodiment of this application; Figure 2 This is a partial cross-sectional view of the packaging carrier in another embodiment; Figure 3 This is a partial cross-sectional view of the packaging carrier in yet another embodiment; Figure 4 This is a partial cross-sectional view of the encapsulation carrier in another embodiment; Figure 5 This is a partial cross-sectional view of the packaging carrier in another embodiment; Figures 6 to 15 This is a process diagram illustrating the fabrication of a packaging substrate provided in an embodiment of this application; Figure 16 This is a flowchart illustrating the use of a packaging carrier provided in an embodiment of this application; Figures 17 to 19This is a diagram illustrating the usage process of a packaging carrier provided in an embodiment of this application.

[0056] Explanation of reference numerals in the attached figures: 10. Packaging substrate; 20. Chip; 21. Sealing layer; 22. Conductive pins; 23. Encapsulating adhesive; 100. Supporting substrate; 200. Flexible layer; 210. Adhesive layer; 300, First conductive layer; 310, First conductive part; 311, First functional layer; 311a, First sub-layer; 311b, Second sub-layer; 312, Second functional layer; 400, First insulating layer; 410, First via; 500, Second conductive layer; 510, Second conductive part; 600, Solder mask; 610, Pad via; 700, Third conductive layer; 710, Third conductive part; 800, Second insulating layer; 810, Second via; 900, conductive pad. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0058] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0059] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0060] For certain elements, terms like "above" or "over" are sometimes used when describing their location, while "below" or "under" is used when describing the location of an element in the opposite direction. Furthermore, when using terms like "above," "over," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only situations where the two elements are directly adjacent but also situations where they are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for descriptive distinction and should not be interpreted as indicating or implying relative importance.

[0061] This application provides a method for fabricating a packaging substrate and a chip packaging structure. The following will describe various embodiments of the method for fabricating the packaging substrate and the chip packaging structure with reference to the accompanying drawings.

[0062] Please see Figure 1 , Figure 1 This is a partial cross-sectional view of a packaging carrier provided in an embodiment of this application.

[0063] like Figure 1 As shown, a first aspect embodiment of this application provides a packaging carrier 10, including: a supporting substrate 100; and a flexible layer 200 located on one side of the supporting substrate 100, wherein the elastic modulus of the flexible layer 200 is less than that of the supporting substrate 100. An m-th conductive layer and an m-1-th insulating layer are sequentially stacked on the side of the flexible layer 200 away from the supporting substrate 100. The m-th conductive layer includes a first conductive layer 300 and an m-th conductive layer, with the m-th conductive layer located on the side of the first conductive layer 300 away from the supporting substrate. The m-1-th insulating layer includes an m-1-th insulating layer, with the m-th conductive layer located on the side of the m-1-th insulating layer away from the supporting substrate 100. Each conductive layer includes at least one signal trace, where m is an integer greater than or equal to 2. A solder mask layer 600 is located on the side of the second conductive layer 500 away from the supporting substrate 100. A plurality of conductive pads 900 are located on the side of the solder mask layer 600 away from the supporting substrate 100. The conductive pads 900 are electrically connected to the m-th conductive layer, and the heat distortion temperature of the solder mask layer 600 is greater than or equal to 350°C.

[0064] According to an embodiment of this application, the packaging substrate 10 includes a supporting substrate 100, a flexible layer 200, a first conductive layer 300, an m-layer conductive layer, an m-1-layer insulating layer, a solder resist layer 600, and conductive pads 900. The flexible layer 200 of the packaging substrate 10 serves as the bottom layer of the subsequent chip packaging structure, achieving insulation between the first conductive layer 300 and other film layers on the side of the flexible layer 200 away from the first conductive layer 300, reducing the risk of short circuits between the first conductive layer 300 and other film layers. Furthermore, the flexible layer 200 replaces the temporary bonding layer in related technologies, omitting temporary bonding materials and their processing steps, thus reducing costs. The m-layer conductive layer serves as the wiring layer of the packaging substrate 10, increasing the wiring space and the number of wirings in the packaging substrate 10, improving the wiring density problem of coreless substrates. The conductive pads 900 are used for soldering with the chip to fix the chip to the packaging substrate 10, forming a chip packaging structure. The (m-1)th insulating layer provides insulation protection for the m-th and (m-1)th conductive layers, reducing the risk of short circuits between them. A support substrate 100 with a high elastic modulus supports the flexible layer 200, ensuring the rigidity and dimensional stability of the coreless substrate during chip bonding, thus improving chip bonding accuracy and yield. The solder resist layer 600 has a heat distortion temperature greater than or equal to 350℃. During subsequent chip packaging structure fabrication, the solder resist layer 600 can be directly dry-etched, simplifying the process and facilitating via precision control, thereby improving chip bonding accuracy and yield. This addresses the problem that the low heat distortion temperature of the solder resist layer 600 makes dry etching prone to damage, hindering chip bonding, and necessitating the use of wet etching, which is complex and has low precision.

[0065] Optionally, the heat distortion temperature of the solder mask layer 600 is 400℃~500℃, for example, 400℃, 430℃, 450℃, 480℃, 500℃, etc. When the heat distortion temperature of the solder mask layer 600 is greater than or equal to 400℃, dry etching can be directly performed on the solder mask layer 600 during the subsequent chip packaging structure fabrication process. This simplifies the process, facilitates the precision control of vias, and improves chip bonding accuracy and yield. It also addresses the problem that a low heat distortion temperature of the solder mask layer 600 can easily damage the solder mask layer during dry etching, making chip bonding difficult and necessitating wet etching, which is complex and has low precision. Conversely, a heat distortion temperature of less than or equal to 500℃ can address the problem that an excessively high heat distortion temperature of the solder mask layer 600 makes it difficult to etch vias.

[0066] Optionally, the conductive layer may be made of metallic materials. Optionally, the insulating layer may be made of organic and / or inorganic materials.

[0067] In some alternative embodiments, the material of the support substrate 100 includes glass.

[0068] In these optional embodiments, the glass support substrate 100 has good hardness. Using the relatively hard support substrate 100 to support the flexible layer 200 ensures the rigidity and dimensional stability of the coreless carrier during the chip bonding process, improving chip bonding accuracy and yield. Since the coreless packaging carrier 10 is usually an ultra-thin carrier, if only the flexible layer 200 is used as the substrate, the overall rigidity of the packaging carrier 10 is low, making it prone to deformation and dimensional instability. Therefore, using the glass support substrate 100 to rigidly support the flexible layer 200 can improve the above-mentioned problems.

[0069] Optionally, the coefficient of thermal expansion of the solder mask 600 is less than 10 ppm. This can improve the problem that an excessively high coefficient of thermal expansion of the solder mask 600 leads to excessive thermal expansion, making it prone to deformation and resulting in poor structural stability. Furthermore, it ensures that the coefficients of thermal expansion of the solder mask 600 and the chip are similar, mitigating the problem of poor bonding accuracy caused by differences in thermal expansion.

[0070] In some optional embodiments, the coefficient of thermal expansion of the solder mask 600 is 3ppm to 8ppm. For example, the coefficient of thermal expansion of the solder mask 600 is 3ppm, 5ppm, 6ppm, 8ppm, etc.

[0071] In these optional embodiments, the coefficient of thermal expansion of the solder resist layer 600 is greater than or equal to 3 ppm, which can improve the poor thermal expansion capacity, poor stress buffering capacity, and poor flexibility of the solder resist layer 600 caused by an excessively small coefficient of thermal expansion. The coefficient of thermal expansion of the solder resist layer 600 is less than or equal to 8 ppm, which can improve the problem of excessive thermal expansion capacity, easy deformation, and poor structural stability caused by an excessively large coefficient of thermal expansion.

[0072] In some alternative embodiments, the flexible layer 200 is made of an organic material. Optionally, the flexible layer 200 is made of polyimide.

[0073] In these alternative embodiments, organic materials exhibit better flexibility. The flexible layer 200 of organic material replaces the temporary bonding layer in related technologies, omitting the temporary bonding material and its processing steps, thus reducing costs. Polyimide material is used as part of the packaging substrate 10 to achieve its multifunctionality, offering lower cost and better performance. The flexible layer 200 is made of polyimide. In the subsequent fabrication of the chip packaging structure, a dry etching process can be used to create openings in the flexible layer 200 to expose the first conductive layer 300. For example, a laser etching process can be used to create openings in the flexible layer 200. The dry etching process offers high precision and simplicity, overcoming the problem that the temporary bonding materials (e.g., organic polymers) used in the existing flexible layer 200 are difficult to dry-etch, requiring the temporary bonding material to be dissolved before attaching a film layer for etching to expose the first conductive layer 300, resulting in a complex and costly solution.

[0074] In some optional embodiments, the thickness of the flexible layer 200 is 2 μm to 20 μm. For example, the thickness of the flexible layer 200 is 2 μm, 8 μm, 15 μm, 20 μm, etc.

[0075] In these optional embodiments, the thickness of the flexible layer 200 is greater than or equal to 2 μm. This can mitigate the problems caused by an excessively thin flexible layer 200, such as the difficulty in fabricating the flexible layer 200, its low structural strength, poor stability, and the difficulty in drilling holes in the flexible layer 200 during subsequent use with the packaging substrate 10. Conversely, a thickness of less than or equal to 20 μm can mitigate the problems caused by an excessively thick flexible layer 200, such as deep vias that make it difficult to guarantee via process accuracy and the difficulty in drilling holes.

[0076] Optionally, the thickness of the flexible layer 200 is 3μm to 10μm. For example, the thickness of the flexible layer 200 can be 3μm, 6μm, 8μm, 10μm, etc. Setting the thickness of the flexible layer 200 within this range can ensure the structural strength and drilling accuracy of the flexible layer 200.

[0077] In some optional embodiments, the coefficient of thermal expansion of the flexible layer 200 is 3ppm to 20ppm. For example, the coefficient of thermal expansion of the flexible layer 200 is 3ppm, 11ppm, 16ppm, 20ppm, etc.

[0078] Objects expand and contract due to changes in temperature. Their capacity for change is expressed as the change in length caused by a unit change in temperature under constant pressure, i.e., the coefficient of thermal expansion.

[0079] In these optional embodiments, the coefficient of thermal expansion of the flexible layer 200 is greater than or equal to 3 ppm, which can improve the poor thermal expansion capacity, poor stress buffering capacity, and poor flexibility of the flexible layer 200 caused by an excessively small coefficient of thermal expansion. Conversely, the coefficient of thermal expansion of the flexible layer 200 is less than or equal to 20 ppm, which can improve the problem of excessive thermal expansion capacity, easy deformation, and poor structural stability caused by an excessively large coefficient of thermal expansion.

[0080] Optionally, the coefficient of thermal expansion of the flexible layer 200 is 3ppm to 10ppm. For example, the coefficient of thermal expansion of the flexible layer 200 is 3ppm, 5ppm, 8ppm, 10ppm, etc. Within this range, the coefficient of thermal expansion of the flexible layer 200 can ensure good stress buffering capacity, flexibility, and structural stability.

[0081] In some alternative embodiments, the solder mask 600 is made of an organic material. Optionally, the solder mask 600 is made of polyimide.

[0082] In these alternative embodiments, the solder resist layer 600 made of organic material can easily be made with a large thickness to cover the m-th conductive layer, thereby achieving insulation between the m-th conductive layer and the chip at the location of the solder resist layer 600, reducing the risk of short circuit between the m-th conductive layer and the chip. The polyimide solder resist layer 600 replaces the solder resist layer in related technologies, omitting the solder resist material and its processing steps, thus reducing costs. The polyimide material serves as part of the packaging substrate 10 to achieve its multifunctionality, offering lower cost and better performance.

[0083] In some alternative embodiments, the solder mask layer 600 and the flexible layer 200 are made of the same material.

[0084] In these alternative embodiments, the solder mask 600 and the flexible layer 200 are made of the same material and can be fabricated using the same process, simplifying the fabrication process of the encapsulation carrier 10. For example, both the solder mask 600 and the flexible layer 200 are polyimide. Polyimide material, as part of the encapsulation carrier 10, achieves its multifunctionality, is low-cost, and has good performance.

[0085] Please see Figure 2 , Figure 2 This is a partial cross-sectional view of the encapsulation carrier in another embodiment.

[0086] like Figure 2 As shown, in some optional embodiments, the encapsulation carrier 10 further includes an adhesion layer 210 located between the flexible layer 200 and the first conductive layer 300.

[0087] In these optional embodiments, since the adhesion between the flexible layer 200 and the first conductive layer 300 is poor, resulting in poor interface stability between the flexible layer 200 and the first conductive layer 300, an additional adhesion layer 210 is provided between the flexible layer 200 and the first conductive layer 300 to improve the adhesion effect between the flexible layer 200 and the first conductive layer 300 and improve the film stability of the encapsulation carrier 10.

[0088] In some optional embodiments, the material of the adhesion layer 210 includes an inorganic material. Optionally, the material of the adhesion layer 210 includes at least one of silicon oxide or silicon nitride.

[0089] In these optional embodiments, the adhesion force between the inorganic material adhesion layer 210 and the flexible layer 200 is greater than the adhesion force between the flexible layer 200 and the first conductive layer 300, and the adhesion force between the inorganic material adhesion layer 210 and the first conductive layer 300 is greater than the adhesion force between the flexible layer 200 and the first conductive layer 300. Therefore, by additionally providing an adhesion layer 210 between the flexible layer 200 and the first conductive layer 300, the adhesion effect between the flexible layer 200 and the first conductive layer 300 can be improved, thereby improving the film stability of the encapsulation carrier 10.

[0090] In some alternative embodiments, the thickness of the adhesive layer 210 is less than the thickness of the flexible layer 200.

[0091] In these alternative embodiments, the thickness of the adhesive layer 210 is set to be smaller, which can improve the problem that the material cost of the adhesive layer 210 is too high and the subsequent drilling difficulty is too high due to the excessive thickness of the adhesive layer 210. The thickness of the flexible layer 200 is set to be larger, which can improve the problem that the manufacturing difficulty of the flexible layer 200 is high, the structural strength of the flexible layer 200 is low and the stability is poor due to the excessive thickness of the flexible layer 200, as well as the problem that the drilling difficulty of the flexible layer 200 is high during the subsequent use of the packaging carrier 10.

[0092] Optionally, the m-th conductive layer includes a second conductive layer 500, and the m-1-th insulating layer includes a first insulating layer 400. The first insulating layer 400 is located between the first conductive layer 300 and the second conductive layer 500, and the first conductive layer 300 and the second conductive layer 500 are electrically connected.

[0093] In some optional embodiments, the first conductive layer 300 includes a plurality of spaced first conductive portions 310, and the second conductive layer 500 includes a plurality of spaced second conductive portions 510, with the first conductive portions 310 and the second conductive portions 510 being electrically connected to each other.

[0094] In these optional embodiments, the first conductive portion 310 and the second conductive portion 510 are electrically connected to each other, that is, one first conductive portion 310 and one second conductive portion 510 are electrically connected through a via. By wiring through the plurality of first conductive portions 310 of the first conductive layer 300 and the plurality of second conductive portions 510 of the second conductive layer 500, the wiring space and the number of wirings of the packaging substrate 10 can be increased, and the problem of poor wiring density of the coreless substrate can be improved.

[0095] Optionally, a plurality of first vias 410 are provided on the first insulating layer 400, and the first conductive part 310 and the second conductive part 510 are electrically connected through the first vias 410.

[0096] Optionally, the solder mask layer 600 has multiple solder pad vias 610, and the conductive solder pad 900 and the second conductive part 510 are electrically connected through the solder pad vias 610.

[0097] Please see Figure 3 , Figure 3 This is a partial cross-sectional view of the packaging carrier in another embodiment.

[0098] like Figure 3 As shown, in some optional embodiments, the first conductive portion 310 includes a first functional layer 311 and a second functional layer 312 stacked along a direction away from the support substrate 100. The orthographic projection of the first functional layer 311 onto the support substrate 100 is located within the orthographic projection of the second functional layer 312 onto the support substrate 100. The thickness of the first functional layer 311 is less than the thickness of the second functional layer 312.

[0099] In these optional embodiments, the first conductive portion 310 includes a first functional layer 311 and a second functional layer 312, which are layered and fabricated. The second functional layer 312 serves as a mask for the first functional layer 311, requiring a greater thickness. This improves the second functional layer 312's etching resistance, reducing the risk of it being etched away before the first functional layer 311 is etched, thus ensuring the integrity of the mask structure. The second functional layer 312 always acts as a mask for the first functional layer 311, guaranteeing its complete etching.

[0100] Optionally, the average resistivity of the second functional layer 312 is less than the average resistivity of the first functional layer 311, and the thickness of the second functional layer 312 is set to be greater, which can reduce the overall resistance of the first conductive part 310.

[0101] In some optional embodiments, the thickness of the second functional layer 312 is 2μm to 30μm. For example, the thickness of the second functional layer 312 is 2μm, 5μm, 20μm, 30μm, etc.

[0102] In these optional embodiments, the thickness of the second functional layer 312 is greater than or equal to 2 μm, which can improve the problem that the fabrication difficulty and structural strength of the second functional layer 312 are too high due to its small thickness. The thickness of the second functional layer 312 is less than or equal to 30 μm, which can improve the problem that the material cost of the second functional layer 312 is increased due to its large thickness.

[0103] Optionally, the thickness of the second functional layer 312 is 5μm to 20μm. Within this range, the thickness of the second functional layer 312 can ensure good structural strength and reduce material costs.

[0104] Optionally, the material of the first conductive layer 300 may include a metallic material, such as copper or titanium. Metallic materials have good electrical conductivity.

[0105] Optionally, the material of the second conductive layer 500 may include a metallic material, such as copper or titanium. Metallic materials have good electrical conductivity.

[0106] Optionally, the material of the second functional layer 312 may include copper. Copper has good electrical conductivity and etching resistance.

[0107] Please see Figure 4 , Figure 4 This is a partial cross-sectional view of the packaging carrier in another embodiment.

[0108] like Figure 4 As shown, in some optional embodiments, the first functional layer 311 includes a first sublayer 311a and a second sublayer 311b stacked along a direction away from the support substrate 100, and the first sublayer 311a and the second sublayer 311b are made of different materials.

[0109] In these optional embodiments, the first functional layer 311 includes a first sub-layer 311a and a second sub-layer 311b, which are arranged in layers. The adhesion between the first sub-layer 311a and the adhesive layer 210 or the flexible layer 200 is greater than the adhesion between the second sub-layer 311b and the adhesive layer 210 or the flexible layer 200. That is, the first sub-layer 311a can increase the adhesion between the first functional layer 311 and the adhesive layer 210 or the flexible layer 200, thereby improving the film stability of the encapsulation carrier 10. Optionally, the resistivity of the first sub-layer 311a is lower than the resistivity of the second sub-layer 311b, and the second sub-layer 311b is used to reduce the overall resistance of the first functional layer 311.

[0110] Optionally, the material of the first sublayer 311a may include titanium. The first sublayer 311a made of titanium material has a large adhesion to the adhesive layer 210 or the flexible layer 200.

[0111] Optionally, the material of the second sublayer 311b may include copper. The copper material of the second sublayer 311b has a low resistivity, which can reduce the overall resistance of the first functional layer 311.

[0112] In some optional embodiments, the thickness of the first sublayer 311a is 10 nm to 100 nm. For example, the thickness of the first sublayer 311a is 10 nm, 30 nm, 50 nm, 100 nm, etc.

[0113] In these optional embodiments, the thickness of the first sublayer 311a is greater than or equal to 10 nm, which can improve the problem that if the thickness of the first sublayer 311a is too small, it will be difficult to fabricate and result in poor structural strength. The thickness of the first sublayer 311a is less than or equal to 100 nm, which can improve the problem that if the thickness of the first sublayer 311a is too large, the material cost of the first sublayer 311a will increase.

[0114] In some optional embodiments, the thickness of the second sublayer 311b is 100nm to 2000nm. For example, the thickness of the second sublayer 311b is 100nm, 300nm, 350nm, 500nm, 2000nm, etc.

[0115] In these alternative embodiments, the thickness of the second sublayer 311b is greater than or equal to 100 nm, which can improve the problem that the overall resistance of the first functional layer 311 is high due to the thickness of the second sublayer 311b being too small. The thickness of the second sublayer 311b is less than or equal to 2000 nm, which can improve the problem that the material cost of the second sublayer 311b is increased due to the thickness of the second sublayer 311b being too large.

[0116] In some alternative embodiments, the thickness of the second sublayer 311b is greater than the thickness of the first sublayer 311a.

[0117] In these alternative embodiments, the thickness of the first sublayer 311a is set to be smaller, which can ensure the adhesion function of the first sublayer 311a and reduce the material cost of the first sublayer 311a. The resistivity of the second sublayer 311b is lower than that of the first sublayer 311a. Making the second sublayer 311b thicker and the first sublayer 311a thinner can reduce the overall resistance of the first functional layer 311.

[0118] Optionally, the materials of the first conductive layer 300 and the second conductive layer 500 are the same, and the first conductive layer 300 and the second conductive layer 500 can be prepared using the same process, simplifying the preparation process. The first conductive layer 300 and the second conductive layer 500 have the same film structure, or the second conductive layer 500 also has a multilayer structure similar to the first functional layer 311 and the second functional layer 312 described above.

[0119] Please see Figure 5 , Figure 5 This is a partial cross-sectional view of the packaging carrier in another embodiment.

[0120] like Figure 5 As shown, in some optional embodiments, the m-th conductive layer includes a third conductive layer 700, the m-1 insulating layer includes a second insulating layer 800, the second insulating layer 800 is located between the second conductive layer 500 and the third conductive layer 700, the second insulating layer 800 is located on the side of the second conductive layer 500 away from the support substrate 100, and the third conductive layer 700 and the second conductive layer 500 are electrically connected.

[0121] In these optional embodiments, a third conductive layer 700 is further disposed between the solder mask layer 600 and the second conductive layer 500, further increasing the wiring space and the number of wirings in the package carrier 10, and improving the problem of poor wiring density in the coreless carrier. The second insulating layer 800 provides insulation protection between the third conductive layer 700 and the second conductive layer 500, reducing the risk of short circuit between the second conductive layer 500 and the third conductive layer 700.

[0122] In some alternative embodiments, the material of the second insulating layer 800 includes organic materials, such as bismaleimide-triazine resin (BT), air bubble film (ABF), etc. Alternatively, the material of the second insulating layer 800 includes an inorganic / organic composite material.

[0123] In these alternative embodiments, the second insulating layer 800 of the organic material can be made to have a large thickness, thereby covering the third conductive layer 700, so as to achieve insulation between the second conductive layer 500 and the third conductive layer 700 at the location of the second insulating layer 800, and reduce the risk of short circuit between the second conductive layer 500 and the third conductive layer 700.

[0124] In some optional embodiments, the thickness of the second insulating layer 800 is 10 μm to 100 μm. For example, the thickness of the second insulating layer 800 is 10 μm, 20 μm, 80 μm, 100 μm, etc.

[0125] In these optional embodiments, the thickness of the second insulating layer 800 is greater than or equal to 10 μm. This can improve the problem that if the thickness of the second insulating layer 800 is too small, it will be difficult for the second insulating layer 800 to cover and protect the third conductive layer 700, resulting in the third conductive layer 700 being exposed and increasing the risk of short circuits. Conversely, if the thickness of the second insulating layer 800 is less than or equal to 100 μm, this can improve the problem that if the thickness of the second insulating layer 800 is too large, the via depth will be too deep, making it difficult to guarantee the via process accuracy and increasing the difficulty of drilling.

[0126] Optionally, the thickness of the second insulating layer 800 is 20μm to 80μm. Within this range, the thickness of the second insulating layer 800 can ensure the insulating protection effect on the third conductive layer 700 and the good process accuracy of the vias.

[0127] Optionally, the second insulating layer 800 and the first insulating layer 400 are made of the same material and can be prepared using the same process, simplifying the preparation process of the encapsulation substrate 10.

[0128] Optionally, the material of the third conductive layer 700 includes metallic materials, such as copper and titanium. Metallic materials have good electrical conductivity.

[0129] In some alternative embodiments, the third conductive layer 700 and the first conductive layer 300 are made of the same material, and / or the third conductive layer 700 and the second conductive layer 500 are made of the same material.

[0130] In these optional embodiments, the third conductive layer 700 and the first conductive layer 300 are made of the same material, or the third conductive layer 700 and the second conductive layer 500 are made of the same material, or the third conductive layer 700, the second conductive layer 500 and the first conductive layer 300 are made of the same material. The third conductive layer 700 and the first conductive layer 300 can be prepared using the same process, or the third conductive layer 700 and the second conductive layer 500 can be prepared using the same process, or the third conductive layer 700, the second conductive layer 500 and the first conductive layer 300 can be prepared using the same process, simplifying the preparation process. The first conductive layer 300 and the third conductive layer 700 have the same film structure, or the third conductive layer 700 also has a multilayer structure similar to the first functional layer 311 and the second functional layer 312 described above.

[0131] Optionally, the third conductive layer 700 includes a plurality of spaced third conductive portions 710, with the first conductive portion 310 and the third conductive portion 710 being electrically connected to each other, and the third conductive portion 710 and the second conductive portion 510 being electrically connected to each other.

[0132] Optionally, a plurality of first vias 410 are formed on the first insulating layer 400, and the first conductive part 310 and the second conductive layer 500 are electrically connected through the first vias 410. Optionally, a plurality of second vias 810 are formed on the second insulating layer 800, and the third conductive part 710 and the second conductive part 510 are electrically connected through the second vias 810.

[0133] Optionally, the m-layer conductive layer has the same material and film structure.

[0134] In some alternative embodiments, the material of the first insulating layer 400 includes organic materials, such as bismaleimide-triazine resin (BT), air bubble film (ABF), etc. Alternatively, the material of the first insulating layer 400 includes an inorganic / organic composite material.

[0135] In these alternative embodiments, the first insulating layer 400 of the organic material can be made to have a large thickness, thereby covering the first conductive layer 300, so as to achieve insulation between the first conductive layer 300 and the third conductive layer 700 or between the first conductive layer 300 and the second conductive layer 500 at the location of the first insulating layer 400, thereby reducing the risk of short circuit between the first conductive layer 300 and the third conductive layer 700 or between the first conductive layer 300 and the second conductive layer 500.

[0136] Optionally, the material of the m-layer insulation layer includes organic materials, such as bismaleimide-triazine resin (BT) and air bubble film (ABF). Alternatively, the material of the m-layer insulation layer may include inorganic / organic composite materials.

[0137] In some optional embodiments, the thickness of the first insulating layer 400 is 10 μm to 100 μm. For example, the thickness of the first insulating layer 400 is 10 μm, 20 μm, 80 μm, 100 μm, etc.

[0138] In these optional embodiments, the thickness of the first insulating layer 400 is greater than or equal to 10 μm, which can improve the problem that if the thickness of the first insulating layer 400 is too small, it is difficult for the first insulating layer 400 to cover and protect the first conductive layer 300, resulting in the first conductive layer 300 being exposed and increasing the risk of short circuit. The thickness of the first insulating layer 400 is less than or equal to 100 μm, which can improve the problem that if the thickness of the first insulating layer 400 is too large, the via depth will be too deep, making it difficult to guarantee the via process accuracy and increasing the difficulty of drilling.

[0139] Optionally, the thickness of the first insulating layer 400 is 20μm to 80μm. Within this range, the thickness of the first insulating layer 400 can ensure the insulating protection effect of the first conductive layer 300 and the good process accuracy of the vias.

[0140] Optionally, the conductive pad 900 may be made of a metallic material. Optionally, the conductive pad 900 may include a micro-copper pillar structure. Optionally, the conductive pad 900 may include a multilayer composite metal layer, such as a Ni / Pd / Au three-layer composite metal layer.

[0141] Optionally, the thickness of the first conductive layer 300 is less than the thickness of the second conductive layer 500. The second conductive layer 500 has a greater thickness, resulting in lower resistance, specifically lower resistance in the conductive layer closer to the chip, thus improving the chip's signal transmission performance. For example, the thickness of the Cu layer in the second conductive layer 500 is greater than the thickness of the Cu layer in the first conductive layer 300.

[0142] Optionally, the thickness of the second conductive layer 500 is less than the thickness of the third conductive layer 700. The third conductive layer 700 has a larger thickness, resulting in lower resistance, specifically lower resistance in the conductive layer closer to the chip, thus improving the chip's signal transmission performance. For example, the thickness of the Cu layer in the third conductive layer 700 is greater than the thickness of the Cu layer in the second conductive layer 500.

[0143] Optionally, the thickness of the m-th conductive layer is greater than the thickness of the (m-1)-th conductive layer. The conductive layer closer to the chip has lower resistance, thus improving the signal transmission performance of the chip. For example, the thickness of the Cu layer in the m-th conductive layer is greater than the thickness of the Cu layer in the (m-1)-th conductive layer.

[0144] Please refer to the following: Figures 6 to 15 , Figures 6 to 15 This is a process diagram of the preparation of a packaging substrate provided in an embodiment of this application.

[0145] like Figures 6 to 15 As shown, this application also provides a method for preparing a packaging carrier 10, comprising: Provide a support substrate 100; A flexible layer 200, a first conductive layer 300, a first insulating layer 400, a second conductive layer 500, a solder resist layer 600, and a conductive pad 900 are sequentially prepared on one side of the support substrate 100. The hardness of the flexible layer 200 is less than that of the support substrate 100. The second conductive layer 500 and the first conductive layer 300 are electrically connected, and the conductive pad 900 and the second conductive layer 500 are electrically connected.

[0146] The present application describes a method for fabricating a packaging substrate 10. The packaging substrate 10 includes a supporting substrate 100, a flexible layer 200, a first conductive layer 300, a first insulating layer 400, a second conductive layer 500, a solder resist layer 600, and conductive pads 900. The flexible layer 200 of the packaging substrate 10 serves as the bottom layer of the subsequent chip packaging structure, achieving insulation between the first conductive layer 300 and other film layers on the side of the flexible layer 200 away from the first conductive layer 300, reducing the risk of short circuits between the first conductive layer 300 and other film layers. Furthermore, the flexible layer 200 replaces the temporary bonding layer in related technologies, omitting temporary bonding materials and their processing steps, thus reducing costs. The first conductive layer 300 and the second conductive layer 500 serve as wiring layers of the packaging substrate 10, increasing the wiring space and the number of wirings in the packaging substrate 10, and improving the wiring density difference problem of coreless substrates. The conductive pads 900 are used for soldering with chips to fix the chips to the packaging substrate 10, forming a chip packaging structure. The first insulating layer 400 insulates the first conductive layer 300 and the second conductive layer 500, reducing the risk of short circuits between the first conductive layer 300 and the second conductive layer 500. A support substrate 100 with high rigidity is used to support the flexible layer 200, ensuring the rigidity and dimensional stability of the coreless carrier board during chip bonding, thereby improving chip bonding accuracy and yield.

[0147] Optionally, the preparation method further includes: An adhesion layer 210 is prepared between the flexible layer 200 and the first conductive layer 300.

[0148] Optionally, the flexible layer 200 can be prepared by: A polyimide film is coated on one side of the support substrate 100 to form a flexible layer 200.

[0149] Optionally, the preparation method of the first conductive layer 300 includes: A titanium metal layer and a copper metal layer are sequentially deposited on the side of the flexible layer 200 away from the support substrate 100. Photoresist is applied to the side of the copper metal layer away from the support substrate 100, and the photoresist is patterned to form multiple first openings. A copper metal layer is electroplated inside the first opening, and the photoresist is removed; Using the electroplated copper metal layer as an etching mask, the deposited titanium metal layer and copper metal layer are etched to form multiple first conductive parts 310.

[0150] Optionally, the preparation method of the solder mask layer 600 includes: An organic film is pressed onto the side of the first conductive layer 300 away from the support substrate 100 by a hot pressing method to form the first insulating layer 400. An opening is made in the first insulating layer 400 to form a plurality of first vias 410, and a plurality of first conductive portions 310 are exposed through the plurality of first vias 410.

[0151] Optionally, the preparation method of the first conductive layer 300 includes: A titanium metal layer and a copper metal layer are sequentially deposited on the side of the first insulating layer 400 away from the support substrate 100. Photoresist is applied to the side of the copper metal layer away from the support substrate 100, and the photoresist is patterned to form multiple second openings. A copper metal layer is electroplated inside the second opening, and the photoresist is removed; Using the electroplated copper metal layer as an etching mask, the deposited titanium metal layer and copper metal layer are etched to form multiple second conductive parts 510.

[0152] Optionally, the preparation method of the solder mask layer 600 includes: A polyimide film is coated on the side of the second conductive layer 500 away from the support substrate 100 to form a solder resist layer 600. A hole is made in the solder mask layer 600 to form a plurality of pad vias 610, and a plurality of second conductive parts 510 are exposed through the plurality of pad vias 610.

[0153] Optionally, a dry etching process can be used to create openings in the solder mask layer 600 to form multiple vias 610. For example, laser etching can be used to create openings in the solder mask layer 600. The dry etching process offers high precision and is simple to implement.

[0154] Please refer to the following: Figures 1 to 19 , Figure 16 This is a flowchart illustrating the use of a packaging carrier provided in an embodiment of this application; Figures 17 to 19 This is a diagram illustrating the usage process of a packaging carrier provided in an embodiment of this application.

[0155] like Figures 1 to 19 As shown in the embodiments of this application, a method for fabricating a chip packaging structure is also provided, including: Step S01: Fix the chip 20 to the conductive pad 900 of the packaging substrate 10; Step S02: Prepare a sealing layer 21 on the side of the chip 20 away from the packaging substrate 10, with the chip 20 positioned within the orthogonal projection of the sealing layer 21 onto the substrate when projected onto the packaging substrate 10. Step S03: Remove the support substrate 100; Step S04: Pattern the flexible layer 200 to expose the first conductive layer 300; Step S05: Prepare conductive pins 22 on the side of the flexible layer 200 opposite to the first conductive layer 300, and electrically connect the conductive pins 22 to the first conductive layer 300.

[0156] According to the method of using the packaging substrate 10 in this application embodiment, in step S01, the chip 20 is fixedly connected to the conductive pad 900, for example, the chip 20 is aligned, bonded, and soldered onto the packaging substrate 10. Then, in step S02, a sealing layer 21 is prepared to reliably seal the chip 20 and the packaging substrate 10. In step S03, the support substrate 100 is peeled off, separating the support substrate 100 from the flexible layer 200, for example, by using a laser lift-off process. In step S04, the flexible layer 200 is patterned, for example, by using a laser etching process to create openings in the flexible layer 200 to expose the first conductive layer 300. In step S05, conductive pins 22 are prepared, and conductive silver paste is electrically connected to the first conductive layer 300, for example, by using chemical plating to prepare the conductive pins 22. Through the above steps, the chip 20 and the packaging substrate 10 are soldered and sealed, realizing the application of the packaging substrate 10. The conductive pin 22 can be used for subsequent connection to a printed circuit board (PCB) in electronic devices.

[0157] Optionally, before step S02, the method further includes: Encapsulating adhesive 23 is filled between chip 20 and packaging substrate 10.

[0158] In these optional embodiments, the encapsulating adhesive 23 serves two purposes: supporting the chip 20 and improving the seal between the chip 20 and the encapsulation substrate 10. Optionally, the encapsulating adhesive 23 includes an organic adhesive.

[0159] Optionally, step S02 includes: A sealing material is cast on the side of the chip 20 away from the packaging substrate 10, and the sealing material is cross-linked to form a sealing layer 21.

[0160] Optionally, the material of the sealing layer 21 may include molding compound.

[0161] Optionally, after step S04, the method further includes: An etching process is used to etch and create openings in the adhesion layer 210.

[0162] Optionally, the adhesion layer 210 can be dry-etched or wet-etched.

[0163] Optionally, the material of the conductive pin 22 may include a metallic material. Optionally, the conductive pin 22 may include copper. Optionally, the conductive pin 22 may include a multilayer composite metal layer, such as a Ni / Pd / Au three-layer composite metal layer, or a Pd / Au two-layer composite metal layer.

[0164] Optionally, a dry etching process can be used to create openings in the flexible layer 200 to expose the first conductive layer 300. For example, laser etching can be used to create openings in the flexible layer 200. The dry etching process has high precision and is simple. It can overcome the problem that the temporary bonding materials used in the existing flexible layer 200 are difficult to dry etch, requiring the temporary bonding materials to be dissolved and then an attached film layer to be etched to expose the first conductive layer 300, which is a complex and costly solution.

[0165] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0166] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

[0167] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A packaging carrier board, characterized in that, include: Support substrate; A flexible layer is located on one side of the supporting substrate, and the elastic modulus of the flexible layer is less than that of the supporting substrate; An m-th conductive layer and an m-1-th insulating layer are sequentially stacked on the side of the flexible layer away from the supporting substrate. The m-th conductive layer includes a first conductive layer and an m-th conductive layer, with the m-th conductive layer located on the side of the first conductive layer away from the supporting substrate. The m-1-th insulating layer includes an m-1-th insulating layer, with the m-th conductive layer located on the side of the m-1-th insulating layer away from the supporting substrate. Each conductive layer includes at least one signal trace, where m is an integer greater than or equal to 2. A solder resist layer is located on the side of the m-th conductive layer that is away from the supporting substrate; Multiple conductive pads are located on the side of the solder resist layer away from the supporting substrate. The conductive pads are electrically connected to the m-th conductive layer. The heat distortion temperature of the solder resist layer is greater than or equal to 350°C.

2. The packaging carrier board according to claim 1, characterized in that, The coefficient of thermal expansion of the solder resist layer is less than 10 ppm; Preferably, the coefficient of thermal expansion of the solder resist layer is 3ppm to 8ppm; Preferably, the material of the conductive layer includes a metallic material; Preferably, the material of the insulating layer includes organic and / or inorganic materials.

3. The packaging carrier board according to claim 1, characterized in that, The flexible layer is made of organic materials; Preferably, the material of the flexible layer includes polyimide; Preferably, the thickness of the flexible layer is 2μm to 20μm; Preferably, the coefficient of thermal expansion of the flexible layer is 3ppm to 20ppm; Preferably, the material of the support substrate includes glass.

4. The packaging carrier board according to claim 1, characterized in that, The material of the solder resist layer includes organic materials; Preferably, the material of the solder resist layer includes polyimide; Preferably, the solder resist layer and the flexible layer are made of the same material.

5. The packaging carrier board according to claim 1, characterized in that, Also includes: An adhesion layer is located between the flexible layer and the first conductive layer; Preferably, the material of the adhesive layer includes inorganic materials; Preferably, the material of the adhesion layer includes at least one of silicon oxide or silicon nitride; Preferably, the thickness of the adhesive layer is less than the thickness of the flexible layer.

6. The packaging carrier board according to claim 1, characterized in that, The m-layer conductive layer includes a second conductive layer, and the m-1-layer insulating layer includes a first insulating layer. The first insulating layer is located between the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer are electrically connected. Preferably, the first conductive layer includes a plurality of spaced first conductive portions, and the second conductive layer includes a plurality of spaced second conductive portions, wherein the first conductive portions and the second conductive portions are electrically connected to each other. Preferably, the material of the first insulating layer includes organic materials and / or inorganic materials; Preferably, the thickness of the first insulating layer is 10μm to 100μm.

7. The packaging carrier board according to claim 6, characterized in that, The first conductive portion includes a first functional layer and a second functional layer stacked in a direction away from the supporting substrate, wherein the thickness of the first functional layer is less than the thickness of the second functional layer; Preferably, the thickness of the second functional layer is 2μm to 30μm; Preferably, the material of the first conductive layer includes a metallic material; Preferably, the material of the second conductive layer includes a metallic material; Preferably, the material of the first conductive layer and the material of the second conductive layer are the same.

8. The packaging carrier board according to claim 7, characterized in that, The first functional layer includes a first sub-layer and a second sub-layer stacked along a direction away from the supporting substrate, wherein the first sub-layer and the second sub-layer are made of different materials; Preferably, the material of the first sublayer includes titanium; Preferably, the material of the second sublayer includes copper; Preferably, the thickness of the first sublayer is 10nm~100nm; Preferably, the thickness of the second sublayer is 100nm~2000nm; Preferably, the thickness of the second sub-layer is greater than the thickness of the first sub-layer.

9. The packaging carrier board according to claim 6, characterized in that, The m-th conductive layer includes a third conductive layer, and the m-1-th insulating layer includes a second insulating layer. The second insulating layer is located between the second conductive layer and the third conductive layer. The second insulating layer is located on the side of the second conductive layer away from the supporting substrate. The third conductive layer and the second conductive layer are electrically connected. Preferably, the material of the second insulating layer includes organic materials and / or inorganic materials; Preferably, the thickness of the second insulating layer is 10 μm to 100 μm; Preferably, the second insulating layer and the first insulating layer are made of the same material; Preferably, the material of the third conductive layer includes a metallic material; Preferably, the third conductive layer is made of the same material as the first conductive layer, and / or the third conductive layer is made of the same material as the second conductive layer.

10. A method for fabricating a chip packaging structure, characterized in that, include: The chip is fixedly connected to the conductive pads of the packaging substrate according to any one of claims 1-9; An sealing layer is prepared on the side of the chip facing away from the packaging substrate, and the chip is positioned within the orthogonal projection of the sealing layer onto the substrate when projected onto the packaging substrate. Remove the supporting substrate; The flexible layer is patterned to expose the first conductive layer; A conductive pin is formed on the side of the flexible layer opposite to the first conductive layer, and the conductive pin is electrically connected to the first conductive layer.

Images