Rapid and highly compatible electrical module test system and test method thereof

Abstract

The invention relates to a rapid and high-compatibility electrical module test system and a test method thereof. The rapid and high-compatibility electrical module test system comprises a presentation layer, an application layer, a process layer and an equipment layer which are connected according to hierarchical logic. The presentation layer is a GUI display layer based on WPF and MaterialDesign, the application layer comprises a test control framework and a data processing module, the equipment layer comprises a DUT interface module, an instrument communication unit and a high-speed signal conditioning module, and the DUT interface module is a universal interface compatible with QSFP, CFP and SFP protocols. Therefore, the problems that an existing testing system is poor in compatibility and needs to replace hardware frequently due to multiple types of DUTs, multiple protocols and different cable lengths are effectively solved. The DUT interface module realizes rapid gating of different protocol pins by means of a relay matrix, and the instrument communication unit can automatically load a corresponding MSA protocol stack according to a DUT model. Meanwhile, according to the design, hardware does not need to be physically replaced or transformed, and mainstream current module models and test scenes can be covered.

Description

Technical Field

[0001] This invention relates to an electrical module testing system and method, and more particularly to a fast and highly compatible electrical module testing system and method. Background Technology

[0002] In the field of electrical module testing system architecture design, distributed architecture is an important direction for improving system versatility and scalability. Currently, common distributed testing system architectures are mainly designed for the testing domain, addressing the low efficiency and poor versatility of centralized testing systems by layering system functions, and providing a basic solution for standardized interaction of testing resources. However, this architecture design is not optimized for testing scenarios of communication electrical modules such as QSFP and SFP, does not integrate automatic adaptation modules for multiple protocols, and does not employ decoupling designs such as MVVM to achieve independent evolution of the interface and business logic. This results in significant adjustments to the core architecture logic when adding testing functions for communication electrical modules, leading to high maintenance costs.

[0003] An improved system exists that uses remote procedure calls to achieve data interaction between services, solving the problems of difficult batch device access and slow deployment in traditional ATE testing platforms. However, the core design of this system focuses on device access efficiency and does not consider the thread synchronization requirements when testing multiple DUTs in parallel. It lacks a timing coordination mechanism for multi-module interaction scenarios, making it impossible to avoid thread blocking or data conflicts, and thus failing to meet the requirements of high-precision interactive testing of communication modules.

[0004] In summary, while existing technologies have made progress in individual dimensions such as distributed architecture optimization, batch device access, and flexible impedance adjustment, they still suffer from shortcomings in meeting the testing requirements of strong compatibility, high parallelism, and low maintenance costs for multiple communication electrical modules such as QSFP and SFP. These shortcomings include insufficient multi-protocol adaptation capabilities, low multi-module synchronization accuracy, and poor coordination between signal conditioning and testing processes, making it difficult to meet the requirements of rapid and high-precision testing of electrical modules in fields such as industrial control and automotive electronics. In view of these shortcomings, the designers have actively researched and innovated to create a rapid and highly compatible electrical module testing system and its testing method, making it more valuable for industrial applications. Summary of the Invention

[0005] To address the aforementioned technical problems, the purpose of this invention is to provide a fast and highly compatible electrical module testing system and testing method.

[0006] This invention discloses a fast and highly compatible electrical module testing system, comprising a presentation layer, an application layer, a process layer, and a device layer logically connected in a hierarchical manner. The presentation layer is a GUI display layer based on WPF and Material Design, including a parameter configuration area, a status display area, and a report export area, used to receive user-inputted test parameters and commands, display test status, and output test reports. The application layer includes a test control framework and a data processing module. The test control framework includes a thread manager and a synchronization point controller. The data processing module includes a real-time acquisition unit, a summarization unit, and a log generator. The output of the real-time acquisition unit is connected to the input of the summarization unit via a data cache channel. The bidirectional ports of the summarization unit are connected to the log generator and the report export area of ​​the presentation layer, respectively. The real-time acquisition unit transmits the acquired raw test data to the summarization unit. The summarization unit classifies and processes the data and then synchronously sends it to the log generator for archiving and to the report export area to generate a test report. The process layer includes a Testplan parsing unit, a condition judgment module, and a test item executor. The Testplan... The output of the parsing unit is connected to the input of the test item executor; the input of the condition judgment module is connected to the output of the test item executor. The Testplan parsing unit is used to decompose the test plan and issue instructions to the test item executor. After the test item executor performs the test, it feeds back the results to the condition judgment module for threshold judgment. The device layer includes a DUT interface module, an instrument communication unit, and a high-speed signal conditioning module. The DUT interface module is a universal interface compatible with QSFP, CFP, and SFP protocols. The instrument communication unit is a controller conforming to the MCB / MSA standard. The input of the DUT interface module is connected to the output of the high-speed signal conditioning module, and the output of the DUT interface module is connected to the input of the instrument communication unit. The high-speed signal conditioning module conditions the signal and transmits it to the DUT interface module. The DUT interface module interacts with the DUT and transmits the data to the instrument communication unit for parsing and processing. The high-speed signal conditioning module is connected in series in a high-speed cable and includes a software-configured impedance matching resistor and a low-pass filter. The impedance matching resistor is 50Ω or 75Ω and can match high-speed cables of lengths of 0.5m, 1m, and 2m.

[0007] Furthermore, in the aforementioned fast and highly compatible electrical module testing system, the thread manager and the synchronization point controller are bidirectionally connected through a mapping table of thread IDs and synchronization flags; the thread manager sends thread status signals to the synchronization point controller, and the synchronization point controller feeds back synchronization control signals to the thread manager. The synchronization point controller is used to receive the ready signal sent by the thread, and send the continue signal after detecting that all threads participating in the interaction meet the synchronization conditions. The thread manager can allocate 2-4 independent threads, and each thread corresponds to one DUT interface module. The threads interact with each other through a lock-free queue. The input end of the lock-free queue is connected to the data output end of each thread, and the output end of the lock-free queue is connected to the data input end of the corresponding receiving thread.

[0008] Furthermore, in the aforementioned fast and highly compatible electrical module testing system, the real-time acquisition unit of the data processing module is connected to the signal output terminal of the DUT interface module via a high-speed ADC or protocol decoder. The real-time acquisition unit transmits the raw data to the aggregation unit through a data buffer channel. The aggregation unit categorizes the acquired data according to DUT number, test item, and result, and then synchronously transmits it to the log generator through a data transmission link. The log generator records log files containing command, response, and exception information through the log storage channel; the report export area obtains categorized data from the summary unit through the data call interface, and supports converting test data into test reports in Excel, PDF, and CSV formats. The data processing module also includes a data preprocessing unit. The input end of the data preprocessing unit is connected to the output end of the real-time acquisition unit, and the output end of the data preprocessing unit is connected to the input end of the aggregation unit. It is used to clean, convert the format, and fill in missing values ​​of the acquired raw data before transmitting it to the aggregation unit.

[0009] Furthermore, in the aforementioned fast and highly compatible electrical module testing system, the DUT interface module of the device layer and the instrument communication unit achieve bidirectional data transmission through a configurable protocol chip. The input terminal of the configurable protocol chip can receive interactive data from the DUT interface module, and the output terminal of the configurable protocol chip can send protocol control signals to the DUT interface module. The instrument communication unit can automatically load the corresponding protocol stack according to the DUT model. The protocol stack includes the CMIS protocol corresponding to QSFP and the SFF-8472 protocol corresponding to SFP. The DUT interface module integrates a relay matrix. The control terminal of the relay matrix is ​​connected to the output terminal of the instrument communication unit, and the signal terminal of the relay matrix is ​​connected to different protocol pins of the DUT interface module to realize fast switching of different protocol interfaces and signal path selection.

[0010] Furthermore, in the aforementioned fast and highly compatible electrical module testing system, the presentation layer and the application layer are connected bidirectionally via MVVM data binding. The parameter configuration signal of the presentation layer is transmitted to the application layer through the data binding channel, and the test status signal of the application layer is fed back to the presentation layer through the data binding channel. The application layer and the process layer interact with each other through API interfaces and shared memory. The application layer sends control commands to the process layer through API interfaces, and the process layer transmits test result data to the application layer through shared memory. The process layer and the device layer are logically connected through process control signals. Test commands from the process layer are transmitted to the device layer through a control signal link, and status feedback signals from the device layer are transmitted to the process layer through a control signal link. The device layer internally achieves physical and protocol connections through high-speed cables and MSA protocol bus. The high-speed cables are used to transmit conditioned signals, and the MSA protocol bus is used to transmit protocol interaction data. Data access to the shared memory is controlled for thread safety using a mutex to prevent data conflicts. The control terminal of the mutex is connected to the thread manager of the application layer, and the signal terminal of the mutex is connected to the access port of the shared memory.

[0011] Furthermore, the aforementioned fast and highly compatible electrical module testing system supports no-code extensions. When adding a new DUT model, the user inputs the corresponding protocol type, test item list, and judgment threshold through the presentation layer configuration interface. The input data is added to the database through the database interaction interface. The database is a relational database that stores DUT configuration information and historical test data. The configuration information storage table of the relational database is connected to the database query interface of the application layer, and the historical test data storage table is connected to the aggregation unit of the data processing module. The database is configured with a data index, which is connected to the database query port to optimize query efficiency.

[0012] Furthermore, in the aforementioned fast and highly compatible electrical module testing system, the historical test data includes the test timestamps, test results, exception records, and log file paths of each DUT. The historical test data is transmitted from the aggregation unit to the database through the data storage link. The system also includes a historical data comparison and analysis module. The input end of the historical data comparison and analysis module obtains the current test results and historical data of the same model DUT from the database through a data query interface. The output end of the module is connected to the status display area of ​​the presentation layer through a data display link, which can perform deviation calculation on the data and display trend analysis charts through the status display area.

[0013] A testing method based on the testing system of claim 1, comprising the following steps: Step 1: Test preparation. The user inputs the DUT model and Testplan selection command through the parameter configuration area of ​​the presentation layer. This command is transmitted to the application layer through the data binding channel. The application layer queries the database to obtain the protocol type, cable length and test item list corresponding to the DUT, generates a thread allocation scheme and transmits it to the thread manager; The instrument communication unit at the device layer loads the corresponding protocol stack, and the high-speed signal conditioning module adjusts the impedance matching resistor parameters according to the cable length. The adjustment signal is transmitted to the high-speed signal conditioning module through the control link. Step 2: Task decomposition. The Testplan parsing unit of the process layer obtains the test item list of the application layer through the data call interface, decomposes the test plan, generates step-by-step execution instructions, and sends them to the test item executor through the instruction transmission channel. Step 3: Parallel testing. The application layer's thread manager starts 2-4 independent threads and transmits control signals to each thread. The synchronization point controller receives the ready signals from each thread and sends a continue signal after detecting that the synchronization conditions are met. The real-time acquisition unit of the data processing module acquires the test data of the DUT interface module through a high-speed ADC or protocol decoder and transmits it to the aggregation unit through the data buffer channel. Step 4: Results Summary. After classifying and processing the collected data, the summary unit transmits the data to the log generator and the report export area of ​​the presentation layer via data links. The log generator generates log files, and the report export area outputs test reports.

[0014] Furthermore, in the above-mentioned test method based on the test system of claim 1, in the test preparation step, the impedance matching resistor of the high-speed signal conditioning module is configured to be 50Ω or 75Ω according to the length of the high-speed cable; when the length of the high-speed cable is 0.5m, 1m or 2m, the application layer controls the high-speed signal conditioning module through the parameter configuration signal to switch it to the corresponding preset impedance parameter. The test preparation steps also include DUT in-situ detection and initialization. The detection end of the DUT interface module collects the level signal and transmits it to the instrument communication unit. After the instrument communication unit judges the DUT connection status, it feeds back to the application layer. The application layer performs power-on initialization configuration of the DUT through the initialization signal.

[0015] Furthermore, in the above-mentioned test method based on the test system of claim 1, in the parallel test step, when the test item involves the interaction of multiple DUTs, after each thread executes to the synchronization step, it sends a ready signal to the synchronization point controller through the signal transmission channel. After the synchronization point controller confirms that all participating interaction threads are ready through the state detection link, it triggers the synchronous execution of each thread. If the real-time acquisition unit detects that the DUT parameters exceed the threshold, it sends an NG result to the aggregation unit through the abnormal signal channel. The aggregation unit then sends a pause signal to the thread manager. After the pause signal is triggered, the system automatically records and stores the corresponding information to the log generator through the log recording link. The corresponding information includes the timestamp of the abnormality, the thread identifier, and the parameter deviation value.

[0016] By means of the above-described solution, the present invention has at least the following advantages: 1. This design effectively solves the problems of poor compatibility and frequent hardware replacements caused by multiple DUT models, protocols, and cable lengths in existing testing systems. The DUT interface module uses a relay matrix to achieve rapid selection of pins for different protocols. The instrument communication unit can automatically load the corresponding MSA protocol stack according to the DUT model. The high-speed signal conditioning module configures the parameters of digital potentiometers and low-pass filters through software, adapting to high-speed cables of different lengths (0.5m / 1m / 2m). Furthermore, this design requires no physical replacement or modification of hardware, covering mainstream electrical module models and testing scenarios, significantly reducing hardware procurement and adjustment costs for multi-specification testing scenarios.

[0017] 2. To address the shortcomings of existing systems, such as low efficiency in serial testing and high data processing latency, this invention constructs a highly efficient testing mechanism that combines multi-threaded parallel scheduling with real-time data flow. On one hand, the application-layer thread manager can dynamically allocate 2-4 independent threads. Combined with a synchronization point control mechanism, and through a thread ID-synchronization flag mapping table and periodic checks, the timing consistency of multi-DUT interactive testing is ensured, avoiding thread blocking and data conflicts, and enabling parallel testing of multiple modules. On the other hand, the data processing layer acquires data in real time through a high-speed ADC and protocol decoder, reducing data flow latency.

[0018] 3. This solution addresses the issues of tight coupling in the existing system's software architecture and the need for large-scale code modifications for functional expansion. The presentation layer, based on the MVVM architecture, achieves complete decoupling between the user interface and business logic. Adjustments to the interface style or optimizations to the test status display logic do not require changes to the core control code. Both the test process and DUT configuration are database-driven. When adding a new DUT model, simply input the protocol type, test items, and thresholds in the presentation layer configuration interface and update the database. The system will automatically parse the configuration and generate the test logic without modifying the core code of the application layer or process layer.

[0019] 4. Regarding data accuracy, the data preprocessing unit can remove outliers and use linear interpolation to fill in missing data, avoiding the impact of acquisition errors on result judgment. Regarding test timing reliability, the synchronization point controller periodically checks the readiness status of participating interaction threads to ensure timing consistency in multi-DUT signal interaction tests, preventing test data mismatch caused by signal conflicts. Regarding problem tracing, each DUT has an independent log file that fully records test commands, response data, anomaly occurrence time, and parameter deviations. Combined with historical test data stored in the database and trend analysis functions, it enables full-link tracing from current test results back to historical data and from anomaly location to specific threads and test steps, providing reliable data support for test quality analysis and DUT performance optimization.

[0020] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the framework of a fast and highly compatible electrical module testing system. Detailed Implementation

[0022] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0023] like Figure 1This is a fast and highly compatible electrical module testing system, employing a four-layer, three-level interactive architecture. The four layers are the presentation layer, application layer, process layer, and device layer. The three-level interaction includes vertical data / control interaction between layers, horizontal collaboration within the same layer, and cross-layer protocol adaptation. The presentation layer serves as the interaction entry point between the system and the user. It is developed using the WPF (Windows Presentation Foundation) framework combined with the MVVM (Model-View-ViewModel) architecture, and integrates the MaterialDesignInXamlToolkit control library to achieve a modern interface style. It has a View (interface control) containing three functional areas: a parameter configuration area, a status display area, and a report export area. Specifically, the parameter configuration area provides a DUT model drop-down selection box (supporting pre-stored QSFP, CFP, SFP, and other models), a Testplan file upload button, cable length (0.5m / 1m / 2m) selection options, and a test start / pause button. Users input basic test parameters through this area. The status display area uses real-time progress bars to show the test progress of each DUT (one progress bar corresponds to one DUT), and uses colors to indicate the test status. For example, green: normal operation, red: abnormal pause, blue: waiting for synchronization. It can also support the display of historical data trend charts, such as the voltage test result curves of the last 10 DUTs of the same model. The report export area provides download buttons for Excel, PDF, and CSV reports, displays the current test report generation status such as "generating" or "completed", and supports direct opening of log files (.log format). A ViewModel (logic binding layer) is set up, implemented using the CommunityToolkit.Mvvm component, and achieves two-way binding between the interface and data through the INotifyPropertyChanged interface. The commands entered by the user in the parameter configuration area are automatically synchronized to the ViewModel, and the ViewModel is then transmitted to the application layer through the data binding channel. The test status feedback from the application layer is also updated in real time to the status display area through the ViewModel, avoiding direct coupling between the interface and business logic.

[0024] In a preferred embodiment of the present invention, the presentation layer and the application layer achieve a bidirectional logical connection through an MVVM data binding channel. Specifically, the ViewModel's attributes, such as SelectedDutModel (the currently selected DUT model) and TestStatus (the test status), are bound to the database interaction module and thread manager of the application layer's test control framework. When the user modifies SelectedDutModel, the binding signal triggers the application layer to query the database to obtain the protocol type and test item list corresponding to that model. When the application layer's thread manager updates TestStatus, the binding signal triggers the View to update the progress bar and color indicators in the status display area, ensuring an interaction delay of ≤100ms.

[0025] Further analysis reveals that the application layer comprises a test control framework layer and a data processing layer. It is responsible for parsing test configurations, scheduling threads, coordinating synchronization, and processing test data. Specifically, the test control framework layer has a thread manager that uses the C# Task class to implement multi-threaded management, supporting the dynamic allocation of 2-4 independent threads (one thread corresponds to one DUT interface module). The number of threads is automatically determined by the "DUT parallel test quantity configuration" obtained by the application layer from the database. For example, if the user configures "2 DUTs in parallel," then 2 threads are allocated. The thread manager assigns a unique ThreadID to each thread and stores it in a memory dictionary through a mapping table between the thread ID and a synchronization flag. The key is the ThreadID, and the value is the synchronization flag, establishing a bidirectional connection with the synchronization point controller. The thread manager writes the running status of each thread to the mapping table in real time, and the synchronization point controller reads the mapping table to determine whether the synchronization conditions are met. Furthermore, threads interact with each other through a lock-free queue (implemented based on ConcurrentQueue, thread-safe). For example, when Thread-DUT1 needs to send a "signal sending complete" notification to Thread-DUT2, it writes the notification data, including ThreadID, notification type, and timestamp, into a lock-free queue. Thread-DUT2 reads the data by polling the lock-free queue, avoiding resource contention and thread blocking caused by traditional locking mechanisms.

[0026] In the context of using the synchronization point controller, for multi-DUT interactive testing scenarios, the controller achieves thread synchronization through the following logic: When a thread executes a test step requiring synchronization, such as DUT2 completing signal sending preparation, it sends a "ready signal" to the synchronization point controller. This signal may contain a ThreadID and a synchronization point identifier. After receiving the ready signal, the synchronization point controller updates the synchronization flag of the corresponding ThreadID in the mapping table to "1" and checks whether the flags of all threads participating in the interaction under that synchronization point identifier are also "1". If all threads are ready, the synchronization point controller sends a "continue signal" (containing the synchronization point identifier) ​​to the thread manager, which then triggers the corresponding thread to continue executing subsequent test steps. If there are any unready threads, the synchronization point controller re-checks every 50ms until the conditions are met. A timeout of 10 seconds can be set; if the timeout occurs, an exception alarm is triggered.

[0027] In the database interaction module, the ADO.NET interface connects to a relational database to implement configuration reading and data writing functions. Specifically, during the test preparation phase, the module reads the protocol type corresponding to the DUT model (e.g., QSFP corresponds to CMIS protocol), cable length (e.g., 1m), test item list, and judgment thresholds. After the test is completed, the summarized test results, including the DUT number, test item results, and timestamps, are written to the historical test data table in the database.

[0028] In practical implementation, the data processing layer includes a real-time acquisition unit that acquires test data in two ways. For analog signals (such as the DUT's power supply voltage), a high-speed ADC is connected to the signal output of the DUT interface module to convert the analog signal into a digital signal. For digital protocol signals, a protocol decoder is used to parse the protocol data transmitted by the DUT interface module. This decoder supports the CMIS / SFF-8472 protocol via an FPGA-based protocol decoding board. The acquired data can include an acquisition timestamp, DUT number, data type, and raw values, and can be transmitted to the data preprocessing unit via a data buffer channel.

[0029] The data preprocessing unit used in this invention can preprocess the raw collected data, solving problems such as data noise, inconsistent formats, and missing data. It includes the following components: Data cleaning employs the 3σ criterion to remove outliers; for example, voltage readings exceeding the reasonable range of "0V-5V" are considered abnormal and removed. Format conversion converts the hexadecimal data output by the ADC to decimal physical quantities. Missing value imputation uses linear interpolation to fill in missing values ​​if a data point is missing (e.g., due to communication interruption). This interpolation is calculated based on two adjacent valid data points. The preprocessed data is then transmitted to the aggregation unit.

[0030] A summary unit is used to classify data according to a hierarchical structure of DUT number, test item, and results. The classification rules are defined by the "Test Item Classification Configuration Table" in the database. The summary unit transmits data through the following two links: A data transmission link, based on the TCP protocol, synchronously transmits the classified data to the log generator. A data retrieval interface, based on a RESTful API, provides data query services to the presentation layer report export area, supporting data filtering by DUT number and test time period. In addition, the summary unit also needs to determine whether the test results are qualified: it compares the classified data with the "judgment threshold" in the database and appends the judgment result to the classified data.

[0031] A log generator is used, employing the StreamWriter class to generate log files, stored in a system-specified directory. The log content includes: basic information (log generation timestamp, DUT number, test plan name); process information (each test command, DUT response, execution time); and exception information (exception timestamp, thread identifier, exception type, parameter deviation). The log files are encoded in UTF-8, supporting subsequent exception backtracking and problem analysis.

[0032] The report generation module integrates NPOI (Excel generation) and iTextSharp (PDF generation) components to generate test reports based on the categorized data provided by the summary unit. Specifically, the Excel report is divided into sheets by DUT number, with each sheet containing the test item name, collected values, threshold range, judgment result, and collection timestamp. The PDF report uses a standardized template and includes test system information, DUT information, a list of test items, result statistics (number of qualified items / total number of items, pass rate), and anomaly details. The CSV report uses comma-separated fields and supports importing third-party data analysis tools (such as MATLAB). After the report is generated, it is available for download through the presentation layer report export area, and the report storage path is simultaneously written to the database's "Report Index Table."

[0033] Furthermore, the process layer of this invention dynamically generates test processes based on database configuration, avoiding maintenance difficulties caused by hard coding. It includes the following components: a Testplan parsing unit, which reads the user-uploaded Testplan file through an XML parser, obtains the corresponding test item parameter configuration from the application layer via a data call interface, generates step-by-step execution instructions, and sends them to the test item executor via an instruction transmission channel. The test item executor, upon receiving the step-by-step execution instructions, executes the specific test items sequentially. It sends a 3V3 voltage acquisition start command to the instrument communication unit at the device layer via a process control signal link. After the instrument communication unit reports completion of the acquisition, it receives the test data and transmits it to the condition judgment module. The condition judgment module reads the judgment threshold for the test item from the database and judges the result transmitted by the test item executor. For example, if the 3V3 voltage test result is 3.32V, and the threshold is 3.135V-3.465V, it is judged as qualified, allowing execution of the next test. If the result is 3.0V, it is judged as NG. Then, a pause signal is sent to the application layer through the flow control signal link, triggering the system to pause the test of the DUT and record the exception.

[0034] During implementation, the DUT interface module used a general-purpose interface board, integrating physical interfaces compatible with QSFP, CFP, and SFP protocols. It can achieve the following functions: Protocol compatibility; integrated relay matrix; the control terminals of the relay matrix are connected to the output terminals (GPIO pins) of the instrument communication unit, and the signal terminals are connected to different protocol pins of the DUT interface module. When switching DUT protocols, the instrument communication unit sends control signals to drive the relay matrix to switch, selecting the signal path of the corresponding protocol, without requiring changes to the hardware interface. Data interaction; bidirectional data transmission is achieved through a configurable protocol chip and the instrument communication unit. The input terminal of the protocol chip receives data exchanged between the DUT interface module and the DUT, converts it according to the protocol, and transmits it to the instrument communication unit. The output terminal of the protocol chip receives protocol control signals sent by the instrument communication unit, converts them into signals recognizable by the DUT, and transmits them to the DUT.

[0035] The instrument communication unit used in this invention employs an embedded controller (such as NXP i.MX8M Plus) that conforms to the MCB (Module Control Board) and MSA (Multi-Source Protocol) standards. Specifically, it includes automatic protocol stack loading, automatically loading the corresponding protocol stack from a locally stored protocol stack library based on the DUT protocol type transmitted by the application layer (such as QSFP). For example, when the DUT is QSFP, the CMIS protocol stack is loaded to achieve CMIS protocol communication with the DUT. When the DUT is SFP, the SFF-8472 protocol stack is loaded, requiring no manual configuration. It also provides status feedback. The operating status of the DUT interface module is collected in real time and fed back to the application layer via a control signal link. For example, when the DUT is not in place, the instrument communication unit detects a low-level signal from the DUT interface module and feeds back the DUT's absence status to the application layer, triggering the display layer to show alarm information.

[0036] This invention employs a high-speed signal conditioning module connected in series in the high-speed cable between the DUT interface module and the test instrument, resolving signal delay, impedance mismatch, and noise interference issues caused by cables of varying lengths. It features an impedance matching resistor, which can be a digital potentiometer and supports software configuration to 50Ω or 75Ω. When the application layer detects a cable length of 0.5m / 1m, it sends a control signal to configure the impedance to 50Ω. For a cable length of 2m, it configures it to 75Ω. A low-pass filter is constructed using an RC low-pass filter circuit to filter out high-frequency noise in the high-speed signal, ensuring a signal-to-noise ratio ≥40dB for the signal transmitted to the DUT. The parameter configuration of the high-speed signal conditioning module (impedance value, filter cutoff frequency) is sent by the application layer through the control link, eliminating the need for manual hardware adjustments.

[0037] During use, data interaction with shared memory is achieved through an API interface. The application layer can issue control commands such as starting and pausing tests to the process layer via the RESTful API. The process layer writes the execution results of test items to shared memory, and the application layer retrieves the results by reading from shared memory. To prevent data conflicts, thread-safe control of data access to shared memory is achieved through mutex locks. The mutex lock controller is connected to the application layer's thread manager. When a thread needs to access shared memory, it first requests the mutex lock, acquires the lock, and then reads or writes data. After reading or writing is completed, the lock is released, preventing data corruption caused by multiple threads accessing the shared memory simultaneously.

[0038] Simultaneously, logical connections can be achieved through process control signal links. A high-level signal can be sent from the test item actuator at the process layer to the instrument communication unit at the device layer, triggering the test instrument to start. The instrument communication unit at the device layer feeds back a low-level signal to the process layer, indicating test completion and ensuring the timing consistency of process execution. High-speed shielded cables are used to transmit conditioned high-speed signals, with the outer layer of the cable wrapped in aluminum foil shielding to reduce external electromagnetic interference. Furthermore, protocol interaction data is transmitted via the MSA protocol bus (based on the I2C / SPI protocol). For example, protocol control signals and status feedback data between the DUT interface module and the instrument communication unit are all transmitted via the MSA protocol bus, ensuring compatible transmission of multi-protocol data.

[0039] Based on the above system architecture, the specific implementation steps of the test method of the present invention are as follows, taking "parallel testing of 2 QSFP type DUTs with a cable length of 1m" as an example.

[0040] Step 1: Test Preparation.

[0041] User configuration input: The user selects the DUT model as "QSFP-400G", the Testplan file as "QSFP_Testplan.xml", and the cable length as "1m" in the presentation layer parameter configuration area, and clicks the "Start Test" button - this instruction is transmitted to the application layer ViewModel through the MVVM data binding channel.

[0042] Application layer configuration parsing: The application layer database interaction module queries the relational database to obtain the configuration information corresponding to the DUT: protocol type is "CMIS", number of parallel tests is "2", test item list is T001 (3V3 voltage test, threshold 3.135V-3.465V), T002 (communication rate test, threshold ≥400Gbps), and the impedance parameter corresponding to the 1m cable is 50Ω. The application layer generates a thread allocation scheme, which can form 2 threads, Thread-DUT1 and Thread-DUT2, and transmits them to the thread manager.

[0043] Device layer initialization: The device communication unit, according to the "CMIS protocol" configuration, automatically loads the CMIS protocol stack and sends the "protocol initialization" command to the DUT interface module through the MSA protocol bus.

[0044] High-speed signal conditioning module: The application layer sends parameter configuration signals through the control link to set the impedance matching resistor to 50Ω and the low-pass filter cutoff frequency to 1GHz.

[0045] DUT In-Situ Detection: The detection end of the DUT interface module acquires the DUT's in-situ level signal and transmits it to the instrument communication unit. The instrument communication unit sends a "DUT in-situ normal" signal back to the application layer, and the application layer sends a "Power-on Initialization" signal to the DUT interface module to complete the DUT's power-on initialization.

[0046] Step 2: Task breakdown.

[0047] The Testplan parsing unit in the process layer obtains the test item list, such as T001 and T002, from the application layer through a data call interface. Then, it reads the Testplan file, parses the test order, executes T001 first, and then executes T002 if it passes, generating step-by-step execution instructions. During this period, T001 (3V3 voltage test) is executed simultaneously by Thread-DUT1 / Thread-DUT2 for 5 seconds. Subsequently, if the previous processing is successful, Thread-DUT1 / Thread-DUT2 executes T002 (communication rate test), with Thread-DUT2 sending a test signal first and Thread-DUT1 receiving the signal. The step-by-step execution instructions are sent to the test item executor via shared memory.

[0048] Step 3: Parallel testing.

[0049] The application-layer thread manager starts Thread-DUT1 and Thread-DUT2, triggering both threads to execute the T001 test simultaneously via thread control signals. Then, the test executor sends a "Start 3V3 Voltage Acquisition" command to the device layer, and a high-speed ADC acquires the supply voltage of DUT1 / DUT2. After cleaning and format conversion by the data preprocessing unit, the data is transmitted to the aggregation unit. Next, the aggregation unit compares the data against a threshold to determine if T001 is qualified, and feeds back to the process layer, which triggers subsequent multi-DUT interactive tests. The multi-DUT interactive test process is as follows: Thread-DUT2 executes the "Send Test Signal" step, and after completion, sends a ready signal to the synchronization point controller. Thread-DUT1 executes to the "Wait to Receive Signal" step, sending a ready signal to the synchronization point controller. The synchronization point controller detects that both thread flags under Sync-Point-001 are 1 and sends a "Continue Signal" to the thread manager. Then, Thread-DUT2 sends a 400Gbps test signal, Thread-DUT1 receives the signal, the protocol decoder acquires the communication rate data, and transmits it to the aggregation unit.

[0050] If an anomaly occurs, it can be handled as follows: If the real-time acquisition unit detects a communication rate of 390Gbps for DUT1, which is lower than the threshold of 400Gbps, an NG result is sent to the aggregation unit through the anomaly signal channel. The aggregation unit sends a pause signal to the thread manager, suspending the Thread-DUT1 test. The system automatically records the anomaly information to the log generator through the log recording link.

[0051] Step 4: Results Summarization. The previous test data is categorized using the summarization unit. Simultaneously, the categorized data is transmitted to the log generator via the data transmission link through the summarization unit, generating log files. Afterwards, the presentation layer report export area retrieves the categorized data from the summarization unit through the data call interface, generating test reports in Excel / PDF / CSV format. Users can click the "Download PDF" button to obtain the report, and the summarization unit simultaneously writes the test results to the "Historical Test Data Table" in the database.

[0052] During implementation, historical data comparison and analysis were conducted using a historical data comparison and analysis module. After testing, the module retrieved the current DUT's test results and the historical test results of the last 10 DUTs of the same model from the "Historical Test Data Table" database via a data query interface. The module could then calculate the deviation between the current and historical results and generate trend analysis charts. The historical data comparison and analysis module transmitted the deviation values ​​and trend charts to the presentation layer status display area via a data display link, allowing users to intuitively view the stability of the current test results.

[0053] Furthermore, the orientations or positional relationships described in this invention are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the purpose of facilitating the description of this invention and simplifying the description, and are not intended to indicate or imply that the device or structure referred to must have a specific orientation, or to operate in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A fast and highly compatible electrical module testing system, characterized in that: This includes the presentation layer, application layer, process layer, and device layer, which are logically connected in a hierarchical manner. The presentation layer is a GUI display layer based on WPF and Material Design, which includes a parameter configuration area, a status display area, and a report export area. It is used to receive test parameters and instructions input by the user, and to display the test status and output test reports. The application layer includes a test control framework and a data processing module. The test control framework includes a thread manager and a synchronization point controller. The data processing module includes a real-time acquisition unit, a summarization unit, and a log generator. The output of the real-time acquisition unit and the input of the summarization unit are connected through a data cache channel. The bidirectional ports of the summarization unit are connected to the log generator and the report export area of ​​the presentation layer, respectively. The real-time acquisition unit is used to transmit the acquired raw test data to the aggregation unit. After classifying and processing the data, the aggregation unit synchronously sends it to the log generator for archiving and to the report export area to generate a test report. The process layer includes a Testplan parsing unit, a condition judgment module, and a test item executor. The output of the Testplan parsing unit is connected to the input of the test item executor; the input of the condition judgment module is connected to the output of the test item executor. The Testplan parsing unit is used to decompose the test plan and issue instructions to the test item executor. After the test item executor executes the test, it feeds back the results to the condition judgment module for threshold judgment. The device layer includes a DUT interface module, an instrument communication unit, and a high-speed signal conditioning module. The DUT interface module is a universal interface compatible with QSFP, CFP, and SFP protocols. The instrument communication unit is a controller conforming to the MCB / MSA standard. The input terminal of the DUT interface module is connected to the output terminal of the high-speed signal conditioning module, and the output terminal of the DUT interface module is connected to the input terminal of the instrument communication unit. The high-speed signal conditioning module conditions the signal and transmits it to the DUT interface module. The DUT interface module interacts with the DUT and transmits the data to the instrument communication unit for parsing and processing. The high-speed signal conditioning module is connected in series in a high-speed cable and includes a software-configurable impedance matching resistor and a low-pass filter. The impedance matching resistor is 50Ω or 75Ω and can match high-speed cables of lengths of 0.5m, 1m, and 2m.

2. The fast and highly compatible electrical module testing system according to claim 1, characterized in that: The thread manager and the synchronization point controller are bidirectionally connected through a mapping table of thread IDs and synchronization flags; the thread manager sends thread status signals to the synchronization point controller, and the synchronization point controller sends synchronization control signals back to the thread manager. The synchronization point controller is used to receive the ready signal sent by the thread, and send the continue signal after detecting that all threads participating in the interaction meet the synchronization conditions. The thread manager can allocate 2-4 independent threads, and each thread corresponds to one DUT interface module. The threads interact with each other through a lock-free queue. The input end of the lock-free queue is connected to the data output end of each thread, and the output end of the lock-free queue is connected to the data input end of the corresponding receiving thread.

3. The fast and highly compatible electrical module testing system according to claim 1, characterized in that: The real-time acquisition unit of the data processing module is connected to the signal output terminal of the DUT interface module through a high-speed ADC or protocol decoder. The real-time acquisition unit transmits the raw data to the aggregation unit through the data buffer channel. The aggregation unit classifies the acquired data according to the DUT number, test item, and result, and then transmits it synchronously to the log generator through the data transmission link. The log generator records log files containing command, response, and exception information through the log storage channel; the report export area obtains categorized data from the summary unit through the data call interface, and supports converting test data into test reports in Excel, PDF, and CSV formats. The data processing module also includes a data preprocessing unit. The input end of the data preprocessing unit is connected to the output end of the real-time acquisition unit, and the output end of the data preprocessing unit is connected to the input end of the aggregation unit. It is used to clean, convert the format, and fill in missing values ​​of the acquired raw data before transmitting it to the aggregation unit.

4. The fast and highly compatible electrical module testing system according to claim 1, characterized in that: The DUT interface module of the device layer and the instrument communication unit realize bidirectional data transmission through a configurable protocol chip. The input end of the configurable protocol chip can receive interactive data from the DUT interface module, and the output end of the configurable protocol chip can send protocol control signals to the DUT interface module. The instrument communication unit can automatically load the corresponding protocol stack according to the DUT model. The protocol stack includes the CMIS protocol corresponding to QSFP and the SFF-8472 protocol corresponding to SFP. The DUT interface module integrates a relay matrix. The control terminal of the relay matrix is ​​connected to the output terminal of the instrument communication unit, and the signal terminal of the relay matrix is ​​connected to different protocol pins of the DUT interface module to realize fast switching of different protocol interfaces and signal path selection.

5. The fast and highly compatible electrical module testing system according to claim 1, characterized in that: The presentation layer and the application layer are connected bidirectionally through MVVM data binding. The parameter configuration signals of the presentation layer are transmitted to the application layer through the data binding channel, and the test status signals of the application layer are fed back to the presentation layer through the data binding channel. The application layer and the process layer interact with each other through API interfaces and shared memory. The application layer sends control commands to the process layer through API interfaces, and the process layer transmits test result data to the application layer through shared memory. The process layer and the device layer are logically connected through process control signals. Test commands from the process layer are transmitted to the device layer through a control signal link, and status feedback signals from the device layer are transmitted to the process layer through a control signal link. The device layer internally achieves physical and protocol connections through high-speed cables and MSA protocol bus. The high-speed cables are used to transmit conditioned signals, and the MSA protocol bus is used to transmit protocol interaction data. Data access to the shared memory is controlled for thread safety using a mutex to prevent data conflicts. The control terminal of the mutex is connected to the thread manager of the application layer, and the signal terminal of the mutex is connected to the access port of the shared memory.

6. The fast and highly compatible electrical module testing system according to claim 1, characterized in that: The system supports no-code extensions. When adding a new DUT model, the user inputs the corresponding protocol type, test item list, and judgment threshold through the presentation layer configuration interface. The input data is added to the database through the database interaction interface. The database is a relational database that stores DUT configuration information and historical test data. The configuration information storage table of the relational database is connected to the database query interface of the application layer, and the historical test data storage table is connected to the aggregation unit of the data processing module. The database is configured with data indexes, which are connected to the database query port to optimize query efficiency.

7. The fast and highly compatible electrical module testing system according to claim 6, characterized in that: The historical test data includes the test timestamps, test results, exception records, and log file paths for each DUT. The historical test data is transmitted from the aggregation unit to the database through the data storage link. The system also includes a historical data comparison and analysis module. The input end of the historical data comparison and analysis module obtains the current test results and historical data of the same model DUT from the database through a data query interface. The output end of the module is connected to the status display area of ​​the presentation layer through a data display link, which can perform deviation calculation on the data and display trend analysis charts through the status display area.

8. A testing method based on the testing system of claim 1, characterized in that... Includes the following steps: Step 1: Test preparation. The user inputs the DUT model and Testplan selection command through the parameter configuration area of ​​the presentation layer. This command is transmitted to the application layer through the data binding channel. The application layer queries the database to obtain the protocol type, cable length and test item list corresponding to the DUT, generates a thread allocation scheme and transmits it to the thread manager; The instrument communication unit at the device layer loads the corresponding protocol stack, and the high-speed signal conditioning module adjusts the impedance matching resistor parameters according to the cable length. The adjustment signal is transmitted to the high-speed signal conditioning module through the control link. Step 2: Task decomposition. The Testplan parsing unit of the process layer obtains the test item list of the application layer through the data call interface, decomposes the test plan, generates step-by-step execution instructions, and sends them to the test item executor through the instruction transmission channel. Step 3: Parallel testing. The application layer's thread manager starts 2-4 independent threads and transmits control signals to each thread. The synchronization point controller receives the ready signals from each thread and sends a continue signal after detecting that the synchronization conditions are met. The real-time acquisition unit of the data processing module acquires the test data of the DUT interface module through a high-speed ADC or protocol decoder and transmits it to the aggregation unit through the data buffer channel. Step 4: Results Summary. After classifying and processing the collected data, the summary unit transmits the data to the log generator and the report export area of ​​the presentation layer via data links. The log generator produces log files, and the report export area outputs test reports.

9. A testing method based on the testing system of claim 8, characterized in that: In the test preparation steps, the impedance matching resistor of the high-speed signal conditioning module is configured to be 50Ω or 75Ω according to the length of the high-speed cable. When the length of the high-speed cable is 0.5m, 1m or 2m, the application layer controls the high-speed signal conditioning module through the parameter configuration signal to switch it to the corresponding preset impedance parameter. The test preparation steps also include DUT in-situ detection and initialization. The detection end of the DUT interface module collects the level signal and transmits it to the instrument communication unit. After the instrument communication unit judges the DUT connection status, it feeds back to the application layer. The application layer performs power-on initialization configuration of the DUT through the initialization signal.

10. A testing method based on the testing system of claim 8, characterized in that: In the parallel testing steps, when the test item involves interaction between multiple DUTs, after each thread executes to the synchronization step, it sends a ready signal to the synchronization point controller through the signal transmission channel. After the synchronization point controller confirms that all participating interaction threads are ready through the state detection link, it triggers the synchronous execution of each thread. If the real-time acquisition unit detects that the DUT parameters exceed the threshold, it sends an NG result to the aggregation unit through the abnormal signal channel. The aggregation unit then sends a pause signal to the thread manager. After the pause signal is triggered, the system automatically records and stores the corresponding information to the log generator through the log recording link. The corresponding information includes the timestamp of the abnormality, the thread identifier, and the parameter deviation value.

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