Bridge

Abstract

A bridge includes a plurality of interfaces including four interfaces and a photonic network. Each interface is an electrical interface configured to electrically connect a respective die to the bridge, each interface including a serializer and a deserializer for connecting to any die of the bridge through the interface. The photonic network comprises a directional photonic link from a serializer of each of the four interfaces to a deserializer of each of the remaining three interfaces, whereby the photonic network and the interfaces provide six bidirectional photonic communication paths terminating at the four interfaces, and each of the four interfaces is bidirectionally coupled to each of the other interfaces of the four interfaces.

Description

[0001] This application is a divisional application of Application No. 202380028350.6, filed with the State Intellectual Property Office of China on September 18, 2024, with an application date of March 17, 2023, entitled "Optical Multi-Die Interconnect Bridge (OMIB)". This application is a national phase application filed with the International Intellectual Property Office on March 17, 2023, with International Application No. PCT / US2023 / 015467, which enters China. It claims priority to U.S. Provisional Patent Application No. 63 / 321,453, filed with the U.S. Patent and Trademark Office on March 18, 2022; U.S. Provisional Patent Application No. 63 / 420,330, filed with the U.S. Patent and Trademark Office on October 28, 2022; and U.S. Provisional Patent Application No. 63 / 448,585, filed with the U.S. Patent and Trademark Office on February 27, 2023. The above applications are incorporated herein by reference.

[0002] Cross-referencing

[0003] This application is a divisional of U.S. Patent Application No. 18 / 742,028, filed June 13, 2024, entitled "Optically Bridged Multicomponent Package with Extended Temperature Range," now USP 12,298,608; which in turn is a divisional of U.S. Patent Application No. 18 / 742,028, filed September 7, 2023, entitled "OPTICAL MULTI-DIE INTERCONNECT BRIDGE WITH OPTICAL INTERFACE," now USP 12,124,095; which in turn is a divisional of U.S. Patent Application No. 18 / 243,474, filed March 17, 2023, entitled "OPTICAL MULTI-DIE INTERCONNECT BRIDGE (OMIB)," now USP 12,298,608. A continuation of U.S. Patent Application No. 18 / 123,083, filed on February 27, 2023, entitled “Optical, Multi-Die Interconnect Bridge (OMIB)”; U.S. Patent Application No. 63 / 448,585, filed on March 18, 2022, entitled “Photonic Memory Fabric for System Memory Interconnection”; and U.S. Patent Application No. 63 / 420,330, filed on October 28, 2022, entitled “ThermallyStable Optical Modulation Elements Coupled to Electronic Elements”.This application is also a continuation of U.S. Patent Application No. 19 / 070,348, filed March 4, 2025, entitled "Multi-Chip Electro-Photonic Networks and Photonic Memory Fabrics for Interconnecting Multiple Circuit Packages"; which is a continuation of U.S. Patent Application No. 17 / 903,455, filed March 4, 2025, entitled "Multi-Chip Electro-Photonic Networks and Photonic Memory Fabrics for Interconnecting Multiple Circuit Packages"; which claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 321,453, filed March 18, 2022, entitled "Photonic Memory Fabric for System Memory Interconnection". This application is also related to the following patent applications: U.S. Patent Application No. 17 / 807,694, filed June 17, 2022; U.S. Patent Application No. 18 / 293,673, filed January 30, 2024; U.S. Patent Application No. 18 / 123,161, filed March 17, 2023; U.S. Patent Application No. 18 / 123,170, filed March 17, 2023; International Patent Application No. PCT / US23 / 15680, filed March 20, 2023; and International Patent Application No. PCT / US22 / 42621, filed September 6, 2022. Technical Field

[0004] Embodiments of this disclosure generally relate to apparatus and methods for use in interconnect semiconductor dies, and more particularly to apparatus and methods for optical interconnection using integrated circuits and / or external chiplets. Background Technology

[0005] The topics discussed in this section should not be considered prior art simply because they are mentioned here. Similarly, problems mentioned in this section or related to the topics provided as background should not be considered as having been previously acknowledged in the prior art. The topics in this section merely represent different methods, which themselves may correspond to implementations of the claimed technology.

[0006] Integrated circuits (ICs) with processors, especially those used to perform artificial intelligence and machine learning functions, move large amounts of data between one or more processor ICs and one or more memory ICs. Chips can facilitate the interconnection of processor dies, memory dies, and other circuitry to increase bandwidth and reduce latency and power consumption in the process. Summary of the Invention

[0007] Processing AI workloads typically uses dedicated hardware. Typical hardware bridges two chips with electrical interconnects. These interconnects consume high power, have pin count limitations, and can only carry data to the edge of the chip. When memory is located in the central region of the chip, the signal needs to travel an additional distance each time the processor sends a request from outside the chip to the edge to access memory. This is highly inefficient and makes it difficult for AI computing hardware to keep up with the demands of AI applications.

[0008] In a first aspect, an embodiment provides a package including a bridging element, a first unidirectional photonic path, and a second unidirectional photonic path. The bridging element includes a first interconnect region and a second interconnect region, both configured to be electrically connected to one or more dies. The unidirectional photonic paths are coupled between the two interconnect regions in opposite directions. A third and fourth unidirectional photonic path can be bidirectionally coupled between the first interconnect region and an optical interface (OI). A first portion of a photonic transceiver can be coupled to the first interconnect region to transmit a first optical signal via the first unidirectional photonic path and receive a second optical signal via the second unidirectional photonic path. It can also be configured to transmit a third optical signal via the third unidirectional photonic path and receive a fourth optical signal via the fourth unidirectional photonic path. The first portion of the photonic transceiver can be located in a photonic integrated circuit (PIC), and the second portion of the photonic transceiver can be located in an electronic integrated circuit (EIC). The first and second portions can be coupled via an electrical interconnect with a length less than 2 mm. The modulator can be an electroabsorption modulator made of germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based III-V materials, or gallium arsenide (GaAs)-based III-V materials. The EIC can include two or more computing elements surrounding a central region. A second section is located near one of these computing elements.

[0009] The nature and advantages of the specific embodiments disclosed herein can be further understood by referring to the remainder of the specification and the accompanying drawings. Attached Figure Description

[0010] The invention will be described with reference to the accompanying drawings, in which:

[0011] Figure 1It is a top view of a wafer and die that may be included or contained in one or more microelectronic packages having an OMIB, according to various embodiments.

[0012] Figure 2 An example OMIB with two bridged dies is shown.

[0013] Figure 3 An example package is shown where two bare dies can be coupled via electrical interconnection.

[0014] Figure 4 An example package is shown where two bare dies can be coupled via electrical interconnection.

[0015] Figures 5A-5E An example package is shown that uses a light engine to provide optical signals for use by a photonic network.

[0016] Figure 6 A perspective view of an example OMIB that bridges two dies and is coupled to a light engine is shown.

[0017] Figure 7A A perspective view of an example OMIB that bridges two dies and receives unmodulated light from a core-light engine (CLE) is shown.

[0018] Figure 7B An example wrapper that can be used with CLE is shown.

[0019] Figure 8A This is a schematic diagram of an example OMIB with a photonic link capable of connecting two dies within a package, according to some implementations.

[0020] Figure 8B An embodiment with two OMIBs coupled between a first die and a second die is shown.

[0021] Figure 9 This is a schematic diagram of an example system for communication from a die to an external device using WDM according to some implementation methods.

[0022] Figure 10 The following are illustrated according to some embodiments. Figure 9 An example reverse channel of a WDM system.

[0023] Figure 11 An example unidirectional logical channel comprising multiple photonic links is shown.

[0024] Figure 12 It shows Figure 11 Transmission of an example eight-word message in a one-way logical channel.

[0025] Figure 13 The example AMS block is shown in more detail.

[0026] Figure 14A The arrangement of three OMIBs bridging a portion of two bare dies is shown.

[0027] Figure 14B An example arrangement of five bare dies bridged by OMIB is shown.

[0028] Figure 14C An example arrangement of bare dies bridged by OMIB and a bridge is shown.

[0029] Figure 14D An example offset chessboard is shown where OMIB bridges the bare chip in two dimensions.

[0030] Figure 15 This is a flowchart illustrating example methods for manufacturing an OMIB according to various implementations.

[0031] Figure 16 The components of an example system in which one or more OMIBs can be used are shown.

[0032] Figures 17A-17D An example of an EIC / OMIB combination is shown, which employs temperature compensation to widen the temperature range of the modulator in the OMIB.

[0033] Figure 18 Example method 1800 of the manufacturing system is shown.

[0034] In the figures, similar reference numerals denote elements with similar functions. The systems and methods shown in the figures and described in the detailed embodiments below can be arranged and designed in a variety of different ways. The figures and detailed descriptions are not intended to limit the scope claimed. Rather, they merely illustrate examples of different embodiments of the invention. Detailed Implementation

[0035] Processing AI workloads typically uses dedicated hardware. Typical hardware bridges two chips with electrical interconnects. These interconnects consume high power, have pin count limitations, and can only carry data to the edge of the chip. When memory is located in the central region of the chip, the signal needs to travel an additional distance each time the processor sends a request from outside the chip to the edge to access memory. This is highly inefficient and makes it difficult for AI computing hardware to keep up with the demands of AI applications.

[0036] This document discloses an Optical Multi-Die Interconnect Bridge (OMIB). An OMIB can be used as a bridge between semiconductor dies (e.g., electronic integrated circuits (EICs)). The bridge can consist of an OMIB alone or in combination with a substrate coupled to or having an OMIB embedded therein. Using an OMIB in a multi-die processing system solves many problems associated with processing AI workloads, including latency, power, and bandwidth. A photon receiver can include two parts, such as a first part in the OMIB and a second part in the EIC, the first part including a modulator and / or photodetector, and the second part including an AMS block, as described below.

[0037] In various arrangements, the OMIB can transmit or receive photonic signals to transmit data. Memory (such as cache) can be located within two millimeters (2 mm) of the AMS block in the central region of the EIC die, such that the photonic transceiver in the OMIB is close to the edge of the memory, which is directly above or below the portion of the die containing the memory edge. The central region can intersect with the center of the EIC die. Computational elements (such as central processing units (CPUs), graphics processing units (GPUs), tensor processing units (TPUs)) can also be advantageously arranged within two millimeters (2 mm) of the photonic transceiver location in the central region of the die, or spatially associated with the memory. Due to the heat generated by the interconnecting chips, the photonic IC has avoided reaching the center of the die where the interconnecting chips are located. The photonic chip can have a limited temperature range within which the modulator operates within specifications. One reason the OMIB in the art of this disclosure can reach the center of the die is that it uses a temperature-stable modulator as described in U.S. Provisional Patent Application Serial No. 63 / 420,330 entitled “Thermally Stable Optical Modulation Elements Coupled to Electronic Elements”.

[0038] Therefore, OMIB is faster and uses lower power consumption compared to traditional systems. By optically transferring data to the computation point rather than the edge of the die, latency is improved. This allows for fewer electrical pipeline stages on the die and also utilizes fewer electrical connections to transfer data from the edge of the die to the interior where the memory resides. The electrical movement of data from the edge of the die to the interior requires a slower and more power-intensive data path. The benefits of optically moving data to the computation point will be repeatedly demonstrated if exemplary systems are used to train AI models, leading to significant cost savings and / or the feasibility of implementing these types of complex AI systems.

[0039] the term

[0040] This description may use perspective-based descriptions (such as top / bottom, inside / outside, up / down, etc.). Such descriptions are only used to facilitate discussion and are not intended to limit the application of the embodiments described herein to any particular direction.

[0041] As used in this article, the phrase “one of” should be interpreted as one of the listed items. For example, the phrase “one of A, B, and C” should be interpreted as meaning any one of only A, only B, or only C.

[0042] As used herein, the phrases “at least one” and “one or more” should be interpreted as one or more items. For example, the phrase “at least one of A, B and C” or the phrase “at least one of A, B or C” should be interpreted as referring to any combination of A, B and / or C.

[0043] Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” “third,” etc., to describe an object merely refers to different instances or categories of that object and does not imply any rank or order.

[0044] The term "coupled" is used in an operational sense, not limited to direct or indirect coupling. "Coupled to" is generally used to mean direct coupling, while "coupled with" is generally used to mean both direct and indirect coupling. In electronic systems, "coupled" can refer to a configuration that allows the flow of information, signals, data, or physical quantities (such as electrons) between two elements coupled to or to each other. In some cases, the flow may be unidirectional; in others, it may be bidirectional or multidirectional. Coupling can be electrical (in this context, meaning a direct electrical connection), capacitive, inductive, electromagnetic, optical, or by any other physically permissible process.

[0045] The term "connection" is used to refer to a direct connection (such as an electrical, optical, electromagnetic, or mechanical connection) between connected things without any intermediate things or devices.

[0046] The term "configured to" perform one or more tasks is a broad description of a structure, generally referring to "circuit having one or more tasks to perform during operation." Therefore, the described item can be configured to perform a task even when the unit / circuit / component is not currently turned on or activated. Generally, the circuit forming the structure corresponding to "configured to" can include hardware circuitry and can also be controlled by switches, fuses, bonding wires, metal masks, firmware, and / or software. Similarly, for ease of description, various items can be described as performing one or more tasks. Such descriptions should be interpreted as including the phrase "configured to."

[0047] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that other factors may influence the determination. That is, a determination may be based solely on the specified factors or on the specified factors plus other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or a factor influencing the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on other factors (such as C). This phrase is also intended to cover implementations where A is determined solely based on B. Therefore, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0048] "Processor" includes any suitable hardware system, mechanism, or component that processes data, signals, or other information. A processor may include a system having a general-purpose central processing unit, multiple processing units, dedicated circuitry for implementing functions, or other systems. Examples of processing systems may include servers, clients, end-user devices, routers, switches, network storage, etc. "Computer" can be any processor that communicates with memory. Memory can be any suitable processor-readable storage medium (such as random access memory (RAM), read-only memory (ROM), magnetic disk, or optical disk) or other tangible medium suitable for storing instructions to be executed by the processor.

[0049] The terms “substantially,” “close,” “approximately,” “near,” and “about” mean within plus or minus 10% of the specified value, unless otherwise expressly stated.

[0050] The following terms or acronyms used in this article are defined, at least in part, as follows:

[0051] AI - Artificial Intelligence

[0052] AMS - Analog / Mixed Signal

[0053] BGA (Ball Grid Array)

[0054] A channel is one or more lanes that can be combined together.

[0055] Chiplet - An integrated circuit with a simple or specialized function used in conjunction with other ICs or chips in a multi-chip assembly.

[0056] CLE-Core Light Engine

[0057] CPU - Central Processing Unit

[0058] CW - Continuous Wave

[0059] DDR memory - Double Data Rate Memory

[0060] DFB - Distributed Fiber Bragg

[0061] DIMM - Dual In-line Memory Module

[0062] DRV - Driver. In some embodiments, the driver is a photonic integrated circuit (PIC) or an electronic integrated circuit (EIC).

[0063] DSP - Digital Signal Processor

[0064] EAM-Electro-Absorption Modulator

[0065] EIC - Electronic Integrated Circuits

[0066] EW - Fleeting Wave

[0067] FAU - Fiber Array Unit

[0068] FBG - Fiber Bragg Grating

[0069] FPGA - Field Programmable Gate Array

[0070] GC-grating coupler - coupling between optical fiber and on-chip photonic waveguide

[0071] GPU - Graphics Processing Unit

[0072] GRIN lens - graded index lens

[0073] HBM - High Bandwidth Memory

[0074] IC – Integrated Circuit – A monolithic integrated circuit is a single semiconductor die that can be delivered as a bare die or a packaged circuit. For the purposes of this article, the term integrated circuit also includes packaged circuits that contain multiple semiconductor dies, stacked dies, or multiple die substrates. This structure is now common in the industry, produced by the same supply chain, and is generally indistinguishable from a monolithic circuit to the average user.

[0075] A channel consists of a serializer, a link, and a deserializer.

[0076] LED - Light Emitting Diode

[0077] LDSU - Load / Storage Unit

[0078] The link described in this patent document is a combination of a modulator, a photonic path (in an optical transmission medium), and a photodetector.

[0079] LGA - Planar Grid Array

[0080] ML - Machine Learning

[0081] MLA-microlens array

[0082] MOD - Modulator

[0083] MZI-Mach-Zehnder Interferometer

[0084] OI - Optical Interface - An interface that uses any method to make an optical interface between optical fibers and photonic ICs.

[0085] OMIB - Optical Multi-Die Interconnect Bridge

[0086] PCB - Printed Circuit Board

[0087] PCIe (PCI Fast-Speed ​​Serial Bus)

[0088] PCM - Phase Change Memory

[0089] PD - photodetector, such as photodiode

[0090] PGA - Pin Grid Array

[0091] PIC - Photonic Integrated Circuit

[0092] QR - Quick Response

[0093] A processing device, processor, compute device, or compute element can refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory.

[0094] RAM - Random Access Memory, some types are Static RAM (SRAM), Dynamic RAM (DRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Conductive Bridged RAM (CBRAM), etc.

[0095] RDL - Redistribution Layer - An additional metal layer on an integrated circuit that allows pads to be used in other locations on the die.

[0096] SCM - Storage Class Memory

[0097] SLD (Super Light Emitting Diode)

[0098] SSD - Solid State Drive

[0099] SOA - Semiconductor Optical Amplifier

[0100] TPU - Tensor Processing Unit

[0101] UCIe - Universal Chip Interconnect, a fast, open specification for die-to-die interconnects and serial buses between chips.

[0102] VCSEL - Vertical Cavity Surface Emitting Laser

[0103] A waveguide is an implementation of a unidirectional photon path in an optical transmission medium.

[0104] WDM (Wavelength Division Multiplexing) Implementation

[0105] The implementation described herein relates to addressing power, delay, or pin count issues by providing various OMIB configurations and various packages that include at least one OMIB. Figure 1 This is a top view of a wafer 100 and die 102 included or incorporated in one or more microelectronic packages having an OMIB, according to various embodiments. The wafer 100 may be composed of semiconductor material and may include one or more dies 102 having an IC structure formed on the surface of the wafer 100. Each die 102 may be a unit of a semiconductor product including a suitable IC. After the semiconductor product is manufactured, the wafer 100 may undergo a dicing process in which the dies are separated from each other to provide discrete “chips” of the semiconductor product. Dies 102 and at least one other die may be included in a microelectronic package having an OMIB.

[0106] A second wafer (not shown) can be used in a second process to form the OMIB in a manner similar to that used to fabricate die 102. The OMIB is a photonic integrated circuit (PIC) and has optical components fabricated therein, as opposed to die 102, which is an electronic integrated circuit (EIC) and typically has electronic components fabricated therein. The OMIB can be embedded in a package substrate. The package substrate can be considered a cored or coreless substrate. The package substrate may include one or more layers of organic or inorganic dielectric material. The package substrate may also include one or more conductive elements (such as vias, pads, traces, microstrips, striplines, etc.). The conductive elements may be inside or on the surface of the package substrate. Typically, the conductive elements allow signals to pass through the package substrate or be routed between components coupled to the package substrate. In some embodiments, the package substrate may be, for example, a printed circuit board (PCB), an interposer, a motherboard, or some other type of substrate.

[0107] Figure 2An example OMIB with two bridged dies is shown. The OMIB 200 formed in the second stage of the manufacturing process can share dimensions with each die 102 (horizontal or vertical) formed in the first stage of the manufacturing process. The die can be as large as possible within the dimensional constraints of the reticles used to manufacture it. Figure 2 In this embodiment, die 102 has a width corresponding to the maximum EIC marking width MRW1 and a height corresponding to the maximum EIC marking height MRH1, and OMIB 200 has a width corresponding to the maximum PIC marking width MRW2. This is likely for manufacturing convenience and cost savings, rather than a limitation on various implementations.

[0108] In some implementations, wafer 100 or die 102 may include a memory device, a computing device, or both (examples include, but are not limited to, random access memory (RAM) devices such as static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or conductive bridged RAM (CBRAM) devices), logic devices (e.g., AND gates, OR gates, NAND gates, NOR gates, or XOR gates), NAND flash memory, solid-state drive (SSD) CMOS memory, thin-film transistor-based memory, phase-change memory (PCM), storage-class memory (SCM), and magnetoresistive memory (MRAM). Resistive RAM, DRAM, high-bandwidth memory (HBM), DDR-based DRAM, DIMM memory, CPU, GPU, MPU, tensor engine, load / store unit (LDSU), neural computing engine, dot product and / or convolution engine, field-programmable gate array (FPGA), AI accelerator, or any other suitable circuit element. Multiple of these devices can be combined on a single die 102. For example, die 102 may include memory comprising multiple memory arrays, one or more processors, other logic circuitry, communication circuitry, and power management functions, and execute instructions stored in the memory arrays, or otherwise interact with the memory arrays using a processor on die 102.

[0109] Figure 3 An example package 300 is shown, in which dies 310 and 320 can be electrically interconnected. Package 300 includes an OMIB 330 that acts as a bridge between dies 310 and 320. An optional substrate 340 is coupled to the OMIB 330, such that the OMIB 330 is embedded within the substrate 340. Although in Figure 3While shown flush with the surface of the substrate 340, the OMIB 330 may not be flush with the surface of the substrate 340, but may at least partially protrude from or be embedded in the inner layers of the substrate 340. Various depicted elements may be on the surface of the OMIB 330 or die 310 and / or die 320, or at least partially protrude from the OMIB 330 or die 310 and / or die 320. Furthermore, in other embodiments, the specific number of elements, interconnects, dies, and other devices may vary. In some embodiments, the package may include adhesives, sealants, underfill, molds, overlays, or other structural or dielectric materials. In some embodiments, certain elements may be located at different positions within the signal path relative to other elements. An optical interface (OI) 350 is included on the surface of the OMIB 330. The optical interface 350 may be coupled to an optical engine 370 to receive unmodulated light via optical fiber 360, and / or coupled to an external device optical interface to exchange modulated and / or unmodulated light in either direction. In addition to the optical interface 350, there may be one or more electrical interfaces on the surface of the OMIB 330 for interfacing with external electronic devices.

[0110] Various implementations can utilize different types of optical engines. The optical engine can be external or integrated into the OMIB. Example implementations can use the following optical engines to transmit and receive optical signals from a package including the OMIB 330: laser diodes – these are highly coherent light sources that produce narrow beams and are widely used in photonic chips for data communication and sensing applications; light-emitting diodes (LEDs) – diodes that emit light when current passes through them (they are inexpensive, compact, and have long lifespans, making them a popular choice for photonic chips); superluminescent diodes (SLDs) – SLDs are similar to LEDs but emit a wider broadband spectrum (SLDs are used in applications such as optical amplification, wavelength division multiplexing, and fiber optic sensing); vertical-cavity surface-emitting lasers (VCSELs) – these lasers emit light perpendicular to the surface of a chip, making them ideal for photonics applications (VCSELs are widely used in data communication and sensing applications such as 3D sensing, LiDAR, and data center interconnects); silicon photonics – devices that utilize the light-carrying properties of silicon to generate light sources on silicon chips (silicon photonics has the potential to revolutionize photonics by reducing the size, cost, and power consumption of photonic components). These are some of the most commonly used light sources in packages including the OMIB 330. The choice of light engine depends on the specific requirements of the implementation (e.g., wavelength, power, and modulation speed).

[0111] The optical engine can be located locally on the OMIB 330 or connected to the OMIB 330 via fiber optic cable 360. When integrated onto the PIC, a distributed fiber Bragg (DFB) laser or a quantum dot laser can be attached during processing or integrated into the local technology where possible. When remote, a continuous wave (CW) laser in any package with power and spectrum suitable for the modulation technique can be used. In one implementation, the light source is a set of DFB lasers attached to a silicon interposer and connected to the PIC via fiber optic cable.

[0112] Optical interface 350 is used to terminate optical fiber at the edge or top of OMIB 330 for optical input and / or output to external processes or devices communicatively coupled to package 300 via optical fiber. The choice of OI depends on the specific requirements of the implementation (e.g., wavelength of light, coupling efficiency, and cost). Optical interface 350, as well as any other optical interfaces in or on OMIB 330, may include any means for optical interface between optical fiber and photonic IC, such as: edge couplers, grating couplers (CG), graded-index (GRIN) lens couplers, fiber Bragg grating (FBG) couplers, microlens array (MLA) couplers, evanescent wave (EW) couplers, thermally adiabatic couplers, wavelength division multiplexing (WDM) couplers, prism couplers, docking couplers, end-fire couplers, and V-groove couplers.

[0113] In one embodiment, the optical interface 350 includes a fiber optic array unit (FAU) for optically connecting the OMIB to a light source and / or optical I / O unit. An FAU is a device used in optical communication systems that combines or separates optical signals from multiple optical fibers into single or multiple optical signals. FAUs can be used in a variety of applications, such as wavelength division multiplexing (WDM), parallel optical interconnects, and optical sensing. Two main types of fiber optic array units can be used: linear and circular. Linear FAUs combine or separate optical signals along a straight line, while circular fiber optic array units combine or separate optical signals in a circular configuration. Both types of fiber optic array units are typically made of precision-molded optical plastic or ceramic materials and can have from a few to hundreds of fibers arranged in a specific pattern. The choice of FAU depends on the specific requirements of the application, such as the number of fibers, the fiber arrangement, the wavelength of the light used, and the desired coupling efficiency. Each die may have an associated Analog / Mixed Signal (AMS) block, which is associated with a portion of its coupled OMIB and one or more transistors or supporting circuitry to route electrical signals to the transistors or some other IC components.

[0114] The OMIB 330 may also include one or more electrical interfaces (EIs). OIs and EIs may be attached to the surface of the OMIB, or between bridged dies 102, or offset in regions in the x or y directions where the die 102 does not extend. EIs function similarly to OIs, except that they enable the OMIB to transmit data to and from the die via electrical connections rather than optical connections, and can connect external I / O blocks to the OMIB, for example, via wires from the EI to external I / O blocks. Different types of electrical connections are possible, including wires, RDLs, etc. Electrical connections typically use known standards or bus protocols to electrically transmit and receive data between the EI and any die bridged by the OMIB or between the EI and external I / O blocks via electrical interconnection. Electrical paths between the EI and the die can be routed via the OMIB, via the substrate, or via both (or, in the case of an RDL, via the OMIB and / or a layer of the substrate).

[0115] Figure 4 An example package 400 is shown, in which dies 410 and 420 can be electrically interconnected. Package 400 is similar to... Figure 3 Package 300 has a similar component number, and furthermore... Figure 4 A first photonic transceiver 432 and a second photonic transceiver 434 are shown. A portion of the first transceiver 432 is in die 410, and a portion of the second photonic transceiver 434 is in die 420. Another portion of the first transceiver 432 is in OMIB 430, and another portion of the second transceiver 434 is in OMIB 430. Figure 4 Bidirectional photonic paths 481, 482, and 483 are shown. Bidirectional photonic path 483 connects a first photonic transceiver 432 and a second photonic transceiver 434. Bidirectional photonic path 483 may include two or more unidirectional photonic paths in opposite directions to create a bidirectional path between the two transceivers, thereby enabling optical communication and / or data movement in both directions via photonic channels between the two dies 410 and 420. Bidirectional photonic path 481 links photonic transceiver 432 to optical interface 450, and bidirectional photonic path 482 links photonic transceiver 434 to optical interface 450. Optical interface 450 is coupled to optical engine 470 via optical fiber 460. Bidirectional photonic paths 481-483 may form a photonic network within OMIB 430. Optical interface 450 may include any device for interfacing between the optical fiber and the photonic IC. Substrate 440 is optional.

[0116] Photonic paths can be implemented in optical transmission media. Optical transmission media can include waveguides on the PIC, optical fibers, or other optical transmission media (such as free-space optics or glass-etched waveguides), or combinations thereof. Examples of optical modulators include, but are not limited to, electro-absorption modulators (EAMs), microring resonators, or any suitable optical component with sufficient thermal stability.

[0117] Figure 5A -E illustrates an example package using a light engine to provide optical signals for use by a photonic network. The light engine may include a laser diode, optics, and / or control electronics. The laser diode is the source of the laser light, the optics are used to shape and control the output of the laser light. The control electronics (not shown) provide the necessary power and modulation to the laser diode to generate the desired output. Figures 5A-5E In this implementation, the optical engine provides optical signals via optical interfaces (such as FAU and GC) to a beam splitter, modulator (MOD) adjacent to the AMS block in the first die, and ultimately to a photodetector (PD) adjacent to the AMS block in the second die. When laser light passes through the particle optical engine (as referenced...), Figure 7A In the case described, FAU is not required, and light can be directly guided into GC. Figures 5A-5E The photonic network in OMIB enables multiple optical paths. Although Figures 5A-5E The diagram shows that GC and FAU together form an optical interface, but any implementation can use any device to interface between the fiber optic cable and the photonic IC.

[0118] Figure 5A Example 500 of the OMIB internal connection is shown, illustrating the optical path that begins at the light engine 570. Figure 5A The device includes a first die 510, which is divided into a general-purpose portion 510B and an AMS portion 510A. The general-purpose portion 510B may include various processing, storage, and communication functions. The AMS portion 510A includes analog / mixed-signal circuitry for interfacing with the OMIB 530. It also includes an optional substrate 540 and an optical engine 570. The AMS portion 510A of the first die 510 may include a driver (DRV1) and a transimpedance amplifier (TIA1). The AMS portion 520A of the second die 520 may include a driver (DRV2) and a transimpedance amplifier (TIA2).

[0119] Optical engine 570 transmits light to beam splitter SP within OMIB 530 via fiber array unit (FAU) and grating coupler GC (or any other OI configured to receive light at OI input and transmit the received light at OI output). Beam splitter SP distributes light to modulators MOD1 and MOD2 via two distinct photonic paths 531 and 532. In some embodiments, beam splitters or beam splitter trees distribute light across more than two distinct photonic paths to feed additional modulators. The photonic paths can be implemented using any suitable optical transmission medium and can include a hybrid of waveguides and optical fibers.

[0120] Modulator MOD1 modulates the light it receives from beam splitter SP with information from driver DRV1 and transmits the modulated light to photodetector PD2 via photonic path 533. Photodetector PD2 converts the received light into an electrical signal for second die 520. Modulator MOD2 modulates the light it receives from beam splitter SP with information from driver DRV2 and transmits the modulated light to photodetector PD1 via photonic path 534. Photodetector PD1 converts the received light into an electrical signal for first die 510. Together with the serializer (not shown) in first die 510, driver DRV1, transimpedance amplifier TIA2, deserializer (not shown) in second die 520, modulator MOD1, photonic path 533, and photodetector PD1, a data channel from first die 510 to second die 520 is formed.

[0121] The OMIB 530, a photonic IC, includes a first interconnect region, a second interconnect region, and an offset region. The first interconnect region includes pad patterns located above MOD1 and PD1, which match pad patterns on a first die 510 located below DRV1 and TIA1, or are otherwise configured to form electrical interconnects between their respective components. The second interconnect region includes pad patterns located above PD2 and MOD2, which match pad patterns on a second die 520 located below TIA2 and DRV2, or are configured to form electrical interconnects between their respective components. Figure 6 The offset regions further shown include optical interfaces (such as GC / FAU). Two or more pads of the pad pattern on the first die 510 are physically and electrically coupled to two or more pads of the pad pattern in the first interconnect region, and two or more pads of the pad pattern on the second integrated circuit are physically and electrically coupled to two or more pads of the pad pattern in the second interconnect region. One or more of the two or more pads on the first die 510 may be located more than 100 micrometers (100 μm) from the edge of the first die 510. The location of one or more of the two or more pads on the second die 520 may be located more than 100 micrometers (m) from the edge of the second die 520. The distance between the (lower) surface of the first die 510 and the (top) surface of the OMIB 530 is less than 2 mm, and in many cases less than 50 micrometers. The distance between the (lower) surface of the second die 520 and the (upper) surface of the OMIB 530 is less than 2 mm, and in many cases less than 50 micrometers.

[0122] Figure 5B The same example is shown, but only the signal path is shown. The path of the unmodulated light is omitted. Figure 5B A signal path is illustrated in bold below. Interface I / F1 in the first die 510 transmits a digital signal carrying information from general-purpose portion 510B of the first die 510 to driver DRV1. Driver DRV1 converts the digital signal into an analog electrical signal suitable for driving a photonic modulator and passes the analog electrical signal to modulator MOD1 in OMIB 530. Modulator MOD1 sends modulated light carrying the information to be transmitted to photodetector PD2 via photonic path 533. Photodetector PD2 converts the modulated light into a current signal and passes this current signal to transimpedance amplifier TIA2, which amplifies the signal and converts it into a voltage signal suitable for digital interface I / F2. Interface I / F2 converts the voltage into a digital signal suitable for processing in general-purpose portion 520B of the second die 520. Similarly, information to be transmitted from the general portion 520B of the second die 520 to the general portion 510B of the first die 510 is propagated through I / F2, DRV2, MOD2, photon path 534, photodetector PD1, transimpedance amplifier TIA1 and interface I / F1.

[0123] Photonic paths 533 and 534 include waveguides or other suitable optical transmission media to carry optical signals from the modulator to the photodetector. The modulator in OMIB 530 is coupled to a driver in the AMS portion of the first or second die via copper pillars or other suitable electrical interconnects. The photodetector in OMIB 530 is coupled to a transimpedance amplifier in the AMS portion of the first or second die via copper pillars or other suitable electrical interconnects. The photonic paths in OMIB 530 can be unidirectional, such that a pair of photonic paths in opposite directions can be contained in a single bidirectional information channel.

[0124] Electrical interconnects are shown as couplings (or adjacent couplings) between components in the AMS component and corresponding components in the OMIB 530. In one embodiment, the interconnect is a copper pillar no more than 2 mm long. In other embodiments, the electrical interconnect can be a solder bump formed of a material such as tin, silver, or copper. If solder bumps are used for interconnects, then the solder bumps can be flip-chip bumps. In other embodiments, the interconnect can be a ball grid array (BGA) component, a pin of a pin grid array (PGA), a planar grid array (LGA) component, or some other type of interconnect. Typically, interconnects physically and electrically couple the AMS block to the OMIB 530. For example, one or more interconnects can be physically coupled to the pads of the die and the substrate 540 and / or the pads of the OMIB 530, allowing electrical signals to pass between them. Interconnects 525 may not have a uniform size, shape, or spacing. Finer interconnect spacing may be required to allow denser communication paths between components coupled to the OMIB. In implementation, the size, shape, spacing, or type of one or more interconnects may differ from those depicted in the figures or from other interconnects. The specific type, size, shape, or spacing of the interconnects may be based on one or more factors (such as usage, materials used, design considerations, and manufacturing considerations).

[0125] Figure 5C An example of an OMIB connection is shown. The path of the unmodulated light is omitted. First die 510 and second die 520 can optically communicate with an external device optical interface 571 using OMIB 580 and fiber optic cable 561. For example, first die 510 can transmit to external device optical interface 571 via I / F1, DRV1, MOD1, photonic path 581, optional multiplexer MUX (in the case of desired wavelength division multiplexing), GC, FAU, and fiber optic cable 561. Conversely, first die 510 can receive from external device optical interface 571 via fiber optic cable 561, FAU, GC, photonic path 583, optional demultiplexer DEMUX (in the case of desired wavelength division multiplexing), PD1, TIA1, and I / F1.

[0126] Figure 5D An example of a stacked die arrangement is shown. AMS circuitry (DRV1 and TIA1) is included in a first AMS die 511A, and general-purpose / digital circuitry is included in a first general-purpose die 511B. The first AMS die 511A is stacked on top of the OMIB 580 via electrical interconnect 526A, and the first general-purpose die 511B is stacked on top of the first AMS die 511A via electrical interconnect 526B. The OMIB 580 interfaces with the optical engine 570 and / or the external device optical interface 571 via fiber optic cable 560, and may also interface with a second die 520.

[0127] Figure 5E An arrangement is shown in which a first general-purpose die 512B and a first AMS die 512A are stacked on an OMIB 590 and placed side by side. Electrical interconnects, such as buses, enable signals to travel to and from the first general-purpose die 512B and the first AMS die 512A (e.g., using UCIe, PCIe, or any suitable protocol). The electrical interconnects may include an electrical path 527A from TIA1 to I / F1 and an electrical path 527B from I / F1 to DRV1.

[0128] Figure 6 A perspective view 600 of an example OMIB 630 bridging two dies (first die 610 and second die 620) and coupled to an optical engine 670 is shown. Substrate 640 is optional. First die 610 and second die 620 each have an AMS block (first AMS portion 610A and second AMS portion 620A) in a region overlapping with OMIB 630, such that the AMS blocks are adjacent to OMIB 630 and / or stacked on OMIB 630 in a configuration that couples first die 610 to OMIB 630 via electrical interconnects and also couples second die 620 to OMIB 630. This interconnect can be made of copper pillars or any other suitable electrical interconnect. Offset portions of the OMIB create offset regions where the OI and / or external optical engine 670 can be positioned. External optical engine 670 provides a light source for the photonic network via the OI. External device optical interface 671 provides bidirectional communication with the dies via an optical fiber between the OI and external device optical interface 671. exist Figure 6 In this design, the top surfaces of OMIB 630 and substrate 640 are shown as substantially coplanar, although, as previously stated, OMIB 630 does not need to be flush with the surface of substrate 640. The bottom surface of the first die 610 or the second die 620 may be physically and electrically coupled to the top surface of OMIB 630. If the first portion of the transceiver (the modulator and / or PD in OMIB 630) is aligned with the second portion of the transceiver (AMS portion 610A or AMS portion 620A), then OMIB 630 and the first die 610 or the second die 620 form an adjacent coupling.

[0129] Figure 7AA perspective view of an example OMIB 730 bridging two dies and receiving unmodulated light from a core-light engine (CLE) is shown. Substrate 740 is optional. A first die 710 and a second die 720 each include an AMS block (710A, 720A) in a region overlapping with OMIB 730, such that the AMS block is above and / or stacked on OMIB 730, configured to couple the two dies to OMIB 730 via suitable electrical interconnects (e.g., where the modulator is directly above the driver and the TIA is directly above the PD). The CLE is located in an offset region of OMIB 730. The CLE includes a laser that can be placed parallel to the surface of the OMIB 730, a first optical component (e.g., a mirror 701 that reflects the laser beam downwards or to one side), and a second optical component (e.g., a lens 702 that focuses the laser beam onto a smaller area). The first and second optical components can be configured to redirect light substantially by ninety (90) degrees, allowing light from the laser to be guided into the OMIB. Inside the OMIB, light can enter the GC, which also includes a 90-degree mirror, allowing light to enter a waveguide parallel to the OMIB surface. An external device optical interface 771 communicates bidirectionally with the die via an optical fiber between the OI and the external device optical interface 771.

[0130] Figure 7B An example package 700 that can use the CLE 775 is shown. Substrate 741 is optional. Optical signals are provided from the CLE 775 to the grating coupler CG1 (or any other interface device between the fiber and the photonic IC) and the beam splitter SP via OMIB 731, from where they are directed to the first die 711 and the second die 721. OMIB 731 also provides optical paths in both directions between the dies. A second grating coupler CG2 and FAU, or other associated fiber optic connectors using any other interface device between the fiber and the photonic IC, can provide access to the external device optical interface 771. In some embodiments, the CLE 775 may be included in a CLE array. In other embodiments, the CLE 775 may include a semiconductor optical amplifier (SOA) or an SOA array to amplify the power of unmodulated light.

[0131] Figure 8AThis is a schematic diagram of an example OMIB 830 with a photonic link capable of connecting two dies within a package, according to some embodiments. The OMIB 830 provides optical communication from each modulator (MOD1-4) in a first die 810 to each photodetector (PD1-4) in a second die 820. A waveguide system in the OMIB can bridge and / or enable connections between a transmitting unit (not shown) in the first die 810 and a receiving unit (not shown) in the second die 820. An optical engine 870, which can be located inside or outside the OMIB 830, outputs a single wavelength. The carrier light of a1. The beam splitter tree (SPT) can split the wavelength on multiple optical paths (four have been drawn) leading to the modulator MOD1-4. a1 light. The modulator modulates a single wavelength. The light from a1 is transmitted to the photodetector PD1-4 via their respective waveguides, and the modulated light is transmitted to the photodetector PD1-4. Figure 8A Four links are shown, each including a modulator, a photon path, and a photodetector. Each link can be part of a channel that also includes a serializer and a deserializer. Multiple channels can be bundled together in a single channel, which can be unidirectional or bidirectional.

[0132] Figure 8B An embodiment is shown having two OMIBs 831 and 832 coupled between a first die 811 and a second die 821. An optical engine 870 outputs carrier light to a beam splitter tree SPT, which can split light among multiple optical paths leading to modulators MOD1-4 associated with one or more photonic channels. For example, a first bidirectional photonic channel may include links MOD1 / PD1 and MOD2 / PD2, and a second bidirectional photonic channel may include links MOD3 / PD3 and MOD4 / PD4.

[0133] Figure 9 This is a schematic diagram of an example system for communication from a die to an external device using WDM according to some implementations. In this example, the first die 910 and the external device are coupled via grating couplers GC and FAU (or any other device for an optical interface between fiber optics and photonic ICs) in OMIB 930, fiber optic cable 991, and external device optical interface 971.

[0134] The light engine 970 can be internal or external. The light engine 970 supplies the OMIB 930 with multiple wavelengths of light (e.g., between 2 and 16 wavelengths), as shown in the four wavelengths illustrated. b1、 b2, b3、 b4. Spectrometer Tree SPT (e.g., similar to...) Figure 8A The SPT (Special Perspective) can divide light into multiple wavelengths across multiple different channels or links located in different OMIBs or different PICs (e.g., two links, only one of which is fully shown). Wavelength is... b1、 b2, b3、 The carrier light of b4 is provided to optical modulator MOD1-4, which modulates four beams containing different portions of the information to be transmitted. A WDM multiplexer (MUX) combines these four beams into a single beam comprising four different wavelengths. The single beam is then transmitted to external device optical interface 971 via GC, FAU, and optical fiber 991.

[0135] Figure 10 The following are illustrated according to some embodiments. Figure 9 This is an example of the reverse channel in a WDM system. The external device optical interface 971 provides optical signals to the WDM demultiplexer (DEMUX) in the OMIB 930 via fiber optic cable 991, FAU, and GC. The WDM demultiplexer splits the optical signal into wavelengths of... b1、 b2, b3、 b4 has four independently modulated signals. These four signals are provided to photodetectors PD1-4 through their respective optical waveguides. Photodetectors PD1-4 are electrically connected to the first die 910 to provide information from external devices to the first die 910.

[0136] While the embodiments discussed above pertain to a photonic channel displaying four optical links in one direction and a WDM multiplexer receiving four different wavelengths, in other embodiments, two or more optical links and a WDM multiplexer receiving two or more different wavelengths can be used. Therefore, the WDM demultiplexer will output two or more different wavelengths corresponding to these alternative embodiments.

[0137] Using intra-OMIB and inter-OMIB photonic channels, typically including one or more links in each direction as described above, processors in a single-package EIC can be connected to an electro-optical network. The resulting network topology typically depends on the choice of die pairs coupled via the associated photonic channels; various example topologies are known in the art. Note that while this document generally refers to bidirectional photonic channels, which offer greater flexibility in network architecture for implementing ML and other computational models compared to unidirectional photonic channels, electro-optical networks can in principle be formed using unidirectional photonic channels, and such networks can retain any of the benefits discussed herein (e.g., power savings due to the transmission of photonic data over longer distances).

[0138] As previously described, a photonic channel comprises at least two sets of one or more unidirectional links capable of forming a bidirectional channel. Examples of such channels include, but are not limited to, photonic channels between two dies when bridged via OMIB, and photonic channels between the OI on the OMIB and the external device optical interface. The nature of the external device optical interface can vary, as long as it has the optical capability to receive messages transmitted from the OMIB and / or transmit messages that can be received and used by the OMIB or any die using the OMIB as a bridge.

[0139] Messages can be in the form of data packets of varying sizes. Figure 11 An example unidirectional logical channel 1100 comprising multiple photonic links is illustrated. Logical channel 1100 has an input link 1101, a transmit binding engine 1102, photonic paths 1103A-D, a receive binding engine 1104, and an output link 1105. Transmit binding engine 1102 can split incoming data packets and add sequence information on an active photonic link. Receive binding engine 1104 uses the sequence information to reassemble data packets. In the described example, data arrives at the receive binding engine via four links.

[0140] Figure 12 It shows Figure 11 The transmission of an eight-word example message in a unidirectional logical channel 1100. This message includes words W0-W7. The transmitting binding engine 1102 splits these words on four active photonic links. For example, the first link transmits words W0 and W4. The second link transmits words W1 and W5, and so on. The transmitting binding engine 1102 adds sequence information to each part of the message, and the receiving binding engine 1104 reassembles the complete message at its output. Binding can allow the construction of high-bandwidth, low-latency channels from multiple lower-bandwidth links and can provide the ability to avoid invalid links.

[0141] Figure 13 The example AMS block is shown in more detail. Figure 13 The AMS transmit block 1310A of the first die and the AMS receive block 1320A of the second die are shown. For simplicity, the AMS receive block 1315 of the first die and the AMS transmit block 1328 of the second die are not described in detail. Each of the AMS blocks 1310A and 1320A can be connected to the OMIB 1330 via one or more electrical interconnects (only interconnect 1314 of the AMS transmit block 1310A and interconnect 1321 of the AMS receive block 1320A are shown herein). Figure 13As shown, each link in the photonic channel includes an optical transmitting unit Tx, an optical receiving unit Rx, and an optical transmission medium (e.g., an optical waveguide or optical fiber) connecting the transmitting unit to the receiving unit. In this case, AMS transmitting block 1310A is coupled to AMS receiving block 1320A, and AMS transmitting block 1335 is coupled to AMS receiving block 1336. The transmitting unit (e.g., transmitting unit 1331) includes an optical modulator (e.g., modulator 1333) and an electrical serializer (e.g., serializer 1313). The optical modulator transmits messages onto an optical signal by modulating carrier light output from optical engine 1370, and the electrical serializer converts electronic messages received in the form of parallel data words into signals suitable for driving the optical modulator. The receiving unit (e.g., receiving unit 1332) includes a photodetector (e.g., photodetector 1334) for converting optical signals received through the transmission medium back into electrical signals, electronics including a transimpedance amplifier (e.g., TIA 1322) for normalizing signal levels and gain control (e.g., gain control 1323), a limiter (e.g., limiter 1324) for extracting the bitstream, and a deserializer (e.g., deserializer 1325) for converting received messages back into parallel data. The AMS transmitting block 1310A also includes a transmit binding engine 1312 that can split messages from the first interface 1311, as referenced... Figure 11 As detailed, AMS receive block 1320A includes receiving messages from binding engine 1326 to reassemble the second interface 1327, as referenced. Figure 12 As detailed above, the OMIB 1330 may also include a receiver block 1336 that interfaces with the AMS receiver block 1315, a transmitter block 1335 that interfaces with the AMS transmitter block 1328, an optical engine 1370, an optical interface OI1, and an optical interface OI2.

[0142] In one implementation, the information is modulated at a rate of 56 Gb / s in non-return-to-zero (NRZ) code form, but more spectrally efficient modulation schemes, such as PAM-4 or PAM-8 or higher-order pulse amplitude modulation, can be used to achieve a link with higher bandwidth and lower latency.

[0143] Figure 14AAn arrangement of three OMIBs bridging portions of two dies is shown. OMIB 1430A bridges two computing elements 1411 in the first die 1410, a first portion of the central region 1412 in the first die 1410, two computing elements 1421 in the second die 1420, and a first portion of the storage region 1422 in the second die 1420. OMIB 1430B bridges the two computing elements 1421 in the second die 1420 and a second portion of the storage region 1422 in the second die 1420. OMIB 1430C bridges the two computing elements 1411 in the first die 1410, a second portion of the central region 1412 in the first die 1410, two computing elements 1421 in the second die 1420, and a third portion of the storage region 1422 in the second die 1420. A central region 1412 is located at the center of the first die 1410 to balance the latency between computing elements 1411 and the central region 1412. The central region 1412 may include memory, cache memory, other shared memory, on-chip network crossbar switches, switches, routing mechanisms, and a memory controller. A memory region 1422 is located at the center of the second die 1420 to balance the latency between computing elements 1421 and the memory region 1422. The memory region 1422 may include cache memory, other shared memory, and a memory controller. The die portion bridged by the OMIB has 10 computing elements and 2 memory regions. Additional OMIBs (not shown) may be located on opposite sides of the first die 1410 and the second die 1420 to bridge additional dies, computing elements, and portions of the memory regions. This arrangement allows data packets to be optically routed from the external device optical interface 1471 to an AMS block that is close to the memory being used or accessed and close to a location where computing elements 1411 or 1421 can perform one or more computations on data in the memory region. The ability of the OMIB to carry instructions from any computing element or external device, such as using data packets carried as photonic signals through the OMIB to the interior of one of the dies 1410 or 1420, to load or store data in memory region 1422 and / or to process data using computing elements 1411 or 1421 located near the central region 1412 or memory region 1422, solves many problems of stranded memory and / or delays introduced when optical signals cannot extend beyond the edges of the dies 1410 or 1420.

[0144] The AMS transmit and receive blocks can transmit optical signals from the optical interface of any external device connected to the OMIB via an inter-OMIB link, or from the AMS transmit and receive blocks having inter-OMIB connections within the bridge, to the central region of any die (e.g., to a memory controller to access memory in the central region). The OIs of each OMIB can also be connected via fiber optic cables, although this is not required. A first side (e.g., the right side) of the AMS transmit block 1413 or AMS receive block 1414 is aligned with a first side (e.g., the right side) of the central region (e.g., central region 1412). The first side of the central region is close to and / or in contact with computing elements 1411 such as CPUs, GPUs, TPUs, etc. A second side (e.g., the left side) of the AMS transmit block 1413 or AMS receive block 1414 is aligned with the left side of the OMIB. The lateral alignment is approximate and does not need to be precise, but typically, the alignment is in at least two dimensions to allow adjacency between optical and electrical elements in the OMIB and AMS blocks, respectively.

[0145] Figure 14B An example arrangement of five dies 1430-1434 bridged by OMIBs is shown. Using this arrangement with package 1440, bridges can be added indefinitely in both dimensions as needed. In this configuration, each OMIB has two interconnect regions for attaching dies. L2 caches or other memory regions can be located and / or fabricated in the central portion of the die, allowing optical access to the memory regions from within the die (rather than at the edges), resulting in lower latency. Optical channels can also be provided between OMIBs, such as connecting two OMIBs via fiber optic cables. OIs can be located in offset regions of the OMIBs. Figure 14B The arrangement can extend infinitely in the x and y directions. Furthermore, Figure 14B The arrangement allows for multi-hop routing in the diagonal direction, which significantly further reduces routing latency.

[0146] Figure 14C An example arrangement of dies 1413-1417 bridged by OMIB and bridge 1419 is shown. In some embodiments, OMIB and bridge are combined in a single die.

[0147] As shown below, one OMIB can bridge four dies. For example, an OMIB can be used to bridge dies vertically and horizontally, so that the four interconnect regions on each OMIB correspond to the four AMS blocks on their respective dies. OMIBs in this arrangement can provide channels in six directions, including two horizontal, two vertical, and two diagonal directions.

[0148] Figure 14DAn offset checkerboard pattern is shown for example OMIB-bridged dies (1410, 1418) in two dimensions. Each OMIB has four interconnect regions and is capable of bridging four dies using six links (2 vertical links, 2 horizontal links, and 2 diagonal links), representing 6 die-to-die interconnections on each OMIB. Some dies (e.g., die 1418) may include memory regions. The AMS block can interface with memory regions as well as any processing elements and other logic. Note that... Figure 14D This may not be drawn to scale. An OMIB with dimensions similar to the dimensions of the bridged die can reach an AMS block near the center of the die. Furthermore, the AMS block can be much smaller than shown in the example, and each die and each OMIB can have more than four interconnect regions.

[0149] Figure 15 This is a flowchart of an example method 1500 for manufacturing an OMIB according to various implementations. Method 1500 includes the following operations.

[0150] Operation 1510 – Fabrication of a bridge comprising a photonic link from a first interconnect region to a second interconnect region, wherein the photonic link includes a first electrical interconnect, a modulator coupled to the first electrical interconnect, an optical transmission medium coupled to the modulator, a photodetector coupled to the optical transmission medium, and a second electrical interconnect. In some embodiments, the modulator is configured to achieve temperature stabilization by applying a stabilizing voltage to the modulator, wherein the stabilizing voltage is related to the die temperature, and wherein the stabilizing voltage causes a change in electrical absorption in the modulator.

[0151] Operation 1520 - Locate interconnect regions to enable electrical interconnection and / or adjacency coupling with AMS blocks in the die.

[0152] Operation 1530 - Create OMIB internal connections between interconnect regions.

[0153] Operation 1540 - Creates an OMIB connection between two interconnect regions and an optical interface.

[0154] Figure 16Components of an example system 1600 that can use one or more OMIBs are shown. Each component or group of components may include an AMS block and an interface for coupling with one or more OMIBs. For example, system 1600 may include display device interface circuitry, such as connectors and drivers to which display device 1606 may be coupled. In this case, display device 1606 does not necessarily need to be integrated into system 1600 or become a component of system 1600. Similarly, system 1600 may not have audio input device 1624 or audio output device 1608, but may have audio input or output device interface circuitry (such as connectors and support circuitry) for coupling to external audio input or external audio output devices.

[0155] System 1600 may include one or more processing devices 1602. Processing device 1602 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), tensor processing units (TPUs), AI accelerators, fixed-gate programmable arrays (FPGAs), load / store units (LDSUs), neural computing engines (NCEs), dot product and / or convolution engines, server processors, or any other suitable processing devices. System 1600 may include memory 1604, which itself may include one or more memory devices, such as volatile memory, non-volatile memory, flash memory, solid-state memory, and / or hard disk drives, including but not limited to: random access memory (RAM) devices (such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, or conductive bridged RAM (CBRAM) devices), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), NAND flash memory, solid-state drive (SSD) memory, NOR flash memory, CMOS memory, thin-film transistor-based memory, phase-change memory (PCM), storage class memory (SCM), magnetoresistive memory (MRAM), resistive RAM, DRAM, high-bandwidth memory (HBM), DDR-based DRAM, and DIMM memory. In some embodiments, memory 1604 may include memory that shares a die with processing device 1602. This memory may be used as a buffer memory and may include embedded dynamic RAM or spin-transfer torque magnetic RAM.

[0156] In some implementations, system 1600 may include a communication chip 1612. For example, communication chip 1612 may be configured to manage wireless communication for transmitting data to and from devices and slave devices.

[0157] The 1612 communication chip can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as “3GPP2”), and others). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are often referred to as WiMAX networks, an abbreviation for Global Interoperability for Microwave Access, and are a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The 1612 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 1612 can operate according to GSM Evolution (EDGE) Enhanced Data, GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1612 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Wireless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivative protocols, as well as any other wireless protocol designated as 3G, 4G, 5G, and above. In other embodiments, the communication chip 1612 can operate according to other wireless protocols. The system 1600 may include an antenna 1622 to facilitate wireless communication and / or receiving other wireless communications (e.g., AM or FM radio transmissions).

[0158] In some embodiments, the communication chip 1612 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet or USB). As described above, the communication chip 1612 may include multiple communication chips. For example, a first communication chip 1612 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1612 may be dedicated to long-range wireless communications such as EDGE, GPRS, CDMA, WiMAX, LTE, or EV-DO. In some embodiments, the first communication chip 1612 may be dedicated to wireless communications, and the second communication chip 1612 may be dedicated to wired communications.

[0159] System 1600 may include a battery / power circuit 1614. The battery / power circuit 1614 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of system 1600 to an external power source (e.g., AC line power). System 1600 may include a display device 1606 (or a corresponding interface circuit, as described above). The display device 1606 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, flat panel display, virtual reality headset, augmented reality headset, etc. System 1600 may include an audio output device 1608 (or a corresponding interface circuit, as described above). The audio output device 1608 may include any device that generates auditory indicators, such as a speaker, headphones, earbuds, vibrating elements, piezoelectric crystals, etc. System 1600 may include an audio input device 1624 (or a corresponding interface circuit, as described above). Audio input device 1624 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., an instrument with a pickup or instrument digital interface (MIDI) output).

[0160] System 1600 may include a positioning device 1618 (or corresponding interface circuitry) such as that based on Global Positioning System (GPS), Galileo, GLONASS, BeiDou, IRNSS, NavIC, and / or QZSS. As known in the art, positioning device 1618 may communicate with satellite-based systems and may receive the location of system 1600. System 1600 may include another output device 1610 (or corresponding interface circuitry, as described above). Examples of other output devices 1610 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices. System 1600 may include another input device 1620 (or corresponding interface circuitry, as described above). Examples of another input device 1620 include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices (such as mice), styluses, touchpads, barcode readers, quick-response (QR) code readers, any sensor, or radio frequency identification (RFID) readers.

[0161] System 1600 can have any desired form factor, such as handheld or mobile devices (e.g., mobile phones, smartphones, tablets, laptops, Internet of Things (IoT) devices, netbooks, ultrabooks, mobile internet devices, music players, personal digital assistants (PDAs), ultra-mobile PCs, and others), desktop electronic devices, server equipment or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control panels, vehicle control units, digital cameras, digital video recorders, or wearable electronic devices. In some embodiments, system 1600 can be any other electronic device that processes data.

[0162] thermal behavior

[0163] The close spacing and adjacency of EIC and PIC chips (less than 2 mm, typically within 50 micrometers) present thermal challenges for OMIB. Depending on the type of modulator used, the operating temperature range within specifications can be less than 30 degrees Celsius. However, the die temperature of the EIC can vary significantly depending on ambient temperature, load conditions, supply voltage, and other factors. Modulator types include Mach-Zehnder interferometers (MZI), ring modulators, and electroabsorption modulators (EAM). Ring modulators have a very narrow temperature range (less than 1 degree Celsius), while MZI and EAM can have operating ranges exceeding 30 degrees Celsius. Modulator temperature and bias voltage both affect the frequency (wavelength) at which the modulator efficiency reaches its peak. The laser wavelength may be unaffected by these parameters or affected differently. Therefore, temperature variations will cause a difference between the laser wavelength and the modulator's efficiency peak wavelength, thus affecting the modulation depth.

[0164] Implementations may include a modulator that is inherently optimal within a desired temperature range. Alternatively, implementations may provide temperature compensation, including temperature sensing or predictive capabilities. Temperature compensation may be fully integrated into the OMIB, or partially integrated into the OMIB and partially integrated into the interconnect die.

[0165] Figures 17A-17D An example of an EIC / OMIB combination is shown, which employs temperature compensation to widen the temperature range of the modulator in the OMIB. Figure 17AAn EIC 1710 is shown, which is physically and electrically coupled to a PIC 1720 (e.g., OMIB) via a metal interconnect (such as bumps or copper pillars). The EIC 1710 includes a driver DRV 1711 and a temperature element TE 1712. TE 1712 may include a temperature sensor, a temperature predictor, or both (the temperature predictor predicts the die or PIC temperature based on processor load conditions known in its software or firmware). In some embodiments, the temperature sensor is located less than two millimeters (2 mm) from the DRV 1711. In other embodiments, the temperature sensor is located less than 50 micrometers (50 μm) from the DRV 1711. The driver DRV 1711 delivers a high data rate modulated signal to the modulator 1721 in the PIC 1720. The TE 1712 provides a low-frequency (compared to the data rate) temperature-dependent bias voltage to the MOD 1721. If the temperature dependence of the bias voltage is inversely matched to the temperature dependence of the modulator over an extended temperature range, it will eliminate the effect of temperature on modulator performance over that extended temperature range. In other embodiments, the TE 1712 includes a lookup table to convert the measured or predicted temperature into a temperature-compensated modulator bias voltage.

[0166] exist Figure 17B In this configuration, EIC 1730 is physically and electrically connected to PIC 1740 (e.g., OMIB). EIC 1730 includes a driver DRV 1731, a temperature element TE 1732, and an adder 1733. PIC 1740 includes a modulator MOD 1741. Adder 1733 adds a low-frequency temperature-dependent bias voltage from TE 1732 to a high-data-rate modulated signal from DRV 1731 and forwards it to MOD 1741. In some implementations, TE 1732 includes a lookup table to convert the measured or predicted temperature into a temperature-compensated modulator bias voltage.

[0167] exist Figure 17C In this configuration, the EIC 1750 is physically and electrically connected to the PIC 1760 (e.g., OMIB). The EIC 1750 includes a driver 1751, while the PIC 1760 (e.g., OMIB) includes a modulator MOD 1761 and a temperature sensor TS 1762. The TS 1762 is located close to the MOD 1761 and provides a temperature-dependent bias voltage to the MOD 1761. Over an extended temperature range, the temperature dependence of the bias voltage is inversely matched to the temperature dependence of the MOD 1761, thereby extending its operating temperature range.

[0168] exist Figure 17DIn this configuration, the EIC 1770 is physically and electrically connected to the PIC 1780 (e.g., OMIB). The PIC 1780 includes a modulator MOD 1781 and a temperature sensor TS 1782. The TS has a temperature sensor output configured to be coupled to external circuitry of the PIC 1780 (e.g., the EIC 1770). The EIC 1770 includes a driver DRV 1771, a temperature controller TC 1772, and an adder 1773. The TC 1772 is configured to receive a first temperature-dependent signal from external circuitry of the EIC 1770 (e.g., from TS 1782 in the PIC 1780). The TC 1772 converts the first temperature-dependent signal into a temperature-dependent bias voltage whose temperature dependence is opposite to that of the MOD 1781 over an extended temperature range. The TC 1772 can perform the conversion using temperature-linear and temperature-nonlinear analog circuitry. Alternatively or additionally, TC 1772 can use digital circuitry to perform the conversion to access the memory 1774 storing the temperature profile. TC 1772 may be included in the temperature element TE (such as...). Figure 17B (TE 1732 in the example). In some implementations, TC 1772 includes a lookup table to convert the measured or predicted temperature into a temperature-compensated modulator bias voltage.

[0169] Some modulators can provide stable operation over a wide modulation temperature range of optical components, for example, when integrated into an OMIB, even without added temperature compensation. Modulators can utilize the Franz-Keldysh effect to achieve inductive changes in optical absorption. A variety of materials can be used in the modulator, including germanium and its alloys, silicon and its alloys, and group III-V materials (such as materials based on indium phosphide (InP) or gallium arsenide (GaAs) material systems). For example, one or more embodiments described herein relate to chip hardware that includes the features and functions of providing thermally stable optical modulation elements coupled to electronic components (e.g., drivers in an AMS transmit block). In one or more embodiments, the hardware is a device including electronic integrated circuits (EICs) and photonic integrated circuits (PICs). PICs can be electrically interconnected with EICs in a coupled or adjacent manner. Each transmit unit may include a thermally stable optical modulator located in a portion of the PIC. Data can be optically moved within the PIC via an optical carrier located between one of the thermally stabilized optical modulators in a first section of the OMIB and one of the receiving units in or interconnected with a second section of the OMIB. In one or more embodiments, the thermally stabilized optical modulator operates over a temperature range greater than thirty degrees Celsius. In this example, the thermally stabilized optical modulator may also comprise a material selected from germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more embodiments, the optical modulator is an electro-absorption modulator (EAM) that uses the Franz-Keldish effect for induced charges in optical absorption.

[0170] In one or more embodiments, the thermally stable optical modulator is an EAM operating over a temperature range of less than 30 degrees Celsius. In this example, the thermally stable optical modulator may include (e.g., comprise) materials selected from germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more embodiments, the thermally stable optical modulator uses the quantum confinement Stark effect (QCSE) to achieve an inductive change in optical absorption. In one or more embodiments, the thermally stable optical modulator has a high optical modulation amplitude output. In this example, the thermally stable optical modulator may include materials selected from germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more embodiments, the thermally stable optical modulator uses the quantum confinement Stark effect (QCSE) to achieve an inductive change in optical absorption. In one or more embodiments, the thermally stable optical modulator is configured to operate stably over a wide temperature range. In this example, the thermally stabilized optical modulator may include a material selected from germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more embodiments, the modulator uses the Franz-Keldish effect to achieve an inductive change in optical absorption.

[0171] manufacture

[0172] Figure 18 An example method 1800 for manufacturing a system is illustrated. Method 1800 includes step 1810, which includes a manufacturing system comprising a first die (integrated circuit), a second die (integrated circuit), a photonic IC providing bridging functionality, a light source, and a data channel. The photonic IC includes a first interconnect region, a second interconnect region, and an offset region. Pad patterns on the first integrated circuit match pad patterns in the first interconnect region, and pad patterns on the second integrated circuit match pad patterns in the second interconnect region. Two or more pads on the first integrated circuit are physically and electrically coupled to two or more pads in the first interconnect region, and two or more pads on the second integrated circuit are physically and electrically coupled to two or more pads in the second interconnect region. The light source is optically coupled to a first optical interface (first OI) in the offset region. The data channel includes a serializer and driver in the first integrated circuit, a modulator, a photonic path and a photodetector in the photonic IC, and a transimpedance amplifier and a deserializer in the second integrated circuit. The distance between the surface of the first integrated circuit and the surface of the photonic IC is less than 2 mm, and the distance between the surface of the second integrated circuit and the surface of the photonic IC is less than 2 mm. In many cases, the distance is less than 50 micrometers (50 At least one of two or more pads on the first integrated circuit may be located more than 100 micrometers (100 m) from the edge of the first integrated circuit. The position of the two or more pads on the second integrated circuit may be located more than 100 micrometers (m) from the edge of the second integrated circuit. The position (m) is specified. The modulator can be an electroabsorption modulator (EAM). The modulator can be a Mach-Zehnder interferometer (MZI). The first die or photonic IC can include a temperature sensor or temperature predictor capable of transmitting a temperature-dependent bias signal.

[0173] Precautions

[0174] Although specific embodiments have been described, these embodiments are illustrative only and not limiting. The description may refer to particular structural embodiments and methods and is not intended to limit the technology to the specifically disclosed embodiments and methods. The technology can be practiced using other features, elements, methods, and embodiments. The embodiments are described to illustrate the technology and not to limit its scope as defined by the claims. Those skilled in the art will recognize various equivalent variations of the above description.

[0175] For example, many examples in this document use grating couplers to couple optical fibers to photonic ICs. However, many implementations work well using other methods of optical interface between the optical fiber and the photonic IC, such as those described in the references. Figure 3 As described. Although many examples only show OMIB bridging the first and second dies, OMIB can bridge any number of dies. While most examples show AMS functionality included in the first and / or second dies, AMS functionality can be partially or fully included in separately stacked ICs, such as... Figures 5D-5E As shown. All such embodiments are within the scope and limits of this disclosure.

[0176] All features disclosed in the specification (including the claims, abstract, and drawings), and all steps in any disclosed method or process, may be combined in any combination, except for combinations in which at least some of such features and / or steps are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in the specification (including the claims, abstract, and drawings) may be replaced by an alternative feature for the same, equivalent, or similar purpose.

[0177] Although specific implementations have been described, these implementations are illustrative only and not limiting. For example, many operations can be implemented using readily available devices on a printed circuit board (PCB), in a system-on-a-chip (SoC), an application-specific integrated circuit (ASIC), a programmable processor, a coarse-grained reconfigurable architecture (CGRA), or in a programmable logic device such as a field-programmable gate array (FPGA), thereby avoiding the need for at least some of any dedicated hardware. Implementations can be as a single chip or as a multi-chip module (MCM) that packages multiple semiconductor dies in a single package. All such variations and modifications are considered to be within the scope of the technology disclosed herein, the nature of which is determined by the foregoing description.

[0178] Any technique suitable for manufacturing electronic devices can be used to implement circuits in a particular embodiment, including complementary metal-oxide-semiconductor (CMOS), fin field-effect transistors (FETs), bipolar CMOS, bipolar JFETs, MOS, NMOS, PMOS, HBTs, MESFETs, etc. Different semiconductor materials can be used (such as silicon, germanium, SiGe, GaAs, InP, GaN, SiC, graphene, etc.). The circuit can have single-ended or differential inputs and single-ended or differential outputs. The terminals of the circuit can be used as inputs, outputs, or both, or in a high-impedance state, or they can be used to receive power, ground references, reference voltages, reference currents, or others. Although the physical processing of signals can be presented in a specific order, this order can be changed in different specific embodiments. In some specific embodiments, multiple elements, devices, or circuits shown sequentially in this specification can operate in parallel.

[0179] Specific implementations can be carried out using programmable general-purpose digital computers, application-specific integrated circuits, programmable logic devices, field-programmable gate arrays, optical, chemical, biological, quantum, or nanoengineered systems, etc. Other components and mechanisms can be used. Generally, the functionality of a specific implementation can be achieved by any means known in the art. Distributed, networked systems, components, and / or circuits can be used. Data communication or transmission can be wired, wireless, or any other means.

[0180] It should also be understood that one or more elements shown in the accompanying drawings / figures may also be implemented in a more separate or integrated manner, or even removed or rendered inoperable in some cases, which may be useful depending on the specific application.

[0181] Therefore, although specific embodiments are described herein, the scope of modifications, variations, and substitutions intended in the foregoing disclosure should be understood. In some cases, certain features of a specific embodiment may be adopted without correspondingly using other features, without departing from the scope and spirit described. Thus, many modifications can be made to adapt specific situations or materials to the basic scope and spirit.

Claims

1. A bridge, comprising: This includes multiple interfaces with four interfaces, among which: Each interface is an electrical interface configured to electrically connect its respective die to the bridge. Each interface includes a serializer and a deserializer for connecting any bare die to the bridge via the interface; Photonic networks, in which: The photonic network includes directional photonic links from the serializer of each of the four interfaces to the deserializer of each of the remaining three interfaces, thereby providing six bidirectional photonic communication paths terminating at the four interfaces, and each of the four interfaces is bidirectionally coupled to each of the other four interfaces.

2. The bridge according to claim 1, wherein, The four interfaces are arranged in a two-dimensional manner, and the six communication paths are two horizontal paths, two vertical paths, and two diagonal paths.

3. The bridge according to claim 1, wherein, Each of the four interfaces includes a respective Analog / Mixed Signal (AMS) block, which includes the serializer and deserializer of the interface.

4. The bridge according to claim 1, wherein, The photonic links of the photonic network are implemented in a bridge substrate.

5. The bridge according to claim 4, wherein, The bridge substrate is an integrated circuit.

6. The bridge according to claim 5, wherein, Each AMS block is disposed on the bridge substrate.

7. The bridge of claim 1 further includes an optical interface coupled to the photonic network.

8. The bridge of claim 1, further comprising four bare dies, each bare die being connected to the bridge via its respective interface, wherein, The four dies include at least one die with a memory region.

9. The bridge according to claim 8, wherein, The four bare pieces are all rectangular and are adjacent to each other horizontally or diagonally.

10. The bridge according to claim 8, wherein, All four bare dies are electrically coupled to the bridge.

11. The bridge according to claim 8, wherein, The four bare dies are all electrically connected to their respective AMS blocks via electrical paths in the bridge.

12. The bridge according to claim 4, wherein, The four interfaces are arranged in a two-dimensional manner, and the six communication paths are two horizontal paths, two vertical paths, and two diagonal paths.

13. The bridge according to claim 4, wherein, Each of the four interfaces includes a respective Analog / Mixed Signal (AMS) block, which includes the serializer and deserializer of the interface.

14. The bridge according to claim 4, wherein, The photonic links of the photonic network are implemented in a bridge substrate.

15. The bridge according to claim 5, wherein, The four interfaces are arranged in a two-dimensional manner, and the six communication paths are two horizontal paths, two vertical paths, and two diagonal paths.

16. The bridge according to claim 5, wherein, Each of the four interfaces includes a respective Analog / Mixed Signal (AMS) block, which includes the serializer and deserializer of the interface.

17. The bridge according to claim 5, wherein, The photonic links of the photonic network are implemented in a bridge substrate including an integrated circuit.

18. The bridge according to claim 8, wherein, The four interfaces are arranged in a two-dimensional manner, and the six communication paths are two horizontal paths, two vertical paths, and two diagonal paths.

19. The bridge according to claim 8, wherein, Each of the four interfaces includes a respective Analog / Mixed Signal (AMS) block, which includes the serializer and deserializer of the interface.

20. The bridge according to claim 8, wherein, The photonic links of the photonic network are implemented in a bridge substrate including an integrated circuit.

21. The bridge of claim 8 further includes an optical interface coupled to the photonic network.

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