Semiconductor process method and semiconductor structure

Abstract

The invention provides a semiconductor process method and a semiconductor structure. The method comprises the following steps: aligning, exposing and developing through an alignment mark on a substrate to obtain a graphical first photoresist layer; forming a first conductive layer in a gap of the first photoresist layer; arranging a metal reflection compensation layer which does not shield the alignment mark; a patterned second photoresist layer is obtained after exposure and development; and forming a second conductive layer in a gap of the second photoresist layer to obtain a double-layer conductive device structure. The metal reflection compensation layer is introduced into the exposure process, exposure parameters are compensated, dynamic errors are reduced, the accuracy and reliability of exposure focus measurement and focal plane selection are improved, the precision of patterns obtained by the exposure process is improved, and the optical performance of photoresist is optimized in a collaborative mode; in addition, the metal reflection compensation layer improves the leveling effect of the light resistance exposure focal plane of the high aspect ratio structure, and is suitable for various high-precision exposure process focusing; and finally, a proper material of the metal reflection compensation layer is arranged, and the focusing optimization effect of the exposure process is further optimized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a semiconductor process method and semiconductor structure. Background Technology

[0002] In semiconductor lithography, during exposure by the lithography machine, minute undulations on the wafer surface, such as uneven photoresist thickness, substrate surface flatness deviations, or lens thermal expansion caused by temperature changes, can all lead to focus drift. If this defocus is not compensated for in real time, it will directly cause pattern transfer distortion, deterioration of critical dimension (CD) uniformity, and even a decrease in device yield. To address this, modern lithography machines generally integrate a Focus & Leveling System (FLS), which measures the wafer surface height in real time and quickly adjusts the Z-axis position of the stage to ensure that the exposed surface is always within the depth of focus (DOF) range of the lens.

[0003] Taking ASML lithography machines as an example, they employ a laser interferometer to perform multi-point scanning of the wafer surface height, achieving sub-nanometer accuracy. Subsequently, a piezoelectric actuator (PZT) drives the wafer stage, completing Z-axis compensation within milliseconds with an accuracy of ±10nm. Furthermore, an autofocus module (AF) performs closed-loop correction for focus drift caused by slow changes such as temperature gradients and lens thermal expansion, ensuring the entire wafer maintains optimal focus throughout the scanning and exposure process.

[0004] However, in traditional photolithography, the strong reflection of the illumination beam by metal or polycrystalline silicon films causes a standing wave within the photoresist, which overlaps with the surface-reflected light, resulting in reflection overlap. This phenomenon makes it difficult to accurately obtain the true morphology of the device structure during in-line metrology, thus affecting the feedback accuracy of FLS and AF, and becoming one of the bottlenecks in achieving high-precision focus compensation.

[0005] Therefore, there is an urgent need for a structure or method that can optimize the leveling and focusing accuracy during the exposure process of photolithography.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the purpose of this invention is to provide a semiconductor process method and semiconductor structure to solve the problem of limited leveling and focusing accuracy in the exposure process of photolithography in the prior art.

[0008] To achieve the above objectives, the present invention provides a semiconductor process method, the semiconductor process method comprising:

[0009] A substrate structure is provided, wherein alignment marks are provided on the upper surface of the substrate structure;

[0010] A first photoresist layer is formed on the substrate structure to obtain a first intermediate structure;

[0011] After aligning the position using the alignment marks, the first photoresist layer of the first intermediate structure is exposed and developed to obtain a patterned first photoresist layer.

[0012] A metal layer is disposed in the gap between the patterned first photoresist layers to form a patterned first conductive layer, thereby obtaining a second intermediate structure;

[0013] A metal reflection compensation layer is provided on the second intermediate structure so that the metal reflection compensation layer does not block the corresponding position above the alignment mark, thus obtaining a third intermediate structure;

[0014] A second photoresist layer is formed on the third intermediate structure to obtain a fourth intermediate structure;

[0015] After aligning the position using the alignment marks, the second photoresist layer of the fourth intermediate structure is exposed and developed to obtain a patterned second photoresist layer.

[0016] A metal layer is disposed in the gap between the patterned second photoresist layers to form a patterned second conductive layer, thereby obtaining a double-layer conductive device structure.

[0017] Optionally, before setting the metal reflection compensation layer, a patterned hard mask is set on the second intermediate structure, the patterned hard mask covering the corresponding position above the alignment mark; after setting the metal reflection compensation layer, the patterned hard mask is removed so that the metal reflection compensation layer does not obscure the corresponding position above the alignment mark.

[0018] Alternatively, before setting the metal reflection compensation layer, no patterned hard mask was set on the second intermediate structure; after setting the metal reflection compensation layer, a blind exposure process was used to perform window etching on the position above the alignment mark of the metal reflection compensation layer according to the graphic design of the alignment mark, so that the metal reflection compensation layer does not block the corresponding position above the alignment mark.

[0019] Optionally, when setting the metal reflection compensation layer, the entire surface of the metal reflection compensation layer is directly set on the second intermediate structure; or, when setting the metal reflection compensation layer, a patterned metal reflection compensation layer is set on the second intermediate structure through a preset compensation hard mask layer, and then the compensation hard mask layer is removed.

[0020] Optionally, the thickness of the metal reflective compensation layer is not less than 10 nanometers.

[0021] Optionally, the metal reflective compensation layer is at least one of Au, Ni, TiW, or Ti.

[0022] Optionally, before exposing the second photoresist layer of the fourth intermediate structure, an interferometric topography is used to obtain a full-field surface height distribution map of the fourth intermediate structure. During the exposure process, the actual height of the second photoresist layer at the corresponding position is obtained by flash measurement using an image focus sensor. Combined with the full-field surface height distribution map obtained by interferometric topography, optical path difference conversion is performed to calculate the effective defocus amount at the corresponding position. The obtained effective defocus amount is then used for dynamic leveling and focusing during the exposure of the second photoresist layer.

[0023] Optionally, before exposing the first photoresist layer of the first intermediate structure, the full-field surface height distribution map of the first intermediate structure is obtained by interference topography. During the exposure process, the actual height of the first photoresist layer at the corresponding position is obtained by flash measurement using an image focus sensor. Combined with the full-field surface height distribution map obtained by interference topography, optical path difference conversion is performed to calculate the effective defocus amount at the corresponding position. The obtained effective defocus amount is used to dynamically level and focus the first photoresist layer during the exposure process.

[0024] Optionally, the aspect ratio of the patterned first conductive layer and the patterned second conductive layer is not less than 3:1.

[0025] Optionally, after obtaining the second intermediate structure, before setting the metal reflection compensation layer, the surface of the second intermediate structure is planarized.

[0026] The present invention also provides a semiconductor structure, which is obtained by any of the semiconductor process methods described above, and the semiconductor structure includes at least:

[0027] A substrate structure, wherein alignment marks are provided on the upper surface of the substrate structure;

[0028] A first conductive layer, the first conductive layer being patterned and located on the substrate structure;

[0029] A metal reflection compensation layer, wherein the metal reflection compensation layer is located at a predetermined position on the surface of the first conductive layer;

[0030] A second conductive layer, graphically represented, is located on the second conductive layer and the metal reflection compensation layer covering the second conductive layer.

[0031] As described above, the semiconductor process method and semiconductor structure of the present invention have the following beneficial effects:

[0032] This invention improves the surface uniformity of the overall device before exposure by introducing a metal reflection compensation layer into the semiconductor exposure process. It compensates for the reflection intensity caused by reflection overlap, optimizes diffraction data, and achieves adjustment and optimization of the surface morphology and flatness of the substrate. This allows for rapid and accurate compensation of the exposure parameter range, reduces dynamic errors, and solves the problem that complex surface structures cannot automatically compensate for exposure focusing and leveling processes due to dynamic scattering, low integrity, and beam damage. It also improves the flattening of the exposure focal plane of the substrate device structure, normalizes the focal plane, effectively improves the accuracy and reliability of exposure focus measurement and focal plane selection, achieves better focusing effect, improves the pattern obtained by the semiconductor exposure process and the fabrication accuracy of the device, and effectively reduces the impact of process fluctuations on the focusing and leveling system.

[0033] This invention optimizes the focusing effect by setting a metal reflection compensation layer, further improving the optical performance of the photoresist, reducing reflectivity, and minimizing interference from reflected light. This, combined with surface morphology adjustment, enhances the device exposure process and achieves compatibility with existing processes.

[0034] This invention utilizes a metal reflective compensation layer to optimize the focusing effect of the exposure process, which can significantly improve the focal plane leveling effect during the yellow light exposure process of photoresist with high aspect ratio structures, thus making it suitable for focusing in the yellow light exposure process of various high-precision dual-layer photoresist devices.

[0035] This invention further optimizes the surface smoothing effect of the metal reflection compensation layer on the substrate by setting a suitable material for the metal reflection compensation layer, thereby improving the focusing optimization effect on the exposure process. Attached Figure Description

[0036] Figure 1 The diagram shows a focus drift pattern in the prior art.

[0037] Figure 2This is a schematic diagram showing the depth of focus corresponding to defocusing and focusing during focusing and leveling in the prior art.

[0038] Figure 3 This is a schematic diagram of the overall exposure structure during the focusing process in the prior art.

[0039] Figure 4 This diagram illustrates the reflection and overlap of exposure light in a double-layer photoresist in the prior art.

[0040] Figure 5 The diagram shows a schematic representation of the substrate structure provided in step 1 of the semiconductor process method according to Embodiment 1 of the present invention.

[0041] Figure 6 The diagram shows the structure of the first photoresist layer in step 2 of the semiconductor process method according to Embodiment 1 of the present invention.

[0042] Figure 7 This is a schematic diagram of the structure presented in step 3 of the semiconductor process method of Embodiment 1 of the present invention when the first photoresist layer is exposed.

[0043] Figure 8 The diagram shows the structure after the first photoresist layer has been exposed and developed in step 3 of the semiconductor process method of Embodiment 1 of the present invention.

[0044] Figure 9 The diagram shows the structure after the metal layer is set in step 4 of the semiconductor process method of Embodiment 1 of the present invention.

[0045] Figure 10 The diagram shows the structure of the metal reflection compensation layer in step 5 of the semiconductor process method of Embodiment 1 of the present invention.

[0046] Figure 11 The diagram shows the structure of the second photoresist layer in step 6 of the semiconductor process method of Embodiment 1 of the present invention.

[0047] Figure 12 This is a schematic diagram of the structure presented in step 7 of the semiconductor process method of Embodiment 1 of the present invention when the second photoresist layer is exposed.

[0048] Figure 13 The diagram shows the structure after the second photoresist layer is exposed and developed in step 7 of the semiconductor process method of Embodiment 1 of the present invention.

[0049] Figure 14 The diagram shows the structure of the semiconductor process method in embodiment 1 of the present invention, specifically step 8, in which a metal layer is formed.

[0050] Figure 15The image shown is a magnified micrograph of a double-layer electrode structure obtained after exposure and development using existing semiconductor processing methods.

[0051] Figure 16 The image shown is a magnified micrograph of the double-layer electrode structure obtained after step 8 of the semiconductor process method in Embodiment 1 of the present invention.

[0052] Figure 17 The image shown is a magnified three-dimensional micrograph of an electrode structure with a single-layer aspect ratio, as described in the prior art.

[0053] Figure 18 The image shown is a magnified top view of the double-layer high aspect ratio electrode structure obtained after step 8 of the semiconductor process method of Embodiment 1 of the present invention.

[0054] Figure 19 Shown is a magnified three-dimensional microscopic view of a double-layer electrode structure with a high aspect ratio obtained after step 8 of the semiconductor process method of Embodiment 1 of the present invention.

[0055] Explanation of icon numbers:

[0056] 11. Lens group; 12. Exposure light; 13. Exposure plane; 14. Stage; 15. Wafer; 16. Quartz; 17. Mask; 18. Photoresist; 19. Electrode;

[0057] 21. Substrate structure; 22. First photoresist layer; 23. Gap; 24. First conductive layer; 25. Metal reflection compensation layer; 26. Second photoresist layer; 27. Second conductive layer. Detailed Implementation

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0060] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0061] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0062] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. The quantity range given in the present invention includes the two boundary values ​​of the quantity range by default unless otherwise specified.

[0063] In semiconductor photolithography, during the exposure process, minute undulations on the wafer surface, such as uneven photoresist thickness, substrate surface flatness variations, or lens thermal expansion due to temperature changes, can all cause focus drift. Figure 1 Compared to the intermediate image, such as Figure 1 In the left and right images, the exposure light, after passing through the optical system (lens group 11), is not focused on the exposure plane 13. If this defocusing is not compensated for in real time, it will directly cause pattern transfer distortion, deterioration of critical dimension (CD) uniformity, and even a decrease in device yield. Therefore, modern lithography machines typically integrate a focus and leveling system (FLS), such as... Figure 2 As shown, this system utilizes real-time measurement of the wafer surface height, and as... Figure 3As shown, the Z-axis position of the stage 14, where the wafer 15 is placed, is rapidly adjusted, thereby adjusting the exposure surface 13 from a defocused state to always be within the depth of focus (DOF) range of the lens. This allows the exposure light 12 to be focused onto the corresponding position on the surface of the wafer 15 by multiple reticles / masks fixed on the quartz 16. Taking ASML lithography machines as an example, they use a laser interferometer to perform multi-point scanning of the wafer surface height, achieving sub-nanometer level detection accuracy. Subsequently, a piezoelectric actuator (PZT) drives the wafer stage, completing Z-axis compensation within milliseconds, with a compensation accuracy of ±10 nm. In addition, the autofocus module (AF) further performs closed-loop correction for focus drift caused by slow changes such as temperature gradient and lens thermal expansion, ensuring that the entire wafer maintains the optimal focal plane throughout the scanning exposure process. However, in traditional photolithography, the metal or polycrystalline silicon films have a strong reflective effect on the exposure beam, such as... Figure 4 As shown, the reflected light from the exposure light 12 and the incident light form a standing wave inside the photoresist 18, which superimposes with the surface reflected light, leading to reflection overlap. This phenomenon makes it difficult to accurately obtain the true morphology of the device structure during in-line metrology, thus affecting the feedback accuracy of the focusing and leveling system and the autofocus module. It particularly significantly impacts the patterning accuracy of the second photoresist layer 18 when fabricating the double-layer electrode 19 structure, becoming one of the bottlenecks in achieving high-precision focus compensation. To solve the above problems, this invention provides the following solution:

[0064] Example 1:

[0065] This embodiment provides a semiconductor process method, the semiconductor process method comprising:

[0066] Step 1: Provide a substrate structure, wherein the upper surface of the substrate structure is provided with alignment marks;

[0067] Step 2: Deposit a first photoresist layer on the substrate structure to obtain a first intermediate structure;

[0068] Step 3: After aligning the positions using the alignment marks, expose and develop the first photoresist layer of the first intermediate structure to obtain a patterned first photoresist layer.

[0069] Step 4: Deposit a metal layer in the gap between the patterned first photoresist layers to form a patterned first conductive layer, thus obtaining the second intermediate structure;

[0070] Step 5: A metal reflection compensation layer is provided on the second intermediate structure so that the metal reflection compensation layer does not block the corresponding position above the alignment mark, thus obtaining the third intermediate structure;

[0071] Step 6: Deposit a second photoresist layer on the third intermediate structure to obtain the fourth intermediate structure;

[0072] Step 7: After aligning the positions using the alignment marks, expose and develop the second photoresist layer of the fourth intermediate structure to obtain a patterned second photoresist layer;

[0073] Step 8: Deposit a metal layer in the gap between the patterned second photoresist layers to form a patterned second conductive layer, thereby obtaining a double-layer conductive device structure.

[0074] The semiconductor process method of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the semiconductor process method protected by the present invention, and those skilled in the art can make changes according to the actual process steps.

[0075] First, proceed to step 1, as follows: Figure 5 As shown, a substrate structure 21 is provided, and an alignment mark (not shown in the figure) is provided on the upper surface of the substrate structure 21.

[0076] Specifically, the alignment mark is used for position alignment during subsequent photolithography processes on the first conductive layer 24 and the second conductive layer 27.

[0077] In one embodiment, the substrate structure 21 comprises, from bottom to top, a silicon substrate, an aluminum layer, an oxide insulating layer, and a seed layer. Specifically, the substrate structure 21 can also be other structures that require two consecutive layers of patterned metal formed by photolithography on top of it, all of which are within the scope of protection of this invention.

[0078] Then, proceed to step 2, as follows: Figure 6 As shown, a first photoresist layer 22 is formed on the substrate structure 21 to obtain a first intermediate structure.

[0079] Next, in step 3, after aligning the positions using the alignment marks, the first photoresist layer 22 of the first intermediate structure is applied as follows: Figure 7 The image shows exposure followed by development using exposure light 12, as shown. Figure 8 As shown, the patterned first photoresist layer 22 is obtained.

[0080] In one embodiment, before exposing the first photoresist layer 22 of the first intermediate structure, the full-field surface height distribution map of the first intermediate structure is obtained by interference topography. During the exposure process, the actual height of the first photoresist layer 22 at the corresponding position is obtained by flash measurement using an image focus sensor. Combined with the full-field surface height distribution map obtained by interference topography, optical path difference conversion is performed to calculate the effective defocus amount at the corresponding position. The obtained effective defocus amount is used to dynamically level and focus the first photoresist layer 22 during the exposure process.

[0081] Specifically, since the exposure process of the first photoresist layer 22 also requires interference topography mapping and image focus flash measurement to achieve leveling, focusing and autofocus operations, a similar approach to the present invention can be adopted before the exposure process of the first photoresist layer 22. A metal reflection compensation layer 25 can be set on the surface of the substrate structure 21 before setting the first photoresist layer 22 to optimize the exposure effect of the first photoresist layer 22. All of these are within the protection scope of the present invention.

[0082] Then, proceed to step 4, as follows: Figure 9 As shown, a metal layer is disposed in the gap 23 between the patterned first photoresist layers 22 to form a patterned first conductive layer 24, thus obtaining a second intermediate structure.

[0083] In one embodiment, the metal layer of the patterned first conductive layer 24 formed in step 4 is made of gold and has a thickness of 35 μm. Specifically, other suitable materials and thicknesses can also be selected for the metal layer, all within the scope of this invention.

[0084] In one embodiment, the aspect ratio of the patterned first conductive layer 24 is not less than 3:1.

[0085] In one embodiment, the aspect ratio of the patterned first conductive layer 24 can be as high as 7:1.

[0086] Specifically, when the pattern of the first conductive layer 24 is a high aspect ratio pattern, it is easier to generate reflection overlap in the exposure process, which makes it difficult to accurately level, focus and autofocus. Therefore, using a high aspect ratio first conductive layer 24 can better reflect the optimization effect of this solution on the photoresist exposure process of high aspect ratio patterns; however, other suitable aspect ratio patterns can also be used as the first conductive layer 24, all of which are within the protection scope of this invention.

[0087] Next, proceed to step 5, as follows: Figure 10As shown, a metal reflection compensation layer 25 is provided on the second intermediate structure so that the metal reflection compensation layer 25 does not block the corresponding position above the alignment mark, thus obtaining the third intermediate structure.

[0088] This invention introduces a metal reflection compensation layer 25 into the semiconductor exposure process to improve the surface uniformity of the overall device before exposing the second photoresist layer 26 in step 7. By compensating for the reflection intensity caused by reflection overlap, the diffraction data is optimized, thereby achieving adjustment and optimization of the substrate surface morphology and flatness. Based on this, it can quickly and accurately compensate for fluctuations in exposure parameters caused by factors such as exposure dose, development time, and photoresist thickness, reducing dynamic errors and solving the problem that the machine cannot automatically compensate for exposure focusing and leveling processes due to dynamic scattering, poor integrity, and beam damage on complex surface structures. This method can improve the flatness of the exposure focal plane of the substrate device structure, normalize the focal plane, effectively improve the accuracy and reliability of exposure focus measurement and die-by-die focal plane selection, achieve better focusing effects, improve the fabrication accuracy of the patterns and devices obtained by the semiconductor exposure process, and effectively reduce the impact of process fluctuations on the focusing and leveling system. Furthermore, the metal reflection compensation layer 25 optimizes the focusing effect while further improving the optical performance of the photoresist, reducing reflectivity, minimizing interference from reflected light, and working synergistically with surface morphology adjustment to enhance the device exposure process and achieve compatibility with existing processes. Moreover, the optimization of the focusing effect during the exposure process using the metal reflection compensation layer 25 significantly improves the focal plane leveling effect during the exposure of photoresist with high aspect ratio structures, making it suitable for focusing in the exposure process of various high-precision dual-layer photoresist devices.

[0089] In one embodiment, after obtaining the second intermediate structure, before setting the metal reflection compensation layer 25, the surface of the second intermediate structure is planarized.

[0090] The present invention performs planarization treatment on the surface of the second intermediate structure before the metal reflection compensation layer 25 is set, thereby further optimizing the overall surface flatness after the metal reflection compensation layer 25 is set, further reducing the interference of reflected light on the accuracy of the leveling and focusing process, and improving the pattern accuracy of the first photoresist layer 22 obtained after the exposure process in conjunction with the setting of the metal reflection compensation layer 25.

[0091] In one embodiment, the planarization treatment of the surface of the second intermediate structure is performed by chemical mechanical polishing (CMP) using a soft-bristled polishing pad. Preferably, the weight of the polishing head and the added weight is controlled within 3 kg; the main component of the polishing liquid is Al2O3, and the abrasive particles in the polishing liquid are less than 0.3 micrometers in size; during the polishing process, the polishing time needs to be controlled according to the polishing effect, so that the over-growth of the mushroom-shaped tip generated on the surface after electroplating the metal layer in step 4 is polished to the same plane, so that the surface of the metal layer emits a metallic luster under microscopic inspection; after polishing, OQD (Ozone Quick Dry) cleaning treatment is performed to ensure the surface cleanliness in preparation for the subsequent deposition of the metal reflection compensation layer 25.

[0092] In this embodiment, before setting the metal reflection compensation layer 25, a patterned hard mask is set on the second intermediate structure, and the patterned hard mask covers the corresponding position above the alignment mark; after setting the metal reflection compensation layer 25, the metal reflection compensation layer 25 does not obscure the corresponding position above the alignment mark.

[0093] The present invention provides a patterned hard mask before setting the metal reflection compensation layer 25, so that the metal reflection compensation layer 25 does not block the corresponding position above the alignment mark, thereby eliminating the need for subsequent removal of the metal reflection compensation layer 25 covering the alignment mark, while ensuring that the metal reflection compensation layer 25 does not affect the position alignment effect when setting the second conductive layer 27 for photolithography.

[0094] In one embodiment, the thickness of the metal reflective compensation layer 25 is not less than 10 nanometers.

[0095] In one embodiment, the thickness of the metal reflective compensation layer 25 is 10 nanometers to 20 nanometers.

[0096] Specifically, 10 nanometers is the minimum thickness of the metal reflection compensation layer 25 that can achieve good results in current experimental processes. Even at this thickness, significant optimization of the focusing effect during the exposure process of the second photoresist layer 26 can still be achieved. Those skilled in the art can also obtain thinner metal reflection compensation layers 25 based on actual process developments and verify their optimization results for the focusing effect during the exposure process of the photoresist layer; all of these are within the scope of protection of this invention.

[0097] It is worth noting that the thickness of the metal reflection compensation layer 25 provided in this invention does not need to make the surface of the second intermediate structure completely flat. The required exposure effect can still be achieved with the minimum thickness, and there is no significant difference in the exposure effect obtained by metal reflection compensation layers 25 of different thicknesses. It can be seen that the metal reflection compensation layer 25 in this invention is not based on the conventional thinking that the metal reflection layer is used as a filler to fill and smooth the surface depressions so that the overall surface is flat or the surface height difference is less than a certain threshold in order to optimize the exposure effect. The metal reflection compensation layer 25 of this invention does not achieve the optimization effect of exposure, focusing and autofocus by compensating for physical thickness.

[0098] In one embodiment, the metal reflection compensation layer 25 is sputtered and deposited in the sputtering machine for 5 cycles. Specifically, other suitable number of cycles can be selected to obtain the metal reflection compensation layer 25 according to the actual application, all of which are within the protection scope of this invention.

[0099] In one embodiment, the metal reflective compensation layer 25 is at least one of Au, Ni, TiW, or Ti. Specifically, Au, Ni, TiW, and Ti are materials that have been experimentally verified to significantly optimize the focusing effect of photoresist exposure processes. Furthermore, the optimization of focusing effect is not achieved solely through physical thickness compensation. However, other suitable materials that can significantly optimize the focusing effect of photoresist exposure processes without physical thickness compensation can be selected based on actual application requirements, and all are within the scope of protection of this invention.

[0100] In one embodiment, the metal reflection compensation layer 25 is a 10-nanometer-thick TiW. Specifically, the metal reflection compensation layer 25 can also be set to other suitable thicknesses and materials as needed, all of which are within the scope of protection of this invention.

[0101] Then, proceed to step 6, as follows: Figure 11 As shown, a second photoresist layer 26 is disposed on the third intermediate structure to obtain a fourth intermediate structure.

[0102] Next, in step 7, after aligning the positions using the alignment marks, the second photoresist layer 26 of the fourth intermediate structure is applied as follows: Figure 12 The image shows exposure followed by development using exposure light 12, as shown. Figure 13 The patterned second photoresist layer 26 is shown.

[0103] In one embodiment, the "exposure" in steps 3 and 7 is performed using a yellow light exposure process. Specifically, other suitable exposure processes can also be selected according to actual application requirements, all of which are within the scope of protection of this invention.

[0104] In one embodiment, before exposing the second photoresist layer 26 of the fourth intermediate structure, the full-field surface height distribution map of the fourth intermediate structure is obtained by interference topography. During the exposure process, the actual height of the second photoresist layer 26 at the corresponding position is obtained by flash measurement using an image focus sensor. Combined with the full-field surface height distribution map obtained by interference topography, optical path difference conversion is performed to calculate the effective defocus amount at the corresponding position. The obtained effective defocus amount is used to dynamically level and focus the second photoresist layer 26 during the exposure process.

[0105] Specifically, since the exposure process of the second photoresist layer 26 requires interference topography mapping and image focus flash measurement to achieve leveling, focusing and autofocus operations, the metal reflection compensation layer 25 provided by the present invention before the exposure process of the second photoresist layer 26 can reduce the problem of reflection overlap during photoresist exposure, optimize the accuracy of the full-field surface height distribution map obtained by interference topography mapping, and optimize the graphic effect obtained by the exposure of the second photoresist layer 26.

[0106] Specifically, since the position of the alignment mark can be seen through the photoresist during the photolithography process, the photoresist covering the alignment mark does not affect the alignment effect. However, the covering of the metal reflection compensation layer 25 will block the alignment mark and affect the alignment effect. Therefore, when setting the metal reflection compensation layer 25, it is necessary to ensure that the metal reflection compensation layer 25 does not block the corresponding position above the alignment mark.

[0107] Finally, proceed to step 8, as follows: Figure 14 As shown, a metal layer is disposed in the gap 23 between the patterned second photoresist layers 26 to form a patterned second conductive layer 27, resulting in a double-layer conductive device structure.

[0108] like Figures 15-16 The comparison shown can be seen that, Figure 15 The poor pattern alignment between the first conductive layer 24 and the second conductive layer 27, as revealed by existing technology, poses a greater risk of failure to achieve electrical connection. Figure 16 The pattern alignment between the first conductive layer 24 and the second conductive layer 27 obtained by exposure after setting the metal reflection compensation layer 25 using the scheme of the present invention is good, and the electrical connection reliability is stronger.

[0109] Specifically, this invention only provides a process for setting a metal reflection compensation layer 25 during the photoresist exposure process when obtaining a double-layer pattern to optimize the exposure focusing effect. However, the ideas of this invention can be used in other device structure processes that require optimization of photoresist exposure effects, and all are within the protection scope of this invention.

[0110] In one embodiment, the thickness of the metal layer forming the patterned second conductive layer 27 in step 8 is 75 micrometers ± 5 micrometers (the allowable thickness error is 5 micrometers). Specifically, other suitable thicknesses of the metal layer can also be selected, all of which are within the scope of protection of this invention.

[0111] In one embodiment, both the first conductive layer 24 and the second conductive layer 27 are electrode layers, resulting in a double-layer conductive device structure that is a double-layer electrode device structure. Specifically, as shown... Figure 17 The image shown is a magnified three-dimensional micrograph of an electrode structure with a high aspect ratio and consisting of only a single layer of electrodes. Figure 18 The image shown is a magnified top view of an electrode structure employing the scheme of the present invention, comprising a first conductive layer 24 and a second conductive layer 27, with a double-layer high aspect ratio electrode. Figure 19 As shown Figure 18 A magnified three-dimensional microscopic view of region A, where the electrode depth-to-width ratio is large. Figure 19 In the magnified 3D image, the first conductive layer 24 at the bottom is obscured and cannot be seen.

[0112] In one embodiment, the aspect ratio of the patterned second conductive layer 27 is not less than 3:1.

[0113] Specifically, when the pattern of the second conductive layer 27 is a high aspect ratio pattern, it is easier to generate reflection overlap in the exposure process, which makes it difficult to accurately level, focus and autofocus. Therefore, using a high aspect ratio second conductive layer 27 can better reflect the optimization effect of this solution on the exposure process of the second photoresist layer 26 used to form a high aspect ratio pattern; however, other suitable aspect ratio patterns can also be used as the second conductive layer 27, all of which are within the protection scope of this invention.

[0114] In one embodiment, the aspect ratio of the patterned second conductive layer 27 is approximately 6:1.

[0115] In one embodiment, the critical dimension (CD) of the patterned second conductive layer 27 is approximately 1 micrometer smaller than the critical dimension of the first conductive layer 24, and the corresponding patterns of the first conductive layer 24 and the second conductive layer 27 are aligned. Each side of each pattern in the second conductive layer 27 is 500 nanometers smaller inward than the corresponding pattern in the first conductive layer 24. Specifically, the critical dimensions and linewidth offset of the first conductive layer 24 and the second conductive layer 27 can also be set according to actual needs, all of which are within the protection scope of this invention.

[0116] In one embodiment, after step 8, the remaining first photoresist layer 22 and second photoresist layer 26 are removed. Alternatively, depending on the specific application requirements, the photoresist layers may not be removed, both of which are within the scope of this invention.

[0117] Example 2:

[0118] This embodiment provides a semiconductor process method, which has other features that are basically the same as the semiconductor process method in Embodiment 1, except that:

[0119] In this embodiment, before setting the metal reflection compensation layer 25 in step 5, no patterned hard mask is set on the second intermediate structure; after setting the metal reflection compensation layer 25, a blind exposure process is used to perform window etching on the position of the metal reflection compensation layer 25 corresponding to the position above the position mark according to the graphic design of the alignment mark, so that the metal reflection compensation layer 25 does not block the corresponding position above the alignment mark.

[0120] The present invention avoids the alignment mark being blocked by the metal reflection compensation layer 25 and thus cannot be used as the exposure position for the second photoresist layer 26 by performing window etching after setting the metal reflection compensation layer 25, thereby ensuring the exposure effect.

[0121] In one embodiment, a chemical blade coating method is used to precisely etch the metal reflection compensation layer 25 at the position corresponding to the alignment mark.

[0122] Example 3:

[0123] This embodiment provides a semiconductor process method. Other features of the semiconductor process method are basically the same as those in Embodiment 1 or 2, except that:

[0124] In this embodiment, when setting the metal reflection compensation layer 25 in step 5, the entire surface of the metal reflection compensation layer 25 is directly set on the second intermediate structure.

[0125] This invention utilizes the characteristic that some metal reflection compensation layers 25 are formed only on metal layers, which can achieve the surface flatness effect of the metal reflection compensation layer 25 on the second intermediate structure without using a hard mask, thereby optimizing the exposure, focusing and autofocusing effects.

[0126] Preferably, the metal reflection compensation layer 25 is at least one of Au, Ni, or Ti. Specifically, experiments have shown that when the metal reflection compensation layer 25 is Au, Ni, or Ti, it will only form on the metal layer and will not form on the first photoresist layer 22 at all. Therefore, the metal reflection compensation layer 25 with ideal effect can be formed by a full-surface application method. When the metal reflection compensation layer 25 is TiW, a trace amount of metal reflection compensation layer 25 will form at the position of the non-metal layer, but it will not have a significant impact on its exposure optimization effect. Specifically, other suitable metal reflection compensation layer 25 materials can also be selected during the full-surface application process based on actual experiments, all of which are within the protection scope of this invention.

[0127] Example 4:

[0128] This embodiment provides a semiconductor process method. Other features of the semiconductor process method are basically the same as those in Embodiment 1 or 2, except that:

[0129] In this embodiment, when setting the metal reflection compensation layer 25, the metal reflection compensation layer 25 is patterned on the second intermediate structure by using a preset compensation hard mask layer, and then the compensation hard mask layer is removed.

[0130] Specifically, the preset compensation hard mask layer can be obtained by empirically analyzing the locations in a certain process that are prone to depressions that lead to poor exposure. By setting a metal reflection compensation layer 25 at the locations where depressions are prone to occur, the exposure effect in the process can be improved in a targeted manner.

[0131] Example 5:

[0132] This embodiment provides a semiconductor structure, which is obtained using any one of the semiconductor process methods described in Embodiments 1-4, and the semiconductor structure includes at least:

[0133] The substrate structure 21 has alignment marks on its upper surface;

[0134] First conductive layer 24, the patterned first conductive layer 24 is located on the substrate structure 21;

[0135] A metal reflection compensation layer 25 is located at a predetermined position on the surface of the first conductive layer 24.

[0136] The second conductive layer 27, which is patterned, is located on the second conductive layer 27 and the metal reflection compensation layer 25 covering the second conductive layer 27.

[0137] Specifically, the “preset position” where the metal reflection compensation layer 25 is located can be the surface of the overall conductive layer, or it can be a position that is prone to depression and thus deteriorates the exposure effect, as determined by empirical statistics.

[0138] By setting a metal reflection compensation layer 25, the present invention optimizes the exposure and focusing effect of the photoresist during the formation of the second conductive layer 27, thereby obtaining a structure with better alignment between the first conductive layer 24 and the second conductive layer 27 and higher pattern accuracy.

[0139] In summary, the semiconductor process method and semiconductor structure of this invention can improve the surface uniformity of the overall device before exposure by introducing a metal reflection compensation layer into the semiconductor exposure technology. This compensates for the reflection intensity caused by reflection overlap, optimizes diffraction data, and achieves adjustment and optimization of the substrate surface morphology and flatness. This allows for rapid and accurate compensation of the exposure parameter range, reduces dynamic errors, and solves the problem that complex surface structures cannot automatically compensate for exposure focusing and leveling processes due to dynamic scattering, low integrity, and beam damage. It also improves the flattening of the exposure focal plane of the substrate device structure, normalizes the focal plane, effectively improves the accuracy and reliability of exposure focus measurement and focal plane selection, achieves better focusing effects, and improves the patterns and device fabrication obtained by the semiconductor exposure process. This system improves focusing accuracy and effectively reduces the impact of process fluctuations on the focusing and leveling system. Simultaneously, by adding a metal reflection compensation layer, the optical performance of the photoresist is further optimized while improving the focusing effect, reducing reflectivity and minimizing interference from reflected light. This, combined with surface morphology adjustment, synergistically enhances the device exposure process, achieving compatibility with existing processes. Furthermore, optimizing the focusing effect of the exposure process using the metal reflection compensation layer significantly improves the focal plane leveling effect during photoresist exposure of high aspect ratio structures, making it suitable for focusing in photoresist exposure processes of various high-precision dual-layer photoresist devices. Finally, by using a suitable material for the metal reflection compensation layer, the surface leveling effect on the substrate is further optimized, improving the focusing optimization effect of the exposure process.

[0140] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0141] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor manufacturing process, characterized in that, The semiconductor process method includes: A substrate structure is provided, wherein alignment marks are provided on the upper surface of the substrate structure; A first photoresist layer is formed on the substrate structure to obtain a first intermediate structure; After aligning the position using the alignment marks, the first photoresist layer of the first intermediate structure is exposed and developed to obtain a patterned first photoresist layer. A metal layer is disposed in the gap between the patterned first photoresist layers to form a patterned first conductive layer, thereby obtaining a second intermediate structure; A metal reflection compensation layer is provided on the second intermediate structure so that the metal reflection compensation layer does not block the corresponding position above the alignment mark, thus obtaining a third intermediate structure; A second photoresist layer is formed on the third intermediate structure to obtain a fourth intermediate structure; After aligning the position using the alignment marks, the second photoresist layer of the fourth intermediate structure is exposed and developed to obtain a patterned second photoresist layer. A metal layer is disposed in the gap between the patterned second photoresist layers to form a patterned second conductive layer, thereby obtaining a double-layer conductive device structure.

2. The semiconductor process method according to claim 1, characterized in that, Before setting the metal reflection compensation layer, a patterned hard mask is set on the second intermediate structure, and the patterned hard mask covers the corresponding position above the alignment mark; after setting the metal reflection compensation layer, the patterned hard mask is removed so that the metal reflection compensation layer does not block the corresponding position above the alignment mark. Alternatively, before setting the metal reflection compensation layer, no patterned hard mask was set on the second intermediate structure; after setting the metal reflection compensation layer, a blind exposure process was used to perform window etching on the position above the alignment mark of the metal reflection compensation layer according to the graphic design of the alignment mark, so that the metal reflection compensation layer does not block the corresponding position above the alignment mark.

3. The semiconductor process method according to claim 1, characterized in that, When setting the metal reflection compensation layer, the entire surface of the metal reflection compensation layer can be set directly on the second intermediate structure; or, when setting the metal reflection compensation layer, a patterned metal reflection compensation layer can be set on the second intermediate structure through a preset compensation hard mask layer, and then the compensation hard mask layer can be removed.

4. The semiconductor process method according to claim 1, characterized in that, The thickness of the metal reflective compensation layer is not less than 10 nanometers.

5. The semiconductor process method according to claim 1, characterized in that, The metal reflective compensation layer is at least one of Au, Ni, TiW, or Ti.

6. The semiconductor process method according to claim 1, characterized in that, Before exposing the second photoresist layer of the fourth intermediate structure, the full-field surface height distribution map of the fourth intermediate structure is obtained by interference morphology mapping. During the exposure process, the actual height of the second photoresist layer at the corresponding position is obtained by flash measurement using an image focus sensor. Combined with the full-field surface height distribution map obtained by interference topography, optical path difference conversion is performed to calculate the effective defocus amount at the corresponding position. The obtained effective defocus amount is used to dynamically level and focus the second photoresist layer during the exposure process.

7. The semiconductor process method according to claim 1, characterized in that, Before exposing the first photoresist layer of the first intermediate structure, the full-field surface height distribution map of the first intermediate structure is obtained by interference morphology mapping. During the exposure process, the actual height of the first photoresist layer at the corresponding position is obtained by flash measurement using an image focus sensor. Combined with the full-field surface height distribution map obtained by interference topography, optical path difference conversion is performed to calculate the effective defocus amount at the corresponding position. The obtained effective defocus amount is used to dynamically level and focus the first photoresist layer during the exposure process.

8. The semiconductor process method according to claim 1, characterized in that, The aspect ratio of the patterned first conductive layer and the patterned second conductive layer is not less than 3:

1.

9. The semiconductor process method according to claim 1, characterized in that, After obtaining the second intermediate structure, before setting the metal reflection compensation layer, the surface of the second intermediate structure is planarized.

10. A semiconductor structure, characterized in that, The semiconductor structure is obtained using the semiconductor process method according to any one of claims 1-9, and the semiconductor structure comprises at least: A substrate structure, wherein alignment marks are provided on the upper surface of the substrate structure; A first conductive layer, the first conductive layer being patterned and located on the substrate structure; A metal reflection compensation layer, wherein the metal reflection compensation layer is located at a predetermined position on the surface of the first conductive layer; A second conductive layer, graphically represented, is located on the second conductive layer and the metal reflection compensation layer covering the second conductive layer.

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