File generation method and device, electronic equipment and readable medium

Abstract

Embodiments of the invention provide a file generation method and apparatus, an electronic device and a readable medium, and relate to the technical field of computers.The method comprises the steps of obtaining an instruction file of a to-be-added architecture; the instruction file comprises instruction information of each binary instruction supported by the architecture to be added, and the instruction information is used for describing components of the binary instructions. On the basis of instruction information in the instruction file, operation codes and instruction names of all binary instructions supported by the to-be-added architecture are obtained; and based on the description file format of the target compiler, the operation code of each binary instruction and the instruction name, generating an instruction set description file adaptive to the target compiler for the to-be-added architecture. Therefore, the instruction set description file adaptive to the target compiler is automatically generated, a developer does not need to manually write the instruction set description file, and the generation efficiency of the instruction set description file is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, electronic device, and readable medium for generating documents. Background Technology

[0002] Currently, in order for a compiler to support compiling code into binary instructions of a specific instruction set architecture, an instruction set description file for that architecture needs to be provided to the compiler. This instruction set description file is used to describe the various binary instructions supported by that instruction set architecture.

[0003] In related technologies, the corresponding instruction set description files are often generated manually by developers based on the instruction manual of the instruction set architecture, resulting in low efficiency in generating instruction set description files. Summary of the Invention

[0004] This invention provides a file generation method, apparatus, electronic device, and readable medium, which can solve the problem of low generation efficiency of instruction set description files.

[0005] To address the aforementioned problems, this invention discloses a file generation method, the method comprising: Obtain the instruction file for the architecture to be added; the instruction file includes instruction information for each binary instruction supported by the architecture to be added; the instruction information is used to describe the components of the binary instruction; Based on the instruction information in the instruction file, obtain the opcode and instruction name of each binary instruction supported by the architecture to be added; Based on the target compiler's description file format, the opcodes of each binary instruction, and the instruction names, an instruction set description file adapted to the target compiler is generated for the architecture to be added.

[0006] On the other hand, embodiments of the present invention disclose a document generation apparatus, the apparatus comprising: The first acquisition module is used to acquire the instruction file of the architecture to be added; the instruction file includes instruction information of each binary instruction supported by the architecture to be added; the instruction information is used to describe the components of the binary instruction. The second acquisition module is used to acquire the opcode and instruction name of each binary instruction supported by the architecture to be added, based on the instruction information in the instruction file. The generation module is used to generate an instruction set description file adapted to the target compiler for the architecture to be added, based on the description file format of the target compiler, the opcode of each binary instruction, and the instruction name.

[0007] In another aspect, embodiments of the present invention disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, the executable instruction causing the processor to execute the aforementioned method.

[0008] This invention also discloses a machine-readable medium storing instructions that, when executed by one or more processors, cause the processors to perform the methods described above.

[0009] The embodiments of the present invention have the following advantages: The file generation method provided by the embodiments of the present invention obtains an instruction file for the architecture to be added; the instruction file includes instruction information for each binary instruction supported by the architecture to be added, and the instruction information is used to describe the components of the binary instruction. Based on the instruction information in the instruction file, the opcode and instruction name of each binary instruction supported by the architecture to be added are obtained respectively. Based on the description file format of the target compiler, the opcode and instruction name of each binary instruction, an instruction set description file adapted to the target compiler is generated for the architecture to be added. In this way, by automatically generating an instruction set description file adapted to the target compiler, developers do not need to manually write instruction set description files, thus improving the generation efficiency of instruction set description files.

[0010] Furthermore, instruction set description files adapted to the target compiler are generated according to the target compiler's description file format, ensuring that the generated instruction set description files conform to the description file format required by the target compiler. This ensures that the generated instruction set description files can be correctly recognized and used by the target compiler, improving the code's universality during the instruction set architecture adaptation process. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below.

[0012] Figure 1 This is a flowchart of the steps of a file generation method provided in an embodiment of the present invention; Figure 2 This is a flowchart of an instruction file processing method provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a processing flow provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the generation of an instruction description provided in an embodiment of the present invention; Figure 5 This is a block diagram of a document generation device provided in an embodiment of the present invention; Figure 6This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0014] The file generation method provided in this invention can be applied to scenarios where compilers automatically generate instruction set description files. Virtual machines have cross-platform support, and the compiler backend running within a virtual machine often needs to support multiple instruction set architectures. During compilation, when the compiler backend generates specific binary instructions, it needs to use the instruction set description file of the required instruction set architecture. Since different instruction set architectures support different instruction sets and binary instruction encodings, their instruction set description files are different. When adding support for a new instruction set architecture to a compiler, it is necessary to adapt the compiler to the instruction set description file for that new architecture. In related technologies, adaptation is usually done manually. Therefore, each time support for a new instruction set architecture is added, the corresponding instruction set description file needs to be manually written, which lacks universality.

[0015] Furthermore, different virtual machine compiler backends have different requirements for the format of instruction set description files. For example, the backends of .NET, JAVA, and Mono compilers all require different formats. Therefore, when adding support for the same new instruction set architecture to multiple compilers, it is necessary to manually write instruction set description files for each compiler. Since an instruction set description file often has hundreds or thousands of lines, the workload for developers in this field is significant, and the efficiency of generating instruction set description files is low.

[0016] Therefore, this invention provides a file generation method, which will be described in detail below.

[0017] Figure 1 This is a flowchart of a file generation method provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the method for generating this file may include the following steps: Step 101: Obtain the instruction file of the architecture to be added; the instruction file includes instruction information of each binary instruction supported by the architecture to be added; the instruction information is used to describe the components of the binary instruction.

[0018] Step 102: Based on the instruction information in the instruction file, obtain the opcode and instruction name of each binary instruction supported by the architecture to be added.

[0019] Step 103: Based on the target compiler's description file format, the opcodes of each binary instruction, and the instruction name, generate an instruction set description file adapted to the target compiler for the architecture to be added.

[0020] In this invention, the architecture to be added can be any instruction set architecture, and the target compiler is the compiler that needs to add support for the architecture to be added. This compiler can be a Just-In-Time (JIT) compiler. The target compiler's current supported instruction set architectures do not include the architecture to be added; the architecture to be added can be considered a new instruction set architecture that needs to be added to the target compiler. For any architecture to be added, an instruction set description file adapted to the target compiler can be automatically generated using this file generation method. Each time a new instruction set architecture needs to be added to the compiler, this new instruction set architecture is used as the architecture to be added, and the above file generation method is executed once to generate the corresponding instruction set description file for that new instruction set architecture. Therefore, this embodiment of the invention has higher versatility and higher generation efficiency.

[0021] The binary instructions supported by the architecture to be added refer to the binary representation of the instructions supported by the architecture to be added. The instruction file for the architecture to be added records the instruction information for each binary instruction supported by the architecture to be added. This instruction information may include the opcode and instruction name of the binary instruction. Since each compiler's instruction set description file needs to record the opcode and instruction name, this embodiment of the invention automatically extracts the opcode and instruction name of each binary instruction supported by the architecture to be added.

[0022] Furthermore, the description file format of the target compiler is used to characterize the instruction set description file format required by the compiler backend of the target compiler. In this embodiment of the invention, according to the description file format of the target compiler, based on the opcode and instruction name of each binary instruction supported by the architecture to be added, an instruction description conforming to the description file format of the target compiler is generated for each binary instruction. Together with the opcode and instruction name of each binary instruction, an instruction set description file adapted to the target compiler is finally obtained.

[0023] In summary, the file generation method provided by this invention obtains an instruction file for the architecture to be added. The instruction file includes instruction information for each binary instruction supported by the architecture to be added, and this instruction information describes the components of the binary instructions. Based on the instruction information in the instruction file, the opcode and instruction name of each binary instruction supported by the architecture to be added are obtained. Based on the target compiler's description file format, the opcodes of each binary instruction, and the instruction names, an instruction set description file adapted to the target compiler is generated for the architecture to be added. Thus, by automatically generating an instruction set description file adapted to the target compiler, developers are not required to manually write the instruction set description file, improving the efficiency of instruction set description file generation.

[0024] Furthermore, instruction set description files adapted to the target compiler are generated according to the target compiler's description file format, ensuring that the generated instruction set description files conform to the description file format required by the target compiler. This ensures that the generated instruction set description files can be correctly recognized and used by the target compiler, improving the code's universality during the instruction set architecture adaptation process.

[0025] Optionally, in this embodiment of the invention, the step of obtaining the instruction file for the architecture to be added may specifically include: Step 1011: Obtain the executable file of the architecture to be added; the executable file includes the binary instructions supported by the architecture to be added.

[0026] Step 1012: Disassemble the executable file of the architecture to be added to obtain the instruction file of the architecture to be added.

[0027] The executable file for the architecture to be added includes the binary form of each instruction supported by that architecture. Disassembly converts the executable file into a human-readable representation, and the disassembly result includes instruction information lines. Each instruction information line defines the instruction name and its binary code; a single instruction information line can be considered a description of the components of a binary instruction. Therefore, to facilitate obtaining the instruction names and opcodes of each instruction, in this embodiment of the invention, after obtaining the executable file for the architecture to be added, the executable file is disassembled, and the resulting assembly code is used as the instruction file for the architecture to be added.

[0028] Specifically, a disassembler can be pre-installed on the electronic device, and then the disassembler commands supported by that disassembler can be executed on the executable file containing the architecture to be added. For example, the command `objdump -d` can be generated and executed to call the disassembler to disassemble the executable file containing the architecture to be added. The output of the disassembler is the assembly code for the architecture to be added, which is stored as an instruction file. This instruction file for the architecture to be added can be named `instrs.txt`.

[0029] In this embodiment of the invention, the executable file of the architecture to be added is first obtained. By disassembling the executable file of the architecture to be added, the instruction file of the architecture to be added can be automatically obtained. This ensures that the instruction name and opcode of each instruction can be easily obtained from the instruction file later.

[0030] Optionally, this embodiment of the invention provides an implementation method one, in which the step of obtaining the executable file of the architecture to be added described above may specifically include: Step 1011a: Obtain the executable file of the infrastructure according to the preset infrastructure assembly instruction file; the executable file of the infrastructure includes the binary instructions supported by the infrastructure.

[0031] Step 1011b: Based on the binary translation tool of the architecture to be added, translate the executable file of the basic architecture into the executable file of the architecture to be added.

[0032] The infrastructure can be any instruction set architecture other than the architecture to be added. For example, in one application scenario, the infrastructure can be an x86 architecture. The executable file for the infrastructure is obtained by compiling the assembly instruction file for that infrastructure. The assembly instruction file for the infrastructure is pre-generated and defines all the instructions supported by the infrastructure. For example, based on all the instructions defined in the infrastructure's instruction manual, all the instructions supported by the infrastructure can be determined, and assembly code for each instruction appearing at least once can be generated as the infrastructure's assembly instruction file. Then, the infrastructure's assembly code file is compiled to obtain the infrastructure's executable file. The infrastructure's assembly instruction file can be written by developers, or a first code requirement description can be input into a code generation tool, and the code output by the code generation tool can be used as the infrastructure's assembly instruction file. The first code requirement description can include: using all the instructions defined in the infrastructure's instruction manual and writing them in assembly language.

[0033] The binary translation tool for the architecture to be added can specifically be static binary translation software used to translate the executable file of the underlying architecture into an executable file of the architecture to be added. This binary translation tool can be pre-installed on the electronic device where the virtual machine resides. Specifically, the executable file of the underlying architecture can be stored in a first specified directory, which can be pre-specified by the developers; this embodiment of the invention does not impose any limitations on this. Accordingly, the first specified directory can be used as the input path of the binary translation tool, the binary translation tool can be started, and translation can be performed by running the binary translation tool. Finally, the files in the output directory of the binary translation tool can be read to obtain the executable file of the architecture to be added.

[0034] For example, assuming the infrastructure is x86, you could input the following into the code generation tool: "Use all instructions defined in the x86 instruction manual and write in assembly language." The code output by the tool would then be the x86 assembly instruction file. Compiling this file yields an x86 executable. Assuming the x86 executable is stored in the directory ` / root / base / x86 file`, and the output directory of the binary translation tool QEMU is ` / root / output / file`, you could set the input path parameter for QEMU to ` / root / base / x86 file`. This would allow QEMU to translate the executable in the input path into an ARM executable. After QEMU finishes running, it reads the file from ` / root / output / file` to obtain the ARM executable.

[0035] Since the assembly instruction file of the infrastructure defines all the instructions supported by the infrastructure, the executable file of the infrastructure obtained by compiling the assembly instruction file includes the binary representation of all the instructions supported by the infrastructure, that is, it includes all the binary instructions supported by the infrastructure. Furthermore, by translating the executable file of the infrastructure, all the binary instructions supported by the infrastructure are translated into binary instructions for the architecture to be added. Therefore, the final executable file also includes the binary instructions supported by the architecture to be added.

[0036] In this implementation, the executable file for the underlying architecture is obtained from the pre-defined assembly instruction file of the underlying architecture. This executable file includes the binary instructions supported by the underlying architecture. A binary translation tool for the architecture to be added then translates the underlying architecture's executable file into the executable file for that architecture. Thus, by leveraging existing binary translation tools, only the assembly instruction file for the underlying architecture needs to be written once. After compiling the underlying architecture's executable file, when multiple architectures need to be added, the executable file can be translated into the corresponding executable file for each architecture using its own binary translation tool. Therefore, obtaining the executable file for the architecture to be added has higher reusability and lower implementation difficulty.

[0037] Optionally, this embodiment of the invention provides a second implementation method. In the second implementation method, the step of obtaining the executable file of the architecture to be added may specifically include: Step 1011c: Obtain the pre-set code to be compiled for the architecture to be added; the code to be compiled includes statements for generating instructions defined in the instruction set of the architecture to be added.

[0038] Step 1011d: Compile the code to be compiled to obtain the executable file of the architecture to be added.

[0039] In this second implementation, for any architecture to be added, pre-prepared compileable code is prepared for that architecture. This compileable code for the architecture to be added can be pre-generated, and it defines statements for generating all instructions supported by the architecture to be added (i.e., all instructions defined in the instruction set of the architecture to be added). For example, if the architectures to be added include ARM and RISC architectures, then before step 101, developers can write the compileable code for the ARM and RISC architectures. The compileable code for the architecture to be added can be written in a high-level language, such as C. The compileable code for the architecture to be added can be written by developers, or a second code requirement description can be input into the code generation tool, and the code output by the code generation tool can be used as the compileable code for the architecture to be added. This second code requirement description can include: using all instructions defined in the instruction manual of the architecture to be added, and writing it in C.

[0040] Based on all instructions defined in the instruction manual of the architecture to be added, all instructions supported by the architecture to be added can be determined. C language code that appears at least once for each instruction is generated as the compilation code for the architecture to be added. The compilation code for the architecture to be added can be stored in a second specified directory, which is different from the first specified directory mentioned above. The second specified directory can be pre-specified by the developer, and this embodiment of the invention does not impose any restrictions on it. Accordingly, the compilation code for the architecture to be added can be obtained by loading the files in the second specified directory. For example, for the architecture to be added: ARM architecture, the code generation tool can be input with: "Use all instructions defined in the instruction manual of the ARM architecture and write it in C language," and then the code output by the code generation tool is used as the compilation code for the ARM architecture. For the architecture to be added: RISC architecture, the code generation tool can be input with: "Use all instructions defined in the instruction manual of the RISC architecture and write it in C language," and then the code output by the code generation tool is used as the compilation code for the RISC architecture.

[0041] In practice, developers can also manually write the compileable code for each architecture to be added. For example, assuming the instruction set of the architecture to be added includes addition, multiplication, division, and store instructions, developers can write code to implement addition, multiplication, division, and store operations. This ensures that the final compiled code includes addition, multiplication, division, and store instructions.

[0042] Furthermore, the code to be compiled for the ARM architecture is stored in a second specified directory: / root / base / arm file, and the code to be compiled for the RISC architecture is stored in a second specified directory: / root / base / RISC file.

[0043] Accordingly, a correspondence can be established between the architecture identifier of the architecture to be added and the second designated directory storing the code to be compiled for the architecture to be added. For example, in this correspondence, the architecture identifier "arm" for the ARM architecture corresponds to " / root / base / arm file", and the architecture identifier "RISC" for the RISC architecture corresponds to " / root / base / RISC file". Accordingly, for any architecture identifier recorded in this correspondence, the code file stored in the second designated directory corresponding to that architecture identifier is determined as the file to be compiled for the architecture to be added represented by that architecture identifier.

[0044] Next, the code to be compiled using a compiler is used to obtain an executable file for the architecture to be added. Specifically, a default compiler can be invoked to compile the code for the architecture to be added. This default compiler is one that already supports the architecture to be added and can be pre-installed on the electronic device. For example, in some implementations, a more general-purpose compiler, such as gcc or clang, can be used as the default compiler. Since the code to be compiled for the architecture to be added contains statements for generating all instructions supported by the architecture to be added, the executable file obtained by compiling the code for the architecture to be added can include the binary representation of all instructions supported by the architecture to be added, that is, it includes all binary instructions supported by the architecture to be added.

[0045] In this embodiment of the invention, if a binary translation tool for the architecture to be added does not currently exist, implementation method two can be executed to obtain the executable file for the architecture to be added. Specifically, the architecture identifier of the basic architecture and the architecture identifier of the architecture to be added can be combined into a target identifier, for example, according to the format of combining the architecture identifier of the basic architecture and the architecture identifier of the architecture to be added. Then, the tool identifier corresponding to the target identifier is searched from the preset correspondence between architecture identifiers and tool identifiers (hereinafter referred to as the first correspondence). The architecture identifier in the first correspondence consists of a pre-translation architecture identifier and a post-translation architecture identifier. For an architecture identifier, the translation tool represented by the tool identifier corresponding to the architecture identifier is used to translate the executable file of the pre-translation architecture represented by the pre-translation architecture identifier into the executable file of the post-translation architecture represented by the post-translation architecture identifier.

[0046] All existing binary translation tools can be installed on the electronic device, and a corresponding table-like mapping entry can be created for each binary translation tool within the first mapping relationship. Each mapping entry includes an architecture identifier and its corresponding tool identifier. For example, assuming the binary translation tool is used to translate an executable file of architecture X into an executable file of architecture Y, and the architecture identifiers for architecture X and architecture Y are X and Y respectively, the tool identifier in the corresponding mapping entry for the binary translation tool is the identifier of the binary translation tool itself, and the architecture identifier in this mapping entry is: XY.

[0047] Furthermore, if the first mapping contains an architecture identifier that matches the target identifier, it indicates that a binary translation tool (hereinafter referred to as the target translation tool) exists that translates the executable file of the basic architecture into an executable file of the architecture to be added. For example, the first mapping can be stored in a first storage location, which can be pre-specified by the developer. The first mapping can be loaded from the first storage location, and each architecture identifier recorded in the first mapping can be compared with the target identifier. If the architecture identifier is the same as the target identifier, it is determined that the first mapping contains an architecture identifier that matches the target identifier.

[0048] For example, suppose the architecture identifiers recorded in the first correspondence include: x86-arm and x86-RISC. If the target identifier is x86-arm, then it can be determined that there exists an architecture identifier in the first correspondence that matches the target identifier. Accordingly, the first implementation method described above can be used. Specifically, the binary translation tool represented by the tool identifier corresponding to the target identifier can be called, and the executable file of the underlying architecture can be translated to obtain the executable file of the architecture to be added.

[0049] Understandably, if no architecture identifier matching the target identifier exists in the first correspondence, it indicates that a target translation tool does not currently exist. Accordingly, a code generation prompt can be output to instruct the user to obtain the code to be compiled for the architecture to be added and write it to the second specified directory. Upon receiving the "written" prompt, the second implementation method described above is executed, calling the compiler to compile the pre-set code to be compiled for the architecture to be added, obtaining the executable file for the architecture to be added. The "written" prompt indicates that the code to be compiled for the architecture to be added has been written.

[0050] In this embodiment of the invention, pre-set code to be compiled for the architecture to be added is obtained; the code to be compiled includes statements used to generate instructions defined in the instruction set of the architecture to be added. The code to be compiled is then compiled to obtain an executable file for the architecture to be added. In this way, even in the absence of a binary translation tool capable of translating the executable file of the basic architecture into an executable file for the architecture to be added, an executable file for the architecture to be added can still be obtained, ensuring that an instruction set description file is ultimately generated for the architecture to be added.

[0051] Optionally, in this embodiment of the invention, the steps of obtaining the opcodes and instruction names of each binary instruction supported by the architecture to be added may specifically include: Step 1021: For any line of instruction information in the instruction file, extract the binary code and instruction name from the instruction information one by one; each line of instruction information corresponds to one binary instruction supported by the architecture to be added.

[0052] Step 1022: Based on the binary encoding, extract the opcode of the binary instruction represented by the instruction information.

[0053] In this embodiment of the invention, the instruction file obtained after disassembly includes instruction information lines and non-instruction information lines, such as address lines and label lines. For example, taking the Loongson architecture as an example, the instruction file for the architecture to be added may include:

[0054]

[0055] In the example above, 000000000000000<arithmetic_ops> ..., <.L11> and All of these are non-command information lines.

[0056] Accordingly, before step 1021, non-instruction information lines in the instruction file can be deleted to remove irrelevant information. For example, since the disassembly output includes hexadecimal binary encoding in the instruction information lines, shell commands can be used. For instance, a `grep` command can be generated to match lines containing a specified symbol and hexadecimal numbers, where the specified symbol can be ":". Executing the `grep` command deletes lines that do not match, thus filtering out lines that do not contain the specified symbol and binary encoding, thereby deleting non-instruction information lines from the instruction file.

[0057] Furthermore, the same disassembler was used to disassemble executable files of different architectures. Accordingly, the instruction information lines in the disassembled output of executable files of different architectures all followed the same format: Instruction offset address: Instruction binary code Instruction name Instruction body The "instruction name and instruction body" part constitutes the assembly representation of the instruction.

[0058] For example, with This instruction information example shows that the instruction's offset address is 0, its binary code is 02ff0063, its name is addi.d, and its instruction body is... .

[0059] Accordingly, the instruction information lines in the instruction file can be traversed. Specifically, after deleting non-instruction information lines in the instruction file, traversal can begin from the first line of the instruction file. For the currently traversed line, the instruction name and binary code are extracted from each instruction information line based on preset extraction rules. The extraction rules are set using regular expressions based on the format followed by the instruction information lines in the disassembly output. For example, the extraction rules may include using the string between the first and second spaces after a specified symbol as the binary code, and the string between the second and third spaces after a specified symbol as the instruction name. The specified symbol can be ":". For example, for the first instruction information line in the above example, when extracting according to this extraction rule, the string between the second and third spaces after the specified symbol can be used as the instruction name, resulting in the instruction name: addi.d.

[0060] Furthermore, the binary code of an instruction is the machine code actually executed by the computer hardware. This binary code contains all the information about the instruction, including the opcode, register fields, and immediate numeric field. These fields collectively define the specific operation of the instruction. Accordingly, after extracting the binary code from the instruction information line, the opcode can be further extracted from it.

[0061] In this embodiment of the invention, for any line of instruction information in the instruction file, the binary code and instruction name are extracted. Each line of instruction information corresponds to one binary instruction for which architecture support is to be added. Then, based on the binary code, the opcode of the binary instruction represented by the instruction information is extracted, thus obtaining the opcode and instruction name of each binary instruction. This can, to a certain extent, ensure overall processing efficiency.

[0062] Optionally, the step of extracting the opcode of the binary instruction represented by the instruction information described above may specifically include: Step 1022a: When the opcode corresponds to a fixed bit field, extract the content of the fixed bit field in the binary code to obtain the opcode.

[0063] Step 1022b: When the opcode corresponds to a non-fixed bit field, determine the bit field where the opcode is located in the binary code based on the value of a specific bit field in the binary code; extract the content of the bit field where the opcode is located to obtain the opcode.

[0064] In practical applications, some instruction set architectures use fixed-byte opcodes, meaning the opcode is a fixed bit field in the binary encoding. For example, the opcode could be the high 6 bits of the binary encoding. Accordingly, the contents of the fixed bit fields in each binary encoding can be extracted to obtain the opcode for that binary encoding. However, in some instruction set architectures, the opcode is not a fixed byte; the bit field of the opcode in the binary encoding is not fixed. For example, the opcode might be the high 6 bits, the high 17 bits, or even the high 10 bits. Accordingly, the bit field where the opcode is located in the binary encoding can be determined first, and then the contents of that bit field can be extracted to obtain the opcode for that binary encoding.

[0065] The text generation method provided in this embodiment of the invention can be implemented in the form of a preset script. This preset script includes the implementation code of the text generation method to carry out its processing. Each time a new instruction set architecture is added, the preset script can be run once to automatically generate an instruction set description file for that new architecture. For example, when adding ARM architecture support, an ARM architecture identifier can be input into the preset script to instruct it to obtain the ARM architecture instruction file and generate an instruction set description file adapted to the target compiler based on the ARM architecture instruction file. Similarly, when adding RISC architecture support, a RISC architecture identifier can be input into the preset script to instruct it to obtain the RISC architecture instruction file and generate an instruction set description file adapted to the target compiler based on the RISC architecture instruction file.

[0066] For a given architecture to be added, in the presence of multiple target compilers, instruction set description files can be generated separately for each target compiler through step 103 described above. This text generation method has high code versatility and can significantly reduce the workload of developers. When running the preset script, i.e., executing the text generation method once, an opcode mask can be pre-input into the main function of the preset script so that the preset script can extract the opcode from the binary encoding. The input mask can be used as a parameter: the value of the opcodeMask parameter. If the opcode in the architecture to be added is a fixed byte, then the length of the mask is the same as the length of a single binary encoding, and the value of each fixed bit field in the mask is 1. If the opcode in the architecture to be added is not a fixed byte, then the value of each bit in the mask is 0.

[0067] Accordingly, if the input mask is not all zeros, it can be determined that the opcode in the architecture to be added corresponds to a fixed bit field. A bitwise AND operation can be performed between the binary code and the mask, and the result of the AND operation can be used as the opcode of the binary instruction represented by the instruction information to which the binary code belongs. Otherwise, if the input mask is all zeros, it can be determined that the opcode in the architecture to be added corresponds to a non-fixed bit field, and the opcode needs to be dynamically obtained. This is achieved by executing step 1022b to extract the opcode from the binary code of the instruction information. Step 1022b can be implemented using an opcode processing program in a preset script, which can predefine opcode extraction methods for various instruction set architectures where the opcode is a non-fixed byte.

[0068] Specifically, instruction set architectures with opcodes that are not fixed bytes are referred to as non-fixed architectures. The opcode extraction methods for different non-fixed architectures may differ, meaning the specific positioning fields corresponding to different non-fixed architectures may differ. For a non-fixed architecture, the specific positioning field is a fixed bit in the binary encoding. A pre-created correspondence between the architecture identifier and the specific positioning field of each non-fixed architecture (hereinafter referred to as the second correspondence) is established. For example, the second correspondence can be stored in a second storage location, which can be pre-specified by the developer. Loading the second correspondence from the second storage location allows comparison of the architecture identifier of the architecture to be added with each architecture identifier in the second correspondence. If they match, the specific positioning field corresponding to the matching architecture identifier is used as the specific positioning field corresponding to the architecture to be added (hereinafter referred to as the target specific positioning field). For example, assuming the target specific positioning field is the high 4 bits, the value of the high 4 bits in the binary encoding of the instruction information (hereinafter referred to as the target value) can be extracted. In this embodiment of the invention, a third correspondence can be pre-created for each non-fixed architecture. From the pre-created correspondence between the conditions satisfied by the value of the specific bit field and the bit field it belongs to (i.e., the third correspondence of the bit field to be added), the bit field in the binary encoding of the opcode corresponding to the target value is found (hereinafter referred to as the target bit field). The third correspondence of the bit field to be added can be stored in a third storage location, which can be pre-specified by the developers.

[0069] For example, a third mapping of the architecture to be added can be loaded from a third storage location, assuming that the third mapping of the architecture to be added includes: [The value of a specific bit field must satisfy the following conditions: the value is equal to 0x6, 0x5, or 0x4; the bit field it belongs to is the first 6 bits] [The value of a specific bit field must satisfy the following conditions: the value is equal to 0x3; the bit field it belongs to is the first 17 bits] [The value of a specific bit field must meet the following conditions: the value is equal to 0x2 and the second 4 bits are greater than or equal to 0x8; the bit field contains the first 10 bits].

[0070] Accordingly, when the target value is 0x6, the target bit field is the first 6 bits. Therefore, the high 6 bits of this binary code can be extracted to obtain the opcode. The opcode is the part of the binary code used to represent the operation type. Specifically, the target bit field in the all-zero mask can be set to 1 to obtain the actual mask. The actual mask is then ANDed with the binary code to obtain the opcode.

[0071] In this embodiment of the invention, when the opcode corresponds to a fixed bit field, the content of the fixed bit field in the binary code is extracted to obtain the opcode. When the opcode corresponds to a non-fixed bit field, the bit field in the binary code where the opcode is located is determined based on the value of the specific bit field in the binary code, and the content of that bit field is extracted to obtain the opcode. In this way, adaptive processing is performed for both fixed and non-fixed bit field cases, which can ensure the accuracy of the opcode to a certain extent.

[0072] Optionally, embodiments of the present invention may further include the following steps: Step S21: Detect whether the opcode and the instruction name exist in the preset set; the preset set is used to record the opcode and instruction name of each binary instruction.

[0073] Step S22: If it does not exist, write the opcode and instruction name into the preset set.

[0074] Step S23: Otherwise, directly extract the next line of instruction information from the instruction file.

[0075] In this embodiment of the invention, when traversing each line of instruction information in the instruction file, after extracting the instruction name and opcode (hereinafter referred to as the instruction name and opcode to be written) from the currently traversed line of instruction information, the instruction name and opcode to be written can be written to a preset set. Since there may be duplicate instruction information lines in the disassembled instruction file, before writing the instruction name and opcode to be written, it is possible to first compare the instruction name and opcode to be written with each existing instruction name and opcode in the preset set to detect whether there are any identical opcodes and instruction names in the preset set.

[0076] The pre-defined set, also known as the `encodeNameMap` set, can be initialized beforehand using a pre-defined set initialization statement to create an empty `encodeNameMap` set. For example, the set initialization statement could be `Map encodeNameMap = null`. The pre-defined set includes columns for the corresponding opcode and instruction name. Each row in the pre-defined set represents the instruction name and opcode of a binary instruction. For example, the opcode column can be used as the key, and the instruction name column as the value; correspondingly, each row in the pre-defined set represents a key-value pair.

[0077] Furthermore, if no identical binary instruction has an opcode and instruction name, the instruction name and opcode to be written can be added to the set as value and key, respectively, and then the process of traversing the next line of instruction information can begin. If identical opcodes and instruction names exist, the writing step is skipped, and the process of traversing the next line of instruction information can begin directly.

[0078] Figure 2 This is a flowchart of an instruction file processing method provided in an embodiment of the present invention, such as... Figure 2 As shown, the instruction file for the architecture to be added can be loaded first, and non-instruction information lines in the instruction file can be deleted. Then, the instruction file is traversed starting from the first line. It is determined whether the pre-input mask is not all zeros to extract the opcode. If so, the pre-input mask is ANDed with the binary code in the currently traversed instruction information line to obtain the opcode in that line. If not, the opcode in the binary code of the currently traversed instruction information line is dynamically obtained. The implementation of this dynamic acquisition operation can refer to step 1022b above, which will not be repeated here. Next, it is determined whether the binary code in the currently traversed instruction information line already exists in the preset set. If it does not exist, it means that the opcode and instruction name in the currently traversed instruction information line do not exist in the preset set, and the opcode and instruction name in the currently traversed instruction information line can be added to the preset set. Further, if the next instruction information line exists, the next instruction information line is traversed.

[0079] In this embodiment of the invention, the binary code in the currently traversed instruction information line can be used as the value of the insEncode parameter, and the instruction name in the currently traversed instruction information line can be used as the value of the insName parameter. When traversing the next instruction information line, the value of the insEncode parameter can be updated to the binary code in the next instruction information line, and the value of the insName parameter can be updated to the instruction name in the next instruction information line.

[0080] For example, in the aforementioned example, the final preset set includes:

[0081] In this embodiment of the invention, by detecting the preset set, the opcode and instruction name are only written into the preset set if there are no duplicate opcodes and instruction names. This ensures the uniqueness of the information in the preset set and avoids the problem of duplicate opcodes and instruction names, which would lead to duplicate instruction descriptions in the final generated instruction set description file.

[0082] Optionally, in this embodiment of the invention, the step of generating an instruction set description file adapted to the target compiler for the architecture to be added may specifically include: Step 1031: For any of the target compilers, obtain the description file template of the target compiler; the description file template follows the description file format of the target compiler and is used to indicate the filling position of the opcode and the instruction name.

[0083] Step 1032: Based on the opcode and instruction name of each binary instruction, fill in the description file template to obtain the corresponding instruction description for each binary instruction.

[0084] Step 1033: Based on the instruction descriptions corresponding to each binary instruction, generate an instruction set description file adapted to the target compiler.

[0085] In this embodiment of the invention, the format requirements of different compiler backends may differ. Therefore, corresponding description file templates can be generated in advance for different compilers according to their required formats. For example, the description file template for the .NET compiler can be: INST(instruction name, "instruction name" instruction type opcode, opcode mask, usage flags) The Mono compiler's description file template can be: "Architecture Name_Instruction Name (Opcode)" For any given compiler, the generated description file template conforms to that compiler's description file format. The compiler identifiers of each compiler and the corresponding description file templates generated for that compiler are stored. Accordingly, the description file template corresponding to the compiler identifier of the target compiler (hereinafter referred to as the target template) can be found from the pre-stored description file templates. For example, the description file template can be stored in a fourth storage location, which is pre-specified by the developers. The compiler identifier of the target compiler can be compared with the compiler identifiers corresponding to each description file template. The description file template corresponding to the matching compiler identifier is then obtained.

[0086] Then, each line in the preset set can be traversed. Each line in the preset set represents the opcode and instruction name of a binary instruction. Based on the opcode and instruction name in each line, the target template is filled to obtain the instruction description of a binary instruction. After completing the traversal of the preset set, an instruction set description file adapted to the target compiler is generated based on the generated instruction descriptions.

[0087] Figure 3 This is a schematic diagram of a processing flow provided by an embodiment of the present invention, such as... Figure 3 As shown, we can first determine if a target translation tool exists. The target translation tool is a binary translation tool that translates the executable file of the basic architecture into the executable file of the architecture to be added. If it exists, the target translation tool is used to translate the executable file of the basic architecture into the executable file of the architecture to be added. If it does not exist, the code to be compiled for the architecture to be added is compiled to obtain the executable file of the architecture to be added.

[0088] The executable file for which the architecture to be added is disassembled to obtain the instruction file for that architecture. The instruction information lines in the instruction file are traversed, and the instruction name and opcode of the currently traversed instruction information line are extracted and written to a preset set. Specifically, if the same instruction name and opcode do not currently exist in the preset set, the extracted instruction name and opcode are written to the preset set. The preset set is traversed, and the description file template is populated based on the instruction name and opcode of the currently traversed line to obtain the instruction description. An instruction set description file is generated based on the generated instruction description.

[0089] In this embodiment of the invention, for any target compiler, a description file template for the target compiler is obtained; the description file template conforms to the description file format of the target compiler. Based on the opcode and instruction name of each binary instruction, the description file template is filled in to obtain the corresponding instruction description for each binary instruction. Based on the corresponding instruction description for each binary instruction, an instruction set description file adapted to the target compiler is generated. In this way, by filling in the description file template of the target compiler, the instruction descriptions required to generate the instruction set description file can be obtained, thereby ensuring generation efficiency to a certain extent.

[0090] Optionally, the step of generating an instruction set description file adapted to the target compiler based on the corresponding instruction descriptions of each binary instruction may specifically include: Step 1033a: Detect whether the total number of instructions described is consistent with the total number of instructions of the architecture to be added.

[0091] Step 1033b: If they match, then the instruction set description file is generated directly based on the corresponding instruction description of each binary instruction.

[0092] Step 1033c: If there is a discrepancy, output the corresponding instruction description and supplementary prompt for each binary instruction; the supplementary prompt is used to prompt the user to supplement the missing instruction description; after receiving the instruction description input by the user in response to the supplementary prompt, generate the instruction set description file based on the corresponding instruction description of each binary instruction and the instruction description input by the user.

[0093] The total number of instructions for the architecture to be added can be collected by the developer after inputting the instruction file for the architecture to be added. For example, each time the text generation method is executed, the total number of instructions for the architecture to be added can be pre-input into the main function of the preset script to determine whether the generated instruction descriptions are complete. The total number of input instructions can be used as the value of the parameter `totalNumInstrs`. The total number of instruction descriptions can be used as the value of the parameter `genNumInst`. For example, the initial value of the counter can be set to 0, and the counter value can be incremented by 1 after each instruction description is generated. After the generation of instruction descriptions ends, the current value of the counter is determined as the total number of instruction descriptions.

[0094] One instruction description corresponds to one binary instruction. If instruction descriptions for all binary instructions are generated, the total number of instruction descriptions in the preset set matches the total number of instructions in the architecture to be added. Conversely, if they do not match—for example, the total number of instruction descriptions is 28, while the total number of instructions in the architecture to be added is 32—then the generated instruction set description file is incomplete, lacking descriptions for 4 instructions. Accordingly, a supplementary prompt can be output to guide the user to supplement the missing instruction descriptions. The supplementary prompt can be in text or voice format; this embodiment of the invention does not limit this. The supplementary prompt can include the number of missing instructions. For example, the supplementary prompt can be text: "Please supplement the instruction descriptions for the missing X instructions." Here, X is the difference between the total number of instructions in the architecture to be added and the total number of instruction descriptions (i.e., the number of missing instructions). For example, the supplementary prompt can be displayed on the device screen to output the supplementary prompt. This way, displaying the number of missing instructions in the supplementary prompt allows the user to easily know the number of instructions that need to be supplemented. Alternatively, in one implementation, the values ​​of the `genNumInst` and `totalNumInstrs` parameters (i.e., the total number of instruction descriptions and the total number of instructions) can be directly output, along with the generated instruction descriptions. By outputting the currently generated instruction descriptions to the user, it facilitates the user's ability to identify which instruction descriptions are missing.

[0095] After obtaining the instruction set description file, the generated instruction set description file can be used as a compiler configuration file and configured for the compiler backend of the target compiler. For example, the instruction set description file can be written into the target compiler's configuration file using the WRITE instruction for use by the target compiler. In this embodiment of the invention, an initial file can also be created in the target compiler's configuration file. The initial file is initially empty and can be a file of type .h.

[0096] Users can enter supplementary instruction descriptions to the generated instruction set description file on the input interface and trigger a submit control, which can be a submit button on the input interface. Correspondingly, the electronic device can receive the user-input instruction descriptions and then write the received instruction descriptions and the currently generated instruction descriptions into an initial file to obtain the final instruction set description file.

[0097] It should be noted that when the user provides supplementary information, a completion prompt message can be output. This message prompts the user to improve the executable file of the basic architecture and the compiled code of the architecture to be added, ensuring that these files cover the instructions corresponding to the user-added instruction description. For example, if the user-added instruction description corresponds to a multiplication instruction, then the functionality requiring multiplication can be added to the compiled code of the architecture to be added. The assembly instructions requiring multiplication are added to the assembly instruction file of the basic architecture, and the file is recompiled to obtain a new executable file for the basic architecture. Correspondingly, the executable file for the architecture to be added can be obtained again based on the compiled code of the architecture to be added or the executable file of the basic architecture. A new instruction set description file is then generated based on the newly obtained executable file for the architecture to be added.

[0098] Understandably, if the total number of instruction descriptions matches the total number of instructions for the architecture to be added, then the generated instruction descriptions are complete. Therefore, the currently generated instruction description file can be directly written into the initial file to obtain the final instruction set description file. Furthermore, the total number of instruction descriptions and the total number of instructions can be output to facilitate users in verifying the quantities again.

[0099] Figure 4 This is a flowchart illustrating the generation of an instruction description provided in an embodiment of the present invention, such as... Figure 4As shown, an initial file can be created first. Starting from the first line of the preset set, iterate through the description file template based on the instruction name and opcode of the currently traversed line to obtain the instruction description. Write the generated instruction description to the preset file and increment the total number of instruction descriptions by 1. The initial value of the total number of instruction descriptions is 0. If a next line still exists in the preset set, begin traversing that next line until all lines in the preset set have been traversed. Once all lines in the preset set have been traversed, the generation of instruction descriptions ends.

[0100] The opcode in the currently traversed line can be used as the value of the insMap.key parameter, and the instruction name in the currently traversed line can be used as the value of the insMap.value parameter. When traversing the next line, the value of the insMap.key parameter can be updated to the binary code of the next line, and the value of the insMap.value parameter can be updated to the instruction name of the next line.

[0101] In this embodiment of the invention, the total number of instructions described is checked against the total number of instructions in the architecture to be added. If they are inconsistent, the user is prompted to supplement the instructions. Thus, even if user supplementation is required, this embodiment of the invention first generates the instruction set description file automatically, requiring only minimal user input, improving efficiency while ensuring the completeness of the final generated instruction set description file.

[0102] Optionally, the step of filling the description file template based on the opcode and instruction name of each binary instruction may specifically include: Step 1032a: For any row of the preset set, write the opcode and the instruction name into the opcode filling position and the name filling position in the description file template, respectively.

[0103] Step 1032b: If the description file template also includes a relevant information filling position, obtain the relevant information based on the opcode and the instruction information to which the instruction name belongs, and write it into the relevant information filling position. The relevant information includes one or more of the following: instruction type, opcode mask, and usage flag.

[0104] In this embodiment of the invention, for a row in the preset set that is currently being traversed, the opcode and instruction name (i.e., the opcode and instruction name of the binary instruction represented by the row) in the row can be written into the opcode filling position and the name filling position in the target template, respectively.

[0105] For example, suppose the target template is: INST(instruction name, "instruction name" instruction type opcode, opcode mask, usage flags) The "Instruction Name" section indicates the instruction name padding location, which can be described as: the instruction name needs to be filled. The "Opcode" section indicates the opcode padding location, which can be described as: the opcode needs to be filled. All other sections are related information padding locations. Specifically, "Instruction Type," "Opcode Mask," and "Usage Flags" are all related information padding locations. "Instruction Type" indicates the type padding location, which can be described as: a flag indicating whether the instruction is a memory operation type; filled with 1 if the instruction is a memory operation type, and 0 otherwise. "Opcode" indicates the mask padding location, which can be described as: the opcode mask of the instruction needs to be filled. "Usage Flags" indicates the usage padding location, which can be described as: flags indicating the use of registers and immediate values ​​in the instruction need to be filled.

[0106] Accordingly, when a type padding position exists, it can be checked whether the instruction name belongs to a preset name set. This preset name set records the instruction names of all instructions of the memory operation type. If it belongs, the value 1 is used as the relevant information for the type padding position. Otherwise, the value 0 is used as the relevant information for the type padding position. When a mask padding position exists, if the input mask is not all zeros, the previously input mask can be used as the relevant information for the mask padding position. If the input mask is all zeros, a mask is generated based on the target bit field in the binary encoding corresponding to the current traversal line (i.e., the binary encoding in the instruction information to which the instruction name belongs in the current traversal line) to serve as the relevant information for the mask padding position. For example, the target bit field in the all-zero mask can be set to 1 to obtain the relevant information for the mask padding position. In this embodiment of the invention, a correspondence between the conditions satisfied by the values ​​of specific bit fields and the usage flags (hereinafter referred to as the fourth correspondence) can be pre-created for each non-fixed architecture. When padding positions exist, the usage flag corresponding to the target value in the binary code of the currently traversed row can be retrieved from the fourth mapping pre-created for the schema to be added, serving as relevant information for using padding positions. The fourth mapping for the schema to be added can be stored in a fourth storage location, which can be pre-specified by the developer. For example, the fourth mapping for the schema to be added can be loaded from the fourth storage location.

[0107] Assume that the fourth correspondence of the architecture to be added includes: [The value of the specific positioning field must meet the following conditions: the value is equal to 0x6, 0x5, or 0x4; the flag used is DF_G_2R12I] [The value of the specific positioning field must satisfy the following conditions: the value is equal to 0x3; the flag used is DF_G_3R].

[0108] Accordingly, when the target value is 0x6, DF_G_2R12I can be used as information related to the padding position.

[0109] Then, write the opcode to the opcode padding position, write the instruction name to the name padding position; write the relevant information of the type padding position to the type padding position, write the relevant information of the mask padding position to the mask padding position, and write the relevant information of the use padding position to the use padding position.

[0110] For example, taking the first row in the current traversal of the preset set as an example, the relevant information for the type padding position determined for this row is: 0, the relevant information for the mask padding position is: 0xffc00000, and the relevant information for the padding position is: DF_G_2R12I. Wherein, DF_G_mRnI indicates that the instruction uses m registers and n-bit immediate values. When m is 0, the mR part can be omitted; when n is 0, the nI part can be omitted. Therefore, in this embodiment, the number of registers used by the instruction is m=2, and the number of immediate values ​​is n=12. Accordingly, the instruction description generated for this row can be: INST (addi_d, "addi_d" 0 0x02c00000, 0xffc00000, DF_G_2R12I) Taking the second row in the current traversal of the preset set as an example, the relevant information for the type padding position determined for this row is: 0; the relevant information for the mask padding position is: 0xffc00000; and the relevant information for the padding position is: DF_G_2R12I. Correspondingly, the instruction description generated for this row can be: INST (st.d, "st.d" 0 0x29c00000, 0xffc00000, DF_G_2R12I) In this embodiment of the invention, for any row of the preset set containing the opcode and instruction name, the opcode and instruction name are respectively written into the opcode filling position and name filling position in the description file template. If the description file template also includes relevant information filling positions, relevant information is obtained based on the instruction information to which the opcode and instruction name belong, and then written into the relevant information filling positions. This ensures the completeness of the generated instruction descriptions and avoids information omissions.

[0111] Reference Figure 5The diagram shows a block diagram of a document generation apparatus provided in an embodiment of the present invention, such as... Figure 5 As shown, the device for generating this file may specifically include: The first acquisition module 201 is used to acquire the instruction file of the architecture to be added; the instruction file includes instruction information of each binary instruction supported by the architecture to be added; the instruction information is used to describe the components of the binary instruction; The second acquisition module 202 is used to acquire, based on the instruction information in the instruction file, the opcode and instruction name of each binary instruction supported by the architecture to be added; The generation module 202 is used to generate an instruction set description file adapted to the target compiler for the architecture to be added, based on the description file format of the target compiler, the opcode of each binary instruction, and the instruction name.

[0112] Optionally, the first acquisition module 201 is specifically used for: Obtain the executable file for the architecture to be added; the executable file includes binary instructions supported by the architecture to be added; The executable file of the architecture to be added is disassembled to obtain the instruction file of the architecture to be added.

[0113] Optionally, the first acquisition module 201 is further configured to: The executable file of the infrastructure is obtained according to the assembly instruction file of the preset infrastructure; the executable file of the infrastructure includes the binary instructions supported by the infrastructure. The binary translation tool based on the architecture to be added translates the executable file of the basic architecture into the executable file of the architecture to be added; Alternatively, obtain the pre-set code to be compiled for the architecture to be added; the code to be compiled includes statements for generating instructions defined in the instruction set of the architecture to be added; The code to be compiled is then compiled to obtain the executable file of the architecture to be added.

[0114] Optionally, the second acquisition module 202 is specifically used for: For any line of instruction information in the instruction file, extract the binary code and instruction name from the instruction information one by one; one line of instruction information corresponds to one binary instruction supported by the architecture to be added. Based on the binary encoding, the opcode of the binary instruction represented by the instruction information is extracted respectively.

[0115] Optionally, the second acquisition module 202 is further configured to: When the opcode corresponds to a fixed bit field, the content of the fixed bit field in the binary code is extracted to obtain the opcode; When the opcode corresponds to a non-fixed bit field, the bit field in the binary code where the opcode is located is determined based on the value of a specific bit field in the binary code, and the content in the bit field is extracted as the opcode.

[0116] Optionally, the device further includes: The detection module is used to detect whether the opcode and the instruction name exist in a preset set; the preset set is used to record the opcode and instruction name of each binary instruction. The writing module is used to write the opcode and instruction name into the preset set if the opcode does not exist. The processing module is used to directly extract the next line of instruction information from the instruction file.

[0117] Optionally, the generation module 203 is specifically used for: For any of the target compilers, obtain the description file template of the target compiler; the description file template follows the description file format of the target compiler and is used to indicate the padding positions of the opcodes and the instruction names; Based on the opcode and instruction name of each binary instruction, the description file template is filled to obtain the corresponding instruction description for each binary instruction; Based on the instruction descriptions corresponding to each binary instruction, an instruction set description file adapted to the target compiler is generated.

[0118] Optionally, the generation module 203 is further configured to: For any row in the preset set, the opcode and the instruction name are written into the opcode filling position and the name filling position in the description file template, respectively. If the description file template also includes a relevant information filling position, the relevant information is obtained based on the opcode and the instruction information to which the instruction name belongs, and written into the relevant information filling position; the relevant information includes one or more of the following: instruction type, opcode mask, and usage flag.

[0119] In summary, the file generation apparatus provided in this embodiment of the invention obtains an instruction file for the architecture to be added. The instruction file includes instruction information for each binary instruction supported by the architecture to be added, and the instruction information describes the components of the binary instructions. Based on the instruction information in the instruction file, the opcode and instruction name of each binary instruction supported by the architecture to be added are obtained. Based on the description file format of the target compiler, the opcode of each binary instruction, and the instruction name, an instruction set description file adapted to the target compiler is generated for the architecture to be added. Thus, by automatically generating an instruction set description file adapted to the target compiler, developers are not required to manually write the instruction set description file, improving the generation efficiency of the instruction set description file.

[0120] Furthermore, instruction set description files adapted to the target compiler are generated according to the target compiler's description file format, ensuring that the generated instruction set description files conform to the description file format required by the target compiler. This ensures that the generated instruction set description files can be correctly recognized and used by the target compiler, improving the code's universality during the instruction set architecture adaptation process.

[0121] Reference Figure 6 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. For example... Figure 6 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus.

[0122] The processor, the memory, and the communication interface communicate with each other via the communication bus; the memory stores at least one executable instruction, which causes the processor to execute the file generation method of the aforementioned embodiment. The executable instructions can form a program.

[0123] This invention provides a machine-readable medium storing instructions that, when executed by one or more processors, enable the processors to perform the file generation method described in the preceding embodiments. The machine-readable medium may be one or more.

[0124] The foregoing has provided a detailed description of a document generation method, a document generation device, an electronic device, and a readable medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for generating a file, characterized in that, The method includes: Obtain the instruction file for the architecture to be added; the instruction file includes instruction information for each binary instruction supported by the architecture to be added; the instruction information is used to describe the components of the binary instruction; Based on the instruction information in the instruction file, obtain the opcode and instruction name of each binary instruction supported by the architecture to be added; Based on the target compiler's description file format, the opcodes of each binary instruction, and the instruction names, an instruction set description file adapted to the target compiler is generated for the architecture to be added.

2. The method according to claim 1, characterized in that, The instruction file for obtaining the architecture to be added includes: Obtain the executable file for the architecture to be added; the executable file includes binary instructions supported by the architecture to be added; The executable file of the architecture to be added is disassembled to obtain the instruction file of the architecture to be added.

3. The method according to claim 2, characterized in that, The step of obtaining the executable file for the architecture to be added includes: The executable file of the infrastructure is obtained according to the assembly instruction file of the preset infrastructure; the executable file of the infrastructure includes the binary instructions supported by the infrastructure. The binary translation tool based on the architecture to be added translates the executable file of the basic architecture into the executable file of the architecture to be added; Alternatively, obtain the pre-set code to be compiled for the architecture to be added; the code to be compiled includes statements for generating instructions defined in the instruction set of the architecture to be added; The code to be compiled is then compiled to obtain the executable file of the architecture to be added.

4. The method according to claim 1, characterized in that, The step of obtaining the opcode and instruction name of each binary instruction supported by the architecture to be added includes: For any line of instruction information in the instruction file, extract the binary code and instruction name from the instruction information one by one; one line of instruction information corresponds to one binary instruction supported by the architecture to be added. Based on the binary encoding, the opcode of the binary instruction represented by the instruction information is extracted respectively.

5. The method according to claim 4, characterized in that, The step of extracting the opcode of the binary instruction represented by the instruction information includes: When the opcode corresponds to a fixed bit field, the content of the fixed bit field in the binary code is extracted to obtain the opcode; When the opcode corresponds to a non-fixed bit field, the bit field in the binary code where the opcode is located is determined based on the value of a specific bit field in the binary code, and the content in the bit field is extracted as the opcode.

6. The method according to claim 4, characterized in that, The method further includes: The system checks whether the opcode and the instruction name exist in a preset set; the preset set is used to record the opcode and instruction name of each binary instruction. If it does not exist, the opcode and instruction name are written into the preset set; Otherwise, extract the instruction information from the next line in the instruction file directly.

7. The method according to any one of claims 1-6, characterized in that, The step of generating an instruction set description file adapted to the target compiler for the architecture to be added includes: For any of the target compilers, obtain the description file template of the target compiler; the description file template follows the description file format of the target compiler and is used to indicate the padding positions of the opcodes and the instruction names; Based on the opcode and instruction name of each binary instruction, the description file template is filled to obtain the corresponding instruction description for each binary instruction; Based on the instruction descriptions corresponding to each binary instruction, an instruction set description file adapted to the target compiler is generated.

8. The method according to claim 7, characterized in that, The description file template is filled based on the opcode and instruction name of each binary instruction, including: For any row in the preset set, the opcode and the instruction name are written into the opcode filling position and the name filling position in the description file template, respectively. If the description file template also includes a relevant information filling position, the relevant information is obtained based on the opcode and the instruction information to which the instruction name belongs, and written into the relevant information filling position; the relevant information includes one or more of the following: instruction type, opcode mask, and usage flag.

9. A document generation device, characterized in that, The device includes: The first acquisition module is used to acquire the instruction file of the architecture to be added; the instruction file includes instruction information of each binary instruction supported by the architecture to be added; the instruction information is used to describe the components of the binary instruction; The second acquisition module is used to acquire the opcode and instruction name of each binary instruction supported by the architecture to be added, based on the instruction information in the instruction file. The generation module is used to generate an instruction set description file adapted to the target compiler for the architecture to be added, based on the description file format of the target compiler, the opcode of each binary instruction, and the instruction name.

10. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that cause the processor to perform the method as described in any one of claims 1 to 8.

11. A machine-readable medium, characterized in that, It stores instructions that, when executed by one or more processors, cause the processors to perform the method as described in any one of claims 1 to 8.

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