Device and method for accelerating encryption algorithm
By designing hardware devices to accelerate encryption algorithms and utilizing DMA control descriptors and data transfer, the hardware-level processing of encryption algorithms is optimized, solving the problems of low computational efficiency and stability of traditional general-purpose processors under high concurrency and large data volumes, and achieving efficient and stable encryption operations.
Patent Information
- Application Number
- CN202511852586.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-10
- Publication Date
- 2026-03-03
AI Technical Summary
Traditional general-purpose processors have low computational efficiency when executing encryption algorithms, especially under high concurrency and large data volume conditions. They are unable to meet the low latency requirements of scenarios such as financial transactions and real-time communication. Furthermore, the software implementation is easily affected by the operating system scheduling and memory access speed, which leads to a decrease in the stability and real-time performance of encryption operations.
Design a device to accelerate encryption algorithms. The device connects to the read control module, write-back control module, and prefetch control module via the AXI main interface and the transmission channel. It utilizes DMA to control the transfer of descriptors and data, reducing CPU involvement. The device employs hardware-level optimization design, including a read channel, write-back channel, read cache, write cache, and algorithm core module, to achieve hardware parsing of the data stream.
It improves the computational efficiency of encryption algorithms, reduces reliance on CPU performance, enhances the stability and real-time performance of data processing, and can meet the low-latency requirements of scenarios such as financial transactions and real-time communication.
Smart Images
Figure CN121598408A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of security encryption technology, specifically to an apparatus and method for accelerating encryption algorithms. Background Technology
[0002] In the digital age, data security has become a core requirement in many fields such as financial transactions, cloud computing, the Internet of Things, and communication transmission. Encryption algorithms, as key technologies for ensuring data confidentiality, integrity, and availability, are seeing their application scope continuously expand. From symmetric encryption algorithms (such as AES and DES) to asymmetric encryption algorithms (such as RSA and ECC), and then to hash algorithms (such as SHA-256 and SM3), different types of encryption algorithms need to provide different levels of security protection depending on the scenario requirements. For example, in real-time payment transactions in the financial sector, the AES algorithm is needed to quickly encrypt transaction data, ensuring that each transaction completes security verification within milliseconds. In cloud computing scenarios, the storage encryption and transmission decryption of massive amounts of user data rely on RSA or ECC algorithms for key negotiation. These scenarios all place extremely high demands on the computational efficiency of encryption algorithms. However, the core computational processes of encryption algorithms (such as large integer modular exponentiation, round function transformation, and hash compression) often involve complex mathematical operations, consuming significant hardware computing resources. Traditional encryption algorithm implementations primarily rely on general-purpose processors (CPUs) for software-level computations. Although general-purpose processors possess flexible programming capabilities and can adapt to various encryption algorithms, their computational efficiency faces significant bottlenecks when dealing with high-concurrency, large-data-volume encryption requirements. Taking the large integer modular exponentiation of the RSA algorithm as an example, when the key length increases to 2048 bits or more to meet higher security levels, the single-threaded computation time of the general-purpose processor increases significantly, making it difficult to meet the low-latency requirements of scenarios such as financial transactions and real-time communication. Furthermore, software implementations are also susceptible to factors such as operating system scheduling and memory access speed, further degrading the stability and real-time performance of encryption operations. With the continuous upgrading of information security requirements, the security strength of encryption algorithms is constantly improving (such as the key length increasing from 1024 bits to 4096 bits, and the hash algorithm upgrading from SHA-1 to SHA-3). Consequently, their computational complexity is also increasing significantly. Traditional general-purpose processor software implementations are gradually becoming inadequate for current application scenarios. Against this backdrop, developing dedicated devices and methods that can specifically accelerate the encryption algorithm computation process through hardware-level optimization design has become a key direction for improving the efficiency of data security processing. Summary of the Invention
[0003] In order to solve the above-mentioned technical problems, this application proposes the following technical solution: In a first aspect, embodiments of this application provide an apparatus for accelerating encryption algorithms, comprising: an AXI main interface, a transmission channel electrically connected to the AXI main interface, the transmission channel being connected to a read control module, a write-back control module, and a prefetch control module respectively, the request end of the prefetch control module being communicatively connected to an algorithm core, the algorithm core module being communicatively connected to both the AHB main interface and the transmission channel; a read arbitrator and a write arbitrator are respectively provided for the read control module and the write-back control module, the read arbitrator and the write arbitrator being connected to a data queue respectively, the read arbitrator and the write arbitrator being used to arbitrate requests for descriptors and requests for data in the data queue, and to determine the processing priority.
[0004] In one possible implementation, the transmission channel includes a read channel and a write-back channel. The read channel retrieves descriptors or reads data from system memory based on the source address or context address of the descriptor. The read channel includes a read buffer that stores the type of the output read command. The command type includes a descriptor, context data, and actual data. The command data is stored in the read buffer along with the queue number. The write-back channel is used for data transmission and descriptor write-back.
[0005] In one possible implementation, the read control module controls the DMA to prefetch descriptors or read data. When the read controller receives a request to read a descriptor, it begins transmitting a read command with a descriptor command type. When the read controller receives a read data transmission request, it begins transmitting a read command with a data command type. When reading data, it is necessary to identify the valid bytes of the data. The write-back control module controls the DMA to write back the state of the descriptor or write back the result data to a specified address. When the write-back controller receives a write-back descriptor request, it begins writing back the state of the descriptor. When the write-back controller receives a write-back data transmission request, it begins writing back the result data.
[0006] In one possible implementation, the data queue includes: a read data queue, a descriptor control queue, and a descriptor write-back control module. The read data queue stores the current descriptors for each queue. When started and the queue buffer is not empty, it reads descriptors from the queue buffer and sends a request to the read arbitrator to request data reading. The descriptor control queue manages the descriptors in the queue. When started, it sends a request to prefetch descriptors. When the number of descriptors in the queue is less than a preset number, it sends a request to prefetch descriptors. The descriptor write-back control module stores descriptors that need to be written back. When the number of descriptors to be written back is greater than a preset number, it requests a write-back status. When the number of descriptors is consistently lower than the preset number, it forces the controller to write back the status.
[0007] In one possible implementation, a read cache module is provided between the transmission channel and the prefetch control module, the read cache module being used to cache the data read back; a write cache module is provided between the transmission channel and the algorithm core module, the write cache module being used to cache the data that needs to be written back.
[0008] In one possible implementation, the algorithm core module includes a symmetric algorithm core, a hash algorithm core, mode control, and algorithm complement control information. The AHB main interface automatically obtains the key required for each encryption based on the channel number of the descriptor and the address configured in the register.
[0009] In one possible implementation, it also includes an AXI slave interface, an AHB slave interface, and a register control module. The AXI slave interface is configured with general information, and the AHB slave interface is configured with key control information. The register control module is used for register control.
[0010] In a second aspect, embodiments of this application provide a method for accelerating encryption algorithms, based on the apparatus described in any possible implementation of the first aspect, comprising: Complete the descriptor filling operation according to application requirements, including the selection of algorithm type, mode selection, data source address, result write-back address, address of additional data, data processing length, and required context information; Configure the corresponding control registers according to the actual application. When a descriptor update is detected, update the queue descriptor tail register according to the actual available descriptors. Based on the retrieved descriptor, the data to be processed is obtained by combining it with the corresponding source address; The processed data is cached within the accelerated IP and written back to the corresponding locations sequentially according to the write-back address in the descriptor; After encryption and decryption are completed, the corresponding descriptor state is written back and the relevant interrupt is triggered to notify the top-level transmission is complete.
[0011] In one possible implementation, updating the queue descriptor tail register according to the actually available descriptors when an update is detected includes: If a descriptor update is detected, the system will automatically determine whether to initiate a descriptor prefetch operation based on the difference between the queue descriptor head register and the queue descriptor tail register maintained by the internal hardware. If prefetching is required, the corresponding descriptor will be retrieved from the already configured descriptor address; The register control module in the architecture outputs descriptor control-related information, and the read control module initiates a read descriptor operation to enter the arbitrator. The read descriptor command enters the read control module, which then enters the AXI main interface. After the read command enters the AXI bus, it obtains the corresponding descriptor information and writes it into the read cache. After the read-back descriptor enters the read control module, it is identified as a read descriptor based on the type of the returned read command, and the read-back data is placed into the corresponding queue descriptor cache in the descriptor control module.
[0012] In one possible implementation, the processed data is cached within the acceleration IP and written back to the corresponding locations sequentially according to the write-back address in the descriptor, including: The read data is categorized by the read control module to determine whether the read data is a descriptor, context, or data that needs to be processed. The processed data enters the read FIFO and then enters the algorithm core through the prefetch control module. The algorithm core inputs data based on whether complement processing is required, the algorithm mode, and the corresponding algorithm core. The processed data is cached in the write FIFO. After the data accumulates to a certain level, a request will be sent to read the relevant information of the write-back descriptor. Based on the write-back address in the descriptor, the data will be written back to the corresponding location in sequence. After the data write-back is completed, the write-back descriptor status is written back. The write-back command enters the write-back control module, enters the AXI main interface through the write channel, and is sent to the AXI bus to reach the specified address.
[0013] In this embodiment, a multi-channel descriptor ring cache is supported. During idle periods when there are valid descriptors and the processor has no data transfer, sufficient descriptors can be acquired, reducing latency during descriptor or channel switching and improving data processing efficiency. Complex algorithm processing is placed within descriptors, and hardware resolution of descriptors enables the processing of the entire data stream, significantly reducing CPU involvement and dependence on CPU performance. Attached Figure Description
[0014] Figure 1 A schematic diagram of a device for accelerating encryption algorithms provided in an embodiment of this application; Figure 2 This is a schematic diagram of a method for accelerating encryption algorithms provided in an embodiment of this application. Detailed Implementation
[0015] The present solution will now be described in conjunction with the accompanying drawings and specific embodiments.
[0016] See Figure 1The apparatus for accelerating encryption algorithms provided in this embodiment includes: an AXI main interface, a transmission channel electrically connected to the AXI main interface, and a traditional channel connected to a read control module, a write-back control module, and a prefetch control module, respectively. The request end of the prefetch control module is communicatively connected to the algorithm core, and the algorithm core module is communicatively connected to both the AHB main interface and the transmission channel. A read arbitrator and a write arbitrator are respectively provided for the read control module and the write-back control module. The read arbitrator and the write arbitrator are each connected to a data queue. The read arbitrator and the write arbitrator are used to arbitrate requests for descriptors and requests for data in the data queue to determine the processing priority.
[0017] In this embodiment, when SYM starts working, the AXI main interface first obtains a descriptor, then reads data from memory based on the source address of the descriptor and pushes it to the SYM kernel. After data encryption or decryption is complete, it writes the result data to memory based on the result address of the descriptor. After the result data transmission is complete, it writes the result status to the descriptor.
[0018] The transmission channels include a read channel and a write-back channel. The read channel includes a read buffer and does not support out-of-order data transmission. The read channel may retrieve descriptors or read data from system memory based on the source address or context address of the descriptor; therefore, we need to distinguish the type of data being read. When data is read back, we need to identify whether the data is a descriptor or context data, whether it is encrypted or decrypted, and which queue the data belongs to. Therefore, we store the type of output read command in the read buffer. Command types include descriptors, context data, and actual data; the command data is stored in the read buffer along with the queue number. The write-back channel is mainly used for data transmission and descriptor write-back.
[0019] The read control module controls the DMA to prefetch descriptors or read data. When the read controller receives a request to read a descriptor, it begins transmitting a read command with a descriptor command type; when the read controller receives a request to read data, it begins transmitting a read command with a data command type. When reading data, it needs to identify the valid bytes of the data.
[0020] The write-back control module controls the DMA to write back the state of the descriptor or to write back the result data to a specified address. When the write-back controller receives a write-back descriptor request, it will begin writing back the descriptor's state; when the write-back controller receives a write-back data transfer request, it will begin writing back the result data.
[0021] The data queue includes a read data queue, a descriptor control queue, and a descriptor write-back control module. The read data queue stores the current descriptors for each queue. Upon startup and when the queue buffer is not empty, it reads descriptors from the queue buffer and sends a request to the arbitration controller to request data read. Initially, it should read context data based on the context address. Context data is used for kernel encryption or decryption. Afterward, it reads the actual data based on the source address.
[0022] The descriptor control queue manages the descriptors in the queue. Upon startup, it sends requests to prefetch descriptors. It also sends requests to prefetch descriptors when the number of descriptors in the queue falls below a defined trigger parameter (configured by registers). Internally, it maintains a virtual head, a real head, and a real tail. The virtual head represents the last descriptor whose state is not written back; the real head indicates the currently used descriptor; and the real tail is updated by software.
[0023] The descriptor write-back control module stores descriptors that need to be written back. When the number of descriptors to be written back exceeds the defined trigger parameter, it will request a write-back status. There is a timeout mechanism; if the number of descriptors remains below the defined trigger parameter for an extended period, the controller will be forced to write back the status.
[0024] A read cache module is provided between the transmission channel and the prefetch control module to cache the read data; a write cache module is provided between the transmission channel and the algorithm core module to cache data that needs to be written back. The prefetch control module is mainly used to prefetch data from the read data cache and then write the prefetched data to the encryption core when the encryption core is idle. The algorithm core module includes a symmetric algorithm core, a hash algorithm core, mode control, and algorithm complement control information. The AHB main interface automatically obtains the key required for each encryption based on the channel number of the descriptor and the address configured in the register.
[0025] The device for accelerating the encryption algorithm in this embodiment further includes an AXI slave interface, an AHB slave interface, and a register control module. The AXI slave interface is configured with general information, and the AHB slave interface is configured with key control information. The register control module is used for register control, which can control some basic control information of the acceleration IP through registers, thereby controlling the acceleration algorithm IP.
[0026] Corresponding to the apparatus for accelerating encryption algorithms provided in the above embodiments, this application also provides an embodiment of a method for accelerating encryption algorithms.
[0027] See Figure 2 The method for accelerating the encryption algorithm in this embodiment includes: S101, complete the descriptor filling operation according to application requirements, including algorithm type selection, mode selection, data source address, result write-back address, address of additional data, data processing length, and required context information. This embodiment provides the following types of algorithms: a1. Symmetric Algorithm Mode: In a.HEADER0, the key mode selection can be based on the context (plaintext or ciphertext) or internally, reading the corresponding key based on the context key ID. The context mode, encryption / decryption mode, and symmetric algorithm mode can also be selected according to actual application requirements; enable address list mode; select symmetric algorithm mode.
[0028] b. Fill in the address list, including the addresses and their length.
[0029] c. Enter the output data address.
[0030] d. Configure the context address.
[0031] e. Fill in the data address and length according to the address list.
[0032] f. Fill in the corresponding context descriptor based on the context address.
[0033] a2. Hash Algorithm Patterns: The context mode, hash algorithm flag, and hash algorithm in HEADER0 can be selected according to actual application requirements; enable address list mode; select hash algorithm mode.
[0034] b. Fill in the address list, including the addresses and their length.
[0035] c. Enter the output data address.
[0036] d. Configure the context address.
[0037] e. Fill in the data address and length according to the address list.
[0038] f. Fill in the corresponding context descriptor based on the context address.
[0039] a3. Authentication Algorithm Mode: The key mode, context mode, encryption / decryption mode, authentication algorithm, and authentication mode in HEADER0 can also be selected according to actual application requirements; enable address list mode; select authentication algorithm mode.
[0040] b. Fill in the address list, including the addresses and their length.
[0041] c. Enter the output data address.
[0042] d. Configure the context address.
[0043] e. Fill in the data address and length according to the address list.
[0044] f. Fill in the corresponding context descriptor based on the context address.
[0045] a4. Additional Data Mode: In a.HEADER0, the key mode, context mode, encryption / decryption mode, extra data authentication length, extra data mode, authentication algorithm, authentication mode, hash algorithm, and symmetric algorithm can be selected according to actual application requirements; enable address list mode; select extra data mode.
[0046] b. Fill in the address list, including the addresses and their length.
[0047] c. Enter the output data address.
[0048] d. Configure the context address.
[0049] e. Fill in the data address and length according to the address list.
[0050] f. Fill in the corresponding context descriptor based on the context address.
[0051] a5. Zu Chongzhi's model: The key mode, context mode, encryption / decryption mode, authentication algorithm, hash algorithm, and symmetric algorithm in HEADER0 can also be selected according to actual application requirements; enable address list mode.
[0052] b. Fill in the address list, including the addresses and their length.
[0053] c. Enter the output data address.
[0054] d. Configure the context address.
[0055] e. Fill in the data address and length according to the address list.
[0056] f. Fill in the corresponding context descriptor based on the context address.
[0057] S102: Configure the corresponding control register according to the actual application. When a descriptor update is detected, update the queue descriptor tail register according to the actual available descriptors.
[0058] Configure the corresponding control registers according to the actual application. These mainly include the queue control register, which enables the entire algorithm core; the queue interrupt enable register, which enables the corresponding interrupt; the queue interrupt control register, which sets the interrupt cascading; the queue descriptor base address register, which sets the descriptor start address; the queue descriptor control register, which sets the descriptor size and the descriptor ring size; and the algorithm key address register, which sets the start address of the internal key. This configuration is primarily used in the architecture's AXI slave interface, AHB slave interface, and register control module.
[0059] The queue descriptor tail register is updated based on the available descriptors. When the algorithm acceleration device detects an update, it automatically determines whether descriptor prefetching needs to be initiated based on the difference between the queue descriptor head register and the queue descriptor tail register maintained internally by the hardware. If prefetching is required, the corresponding descriptor is retrieved from the configured descriptor address. The register control module in the architecture outputs descriptor control information, and the read control module initiates a read descriptor operation, entering the arbitrator. Since there is only a read descriptor operation, arbitration is not required. The read descriptor command enters the read control module, which then enters the AXI main interface. After the read command enters the AXI bus, the corresponding descriptor information is obtained and written to the read buffer. The read descriptor, upon entering the read control module, is identified as a read descriptor based on the returned read command type, and the read data is placed into the corresponding queue descriptor buffer in the descriptor control module.
[0060] S103: Based on the retrieved descriptor, retrieve the data to be processed using the corresponding source address.
[0061] The read control module issues a command to retrieve the data to be processed from the corresponding source address; based on the control information configuration of the descriptor, the read control module outputs the corresponding algorithm core enable and mode information; based on the channel number and key mode in the descriptor, the AHB main interface decides whether to retrieve the key required by the corresponding algorithm; the read control module issues a command to read the context information required by the algorithm based on the context address in the descriptor.
[0062] S104: The processed data is cached within the accelerated IP and written back to the corresponding locations sequentially according to the write-back address in the descriptor.
[0063] The read data is categorized by the read control module, determining whether it is a descriptor, context, or data to be processed based on its type. Processed data enters the read FIFO and is then fed into the algorithm core via the prefetch module. The algorithm core inputs data based on whether complement processing is required, the algorithm mode, and the corresponding algorithm core. Processed data is buffered in the write FIFO. Once a certain amount of data has accumulated, a request is sent to read the write-back descriptor information. Based on the write-back address in the descriptor, the data is written back to the corresponding location sequentially. After the data write-back is complete, the descriptor state is written back. Therefore, the arbitrator on the right receives two types of data: write-back data and write-back descriptors. The write-back command enters the write-back control module, enters the AXI main interface through the write channel, and is sent to the specified address on the AXI bus. a1. Symmetric Algorithm Mode: a. Write back the calculation result data based on the data output address.
[0064] b. Write back the specific length of the output data to the high 16 bits of the data address descriptor.
[0065] c. The write-back is the initial value position in the context structure used during the encryption and decryption process.
[0066] a2. Hash Algorithm Patterns: a. Write back the last hash value to the digest value location of the context address.
[0067] a3. Authentication Mode: a. Write back the last authentication value to the authentication digest value location in the context address.
[0068] a4. Additional Data Mode: a. Write back the calculation result data based on the data output address.
[0069] b. Write back the specific length of the output data to the high 16 bits of the data address descriptor.
[0070] c. Write back the last authentication value to the authentication digest value location in the context address.
[0071] d. The initial value position of the IV used in the encryption and decryption process is written back to the context structure.
[0072] e. Write back the GHASH value to the corresponding location in the context address.
[0073] a5. Zu Chongzhi Model a. Write back the calculation result data based on the data output address.
[0074] b. Write back the specific length of the output data to the high 16 bits of the data address descriptor.
[0075] c. Write back the last authentication value to the authentication digest value location in the context address.
[0076] S105, after encryption and decryption are completed, write back the corresponding descriptor state and set the relevant interrupt to notify the top-level transmission is complete.
[0077] After encryption and decryption are complete, the corresponding descriptor state is written back and the relevant interrupt is triggered to notify the top-level transmission is complete. This operation is mainly performed in the register control module. Interrupts support cascading, allowing multiple interrupts to respond to a single interrupt, reducing CPU processing time.
[0078] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.
[0079] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.
Claims
1. An apparatus for accelerating encryption algorithms, characterized in that, include: The AXI main interface is connected to a transmission channel electrically connected to the AXI main interface. The traditional channel is connected to a read control module, a write-back control module, and a prefetch control module, respectively. The request end of the prefetch control module is communicatively connected to the algorithm core. The algorithm core module is communicatively connected to both the AHB main interface and the transmission channel. A read arbitrator and a write arbitrator are respectively set for the read control module and the write-back control module. The read arbitrator and the write arbitrator are each connected to a data queue. The read arbitrator and the write arbitrator are used to arbitrate the requests for descriptors and data in the data queue to determine the processing priority.
2. The apparatus for accelerating encryption algorithms according to claim 1, characterized in that, The transmission channel includes a read channel and a write-back channel. The read channel retrieves descriptors or reads data from system memory based on the source address or context address of the descriptor. The read channel includes a read buffer, which stores the type of output read command. The command type includes descriptor, context data, and actual data. The command data is stored in the read buffer along with the queue number. The write-back channel is used for data transmission and descriptor write-back.
3. The apparatus for accelerating encryption algorithms according to claim 2, characterized in that, The read control module is used to control the DMA to prefetch descriptors or read data. When the read controller receives a request to read a descriptor, it will start transmitting a read command with a descriptor command type. When the read controller receives a read data transfer request, it will begin transmitting a read command in the data command type; when reading data, it needs to identify the valid bytes of the data; The write-back control module is used to control the DMA to write back the state of the descriptor or to write back the result data to a specified address. When the write-back controller receives a write-back descriptor request, it will start writing back the state of the descriptor; when the write-back controller receives a write-back data transmission request, it will start writing back the result data.
4. The apparatus for accelerating encryption algorithms according to claim 1, characterized in that, The data queue includes a read data queue, a descriptor control queue, and a descriptor write-back control module. The read data queue stores the current descriptors for each queue. When started and the queue buffer is not empty, it reads descriptors from the queue buffer and sends a request to the read arbitrator to request data reading. The descriptor control queue manages the descriptors in the queue. When started, it sends a request to prefetch descriptors. When the number of descriptors in the queue is less than a preset number, it sends a request to prefetch descriptors. The descriptor write-back control module stores descriptors that need to be written back. When the number of descriptors to be written back is greater than a preset number, it requests a write-back status. When the number of descriptors is consistently lower than the preset number, it forces the controller to write back the status.
5. The apparatus for accelerating encryption algorithms according to claim 1, characterized in that, A read cache module is provided between the transmission channel and the prefetch control module, which is used to cache the data read back; a write cache module is provided between the transmission channel and the algorithm core module, which is used to cache the data that needs to be written back.
6. The apparatus for accelerating encryption algorithms according to claim 5, characterized in that, The algorithm core module includes a symmetric algorithm core, a hash algorithm core, mode control, and algorithm complement control information. The AHB main interface automatically obtains the key required for each encryption based on the channel number of the descriptor and the address configured in the register.
7. The apparatus for accelerating encryption algorithms according to any one of claims 1-6, characterized in that, It also includes an AXI slave interface, an AHB slave interface, and a register control module. The AXI slave interface is configured with general information, and the AHB slave interface is configured with key control information. The register control module is used for register control.
8. A method for accelerating encryption algorithms, characterized in that, The apparatus based on any one of claims 1-7 comprises: Complete the descriptor filling operation according to application requirements, including the selection of algorithm type, mode selection, data source address, result write-back address, address of additional data, data processing length, and required context information; Configure the corresponding control registers according to the actual application. When a descriptor update is detected, update the queue descriptor tail register according to the actual available descriptors. Based on the retrieved descriptor, the data to be processed is obtained by combining it with the corresponding source address; The processed data is cached within the accelerated IP and written back to the corresponding locations sequentially according to the write-back address in the descriptor; After encryption and decryption are completed, the corresponding descriptor state is written back and the relevant interrupt is triggered to notify the top-level transmission is complete.
9. The method for accelerating encryption algorithms according to claim 8, characterized in that, The step of updating the queue descriptor tail register according to the actual available descriptors when a descriptor update is detected includes: If a descriptor update is detected, the system will automatically determine whether to initiate a descriptor prefetch operation based on the difference between the queue descriptor head register and the queue descriptor tail register maintained by the internal hardware. If prefetching is required, the corresponding descriptor will be retrieved from the already configured descriptor address; The register control module in the architecture outputs descriptor control-related information, and the read control module initiates a read descriptor operation to enter the arbitrator. The read descriptor command enters the read control module, which then enters the AXI main interface. After the read command enters the AXI bus, it obtains the corresponding descriptor information and writes it into the read cache. After the read-back descriptor enters the read control module, it is identified as a read descriptor based on the type of the returned read command, and the read-back data is placed into the corresponding queue descriptor cache in the descriptor control module.
10. The method for accelerating encryption algorithms according to claim 8, characterized in that, The processed data is cached within the accelerated IP and written back to the corresponding locations sequentially according to the write-back address in the descriptor, including: The read data is categorized by the read control module to determine whether the read data is a descriptor, context, or data that needs to be processed. The processed data enters the read FIFO and then enters the algorithm core through the prefetch control module. The algorithm core inputs data based on whether complement processing is required, the algorithm mode, and the corresponding algorithm core. The processed data is cached in the write FIFO. After the data accumulates to a certain level, a request will be sent to read the relevant information of the write-back descriptor. Based on the write-back address in the descriptor, the data will be written back to the corresponding location in sequence. After the data write-back is completed, the write-back descriptor status is written back. The write-back command enters the write-back control module, enters the AXI main interface through the write channel, and is sent to the AXI bus to reach the specified address.