Capacitive element and circuit structure including capacitive element

Abstract

The invention relates to a capacitive element (CE) and a circuit structure comprising the CE. The CE includes first, second, and third transistors (dual gate n-type field effect transistors) connected in series. Shared source / drain regions between the second and first transistors and between the first and third transistors are respectively connected to a capacitor. The first transistor is larger than the second and third transistors. The front gate of the first transistor and the back gates of all three transistors receive a first control voltage (VC1). Front gates of the second and third transistors receive a second control voltage (VC2). The VC1 and the VC2 can be switched at the same time so as to switch the three transistors between an on state and an off state at the same time. A high voltage level and a low voltage level of VC1 are at a first positive voltage level and ground. The high voltage level and the low voltage level of the VC2 are at a first positive voltage level and a second positive voltage level.

Description

Technical Field

[0001] This disclosure relates to capacitors, and more particularly to embodiments of capacitive elements (CEs) and embodiments of circuit structures including one or more CEs (e.g., compact digitally adjustable capacitor structures). Background Technology

[0002] The goals of modern integrated circuit design include, but are not limited to, improving performance, reducing size, and reducing power consumption. Typically, design changes aimed at one of these goals may result in undesirable trade-offs with one or more other goals. For example, currently available digitally adjustable capacitors typically consume a relatively large amount of chip area and have: (1) a large tuning range and a low on-state quality factor (Q), thus consuming a relatively high amount of power; or (2) a small tuning range and a high on-state Q, thus consuming a relatively low amount of power. In other words, there is a substantial trade-off between the size of the tuning range and the on-state Q. Summary of the Invention

[0003] This document discloses embodiments of capacitive elements (CEs). It also discloses embodiments of circuit structures including one or more CEs (e.g., compact digitally adjustable capacitors).

[0004] More specifically, this document discloses embodiments of a CE structure. The CE structure may include three transistors. These three transistors may include: a first transistor having a first front gate and a first back gate; a second transistor having a second front gate and a second back gate; and a third transistor having a third front gate and a third back gate. The first transistor may be connected in series between the second transistor and the third transistor. The first front gate, the first back gate, the second back gate, and the third back gate may be connected to receive a first control voltage, while the second front gate and the third front gate may be connected to receive a second control voltage. The CE may also include a pair of capacitors. The capacitors may include: a first capacitor connected to a first shared source / drain region between the first transistor and the second transistor; and a second capacitor connected to a second shared source / drain region between the first transistor and the third transistor.

[0005] This document also discloses embodiments of a circuit structure (e.g., a compact digitally adjustable capacitor) including one or more CE structures. Specifically, the circuit structure may include: a first voltage line; a second voltage line; and at least one CE connected between the first voltage line and the second voltage line. The CE may include three transistors. These three transistors may include: a first transistor having a first front gate and a first back gate; a second transistor having a second front gate and a second back gate; and a third transistor having a third front gate and a third back gate. The first transistor may be connected in series between the second transistor and the third transistor. The second transistor may be connected between a ground rail and the first transistor, and the third transistor may be connected between the first transistor and the ground rail. The first front gate, the first back gate, the second back gate, and the third back gate may be connected to receive a first control voltage, while the second front gate and the third front gate may be connected to receive a second control voltage. The CE may also include a pair of capacitors. The capacitor may include: a first capacitor connected between the first voltage line and a first shared source / drain region, the first shared source / drain region being located between the first transistor and the second transistor; and a second capacitor connected between the second voltage line and a second shared source / drain region, the second shared source / drain region being located between the first transistor and the third transistor.

[0006] In some embodiments, the disclosed circuit structure (e.g., the disclosed compact digitally adjustable capacitor) may include a first voltage line; a second voltage line; and a plurality of capacitors (CEs) connected in parallel between the first voltage line and the second voltage line. Each CE may include three transistors. These three transistors may include: a first transistor having a first front gate and a first back gate; a second transistor having a second front gate and a second back gate; and a third transistor having a third front gate and a third back gate. The first transistor may be connected in series between the second transistor and the third transistor. The second transistor may be connected between a ground rail and the first transistor, and the third transistor may be connected between the first transistor and the ground rail. The first front gate, the first back gate, the second back gate, and the third back gate may be connected to receive a first control voltage, while the second front gate and the third front gate may be connected to receive a second control voltage. The CE may also include a pair of capacitors. The capacitor may include: a first capacitor connected between the first voltage line and a first shared source / drain region, the first shared source / drain region being located between the first transistor and the second transistor; and a second capacitor connected between the second voltage line and a second shared source / drain region, the second shared source / drain region being located between the first transistor and the third transistor.

[0007] It should be noted that all aspects, examples, and features of the disclosed embodiments mentioned in the foregoing summary can be combined in any technically possible manner. That is, two or more aspects of any disclosed embodiment, including those described in the summary section, can be combined to form embodiments not specifically described herein. Details of one or more embodiments are set forth in the drawings and the following description. Other features, objects, and advantages will be apparent from the specification, drawings, and claims. Attached Figure Description

[0008] This disclosure will be better understood through the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, wherein:

[0009] Figure 1 This is a schematic diagram illustrating a disclosed embodiment of a capacitive element (CE) and also illustrating a disclosed embodiment of a circuit structure including multiple CEs (e.g., a digitally adjustable capacitor).

[0010] Figure 2A and 2B These are shown in more detail. Figure 1 A cross-sectional view and top view of an embodiment of the CE;

[0011] Figure 3 To show in more detail Figure 1 A cross-sectional view of another embodiment of the CE;

[0012] Figure 4 This is a table showing examples of high and low voltage levels that can be used for VC1 and VC2;

[0013] Figure 5 This is a table illustrating examples of various performance values ​​achievable through the disclosed CE embodiments, including on-state capacitance (Con), off-state capacitance (Coff), tuning ratio, on-state Q (Qon), and off-state Q (Qoff).

[0014] Figure 6.1 This shows that it can be incorporated into Figure 1 A schematic diagram of an example of the first voltage source in a circuit structure;

[0015] Figure 6.2 This shows that it can be incorporated into Figure 1 A schematic diagram illustrating an example of a second voltage source in a circuit structure; and

[0016] Figure 7 This is a schematic diagram showing a conventional CE. Detailed Implementation

[0017] As mentioned above, the goals of modern integrated circuit design include, but are not limited to, improving performance, reducing size, and reducing power consumption. Typically, design changes aimed at one of these goals may result in undesirable trade-offs with one or more other goals. For example, currently available digitally adjustable capacitors typically consume a relatively large amount of chip area and have: (1) a large tuning range and a low on-state quality factor (Q), thus consuming a relatively high amount of power; or (2) a small tuning range and a high on-state Q, thus consuming a relatively low amount of power. That is, there is a substantial trade-off between the size of the tuning range and the on-state Q. Those skilled in the art will recognize that Q represents the efficiency of a given capacitor in terms of energy loss. More specifically, Q can be defined as: Where X represents the reactance of the capacitor, R represents the series resistance of the capacitor, C represents the capacitance of the capacitor, and ω0 represents the frequency of the measurement (in radians).

[0018] Figure 7This is a schematic diagram illustrating an example of a capacitive element 1 that can be used with a digitally adjustable capacitor. The capacitive element 1 includes a first capacitor 61, a first N-type field-effect transistor (NFET) 10, and a second capacitor 62 connected in series between voltage lines VP and VM. It also includes second and third NFETs 20 and 30, respectively connected in series between the source / drain regions of the first NFET 10 and ground. The gate and body regions of the three NFETs 10, 20, and 30 are connected to the same control voltage (VC). For the highest on-state Q, the first NFET 10 has a relatively short channel length to achieve a low resistance (Ron) when VC goes high, thus turning the NFET on. However, the second NFET 20 and the third NFET 30 must have relatively long channel lengths (thus increasing chip area) to provide a high turn-off resistance (Roff) when VC goes low. This Roff can be in the gigahertz range, depending on the process corner and temperature. In the off-state, nodes A and B will float. However, individual NFETs 20 and 30 introduce additional parasitic capacitance, which reduces the tuning range. Ideally, the tuning range should be increased without reducing the Q values ​​in either the on or off states.

[0019] In view of the above, embodiments of capacitive elements (CEs) are disclosed herein. An CE may include three transistors (i.e., a first transistor, a second transistor, and a third transistor) having a shared active device region and a pair of capacitors (i.e., a first capacitor and a second capacitor). A second transistor may be connected between a ground rail and the first transistor, and a third transistor may be connected between the first transistor and the ground rail. A first shared source / drain region between the second transistor and the first transistor may be connected to the first capacitor, while a second shared source / drain region between the first transistor and the third transistor may be connected to the second capacitor. The three transistors may be N-type field-effect transistors (NFETs), wherein the first transistor is larger than the second and third transistors (e.g., the first transistor may have more gate fingers, and therefore, a larger total channel width than the second or third transistor). The three transistors may be dual-gate transistors (i.e., each may have a front gate and a back gate). For example, the three transistors may be formed using advanced semiconductor-on-insulator (SOS) processing techniques, wherein the device region is located within a continuous portion of a semiconductor layer (referred to herein as the active device region), and the back gate shares a well region in a semiconductor substrate beneath the insulating layer. In any case, the front gate of the first transistor and the back gates of all three transistors can receive a first control voltage (VC1), while the front gates of the second and third transistors can receive a second control voltage (VC2). VC1 and VC2 can be switched simultaneously between high and low voltage levels to simultaneously switch the three transistors between an on and off state. The high and low voltage levels of VC1 can be at a first positive voltage level (above the threshold voltage of the three transistors) and at ground (e.g., 0.0 volts (V)), while the high and low voltage levels of VC2 can be at a first positive voltage level and a second positive voltage level, the second positive voltage level being lower than the first positive voltage level but higher than 0.0V (e.g., at or near the threshold voltage of the three transistors). Embodiments of compact digitally adjustable capacitors including such an array of CEs are also disclosed herein.

[0020] More specifically, Figure 1 This indicates the CE (for example, see CE 101). 0-n The disclosed embodiments are shown, and multiple CE 1010-101 are also illustrated. n A schematic diagram of a disclosed embodiment of a circuit structure 100 (e.g., a compact digitally adjustable capacitor (TC), hereinafter referred to as TC 100).

[0021] As shown in the figure, TC 100 may include parallel voltage lines, specifically a first voltage line 102 and a second voltage line 103 (also referred to herein as a positive voltage (VP) line and a negative voltage (VM) line or a differential voltage line). TC 100 may also include one or more CEs (e.g., see CE 101) connected in parallel between the first and second voltage lines 102-103. 0-n Each CE101 0-n It can be programmed independently (i.e., numerically controlled), as discussed in more detail below, to be in an off state with a relatively low off-state capacitor (Coff) or an on state with a relatively high on-state capacitor (Con). This is achieved by selectively controlling the CE101... 0-n One or more of them are programmed to be in the ON state, allowing selective adjustment (i.e., tuning) of the total capacitance (Ctotal) provided by TC 100. Those skilled in the art will recognize that Ctotal will be equal to CE 101. 0-n The sum of the capacitances (in the on or off state).

[0022] Each CE 101 0-n It can include three transistors, specifically three N-type field-effect transistors (NFETs). That is, each CE 101 0-nThe device may include a first transistor 110 (also referred to herein as a first NFET 110), a second transistor 120 (also referred to herein as a second NFET 110), and a third transistor 130 (also referred to herein as a third NFET 130). These transistors may be connected in series and may share an active device region defined in the semiconductor layer. Specifically, the second NFET 120 may be connected in series between a ground rail 199 (e.g., at 0.0V) and the first NFET 110, and the third NFET 130 may be connected in series between the first NFET 100 and the ground rail 199. All three transistors may be dual-gate NFETs. That is, each transistor may also include a front gate and a back gate opposite to the front gate, in addition to other components discussed in more detail below. Furthermore, the first NFET 110 may be larger than the second NFET 120 and the third NFET 130, and specifically, may have a larger total channel width than the second NFET 120 and the third NFET 130. For example, all three transistors can be formed from a generally rectangular active device region patterned from a semiconductor layer. The front gate of the first NFET 110 can have multiple front gate fingers traverse the active device region, while the front gates of the second NFET 120 and the third NFET 130 can each have fewer front gate fingers than the first NFET 100. For example, the second NFET 120 and the third NFET 130 can each have a single front gate finger or fewer front gate fingers than the first NFET 110. All front gate fingers of all three transistors can have equal dimensions. However, those skilled in the art will recognize that because the number of gate fingers in the first NFET 110 is greater than the number of gate fingers in the second NFET 120 and the third NFET 130, the first NFET 100 has a larger total channel width than the second NFET 120 and the third NFET 130.

[0023] More specifically, Figure 2A and 2B The figures show a cross-sectional view and a top view layout of an example of CE 101 that can be incorporated into TC 100. In this example, a first NFET 110, a second NFET 120, and a third NFET 130 are formed using an advanced semiconductor-on-insulator (SOI) technology processing platform. That is, the first NFET 110, the second NFET 120, and the third NFET 130 are semiconductor-on-insulator (SOI) NFETs (e.g., silicon-on-insulator (SOI) NFETs), such as fully depleted SOI NFETs (e.g., fully depleted SOI (FDSOI) NFETs) or partially depleted SOI NFETs (e.g., partially depleted SOI (PDSOI) NFETs).

[0024] like Figure 2A and 2B As shown in the diagram, CE 101 (and all other CEs of TC 100) can be formed on semiconductor substrate 201. Semiconductor substrate 201 can be, for example, a single-crystal silicon substrate, or alternatively, a single-crystal substrate of any other suitable semiconductor material (e.g., silicon-germanium, etc.). Insulator layer 203 can be located on the top surface of semiconductor substrate 201. Insulator layer 203 can be, for example, a silicon dioxide layer or any other suitable insulating material layer. Semiconductor layer 204 can be located on the top surface of insulator layer 203. Semiconductor layer 204 can be, for example, a single-crystal silicon layer or a layer of any other suitable single-crystal semiconductor material (e.g., silicon-germanium, etc.).

[0025] Trench isolation region 205 (e.g., shallow trench isolation (STI) structure) may define a continuous portion of semiconductor layer 204 (referred herein to as active device region 207) that includes device regions for the three transistors 110-130 for CE 101. For example, such an STI structure may include one or more trenches that are patterned (e.g., photolithographically etched) to extend vertically from the top surface of semiconductor layer 204 to (and optionally through) insulating layer 203, thereby defining (i.e., laterally surrounding) the shape of active device region 207. In some embodiments, the defined shape of active device region 207 may be substantially rectangular (when viewed from top to bottom, as shown in the figure below). Figure 2B (As shown). The trench can be filled with one or more layers of insulating material (e.g., silicon dioxide, silicon nitride, silicon oxynitride, etc.) to form an STI structure.

[0026] The first NFET 110 may be laterally located between the second NFET 120 and the third NFET 130. The first NFET 110 may include a first front gate having a plurality of first front gate fingers 115. The first front gate fingers 115 may be parallel, physically spaced apart from each other, and may span the active device region 207 such that they are adjacent (e.g., above and immediately adjacent to) a corresponding first channel region 113 of the first NFET 110 within the central portion of the active device region 207. The first front gate fingers 115 may be electrically connected, as discussed in more detail below. In any case, each first channel region 113 within the active device region 207 may be laterally located between the first source / drain regions 112.

[0027] The second NFET 120 may include a second front gate having one or more second front gate fingers 125. The second front gate fingers 125 may span the active device region 207, and more specifically, may be adjacent (e.g., above and immediately adjacent to) a corresponding second channel region 123 of the second NFET 120 within one end of the active device region 207. It should be understood that if the second NFET 120 has more than one second front gate finger 125, these second front gate fingers may be connected in parallel with each other and electrically connected. Each second channel region 123 may be laterally located between the second source / drain regions 122. As shown, a portion of the semiconductor layer 204 extending between the second front gate fingers 125 and the first front gate fingers 115 may be shared by the second source / drain regions 122 and the first source / drain regions 112, and is referred to herein as the first shared source / drain regions 122 / 112.

[0028] The third NFET 130 may include a third front gate having one or more third front gate fingers 135. The third front gate fingers 135 may span the active device region 207, and more specifically, may be adjacent (e.g., above and immediately adjacent) to the corresponding third channel region 133 of the third NFET 130 at opposite ends of the active device region 207. Each third channel region 133 may be laterally located between the third source / drain regions 132. It should be understood that if the third NFET 130 has more than one third front gate finger 135, these third front gate fingers may be connected in parallel with each other and electrically connected. As shown, a portion of the semiconductor layer 204 extending between the first front gate finger 115 and the third front gate finger 135 may be shared by the first source / drain region 112 and the third source / drain region 132, and is referred to herein as the second shared source / drain region 112 / 132.

[0029] For illustrative purposes, both the second NFET 120 and the third NFET 130 are shown as having only a single front gate finger. It should be understood that these two NFETs 120, 130 may alternatively have multiple front gate fingers, provided that the number of the second and third front gate fingers is the same (and therefore CE is symmetrical), and that this number is less than the total number of the first front gate fingers 115. Alternatively, dummy gate fingers 145 may be located at opposite ends of the structure and are not electrically connected to the gate fingers of NFETs 110, 120, or 130.

[0030] In any case, the front gate fingers (including the first front gate finger 115, the second front gate finger 125, the third front gate finger 135, and any dummy front gate finger 145) may have the same multilayer configuration. For example, each front gate finger may include a gate dielectric layer (including one or more layers of gate dielectric material) adjacent to the channel region within the semiconductor layer 204 and a gate conductor layer (including one or more layers of gate conductor material) on the gate dielectric layer. Each front gate finger may be any of a gate-first polysilicon gate structure, a gate-first high-k metal gate (HKMG) structure, a gate-back HKMG structure (also known as a replacement metal gate (RMG) structure), or any other suitable type of front gate structure. Although not shown in the figures to avoid confusion, each front gate finger may also include a gate sidewall spacer laterally positioned adjacent to its sidewall to electrically isolate it from adjacent source / drain regions. Such gate and gate sidewall spacer structures are well known in the art, and therefore, details thereof are omitted in the specification in order to allow the reader to focus on the prominent aspects of the disclosed embodiments.

[0031] As described above, for each NFET having a plurality of front gate fingers (e.g., for at least the first NFET 110), the front gate fingers can be electrically connected. For example, as Figure 2B As shown, the electrical connections between all the first front gate fingers 115 can be achieved through gate patterning. Specifically, the connecting gate structure 119 (having the same multilayer configuration as each first front gate finger 115) can be patterned and etched simultaneously with the front gate fingers, so that it lands on the trench isolation region 205 and is perpendicular to and adjacent to each first front gate finger 115. Alternatively, any other suitable technique for electrically connecting the first front gate fingers 115 can be employed (e.g., a combination of mid-stage (MOL) contact and back-stage (BEOL) wiring; etc.).

[0032] Optionally, all front gate fingers (including the first front gate finger 115, the second front gate finger 125, the third front gate finger 135, and any dummy front gate finger 145) may be substantially parallel and may extend across the entire width of the active device region 207 (as defined by the trench isolation region 205). They may also be spaced by substantially the same distance (i.e., the front gate fingers may have substantially uniform gate pitch). That is, the spacing between the front gate fingers may be equal (except for minor process variations). Furthermore, they may have substantially the same dimensions (including gate finger length, height, etc., measured across the channel region from one source / drain region to another). In this configuration, each of the multiple first channel regions 113, each of the one or more second channel regions 123, and each of the one or more third channel regions 133 will have substantially equal channel lengths (except for minor process variations), as measured between adjacent first source / drain regions 112, adjacent second source / drain regions 122, and adjacent third source / drain regions 132, respectively. As described above, since all gate fingers have the same size, and since the number of gate fingers in the first NFET 110 is greater than the number of gate fingers in the second NFET 120 and the third NFET 130, the first NFET 100 has a larger total channel width than the second NFET 120 and the third NFET 130.

[0033] It should be noted that within the first NFET 110, the second NFET 120, and the third NFET 130, each channel region can be an intrinsic channel region (i.e., an undoped channel region) or a P-type channel region (i.e., a P-channel region) with a relatively low conductivity level. Each source / drain region can be an N-type source / drain region (i.e., an N+ source / drain region) with a relatively high conductivity level. The N-type source / drain region can include the lower portion of the semiconductor layer 204, specifically an N-doped portion. Alternatively, although not shown in the figures to avoid confusion, the N-type source / drain region may also include an upper portion or a raised portion. The upper portion can be an N-doped single-crystal semiconductor layer epitaxially grown on the top surface of the semiconductor layer 204, located above and immediately adjacent to the lower portion.

[0034] The first NFET 110, the second NFET 120, and the third NFET 130 may further include a first back gate 116, a second back gate 126, and a third back gate 136, respectively. Specifically, the semiconductor substrate 201 may include a well region 202 located therein. The well region 202 may be located at the top surface of the semiconductor substrate 201, adjacent to the insulating layer 203, and may also be aligned below the active device regions 207 of the NFETs 110, 120, and 130. For the purposes of this disclosure, a well region refers to a region of semiconductor material that has been doped (e.g., via a dopant implantation process or any other suitable doping process) to have a specific conductivity type.

[0035] Those skilled in the art will recognize that one advantage of advanced semiconductor-on-insulator (SOS) technology processing platforms is that FETs can be formed on an insulating layer over a specific type of well region (e.g., an N-type well region (N-well) or a P-type well region (P-well)) to realize different types of NFETs or PFETs with different threshold voltages (VT). For example, for ultra-low threshold voltage (SLVT) or low threshold voltage (LVT) FETs, an NFET can be formed over an N-well. For conventional threshold voltage (RVT) or high threshold voltage (HVT) FETs, an NFET can be formed over a P-well and a PFET over an N-well. Whether the FET is an SLVT or an LVT FET, or whether they are RVT or HVT FETs, will depend on the design (e.g., device size, etc.) and process specifications (e.g., dopant concentration, etc.). In the CE disclosed herein, the three transistors can be either SLVT or LVT NFETs (i.e., well region 202 can be an N-well), or they can be RVT or HVT NFETs (i.e., well region 202 can be a P-well). Another advantage of advanced semiconductor-on-insulator (SOS) technology platforms is that the corresponding portion of the insulating layer and well region beneath each FET effectively forms the back gate, which can be biased (called back gate bias or back bias) to fine-tune the threshold voltage. Forward back bias (FBB) applies a gate bias voltage to the back gate (specifically, to its well region) to reduce the FET's threshold voltage (VT). Reverse back bias (RBB) applies a gate bias voltage to the back gate (specifically, to its well region) to increase the FET's VT, thereby reducing switching speed and leakage current.

[0036] Because the same well region 202 is located beneath all three transistors, the first back gate 116 of the first NFET 110, the second back gate 126 of the second NFET 120, and the third back gate 136 of the third NFET 130 are formed from different portions of the same insulating layer and well region, and back bias can be performed simultaneously by biasing the well region 202 (discussed in more detail below). For ease of back gate biasing, the structure may also include a body region (also referred to as a hybrid region). This body region may lack the insulating layer 203 and instead include a well contact region 206 (also referred to herein as a well tap) on the top surface of the semiconductor substrate 201, adjacent to the well region 202 and electrically isolated from the active device region via an STI structure. The well contact region 206 may, for example, comprise an epitaxial single-crystal semiconductor layer (e.g., an epitaxial silicon layer or any other suitable semiconductor material) grown on the top surface of the semiconductor substrate 201, adjacent to the well region 202, and may be in-situ doped or subsequently implanted to have the same type of conductivity, but at a higher level than the underlying well region. Alternatively, the well contact region 206 may be a highly doped region within the well region 202 and at the top surface of the well region 202.

[0037] It should be understood that Figure 2A-2B The example dual-gate NFET shown in the CE is just one type of dual-gate NFET that can be incorporated into the TC 100. Alternatively, any other type of dual-gate NFET with a biasable front gate and back gate can be used.

[0038] Each CE 101 may also include a pair of capacitors (Cu). Specifically, each CE 101 may include a first capacitor 161 and a second capacitor 162. The first capacitor 161 may include a pair of capacitor plates separated by a capacitor dielectric. One capacitor plate may be connected to a first shared source / drain region 122 / 112 between the first NFET 110 and the second NFET 120, and the other capacitor plate may be connected to a first voltage line 102. The second capacitor 162 may similarly include a pair of capacitor plates separated by a capacitor dielectric. One capacitor plate may be connected to a second shared source / drain region 112 / 132 between the first NFET 110 and the third NFET 130, and the other capacitor plate may be connected to a second voltage line 103. The first and second capacitors 161-162 may be any suitable type of back-end process (BEOL) capacitor, such as a metal-oxide-metal capacitor (MOMCAP) (e.g., a vertical native capacitor (VNCAP)) or a metal-insulator-metal capacitor (MIMCAP). Such BEOL capacitors are well known in the art; therefore, details have been omitted from the specification and drawings in order to allow the reader to focus on the prominent aspects of the disclosed embodiments. In some embodiments, such as Figure 2A-2B As shown, the first and second capacitors 161-162 can be located within the BEOL metal layer such that they are completely offset from the three transistors below (i.e., the first NFET 110, the second NFET 120, and the third NFET 130) to minimize any parasitic capacitance between them. Alternatively, to reduce the chip area consumed by each CE 101, the first and second capacitors 161-162 can each partially cover one or more of the three transistors. Figure 3 In the example CE 101' shown, the first capacitor 161 may cover the second NFET 120 and optionally partially cover the first NFET 110, while the second capacitor 162 may cover the third NFET 130 and optionally partially cover the first NFET 110.

[0039] It should be noted that since the drain regions of the second NFET 120 and the third NFET 130 are shared with the first NFET 110, the parasitic capacitance at nodes A (i.e., the connection with the first capacitor 161) and B (i.e., the connection with the second capacitor 162) is reduced.

[0040] Alternatively, the above and [other methods] can be generated by modifying the cell of a single multi-finger NFET. Figure 2A-2B The design layout of NFETs 110, 120, and 130 is shown. For example, the basic unit of a multi-finger NFET may include a total of X gate fingers, where X is fixed or customizable. A certain number Y (where Y ≤ X-2) of the X gate fingers spanning the central portion of the active device region can be assigned to the first NFET 110, and any remaining gate fingers spanning the ends of the active device region 207 can be assigned to the second NFET 120 and the third NFET 130. Again, in combination... Figure 2A (or Figure 3 )refer to Figure 1 The first front gate (i.e., the first front gate finger 115) and the first back gate 116, the second back gate 126, and the third back gate 136 (e.g., via the well contact region 206) can be connected to a first control voltage node to receive a first control voltage (VC1). The second front gate (i.e., the second front gate finger 125) and the third front gate (i.e., the third front gate finger 135) can be connected to a second control node to receive a second control voltage (VC2).

[0041] VC1 and VC2 can switch between high and low voltage levels simultaneously to switch three transistors (i.e., the first NFET 110, the second NFET 120, and the third NFET 130) between the on and off states at the same time.

[0042] Figure 4 This table illustrates examples of high and low voltage levels that can be used for VC1 and VC2 when the transistors have a threshold voltage, for example, equal to or lower than 0.9V. For example, the high voltage level of VC1 can be at a first positive voltage level (VH) (e.g., 0.9V), which is higher than the threshold voltage (VT) of the three transistors. The low voltage level of VC1 can be at VL1 (e.g., ground or more specifically, at 0.0V). The high voltage level of VC2 can similarly be at VH. However, the low voltage level of VC2 can be at a second positive voltage level (VL2), instead of ground, VL2 is lower than VH but higher than VL1 (i.e., higher than 0.0V). For example, VL2 can be close to or equal to the VT of the three transistors. In some embodiments, VL2 can be at a sub-VT level, or more specifically, at a voltage level slightly lower than but close to VT. When both VC1 and VC2 are high, the on-resistance (Ron) is low, CE is switched to the on state, and the first and second capacitors 161-162 are shorted to ground. In this configuration, the differential capacitor between the first and second voltage lines 102-103 will be equal to 0.5*Cu. It should be noted that the Ron exhibited by the disclosed CE 101 may be lower than that exhibited by a conventional CE; therefore, Qon can be improved (e.g., slightly higher). However, when both VC1 and VC2 go low, the first NFET 110 will be completely turned off because VC1 is grounded, but the second NFET 120 and the third NFET 130 will be biased using VL2 (e.g., in the sub-VT region) to provide a high turn-off resistance (Roff) impedance when the CE is off.

[0043] Figure 5 This is a table showing examples of various performance values, including on-state capacitance (Con), off-state capacitance (Coff), tuning ratio, on-state Q(Qon), and off-state Q(Qoff). These performance values ​​can be represented using currently available CE, Figure 2A-2B CE 101 and Figure 3 This is achieved using CE 101'. For example, the value of Con can be close to the capacitance of capacitors 161 and 162. It should be noted that CE 101 and 101' are relatively compact compared to currently available CEs, exhibiting similar or negligible smaller Con values, lower Coff values, higher tuning ratios (i.e., Con / Coff), and higher on-state Q (Qon). As shown, although Qoff may be lower, those skilled in the art will recognize that a lower value of Qoff may not be significant as long as Qoff is significantly greater than Qon (e.g., two or more times Qon).

[0044] Refer again Figure 1TC 100 may also include additional circuitry to enable support for each CE 101. 0-n Selective programming allows it to be in an on or off state, as described above. Specifically, this additional circuitry may include an input node for receiving (e.g., from the controller) a digital-to-analog converter (DAC) code with n+1 bits (i.e., DAC_Code). <n:0>Each bit within the DAC code can correspond to CE 101 in TC 100. 0-n This is one of the different ones. The additional circuitry may also include components configured to invert the DAC_Code. <n:0>The inverter. This additional circuit may also include an inverter for each CE 101. 0-n Control voltage circuit 190 0-n Each CE control voltage circuit may include a first voltage source 191 for providing VC1 to the CE and a second voltage source 192 for providing VC2 to the CE.

[0045] Figure 6.1 This is a schematic diagram illustrating an example of a first voltage source 191. The first voltage source 191 can be connected to receive a switching control signal (DO) and an inverting switching control signal (DOb). The first voltage source 191 may also include a first pair of digitally controlled switches 611-612 that, in response to DO and DOb, selectively connect a first control voltage node 619 to a positive power supply voltage rail 698 at VH or to a ground rail 199 (e.g., at VL1, or more specifically, at 0.0V). In some embodiments, the first pair of digitally controlled switches may be NFETs, wherein DO and DOb are respectively applied to the gates of the NFETs. Thus, when DO is high and DOb is low, the first control voltage node receives VH; and when DO is low and DOb is high, the first control voltage node is pulled to ground. Alternatively, any other suitable type of digitally controlled switch may be used.

[0046] Figure 6.2 This is a schematic diagram illustrating an example of a second voltage source 192. The second voltage source 192 may also be connected to receive a switching control signal (DO) and an inverting switching control signal (Dob). The second voltage source 192 may include a reference current source 630 and an additional transistor 620 connected in series between the reference current source 630 and the ground rail 199. The additional transistor 620 may be an NFET (hereinafter referred to as additional NFET 620). The additional NFET 620 may be a dual-gate NFET and may be relatively large compared to the first NFET 110, the second NFET 120, and the third NFET 130. For example, the additional NFET 620 may be at least three (3) times or greater (e.g., 3-4 times, 5 times, up to 10 times) of each of the NFETs 110, 120, and 130 to ensure that Qoff meets the required specifications. In any case, the additional NFET 620 may include a channel region 623 located between source and drain regions 621-622, and a front gate and a back gate 625-626 adjacent to the opposing surfaces of the channel region 623. The back gate 626 may be connected to the source region 621, and the front gate 625 may be connected to the drain region 622. The second voltage source 192 may further include a second control voltage node 629 and a second pair of digitally controlled switches 641-642, which, in response to signals DO and DOb, selectively connect the second control voltage node 629 to a positive power supply voltage rail 698 at VH or to the drain region 622 of the additional NFET 620 to receive VL2. In some embodiments, the second pair of digitally controlled switches may be NFETs, wherein DO and DOb are respectively applied to the gates of the NFETs. Thus, when DO is high and DOb is low, the second control voltage node receives VH; and when DO is low and DOb is high, the second control voltage node receives VL2. Alternatively, any other suitable type of CNC switch can be used.

[0047] It should be understood that in the above methods and structures, semiconductor materials refer to materials whose conductivity can be altered by doping with impurities. Exemplary semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon carbide germanium, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements such as aluminum (Al), gallium (Ga), or indium (In) with group V elements such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). Pure semiconductor materials, more specifically, semiconductor materials that are not doped with impurities to increase conductivity (i.e., undoped semiconductor materials) are referred to in the art as intrinsic semiconductors. Semiconductor materials that are doped with impurities to increase conductivity (i.e., doped semiconductor materials) are referred to in the art as extrinsic semiconductors and will be more conductive than intrinsic semiconductors made from the same substrate. That is, extrinsic silicon is more conductive than intrinsic silicon; extrinsic silicon germanium is more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different types of conductivity (e.g., P-type and N-type conductivity) can be achieved using different impurities (i.e., different dopants), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with group III dopants such as boron (B) or indium (In) to achieve P-type conductivity, while silicon-based semiconductor materials are typically doped with group V dopants such as arsenic (As), phosphorus (P), or antimony (Sb) to achieve N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different levels of conductivity depend on the relative concentration levels of one or more dopants in a given semiconductor region.

[0048] It should be understood that the terminology used herein is for describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, as used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, as used herein, when oriented and shown in figures, terms such as "right," "left," "vertical," "horizontal," "top," "bottom," "upper," "lower," "below," "under," "subordinate," "above," "overlapping," "parallel," "vertical," etc., are intended to describe relative positions (unless otherwise stated), and terms such as "touching," "directly in contact," "adjacent," "directly adjacent," "closely adjacent," etc., are intended to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term "lateral" is used herein to describe the relative position of elements, and more specifically, when elements are oriented and shown in figures, to indicate that one element is located to the side of another element, rather than above or below it. For example, an element laterally adjacent to another element will be beside the other element, an element laterally adjacent to another element will be directly beside the other element, and an element laterally surrounding another element will be adjacent to and bound to the outer wall of the other element. All means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent for performing functions in combination with other elements of the specific claims.

[0049] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with either surface-mount or buried interconnects, or both). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes the integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0050] The descriptions of various disclosed embodiments are given for illustrative purposes and are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications of techniques found in the market, or improvements to techniques, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: Three transistors, which include: A first transistor having a first front gate and a first back gate; The second transistor has a second front gate and a second back gate; and The third transistor has a third front gate and a third back gate. The first transistor is connected in series between the second transistor and the third transistor. The first front gate, the first back gate, the second back gate, and the third back gate are connected to receive a first control voltage. The second front gate and the third front gate are connected to receive a second control voltage; A first capacitor is connected to a first shared source / drain region between the first transistor and the second transistor; and A second capacitor is connected to a second shared source / drain region between the first transistor and the third transistor.

2. The structure according to claim 1, wherein, The second transistor is connected between the ground rail and the first transistor, and the third transistor is connected between the first transistor and the ground rail.

3. The structure according to claim 1, wherein, The first transistor has a larger total channel width than the second transistor and a larger total channel width than the third transistor.

4. The structure according to claim 3, wherein, The first front gate has a plurality of first gate fingers, the second front gate has a single second gate finger, and the third front gate has a single third gate finger, wherein the plurality of first gate fingers, the single second gate finger, and the single third gate finger have equal dimensions.

5. The structure according to claim 1, wherein, The first capacitor includes a first capacitor plate connected to the first shared source / drain region and the first voltage line, respectively, and the second capacitor includes a second capacitor plate connected to the second shared source / drain region and the second voltage line, respectively.

6. The structure according to claim 1, in, The three transistors are N-type field-effect transistors. The first control voltage and the second control voltage can switch between high and low voltage levels simultaneously to switch the three transistors between on and off states simultaneously. Wherein, the high voltage level and the low voltage level of the first control voltage are respectively at a first positive voltage level and 0.0V. Wherein, the first positive voltage level is higher than the threshold voltage of any of the three transistors and is at 0.0 volts. Wherein, the high voltage level and the low voltage level of the second control voltage are respectively at the first positive voltage level and the second positive voltage level, and Wherein, the second positive voltage level is lower than the first positive voltage level but higher than 0.0V.

7. The structure according to claim 6, further comprising: A first control voltage node is connected to receive the first control voltage from a first voltage source; as well as A second control voltage node is connected to receive the second control voltage from a second voltage source, wherein the first voltage source includes a first pair of digitally controlled switches that selectively connect the first control voltage node to one of a positive power supply voltage rail and a ground rail, the positive power supply voltage rail being at a first positive voltage level higher than the threshold voltage of the three transistors. The second voltage source includes: Reference current source; An additional transistor, connected in series between the reference current source and the ground rail, wherein the additional transistor is at least three times the size of each of the three transistors, and wherein the gate and drain regions of the additional transistor are electrically connected; and A second pair of digitally controlled switches selectively connects the second control voltage node to one of the positive power supply voltage rail at the first positive voltage level and the drain region of the additional transistor at a second positive voltage level, the second positive voltage level being lower than the first positive voltage level and higher than 0.0 volts.

8. The structure according to claim 1, further comprising: Semiconductor substrate; A well region located within the semiconductor substrate; An insulating layer located on the semiconductor substrate; An active device region is located on the insulating layer, wherein the active device region includes device regions for the three transistors, and wherein the first back gate, the second back gate, and the third back gate include corresponding portions of the insulating layer and the well region aligned below the active device region; and A well tap, which is adjacent to the well region and isolated from the active device region, wherein the well tap is connected to receive the first control voltage.

9. The structure according to claim 1, wherein, The first capacitor and the second capacitor are either metal-oxide-metal capacitors or metal-insulator-metal capacitors, and wherein the first capacitor and the second capacitor are completely offset from the three transistors.

10. The structure according to claim 1, wherein, The first capacitor and the second capacitor are either metal-oxide-metal capacitors or metal-insulator-metal capacitors that at least partially cover at least the second transistor and the third transistor.

11. A structure comprising: First voltage line; Second voltage line; as well as A capacitive element, wherein the capacitive element comprises: Three transistors, which include: A first transistor having a first front gate and a first back gate; The second transistor has a second front gate and a second back gate; and The third transistor has a third front gate and a third back gate. In this configuration, the first transistor is connected in series between the second transistor and the third transistor, wherein the second transistor is connected between the ground rail and the first transistor, and the third transistor is connected between the first transistor and the ground rail. The first front gate, the first back gate, the second back gate, and the third back gate are connected to receive a first control voltage, and The second front gate and the third front gate are connected to receive a second control voltage; A first capacitor is connected between the first voltage line and a first shared source / drain region, the first shared source / drain region being located between the first transistor and the second transistor; and A second capacitor is connected between the second voltage line and the second shared source / drain region, which is located between the first transistor and the third transistor.

12. The structure according to claim 11, wherein, The first transistor has a larger total channel width than the second transistor and a larger total channel width than the third transistor.

13. The structure according to claim 12, in, The first front gate has a plurality of first gate fingers, the second front gate has a single second gate finger, and the third front gate has a single third gate finger. The plurality of first gate fingers, the single second gate finger, and the single third gate finger have equal dimensions.

14. The structure according to claim 11, wherein, The first capacitor includes a first capacitor plate connected to the first shared source / drain region and the first voltage line, respectively, and the second capacitor includes a second capacitor plate connected to the second shared source / drain region and the second voltage line, respectively.

15. The structure according to claim 11, in, The three transistors are N-type field-effect transistors, and The first control voltage and the second control voltage can switch between high voltage level and low voltage level simultaneously to switch the three transistors between on state and off state simultaneously.

16. The structure according to claim 15, further comprising: A first control voltage node is connected to receive the first control voltage from a first voltage source; as well as A second control voltage node is connected to receive the second control voltage from a second voltage source, wherein the first voltage source includes a first pair of digitally controlled switches that selectively connect the first control voltage node to one of a positive power supply voltage rail and a ground rail, the positive power supply voltage rail being at a first positive voltage level higher than the threshold voltage of the three transistors. The second voltage source includes: Reference current source; An additional transistor, connected in series between the reference current source and the ground rail, wherein the additional transistor is at least three times larger than any one of the three transistors, and wherein the gate and drain regions of the additional transistor are electrically connected; and A second pair of digitally controlled switches selectively connects the second control voltage node to one of the positive power supply voltage rail at the first positive voltage level and the drain region of the additional transistor at a second positive voltage level, the second positive voltage level being lower than the first positive voltage level and higher than 0.0 volts.

17. The structure according to claim 11, further comprising: Semiconductor substrate; A well region located within the semiconductor substrate; An insulating layer located on the semiconductor substrate; An active device region is located on the insulating layer, wherein the active device region includes device regions for the three transistors, and wherein the first back gate, the second back gate, and the third back gate include corresponding portions of the insulating layer and the well region aligned below the active device region; and A well tap, which is adjacent to the well region and isolated from the active device region, wherein the well tap is connected to receive the first control voltage.

18. The structure according to claim 11, wherein, The first capacitor and the second capacitor are either metal-oxide-metal capacitors or metal-insulator-metal capacitors, and wherein the first capacitor and the second capacitor are completely offset from the three transistors.

19. The structure according to claim 11, wherein, The first capacitor and the second capacitor are either metal-oxide-metal capacitors or metal-insulator-metal capacitors that at least partially cover at least the second transistor and the third transistor.

20. A structure comprising: First voltage line; Second voltage line; as well as Multiple capacitive elements are connected in parallel between the first voltage line and the second voltage line. Each capacitive element includes: Three transistors, which include: A first transistor having a first front gate and a first back gate; The second transistor has a second front gate and a second back gate; and The third transistor has a third front gate and a third back gate. In this configuration, the first transistor is connected in series between the second transistor and the third transistor, wherein the second transistor is connected between the ground rail and the first transistor, and the third transistor is connected between the first transistor and the ground rail. The first front gate, the first back gate, the second back gate, and the third back gate of the capacitive element are connected to receive a first control voltage, and The second front gate and the third front gate of the capacitive element are connected to receive a second control voltage; A first capacitor is connected between the first voltage line and a first shared source / drain region, the first shared source / drain region being located between the first transistor and the second transistor; and A second capacitor is connected between the second voltage line and the second shared source / drain region, which is located between the first transistor and the third transistor.

Images