Pixel, display device including same, and electronic device

Abstract

There is provided a pixel including a display device and an electronic device including the pixel, the pixel including: a first transistor for generating a driving current and including a first electrode, a control electrode connected to a first node, and a second electrode connected to a second node; a second transistor including a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node; a second capacitor including a second electrode and a first electrode connected to the third node; and a light emitting element for emitting light by receiving the driving current.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0112767, filed on August 22, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The disclosure relates to a pixel, a display device including the pixel, and an electronic device. Background Technology

[0003] With the development of information technology, the importance of display devices as the connection medium between users and information is becoming increasingly apparent. In response, the use of display devices (such as liquid crystal displays, organic light-emitting displays, and inorganic light-emitting displays) is increasing. Summary of the Invention

[0004] The disclosed aspect lies in providing a pixel that achieves high resolution.

[0005] Another aspect disclosed is the provision of an electronic device and a display device including pixels.

[0006] To achieve the disclosed aspects, according to the disclosed embodiments, a pixel may include: a first transistor for generating a drive current, and including a first electrode, a control electrode connected to a first node, and a second electrode connected to a second node; a second transistor including a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node; a second capacitor including a second electrode and a first electrode connected to the third node; and a light-emitting element for emitting light by receiving the drive current.

[0007] The pixel may also include a fourth transistor, which includes a control electrode for receiving a reference gate signal, a first electrode connected to a second node, and a second electrode connected to a third node.

[0008] The first transistor can be an N-channel metal-oxide-semiconductor (NMOS) transistor.

[0009] The pixel may also include a seventh transistor, which includes a control electrode for receiving a bias gate signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the light-emitting element.

[0010] The pixel may further include: a fifth transistor, including a control electrode for receiving a first transmission signal, a first electrode for receiving a first electrical voltage, and a second electrode connected to the first transistor; and a sixth transistor, including a control electrode for receiving a second transmission signal, a first electrode connected to the first transistor, and a second electrode connected to the light-emitting element.

[0011] The pixel may also include a seventh transistor, which includes a control electrode for receiving a first emission signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the light-emitting element.

[0012] The seventh transistor may be of a different type than the fifth transistor.

[0013] The pixel may also include a third transistor, which includes a control electrode for receiving a reference gate signal, a first electrode for receiving a reference voltage, and a second electrode connected to the first node.

[0014] The pixel may also include a third transistor, which includes a control electrode for receiving a reference gate signal, a first electrode for receiving a first electrical voltage, and a second electrode connected to the first node.

[0015] The first transistor may also include a back gate electrode connected to the second node.

[0016] The first transistor may also include a back gate electrode connected to the anode electrode of the light-emitting element.

[0017] The pixel may further include: a first electrode layer including a second electrode of a second capacitor; a second electrode layer above the first electrode layer and including a second electrode of the first capacitor and a first electrode of the second capacitor; an additional electrode layer above the second electrode layer and including a first electrode pattern and a second electrode pattern, the first electrode pattern including a back gate electrode of a first transistor and the second electrode pattern including a first electrode of the first capacitor; an active layer above the additional electrode layer and including a channel region of the first transistor; and a third electrode layer above the active layer, including a control electrode of the first transistor and electrically connected to the second electrode pattern.

[0018] The pixel may further include: a first electrode layer including a first electrode of a first capacitor; a second electrode layer above the first electrode layer and including a second electrode of the first capacitor and a first electrode of the second capacitor; an additional electrode layer above the second electrode layer and including a first electrode pattern and a second electrode pattern, the first electrode pattern including a back gate electrode of a first transistor and the second electrode pattern including a second electrode of a second capacitor; an active layer above the additional electrode layer and including a channel region of the first transistor; and a third electrode layer above the active layer, including a control electrode of the first transistor and electrically connected to the first electrode layer.

[0019] To achieve the disclosed aspects, according to the disclosed embodiments, a pixel may include: a first transistor including a first electrode, a control electrode connected to a first node, and a second electrode connected to a second node; a fourth transistor including a control electrode for receiving a reference gate signal, a first electrode connected to a second node, and a second electrode connected to a third node; a first capacitor including a first electrode connected to a first node and a second electrode connected to a third node; a second capacitor including a second electrode and a first electrode connected to a third node; and a light-emitting element for emitting light by receiving a drive current.

[0020] To achieve the disclosed aspects, according to the disclosed embodiments, the display device may include: a display panel including pixels; and a display panel driver configured to drive the display panel, wherein the pixels include: a first transistor for generating a drive current and including a first electrode, a control electrode connected to a first node, and a second electrode connected to a second node; a second transistor including a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node; a second capacitor including a second electrode and a first electrode connected to the third node; and a light-emitting element for emitting light by receiving the drive current.

[0021] The pixel may also include a fourth transistor, which includes a control electrode for receiving a reference gate signal, a first electrode connected to a second node, and a second electrode connected to a third node.

[0022] The first transistor may include an N-channel metal-oxide-semiconductor (NMOS) transistor.

[0023] The pixel may also include a seventh transistor, which includes a control electrode for receiving a bias gate signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the light-emitting element.

[0024] The pixel may further include: a fifth transistor, including a control electrode for receiving a first transmission signal, a first electrode for receiving a first electrical voltage, and a second electrode connected to the first transistor; a sixth transistor, including a control electrode for receiving a second transmission signal, a first electrode connected to the first transistor, and a second electrode connected to the light-emitting element; and a seventh transistor, including a control electrode for receiving the first transmission signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the light-emitting element.

[0025] The pixel may further include: a fifth transistor, including a control electrode for receiving a first transmitted signal, a first electrode for receiving a first electrical voltage, and a second electrode connected to the first transistor; a sixth transistor, including a control electrode for receiving a second transmitted signal, a first electrode connected to the first transistor, and a second electrode connected to the light-emitting element, wherein the display panel driver is configured to adjust the cutoff duty cycle of at least one of the first transmitted signal and the second transmitted signal according to the transmission cutoff ratio.

[0026] The display panel driver can be configured to adjust the cutoff duty cycle of the second transmit signal based on the transmit cutoff ratio.

[0027] The pixel may also include a third transistor, which includes a control electrode for receiving a reference gate signal, a first electrode for receiving a reference voltage, and a second electrode connected to the first node.

[0028] The pixel may also include a third transistor, which includes a control electrode for receiving a reference gate signal, a first electrode for receiving a first electrical voltage, and a second electrode connected to the first node.

[0029] The first transistor may also include a back gate electrode connected to the second node.

[0030] The first transistor may also include a back gate electrode connected to the anode electrode of the light-emitting element.

[0031] To achieve the disclosed aspects, according to the disclosed embodiments, the electronic device may include: a processor for providing input image data; and a display device for displaying images based on the input image data, and including: a display panel including pixels; and a display panel driver configured to drive the display panel, wherein the pixels include: a first transistor for generating a drive current, and including a first electrode, a control electrode connected to a first node, and a second electrode connected to a second node; a second transistor including a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node; a second capacitor including a second electrode and a first electrode connected to the third node; and a light-emitting element for emitting light by receiving the drive current.

[0032] According to the disclosed embodiments, high resolution can be achieved by connecting two capacitors in series.

[0033] The display device and electronic device according to the disclosed embodiments can reduce the amount of wiring used by providing a first transmission signal to the control electrode of the seventh transistor. Therefore, the display device can achieve high resolution.

[0034] Because the first capacitor to which the data voltage is written is not directly connected to the second electrode of the first transistor, the pixel according to the disclosed embodiment can reduce or minimize the influence of the drive current on the voltage written to the first capacitor. Therefore, the error in threshold voltage compensation can be reduced.

[0035] However, the effects of openness are not limited to those described above, and can be extended in different ways without departing from the spirit and scope of openness. Attached Figure Description

[0036] The above and other aspects of the disclosure will become more apparent from the further detailed description of the disclosed embodiments with reference to the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a display device according to a disclosed embodiment; Figure 2 It is shown Figure 1 A circuit diagram of an example of pixels in a display device; Figure 3 It is shown Figure 2 A cross-sectional view of an example of a first transistor, a first capacitor, and a second capacitor; Figure 4 It is shown Figure 1 A conceptual diagram of the driving operation of a display device; Figures 5 to 9 It is shown that Figure 1A diagram illustrating an example of a display device performing a display scanning operation; Figure 10 It is shown that Figure 1 A timing diagram of an example of a display device performing a self-scanning operation; Figure 11 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment; Figure 12 It is shown that Figure 11 A timing diagram illustrating an example of a display device performing a display scanning operation; Figure 13 It is shown that Figure 11 A timing diagram of an example of a display device performing a self-scanning operation; Figure 14 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment; Figure 15 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment; Figure 16 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment; Figure 17 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment; Figure 18 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment; Figure 19 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment; and Figure 20 This is a block diagram illustrating an electronic device according to a disclosed embodiment. Detailed Implementation

[0037] Features of some embodiments of this disclosure and methods of implementation thereof can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and the described embodiments will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential for a person of ordinary skill in the art to fully understand aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated description may be omitted.

[0038] The described embodiments may have various modifications and may be implemented in different ways, and should not be construed as being limited to the embodiments shown herein. In describing one or more embodiments, the use of “can,” “may,” or “may not” corresponds to one or more embodiments of this disclosure.

[0039] Those skilled in the art will understand that, in view of the overall nature of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined or combined with each other in part or in whole, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently or in combination with each other in any suitable manner, unless otherwise shown or implied.

[0040] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto, as the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of description. Additionally, the use of crosshairs and / or shading in the drawings is generally intended to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement regarding the specific material, material properties, dimensions, scale, commonalities between the elements shown, or any other characteristics, properties, or characteristics of the elements.

[0041] Various embodiments are described herein with reference to sectional views that serve as schematic illustrations and / or intermediate structures. Thus, variations in the shape of the illustrations will be anticipated, for example, due to manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the elements, layers, or regions shown, but will include deviations in shape due to, for example, manufacturing processes.

[0042] For example, an injection region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from the injection region to the non-injection region. Similarly, a buried region formed by injection can induce some injection in the region between the buried region and the surface through which the injection occurs.

[0043] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above,” “higher,” “upper side,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element or feature as shown in the accompanying drawings to other elements or features. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are also intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below,” “under,” or “below” other elements or features would then be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this indicates that the first part is arranged on the upper or lower side of the second part based on the direction of gravity, and is not limited to the upper side of it.

[0044] Furthermore, the phrase "in a plan view" means when viewing a portion of an object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting through a portion of an object from the side. The term "overlapping" or variations thereof means that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlapping" can include stacking, facing, or variations thereof, extending over, covering, or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separated," "away from," or "offset," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can mean that the first object may be directly or indirectly opposite the second object. Where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, although still facing each other.

[0045] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operationally, functionally, or communicatively) incorporated into" another component, layer, region, or assembly, that component, layer, region, or assembly may be directly formed on, directly on, directly connected to, or directly incorporated into the other component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into the other component, layer, region, or assembly, such that one or more intermediary components, intermediary layers, intermediary regions, or intermediary assemblies may exist. Furthermore, this can uniformly mean direct or indirect incorporation or connection, as well as integral or non-integral incorporation or connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, that layer, region, or component may be directly electrically connected or directly bonded to said other layer, region, and / or component, or one or more intermediary layers, intermediary regions, or intermediary components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, the connection is not limited to the connections shown in the accompanying drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on" means that one component is directly connected to or directly bonded to another component, or on another component without intermediate components.

[0046] Furthermore, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the formation direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing the relationship between components, such as "between," "directly between," or "adjacent to," can be interpreted in a similar manner. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0047] For the purposes of this disclosure, when expressions such as “at least one of…” or “any one of…” or “one or more of…” follow a list of elements, they modify the entire list of elements without modifying individual elements within the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ), or any variations thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of…”, “multiple (species / beings)…”, “one of…”, and other prepositional phrases, when placed before / after a list of elements, modify the entire list of elements without modifying any individual elements within the list. When “C to D” is stated, unless otherwise specified, it means C or greater and D or less.

[0048] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or superiority and are used only to distinguish one element, component, assembly, region, area, layer, section, or part from another element, component, assembly, region, area, layer, section, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, first assembly, first region, first layer, or first section described below may be referred to as a second element, second assembly, second region, second layer, or second section. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively mean “first category (or first group),” “second category (or second group),” etc.

[0049] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0050] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of this disclosure. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are intended to include the plural forms, and the plural forms are intended to include the singular forms. It will also be understood that when the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% for the corresponding value. Taking into account the measurement being discussed and the errors associated with the measurement of a specific quantity (i.e., the limitations of the measurement system), “about” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation from the specific value as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the use of “may” when describing embodiments of this disclosure refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that would be tolerated by one of ordinary skill in the art. Other expressions may also omit “substantially.”

[0052] In some embodiments, well-known structures and arrangements may be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, wire connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, in some embodiments, without departing from the scope of this disclosure, blocks, units, and / or modules may be physically divided into two or more interactive and discrete blocks, units, and / or modules. In addition, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of this disclosure.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense, unless so explicitly defined herein.

[0054] Figure 1 This is a block diagram illustrating a display device according to a disclosed embodiment.

[0055] Reference Figure 1 The display device may include a display panel 100, a drive controller 200, a gate driver 300, a data driver 400, and a transmit driver 500. In one or more embodiments, the drive controller 200 and the data driver 400 may be integrated into a single chip. The drive controller 200 may be referred to as the display panel driver.

[0056] The display panel 100 may include a display area DA for displaying images and a non-display area NDA positioned adjacent to the display area DA. In one or more embodiments, a gate driver 300 and a transmitter driver 500 may be mounted in the non-display area NDA.

[0057] The display panel 100 may include multiple gate lines GL, multiple data lines DL, multiple emitter lines EL, and multiple pixels P electrically connected to the gate lines GL, data lines DL, and emitter lines EL. The gate lines GL and emitter lines EL may extend in a first direction DR1, and the data lines DL may extend in a second direction DR2 that intersects the first direction DR1.

[0058] The drive controller 200 can receive input image data IMG and input control signal CONT from a main processor (e.g., a graphics processing unit (GPU)). For example, the input image data IMG may include red image data, green image data, and blue image data. In one or more embodiments, the input image data IMG may also include white image data. As another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0059] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0060] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and can output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0061] The drive controller 200 can generate a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 400, and can output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0062] The drive controller 200 can generate a data signal DATA by receiving input image data IMG and input control signal CONT. The drive controller 200 can output the data signal DATA to the data driver 400.

[0063] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the transmitter driver 500, and can output the third control signal CONT3 to the transmitter driver 500. The third control signal CONT3 may include a vertical start signal and a transmit clock signal.

[0064] The gate driver 300 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL. For example, the gate driver 300 can sequentially output the gate signal to the gate line GL.

[0065] The data driver 400 can receive a second control signal CONT2 and a data signal DATA from the drive controller 200. The data driver 400 can generate a data voltage obtained by converting the data signal DATA into an analog voltage. The data driver 400 can output the data voltage to the data line DL.

[0066] The transmitter driver 500 can generate a transmit signal for driving the transmitter line EL in response to a third control signal CONT3 received from the drive controller 200. The transmitter driver 500 can output the transmit signal to the transmitter line EL. For example, the transmitter driver 500 can sequentially output the transmit signal to the transmitter line EL.

[0067] Figure 2 It is shown Figure 1 A circuit diagram of an example of pixels in a display device.

[0068] Reference Figure 2Each of the pixels P may include: a first transistor T1, including a control electrode connected to a first node N1, a first electrode connected to a second electrode connected to a fifth transistor T5, a second electrode connected to a second node N2, and a back gate electrode connected to the second node N2; a second transistor T2, including a control electrode for receiving a write gate signal GW, a first electrode for receiving a data voltage VDATA, and a second electrode connected to a third node N3; a third transistor T3, including a control electrode for receiving a reference gate signal GR, a first electrode for receiving a reference voltage VREF, and a second electrode connected to the first node N1; a fourth transistor T4, including a control electrode for receiving a reference gate signal GR, a first electrode connected to the second node N2, and a second electrode connected to the third node N3; and a fifth transistor T5, including a control electrode for receiving a first transmit signal EM1, a first electrode for receiving a first transmit signal EM1, a second ... The first electrode of the power voltage ELVDD (e.g., high power voltage) and the second electrode connected to the first electrode of the first transistor T1; the sixth transistor T6, including a control electrode for receiving the second transmit signal EM2, a first electrode connected to the second node N2 and a second electrode connected to the fourth node N4; the seventh transistor T7, including a control electrode for receiving the bias gate signal GB, a first electrode for receiving the initialization voltage VAINT and a second electrode connected to the fourth node N4; the first capacitor C1, including a first electrode connected to the first node N1 and a second electrode connected to the third node N3; the second capacitor C2, including a first electrode connected to the third node N3 and a second electrode connected to the fourth node N4; and the light-emitting element LD, including an anode electrode connected to the fourth node N4 and a second electrode for receiving the second power voltage ELVSS (e.g., low power voltage).

[0069] In the following description, it is assumed that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are implemented as N-channel metal-oxide-semiconductor (NMOS) transistors, and the fifth transistor T5 and the sixth transistor T6 are implemented as P-channel metal-oxide-semiconductor (PMOS) transistors. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be N-type oxide thin-film transistors, and the fifth transistor T5 and the sixth transistor T6 may be P-type silicon thin-film transistors. In one or more other embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be PMOS transistors, and the fifth transistor T5 and the sixth transistor T6 may be NMOS transistors. In other words, the disclosure is not limited to the type of transistors.

[0070] An oxide thin-film transistor can be a low-temperature polycrystalline oxide (LTPO) thin-film transistor in which the active pattern (semiconductor layer) comprises oxide. However, this is merely an example, and N-type transistors are not limited thereto. For example, the active pattern (semiconductor layer) included in an N-type transistor can include inorganic semiconductors (e.g., amorphous silicon or polycrystalline silicon) or organic semiconductors, etc. A silicon thin-film transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor in which the active pattern (semiconductor layer) comprises amorphous silicon or polycrystalline silicon, etc.

[0071] In the case of NMOS transistors, a low voltage level can be a disable level, and a high voltage level can be an enable level. For example, when a signal applied to the control electrode of an NMOS transistor has a low voltage level, the NMOS transistor can be turned off. Conversely, when a signal applied to the control electrode of an NMOS transistor has a high voltage level, the NMOS transistor can be turned on.

[0072] In the case of a PMOS transistor, a low voltage level can be the activation level, and a high voltage level can be the deactivation level. For example, when a signal applied to the control electrode of a PMOS transistor has a low voltage level, the PMOS transistor can be turned on. Conversely, when a signal applied to the control electrode of a PMOS transistor has a high voltage level, the PMOS transistor can be turned off. In other words, the activation and deactivation levels can be determined based on the type of transistor.

[0073] Figure 3 It is shown Figure 2 A cross-sectional view of an example of a first transistor, a first capacitor, and a second capacitor.

[0074] Reference Figure 2 and Figure 3 Pixel P may include a first electrode layer GAT1, a first gate insulating layer GIL1, a second electrode layer GAT2, a second gate insulating layer GIL2, an additional electrode layer CMTL, a first interlayer insulating layer ILD1, an active layer ACT, a third gate insulating layer GIL3, a third electrode layer GAT3, a second interlayer insulating layer ILD2, a connecting electrode layer SD1, and a via layer VIA1.

[0075] In one or more embodiments, the first electrode layer GAT1 may form the second electrode of the second capacitor C2. For example, the first electrode layer GAT1 may be formed as a conductive pattern of at least one material selected from copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0076] In one or more other embodiments, the first electrode layer GAT1 may form the first electrode of the first capacitor C1. In this case, the first electrode layer GAT1 may be electrically connected to the third electrode layer GAT3. For example, the connection electrode layer SD1 connected to the first electrode layer GAT1 through contact hole CNT may be connected to the connection electrode layer SD1 connected to the third electrode layer GAT3 through contact hole CNT. For example, the connection electrode layer SD1 connected to the first electrode layer GAT1 through contact hole CNT and the connection electrode layer SD1 connected to the third electrode layer GAT3 through contact hole CNT may form a conductive pattern. For example, the conductive pattern forming the connection electrode layer SD1 connected to the first electrode layer GAT1 through contact hole CNT and the conductive pattern forming the connection electrode layer SD1 connected to the third electrode layer GAT3 through contact hole CNT may be connected in another layer through a via through the via layer VIA1.

[0077] The first gate insulating layer GIL1 may be located on the first electrode layer GAT1 (as used herein, "located on" can mean "above"). The first gate insulating layer GIL1 may be an inorganic insulating layer comprising an inorganic material. For example, the first gate insulating layer GIL1 may comprise a metal oxide (such as silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) or aluminum oxide (AlO x At least one of the following. However, the first gate insulating layer GIL1 is not limited thereto. For example, the first gate insulating layer GIL1 may include an organic insulating layer comprising an organic material.

[0078] The first gate insulating layer GIL1 can electrically insulate the conductive pattern and / or semiconductor pattern that are positioned between the conductive pattern and / or semiconductor pattern. For example, the first gate insulating layer GIL1 can be located between the first electrode layer GAT1 and the second electrode layer GAT2, such that the first electrode layer GAT1 and the second electrode layer GAT2 are spaced apart. In an embodiment, the first gate insulating layer GIL1 can cover the first electrode layer GAT1.

[0079] The second electrode layer GAT2 is located on the first gate insulating layer GIL1. The second electrode layer GAT2 can form the first electrode of the second capacitor C2 and the second electrode of the first capacitor C1. For example, the second electrode layer GAT2 can be formed as a conductive pattern of at least one material selected from copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0080] In one or more embodiments, the width of the second electrode layer GAT2 may be narrower than the width of the first electrode layer GAT1. Therefore, even if the position of the second electrode layer GAT2 is slightly misaligned during the process of forming the second electrode layer GAT2, the capacitance of the first capacitor C1 or the second capacitor C2 can be maintained.

[0081] As described above, the first capacitor C1 and the second capacitor C2 can be connected in series by sharing the second electrode layer GAT2. Therefore, the area occupied by pixel P is reduced, and high resolution is possible.

[0082] The second gate insulating layer GIL2 can be located on the first gate insulating layer GIL1 and the second electrode layer GAT2. The second gate insulating layer GIL2 can be an inorganic insulating layer comprising inorganic materials. For example, the second gate insulating layer GIL2 can include metal oxides (such as silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) or aluminum oxide (AlO x At least one of the following. However, the second gate insulating layer GIL2 is not limited thereto. For example, the second gate insulating layer GIL2 may include an organic insulating layer containing organic materials.

[0083] The second gate insulating layer GIL2 can electrically insulate the conductive pattern and / or semiconductor pattern that are positioned between the conductive pattern and / or semiconductor pattern. For example, the second gate insulating layer GIL2 can be located between the additional electrode layer CMTL and the second electrode layer GAT2, such that the additional electrode layer CMTL and the second electrode layer GAT2 are spaced apart. In an embodiment, the second gate insulating layer GIL2 can be integrally disposed on the second electrode layer GAT2 and the first gate insulating layer GIL1 to cover the second electrode layer GAT2 and the first gate insulating layer GIL1.

[0084] The first transistor T1 may be located on the second gate insulating layer GIL2. The first transistor T1 may include an active layer ACT, a third electrode layer GAT3, and a first electrode pattern CMTL1 of an additional electrode layer CMTL.

[0085] The additional electrode layer CMTL may include a first electrode pattern CMTL1 and a second electrode pattern CMTL2. The additional electrode layer CMTL is located on the second gate insulating layer GIL2. For example, the additional electrode layer CMTL may be formed as a conductive pattern of at least one material selected from copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0086] The first electrode pattern CMTL1 can form the back gate electrode of the first transistor T1. For example, at least a portion of the first electrode pattern CMTL1 can be stacked with the channel region CH of the active layer ACT. The first electrode pattern CMTL1 can also be connected to another electrode via the connecting electrode layer SD1.

[0087] In one or more embodiments, the second electrode pattern CMTL2 can form the first electrode of the first capacitor C1. In this case, the second electrode pattern CMTL2 can be electrically connected to the third electrode layer GAT3. For example, the connection electrode layer SD1 connected to the second electrode pattern CMTL2 through contact holes CNT can be connected to the connection electrode layer SD1 connected to the third electrode layer GAT3 through contact holes CNT. For example, the connection electrode layer SD1 connected to the second electrode pattern CMTL2 through contact holes CNT and the connection electrode layer SD1 connected to the third electrode layer GAT3 through contact holes CNT can form a single conductive pattern. For example, the conductive pattern forming the connection electrode layer SD1 connected to the second electrode pattern CMTL2 through contact holes CNT and the conductive pattern forming the connection electrode layer SD1 connected to the third electrode layer GAT3 through contact holes CNT can be connected in different layers through vias passing through the via layer VIA1.

[0088] In one or more other embodiments, the second electrode pattern CMTL2 may form the second electrode of the second capacitor C2. For example, the second electrode pattern CMTL2 may be electrically connected to the light-emitting element LD.

[0089] In one or more embodiments, the width of the second electrode pattern CMTL2 may be narrower than the width of the second electrode layer GAT2. Therefore, even if the position of the second electrode pattern CMTL2 is slightly misaligned during the process of forming the second electrode pattern CMTL2, the capacitance of the first capacitor C1 or the second capacitor C2 can be maintained.

[0090] The first interlayer insulating layer ILD1 may be located on the second gate insulating layer GIL2 and the additional electrode layer CMTL. The first interlayer insulating layer ILD1 may be an inorganic insulating layer comprising inorganic materials. For example, the first interlayer insulating layer ILD1 may comprise metal oxides (such as silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) or aluminum oxide (AlO x At least one of the following. However, the first interlayer insulation layer ILD1 is not limited thereto. For example, the first interlayer insulation layer ILD1 may include an organic insulation layer containing organic materials.

[0091] The first interlayer insulating layer ILD1 electrically insulates the conductive pattern and / or semiconductor pattern that are positioned between the conductive pattern and / or semiconductor pattern. For example, the first interlayer insulating layer ILD1 may be located between the additional electrode layer CMTL and the active layer ACT, such that the additional electrode layer CMTL and the active layer ACT are spaced apart. In an embodiment, the first interlayer insulating layer ILD1 may be integrally disposed on the additional electrode layer CMTL and the second gate insulating layer GIL2 to cover the additional electrode layer CMTL and the second gate insulating layer GIL2.

[0092] The active layer ACT can be located on the first interlayer insulating layer ILD1. The active layer ACT can include one of various types of semiconductors (e.g., amorphous silicon semiconductor, monocrystalline silicon semiconductor, polycrystalline silicon semiconductor, low-temperature polycrystalline silicon semiconductor, and oxide semiconductor).

[0093] The active layer ACT can form the channel region CH of the first transistor T1. The active layer ACT may include a first contact region CA1 and a second contact region CA2 connected to the connection electrode layer SD1. The first contact region CA1 and the second contact region CA2 can be connected to the connection electrode layer SD1 through contact holes CNT.

[0094] The region between the first contact region CA1 and the second contact region CA2 can be a channel region CH. The channel region CH can be stacked with the third electrode layer GAT3 that forms the control electrode of the first transistor T1. The channel region CH can be an undoped semiconductor pattern and can be an intrinsic semiconductor. The first contact region CA1 and the second contact region CA2 can be doped semiconductor patterns.

[0095] The third gate insulating layer GIL3 can be located on the first interlayer insulating layer ILD1 and the active layer ACT. The third gate insulating layer GIL3 can be an inorganic insulating layer comprising inorganic materials. For example, the third gate insulating layer GIL3 can include metal oxides (such as silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) or aluminum oxide (AlO x At least one of the following. However, the third gate insulating layer GIL3 is not limited thereto. For example, the third gate insulating layer GIL3 may include an organic insulating layer containing organic materials.

[0096] The third gate insulating layer GIL3 can electrically insulate the conductive pattern and / or semiconductor pattern on which the third gate insulating layer GIL3 is positioned between the conductive pattern and / or semiconductor pattern. For example, the third gate insulating layer GIL3 can be located between the active layer ACT and the third electrode layer GAT3, such that the active layer ACT and the third electrode layer GAT3 are spaced apart. In an embodiment, the third gate insulating layer GIL3 can be integrally disposed on the active layer ACT and the first interlayer insulating layer ILD1 to cover the active layer ACT and the first interlayer insulating layer ILD1.

[0097] The third electrode layer GAT3 is located on the third gate insulating layer GIL3. The third electrode layer GAT3 can form the control electrode of the first transistor T1. The third electrode layer GAT3 can be stacked with the channel region CH of the active layer ACT. For example, the third electrode layer GAT3 can be formed as a conductive pattern of at least one material selected from copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0098] The second interlayer insulating layer ILD2 can be located on the third gate insulating layer GIL3 and the third electrode layer GAT3. The second interlayer insulating layer ILD2 can be an inorganic insulating layer comprising inorganic materials. For example, the second interlayer insulating layer ILD2 can include metal oxides (such as silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y) or aluminum oxide (AlO x At least one of the following. However, the second interlayer insulation layer ILD2 is not limited thereto. For example, the second interlayer insulation layer ILD2 may include an organic insulation layer containing organic materials.

[0099] The second interlayer insulating layer ILD2 electrically insulates the conductive and / or semiconductor patterns positioned between the conductive and / or semiconductor patterns. For example, the second interlayer insulating layer ILD2 may be located between the third electrode layer GAT3 and the connection electrode layer SD1, such that the third electrode layer GAT3 is spaced apart from the connection electrode layer SD1. In an embodiment, the second interlayer insulating layer ILD2 may be integrally disposed on the third gate insulating layer GIL3 and the third electrode layer GAT3 to cover the third gate insulating layer GIL3 and the third electrode layer GAT3.

[0100] The connecting electrode layer SD1 is located on the second interlayer insulating layer ILD2. The connecting electrode layer SD1 can be connected to the active layer ACT, the first electrode layer GAT1, the second electrode layer GAT2, the third electrode layer GAT3, and the additional electrode layer CMTL through contact holes CNT. For example, the connecting electrode layer SD1 can be formed as a conductive pattern of at least one material selected from copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0101] The via layer VIA1 can be located on the connection electrode layer SD1. A via layer VIA1 and a connection electrode layer SD1 are shown as an example, but the disclosure is not limited to the number of via layers and connection electrode layers. When the number of connection electrode layers is multiple, the individual via layers can electrically insulate the connection electrode layers from each other.

[0102] Figure 4 It is shown Figure 1 A conceptual diagram of the driving operation of a display device. Figures 5 to 9 It is shown that Figure 1 A diagram illustrating an example of a display device performing a display scanning operation. Figure 10 It is shown that Figure 1 A timing diagram of an example of a display device performing a self-scanning operation.

[0103] Reference Figure 1 , Figure 2 and Figure 4 It can perform either a display scan operation (DISPLAY SCAN) or a self-scan operation (SELF SCAN) within a single frame. When performing a display scan operation (DISPLAY SCAN), a data voltage VDATA can be written. When performing a self-scan operation (SELF SCAN), an illumination operation can be performed without writing the data voltage VDATA.

[0104] At the maximum driving frequency of the display panel 100 (for example, when the driving frequency is about 240 Hz), a display scan operation of one frame can be repeated continuously, and a display scan operation of one frame can be a driving frame.

[0105] At the maximum driving frequency excluding the display panel 100 (i.e., assuming...) Figure 4 At drive frequencies of approximately 120 Hz, approximately 80 Hz, approximately 60 Hz and approximately 48 Hz (the maximum drive frequency in the system is approximately 240 Hz), a display scan operation (DISPLAY SCAN) can be performed in one frame, and a self-scan operation (SELF SCAN) can be performed in at least one frame.

[0106] For example, when the drive frequency is approximately 120 Hz, one frame of display scan operation (DISPLAY SCAN) and one frame of self-scan operation (SELF SCAN) can be repeated, and one frame of display scan operation (DISPLAY SCAN) and one frame of self-scan operation (SELF SCAN) can be configured as one drive frame (i.e., the same image can be displayed during one drive frame). When the drive frequency is approximately 80 Hz, one frame of display scan operation (DISPLAY SCAN) and two frames of self-scan operation (SELF SCAN) can be repeated, and one frame of display scan operation (DISPLAY SCAN) and two frames of self-scan operation (SELF SCAN) can be configured as one drive frame. When the drive frequency is approximately 60 Hz, one frame of display scan operation (DISPLAY SCAN) and three frames of self-scan operation (SELF SCAN) can be repeated, and one frame of display scan operation (DISPLAY SCAN) and three frames of self-scan operation (SELF SCAN) can be configured as one drive frame. When the drive frequency is approximately 48Hz, a display scan operation (DISPLAY SCAN) of one frame and a self-scan operation (SELF SCAN) of four frames can be repeated, and a drive frame can be configured for a display scan operation (DISPLAY SCAN) of one frame and a self-scan operation (SELF SCAN) of four frames.

[0107] As described above, the drive controller 200 can change the drive frequency by adjusting the length of the SELF SCAN operation.

[0108] Reference Figure 2 and Figure 5 The data voltage VDATA can be written into the frame in which the Display Scan operation is performed. The frame in which the Display Scan operation is performed may include a first initialization period IP1, a compensation period CP, a write period WP, ​​and a transmit period EP.

[0109] Reference Figure 2 , Figure 5 and Figure 6 During the first initialization period IP1, the second transmit signal EM2, the reference gate signal GR, and the bias gate signal GB can be activated, and the third transistor T3, the sixth transistor T6, and the seventh transistor T7 can be turned on. Therefore, the reference voltage VREF can be applied to the first node N1, and the initialization voltage VAINT can be applied to the third node N3 and the fourth node N4. Thus, the first capacitor C1 and the second capacitor C2 can be initialized.

[0110] Reference Figure 2 , Figure 5 and Figure 7 During the compensation period CP, the first transmit signal EM1, the reference gate signal GR, and the bias gate signal GB are at active levels, and the third transistor T3 through the fifth transistor T5 and the seventh transistor T7 can be turned on. Therefore, the reference voltage VREF can be applied to the first node N1, the voltage of the second node N2 can be increased by subtracting the threshold voltage VTH of the first transistor T1 from the voltage of the first node N1, and the initialization voltage VAINT can be applied to the fourth node N4. Additionally, the voltage of the second node N2 can be transmitted to the third node N3.

[0111] Reference Figure 2 , Figure 5 and Figure 8 During the write phase WP, the write gate signal GW and the bias gate signal GB can be active, and the second transistor T2 and the seventh transistor T7 can be turned on. Therefore, the data voltage VDATA can be applied to the third node N3, and the initialization voltage VAINT can be applied to the fourth node N4. Additionally, the voltage of the first node N1 can change the voltage change ΔV of the third node N3 through the coupling of the first capacitor C1. Therefore, the data voltage VDATA can be written to the first capacitor C1.

[0112] After the write gate signal GW has an active level, the first transmit signal EM1 may also have an active level, but the disclosure is not limited thereto. For example, the write gate signal GW and the first transmit signal EM1 may have active levels concurrently or simultaneously.

[0113] Reference Figure 2 , Figure 5 and Figure 9During the transmission period EP, the first transmission signal EM1 and the second transmission signal EM2 can have an active level, and the fifth transistor T5 and the sixth transistor T6 can be turned on. Therefore, the first power voltage ELVDD can be applied to the first transistor T1, and the first transistor T1 can generate a drive current corresponding to the voltage of the first node N1. The light-emitting element LD can emit light with a brightness corresponding to the drive current.

[0114] Because the first capacitor C1 to which the data voltage VDATA is written is not directly connected to the second electrode of the first transistor T1, the influence of the driving current on the voltage written to the first capacitor C1 can be reduced or minimized, and the error of the threshold voltage compensation can be reduced.

[0115] Reference Figure 2 and Figure 10 The frame performing the SELF SCAN operation may include a second initialization period (IP2) and a transmit period (EP). This is because the transmit period (EP) is associated with the display scan operation (DISPLAY SCAN) performed within it (see [reference]). Figure 5 The transmission time period (EP) of the frames is basically the same, so repeated descriptions are omitted.

[0116] During the second initialization period IP2, the bias gate signal GB can have an active level, and the seventh transistor T7 can be turned on. Therefore, the initialization voltage VAINT can be applied to the fourth node N4. Thus, the anode electrode of the light-emitting element LD can be initialized.

[0117] Reference Figure 2 , Figure 5 and Figure 10 Drive controller 200 (refer to) Figure 1 The cutoff duty cycle of at least one of the first transmitted signal EM1 and the second transmitted signal EM2 can be adjusted based on the transmit cutoff ratio AOR. For example, the drive controller 200 (see reference) Figure 1 The cutoff duty cycle of the first transmit signal EM1 can be adjusted based on the transmit cutoff ratio AOR. In this case, within the frame where the self-scan operation is performed, the cutoff duty cycle of the first transmit signal EM1 can be adjusted by applying the first transmit signal EM1 with an inactive level during the transmit period EP. For example, the drive controller 200 (see reference) Figure 1 The cutoff duty cycle of the second transmitted signal EM2 can be adjusted according to the transmit cutoff ratio AOR. For example, the drive controller 200 (refer to...) Figure 1The cutoff duty cycle of the first transmitted signal EM1 and the second transmitted signal EM2 can be adjusted according to the transmit cutoff ratio AOR. Here, the transmit cutoff ratio AOR means the proportion of time in a frame during which the light-emitting element LD emits light, and the cutoff duty cycle means the proportion of time in a frame during which there is an inactive level.

[0118] When neither the first transmission signal EM1 nor the second transmission signal EM2 has an activation level, the light-emitting element LD does not emit light. Therefore, the drive controller 200 can adjust the emission cutoff ratio AOR by adjusting the cutoff duty cycle of at least one of the first transmission signal EM1 and the second transmission signal EM2.

[0119] The transmit cutoff ratio AOR can be adjusted by only adjusting the cutoff duty cycle of the second transmit signal EM2, but it can also be adjusted by only adjusting the cutoff duty cycle of the first transmit signal EM1.

[0120] In one or more embodiments, the transmit cutoff ratio AOR may be a value set by the user. In one or more other embodiments, the transmit cutoff ratio AOR may be a value automatically determined based on a setting value (such as screen brightness or maximum brightness) when the user determines such a setting value.

[0121] Figure 11 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment. Figure 12 It is shown that Figure 11 A timing diagram illustrating an example of a display device performing a display scanning operation. Figure 13 It is shown that Figure 11 A timing diagram of an example of a display device performing a self-scanning operation.

[0122] Because, in addition to the first transmission signal EM1 being applied to the control electrode of the seventh transistor T7, the display device according to this embodiment and Figure 1 The configurations of the display devices are basically the same, so the same reference numerals and reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0123] Reference Figures 11 to 13 Pixel P may include a seventh transistor T7, which includes a control electrode for receiving a first transmission signal EM1, a first electrode for receiving an initialization voltage VAINT, and a second electrode connected to a fourth node N4. The seventh transistor T7 may be of a different type than the fifth transistor T5. For example, as... Figure 6As shown, when the seventh transistor T7 is an NMOS transistor, the fifth transistor T5 can be a PMOS transistor. That is, when the seventh transistor T7 is on, the fifth transistor T5 can be off, and when the seventh transistor T7 is off, the fifth transistor T5 can be on. As described above, since the seventh transistor T7 is controlled by the first transmit signal EM1, the number of lines used can be reduced, and high-resolution implementation is possible.

[0124] Because the Display Scan and Self Scan operations are related to the reference... Figures 5 to 10 The described embodiments are essentially the same, so repeated descriptions have been omitted.

[0125] Figure 14 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment.

[0126] Because, in addition to the first power voltage ELVDD being applied to the first electrode of the third transistor T3, the display device according to this embodiment and Figure 1 The configurations of the display devices are basically the same, so the same reference numerals and reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0127] Reference Figure 14 Pixel P may include a third transistor T3, which includes a control electrode for receiving a reference gate signal GR, a first electrode for receiving a first power voltage ELVDD, and a second electrode connected to a first node N1.

[0128] Figure 15 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment.

[0129] Because, apart from the back gate electrode of the first transistor T1 being connected to the fourth node N4, the display device according to this embodiment and Figure 1 The configurations of the display devices are basically the same, so the same reference numerals and reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0130] Reference Figure 15 Pixel P may include a first transistor T1, which includes a control electrode connected to a first node N1, a first electrode connected to a second electrode connected to a fifth transistor T5, a second electrode connected to a second node N2, and a back gate electrode connected to a light-emitting element LD. For example, the back gate electrode of the first transistor T1 may be connected to the anode electrode of the light-emitting element LD.

[0131] and Figure 11 , Figure 14 and Figure 15At least two of the corresponding one or more embodiments can be combined to configure one or more other embodiments.

[0132] Figure 16 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment.

[0133] Because, apart from the fifth transistor T5 and the sixth transistor T6 being NMOS transistors, according to the circuit diagram of this embodiment and Figure 2 The circuit diagrams are configured in a basically the same way, so the same reference numerals and figure numbers are used for the same or similar components, and repeated descriptions are omitted.

[0134] Reference Figure 16 The first transistor T1 through the seventh transistor T7 can be implemented as NMOS transistors. In this case, applied to Figure 16 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can be applied to Figure 2 The first emission signal EM1 and the second emission signal EM2 of pixel P are opposite. For example, when applied to Figure 2 When the first transmission signal EM1 and the second transmission signal EM2 of pixel P have a high voltage level, the timing is applied to Figure 16 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can have low voltage levels. Similarly, when applied to Figure 2 When the first transmission signal EM1 and the second transmission signal EM2 of pixel P have a low voltage level, the timing is applied to Figure 16 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can have a high voltage level.

[0135] In one or more embodiments, at least one of the first transistors T1 to the seventh transistor T7 may include an oxide semiconductor. For example, at least one of the first transistors T1 to the seventh transistor T7 may be an oxide semiconductor transistor that includes an oxide semiconductor.

[0136] Figure 17 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment.

[0137] Because, apart from the fifth transistor T5 and the sixth transistor T6 being NMOS transistors, according to the circuit diagram of this embodiment and Figure 11 The circuit diagrams are configured in a basically the same way, so the same reference numerals and figure numbers are used for the same or similar components, and repeated descriptions are omitted.

[0138] Reference Figure 17 The first transistor T1 through the seventh transistor T7 can be implemented as NMOS transistors. In this case, applied to Figure 17 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can be applied to Figure 11 The first emission signal EM1 and the second emission signal EM2 of pixel P are opposite. For example, when applied to Figure 11 When the first transmission signal EM1 and the second transmission signal EM2 of pixel P have a high voltage level, the timing is applied to Figure 17 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can have low voltage levels. Similarly, when applied to Figure 11 When the first transmission signal EM1 and the second transmission signal EM2 of pixel P have a low voltage level, the timing is applied to Figure 17 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can have a high voltage level.

[0139] In one or more embodiments, at least one of the first transistors T1 to the seventh transistor T7 may include an oxide semiconductor. For example, at least one of the first transistors T1 to the seventh transistor T7 may be an oxide semiconductor transistor that includes an oxide semiconductor.

[0140] Figure 18 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment.

[0141] Because, apart from the fifth transistor T5 and the sixth transistor T6 being NMOS transistors, according to the circuit diagram of this embodiment and Figure 14 The circuit diagrams are configured in a basically the same way, so the same reference numerals and figure numbers are used for the same or similar components, and repeated descriptions are omitted.

[0142] Reference Figure 18 The first transistor T1 through the seventh transistor T7 can be implemented as NMOS transistors. In this case, applied to Figure 18 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can be applied to Figure 14 The first emission signal EM1 and the second emission signal EM2 of pixel P are opposite. For example, when applied to Figure 14 When the first transmission signal EM1 and the second transmission signal EM2 of pixel P have a high voltage level, the timing is applied to Figure 18 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can have low voltage levels. Similarly, when applied to Figure 14 When the first transmission signal EM1 and the second transmission signal EM2 of pixel P have a low voltage level, the timing is applied to Figure 18 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can have a high voltage level.

[0143] In one or more embodiments, at least one of the first transistors T1 to the seventh transistor T7 may include an oxide semiconductor. For example, at least one of the first transistors T1 to the seventh transistor T7 may be an oxide semiconductor transistor that includes an oxide semiconductor.

[0144] Figure 19 This is a circuit diagram illustrating the pixels of a display device according to a disclosed embodiment.

[0145] Because, apart from the fifth transistor T5 and the sixth transistor T6 being NMOS transistors, according to the circuit diagram of this embodiment and Figure 15 The circuit diagrams are configured in a basically the same way, so the same reference numerals and figure numbers are used for the same or similar components, and repeated descriptions are omitted.

[0146] Reference Figure 19 The first transistor T1 through the seventh transistor T7 can be implemented as NMOS transistors. In this case, applied to Figure 19 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can be applied to Figure 15 The first emission signal EM1 and the second emission signal EM2 of pixel P are opposite. For example, when applied to Figure 15 When the first transmission signal EM1 and the second transmission signal EM2 of pixel P have a high voltage level, the timing is applied to Figure 19 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can have low voltage levels. Similarly, when applied to Figure 15 When the first transmission signal EM1 and the second transmission signal EM2 of pixel P have a low voltage level, the timing is applied to Figure 19 The first transmission signal EM1 and the second transmission signal EM2 of pixel P can have a high voltage level.

[0147] In one or more embodiments, at least one of the first transistors T1 to the seventh transistor T7 may include an oxide semiconductor. For example, at least one of the first transistors T1 to the seventh transistor T7 may be an oxide semiconductor transistor that includes an oxide semiconductor.

[0148] Figure 20 This is a block diagram illustrating an electronic device according to a disclosed embodiment.

[0149] Reference Figure 20 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device (I / O device) 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be... Figure 1The electronic device 1000 may also include several ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc., or with other systems. In one or more embodiments, the electronic device 1000 may be implemented as a smartphone. However, this is merely an example, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a mobile phone, television, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation device, computer monitor, laptop computer, or head-mounted display device, etc.

[0150] Processor 1010 can perform specific calculations or tasks. According to one or more embodiments, processor 1010 can be a microprocessor, central processing unit, or application processor, etc. Processor 1010 can be connected to other components via an address bus, control bus, or data bus, etc. According to one or more embodiments, processor 1010 can also be connected to an expansion bus (such as a peripheral component interconnect (PCI) bus).

[0151] The memory device 1020 can store data suitable for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices (such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nanofloating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, and ferroelectric random access memory (FRAM) devices) and / or volatile memory devices (such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices).

[0152] Storage device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), and CD-ROMs, etc.

[0153] Input / output device 1040 may include input devices (such as a keyboard, keypad, touchpad, touchscreen, and mouse) and output devices (such as a speaker and printer). According to one or more embodiments, display device 1060 may be included in input / output device 1040.

[0154] The power supply 1050 can supply power suitable for the operation of the electronic device 1000. For example, the power supply 1050 can be a power management integrated circuit (PMIC).

[0155] The display device 1060 can display an image corresponding to the visual information of the electronic device 1000. In this case, the display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited thereto. The display device 1060 can be connected to other components via a bus or other communication link.

[0156] Furthermore, the disclosure can be applied to display devices and electronic devices that include display devices. For example, the disclosure can be applied to digital TVs, 3D TVs, mobile phones, smartphones, tablet computers, VR devices, PCs, home electronic devices, laptop computers, PDAs, PMPs, digital cameras, music players, portable game consoles, and navigation systems, etc.

[0157] Although some embodiments and examples are described herein, these embodiments and examples are provided only to facilitate a more general understanding of the disclosure. The disclosure is not limited to the above embodiments, and those skilled in the art to which the disclosure pertains can make different corrections and modifications based on such description.

[0158] Therefore, the spirit of the disclosure should not be limited to the described embodiments, and the claims and all modifications identical or equivalent to the claims may fall within the scope of the spirit of the disclosure.

[0159] Although described with reference to the above embodiments, it will be understood that those skilled in the art can make different modifications and changes to the disclosure without departing from the spirit and scope of the disclosure described in the claims and their functional equivalents to be included therein.

Claims

1. A pixel, the pixel comprising: A first transistor is used to generate a drive current and includes a first electrode, a control electrode connected to a first node, and a second electrode connected to a second node. The second transistor includes a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node. The first capacitor includes a first electrode connected to the first node and a second electrode connected to the third node; The second capacitor includes a second electrode and a first electrode connected to the third node; as well as A light-emitting element for emitting light by receiving the driving current.

2. The pixel of claim 1, further comprising a fourth transistor, the fourth transistor comprising a control electrode for receiving a reference gate signal, a first electrode connected to the second node, and a second electrode connected to the third node.

3. The pixel according to claim 1, wherein, The first transistor is an N-channel metal-oxide-semiconductor transistor.

4. The pixel according to claim 1, the pixel further comprising a seventh transistor, the seventh transistor comprising a control electrode for receiving a bias gate signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the light-emitting element.

5. The pixel according to claim 1, wherein the pixel further comprises: The fifth transistor includes a control electrode for receiving a first transmitted signal, a first electrode for receiving a first electrical voltage, and a second electrode connected to the first transistor; The sixth transistor includes a control electrode for receiving a second transmission signal, a first electrode connected to the first transistor, and a second electrode connected to the light-emitting element; as well as The seventh transistor includes a control electrode for receiving the first transmitted signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the light-emitting element. The seventh transistor includes a type different from that of the fifth transistor.

6. The pixel of claim 1, further comprising a third transistor, the third transistor comprising a control electrode for receiving a reference gate signal, a first electrode for receiving a reference voltage, and a second electrode connected to the first node.

7. The pixel of claim 1, further comprising a third transistor, the third transistor comprising a control electrode for receiving a reference gate signal, a first electrode for receiving a first power voltage, and a second electrode connected to the first node.

8. The pixel according to claim 1, wherein, The first transistor also includes a back gate electrode connected to the second node.

9. The pixel according to claim 1, wherein, The first transistor also includes a back gate electrode connected to the anode electrode of the light-emitting element.

10. The pixel according to claim 1, wherein the pixel further comprises: The first electrode layer includes the second electrode of the second capacitor; The second electrode layer is located above the first electrode layer and includes the second electrode of the first capacitor and the first electrode of the second capacitor. An additional electrode layer is provided above the second electrode layer and includes a first electrode pattern and a second electrode pattern, wherein the first electrode pattern includes the back gate electrode of the first transistor and the second electrode pattern includes the first electrode of the first capacitor. An active layer is located above the additional electrode layer and includes the channel region of the first transistor. as well as A third electrode layer, above the active layer, includes the control electrode of the first transistor and is electrically connected to the second electrode pattern.

11. The pixel according to claim 1, wherein the pixel further comprises: The first electrode layer includes the first electrode of the first capacitor; The second electrode layer is located above the first electrode layer and includes the second electrode of the first capacitor and the first electrode of the second capacitor. An additional electrode layer is provided above the second electrode layer and includes a first electrode pattern and a second electrode pattern, wherein the first electrode pattern includes the back gate electrode of the first transistor and the second electrode pattern includes the second electrode of the second capacitor. An active layer is located above the additional electrode layer and includes the channel region of the first transistor. as well as A third electrode layer, above the active layer, includes the control electrode of the first transistor and is electrically connected to the first electrode layer.

12. A display device, the display device comprising: Display panel, including pixels; as well as A display panel driver is configured to drive the display panel. The pixels include: A first transistor is used to generate a drive current and includes a first electrode, a control electrode connected to a first node, and a second electrode connected to a second node. The second transistor includes a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node. The first capacitor includes a first electrode connected to the first node and a second electrode connected to the third node; The second capacitor includes a second electrode and a first electrode connected to the third node; and A light-emitting element for emitting light by receiving the driving current.

13. The display device according to claim 12, wherein, The pixel further includes a fourth transistor, which includes a control electrode for receiving a reference gate signal, a first electrode connected to the second node, and a second electrode connected to the third node.

14. The display device according to claim 12, wherein, The first transistor includes an N-channel metal-oxide-semiconductor transistor.

15. The display device according to claim 12, wherein, The pixel also includes a seventh transistor, which includes a control electrode for receiving a bias gate signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the light-emitting element.

16. The display device according to claim 12, wherein, The pixels also include: The fifth transistor includes a control electrode for receiving a first transmitted signal, a first electrode for receiving a first electrical voltage, and a second electrode connected to the first transistor; The sixth transistor includes a control electrode for receiving a second transmitted signal, a first electrode connected to the first transistor, and a second electrode connected to the light-emitting element; and The seventh transistor includes a control electrode for receiving the first transmitted signal, a first electrode for receiving an initialization voltage, and a second electrode connected to the light-emitting element.

17. The display device according to claim 12, wherein, The pixels also include: The fifth transistor includes a control electrode for receiving a first transmitted signal, a first electrode for receiving a first electrical voltage, and a second electrode connected to the first transistor; The sixth transistor includes a control electrode for receiving a second transmitted signal, a first electrode connected to the first transistor, and a second electrode connected to the light-emitting element. The display panel driver is configured to adjust the cutoff duty cycle of at least one of the first transmission signal and the second transmission signal according to the transmission cutoff ratio.

18. The display device according to claim 12, wherein, The pixel further includes a third transistor, which includes a control electrode for receiving a reference gate signal, a first electrode for receiving a reference voltage, and a second electrode connected to the first node.

19. The display device according to claim 12, wherein, The pixel further includes a third transistor, which includes a control electrode for receiving a reference gate signal, a first electrode for receiving a first power voltage, and a second electrode connected to the first node.

20. An electronic device, the electronic device comprising: A processor used to provide input image data; as well as A display device for displaying an image based on the input image, and comprising: a display panel including pixels; and a display panel driver configured to drive the display panel. The pixels include: A first transistor is used to generate a drive current and includes a first electrode, a control electrode connected to a first node, and a second electrode connected to a second node. The second transistor includes a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node. The first capacitor includes a first electrode connected to the first node and a second electrode connected to the third node; The second capacitor includes a second electrode and a first electrode connected to the third node; and A light-emitting element for emitting light by receiving the driving current.

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