Electronic device operation method

Abstract

The invention relates to an operation method of an electronic device, which comprises the following steps of: providing a first transistor comprising one end and the other end; providing a power consumption device which is electrically connected with one end of the first transistor; a signal source is provided and is electrically connected with the other end of the first transistor; wherein in a time frame having a write-in period and an output period, the signal source provides a high voltage level in the output period, and the signal source maintains a low voltage level in the write-in period.

Description

Technical Field

[0001] This disclosure relates to an operating method, particularly an operating method for an electronic device having an array circuit. Background Technology

[0002] Traditional pixel array circuits typically update data sequentially and maintain data continuity through energy storage elements (such as capacitors) in the array. While this method of updating data can increase the duration of data conversion into output energy, for some electronic devices with power consumption, such as exposure devices or 3D printing devices, these devices often require overall data updates (e.g., all array units updating data). Therefore, if the traditional sequential data update method is used, the material properties of the components in the array circuit may cause array units that have not yet received data to be affected by the data received by other array units, resulting in uneven data updates across the entire array.

[0003] Therefore, a novel method of operating electronic devices is needed to improve the above problems. Summary of the Invention

[0004] This disclosure provides an operating method for an electronic device, comprising the steps of: providing a first transistor, including one end and another end; providing a power consumption device electrically connected to one end of the first transistor; and providing a signal source electrically connected to the other end of the first transistor; wherein in a time frame having a write cycle and an output cycle, the signal source provides a high voltage level during the output cycle and maintains a low voltage level during the write cycle.

[0005] This disclosure also provides another method of operating an electronic device, comprising the steps of: providing a first transistor, including one end and another end; providing a power consumption device electrically connected to one end of the first transistor; and providing a signal source electrically connected to the other end of the first transistor; wherein, in a time frame having a write cycle and an output cycle, the signal source provides a low voltage level during the output cycle and maintains a high voltage level during the input cycle. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0007] Figure 2A This corresponds to an embodiment of the present disclosure. Figure 1 Timing diagrams of each signal.

[0008] Figure 2B Another embodiment of this disclosure corresponds to Figure 1 Timing diagrams of each signal.

[0009] Figure 3This is a schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0010] Figure 4A This corresponds to an embodiment of the present disclosure. Figure 3 Timing diagrams of each signal.

[0011] Figure 4B This corresponds to another embodiment of the present disclosure. Figure 3 Timing diagrams of each signal.

[0012] Figure 5 This is a schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0013] Figure 6A This corresponds to an embodiment of the present disclosure. Figure 5 Timing diagrams of each signal.

[0014] Figure 6B This corresponds to another embodiment of the present disclosure. Figure 5 Timing diagrams of each signal.

[0015] Figure 7 This is a schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0016] Figure 8A This corresponds to an embodiment of the present disclosure. Figure 7 Timing diagrams of each signal.

[0017] Figure 8B This corresponds to another embodiment of the present disclosure. Figure 7 Timing diagrams of each signal.

[0018] Figure 9 This is a schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0019] Figure 10A This corresponds to an embodiment of the present disclosure. Figure 9 Timing diagrams of each signal.

[0020] Figure 10B This corresponds to another embodiment of the present disclosure. Figure 9 Timing diagrams of each signal.

[0021] Explanation of reference numerals in the attached figures:

[0022] 1: Electronic devices;

[0023] T1, T2, T3, T4, T5, T6, T7: Transistors;

[0024] a1, b1, c1, d1, e1, f1, g1: First end;

[0025] a2, b2, c2, d2, e2, f2, g2: the second end;

[0026] a3, b3, c3, d3, e3, f3, g3: Control terminals;

[0027] P: Array unit;

[0028] row[1]~row[n]: columns;

[0029] 10: Power consumption devices;

[0030] 20, 30, 50, 60: Signal source;

[0031] D[1]~D[m]: Data cable;

[0032] G[1]~G[n]: Scan lines;

[0033] DS(1)~DS(m): Data signals;

[0034] SS(1)~SS(n): Scan signals;

[0035] Ca1, Ca2: Capacitors;

[0036] V1: First signal;

[0037] Frame1, Frame2: Time frame;

[0038] P1, P2: Write cycle;

[0039] P0: Output cycle;

[0040] V1_H: High voltage level of the first signal;

[0041] V1_L: ​​Low voltage level of the first signal;

[0042] VDD, VDD_H: High voltage level signal;

[0043] EM: Control signal;

[0044] EM_H: High voltage level of the control signal;

[0045] EM_L: Low voltage level of the control signal;

[0046] V2: Second signal;

[0047] 40: Inverter;

[0048] n1: Node-in-Node;

[0049] n2: Node output node;

[0050] V2_H: High voltage level of the second signal;

[0051] V2_L: Low voltage level of the second signal;

[0052] Vinit: Start signal;

[0053] I device : First current value. Detailed Implementation

[0054] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0055] Throughout this specification and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will understand that sensor manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that have the same function but different names. In the following specification and claims, words such as "containing," "comprising," and "including" are open-ended terms and should therefore be interpreted as meaning "containing but not limited to...".

[0056] The terms “approximately,” “substantially,” or “roughly” are generally interpreted as being within 10% of a given value or range, or as being within 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0057] The term "electrical connection" encompasses any means of direct or indirect electrical connection. An electrical connection between two components can be achieved through direct contact for transmitting electrical signals, with no other components between them. Alternatively, an electrical connection can be achieved by bridging the two components through an intervening component to transmit electrical signals. "Electrical connection" can also be referred to as "coupling."

[0058] The use of ordinal numbers such as "first," "second," etc., in the specification and claims to modify elements does not in itself imply or represent any prior ordinal number for that element (or those elements), nor does it represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0059] In this disclosure, the terms "given range is from the first value to the second value" and "given range falls within the range of the first value to the second value" indicate that the given range includes the first value, the second value, and other values ​​in between.

[0060] Furthermore, the electronic devices disclosed herein may include exposure apparatus, printing apparatus, 3D printing apparatus, display devices, vehicle-mounted devices, imaging apparatus, assembly apparatus, backlight devices, antenna devices, splicing devices, touch displays, curved displays, or free-shape displays, but are not limited thereto. Electronic devices may include, for example, liquid crystal, light-emitting diode, fluorescence, phosphorescence, other suitable display media, or combinations thereof, but are not limited thereto. Display devices may be non-emissive or self-emissive. Antenna devices may be liquid crystal or non-liquid crystal antenna devices, and sensing devices may be sensing capacitive, light, heat, or ultrasonic sensors, but are not limited thereto. Splicing devices may include, for example, display splicing devices or antenna splicing devices, but are not limited thereto. It should be noted that electronic devices may be any arrangement or combination of the foregoing, but are not limited thereto. Furthermore, electronic devices may be bendable or flexible. It should be noted that the electronic device can be any of the aforementioned arrangements and combinations, but is not limited thereto. Furthermore, the electronic device can be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device can have peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, or splicing devices.

[0061] It should be understood that the features described below can be replaced, recombined, or mixed in multiple different embodiments to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0062] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that such terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of this disclosure.

[0063] Furthermore, the term "adjacent" in the specification and claims is used to describe objects that are close to each other, and there may be contact or no contact between adjacent objects.

[0064] Furthermore, descriptions such as "when..." or "...when" in this disclosure indicate states such as "at present, before, or after," and are not limited to simultaneous occurrences; this is stated in advance. Descriptions such as "set on..." in this disclosure indicate the corresponding positional relationship between two elements, and do not limit whether the two elements are in contact, unless specifically limited; this is stated in advance. Moreover, when this disclosure describes multiple functions, the use of the word "or" between functions indicates that the functions can exist independently, but does not preclude the possibility of multiple functions existing simultaneously.

[0065] For ease of explanation, the following description will use the electronic device of this disclosure as an exposure device, a printing device, or a 3D printing device as an example, but the electronic device of this disclosure is not limited thereto.

[0066] Figure 1 This is a schematic diagram of an electronic device 1 according to an embodiment of the present disclosure. (As shown...) Figure 1 As shown, electronic device 1 may include n scan lines G[1]~G[n] and m data lines D[1]~D[m], where n and m are positive integers greater than 1. The N scan lines G[1]~G[n] may extend along a first direction X, and the m data lines D[1]~D[m] may extend along a second direction Y. The scan lines G[1]~G[n] and the data lines D[1]~D[m] may be arranged alternately to define multiple array units P (one array unit P can be regarded as one pixel), and multiple array units P can form an array. The array formed by the array unit P can contain n columns row[1]~row[n] and m rows col[1]~col[m]. The n columns row[1]~row[n] can be arranged sequentially along the second direction Y, where each column row[1]~row[n] can contain m array units P. The m rows col[1]~col[m] can be arranged sequentially along the first direction X, where each row col[1]~col[m] can contain n array units P, and is not limited to this.

[0067] In one embodiment, each array unit P may include transistor T1, transistor T2, capacitor Ca1, and power consumption device 10. Transistor T1 may include a first terminal a1, a second terminal a2, and a control terminal a3. Transistor T2 may include a first terminal b1, a second terminal b2, and a control terminal b3. The first terminal b1 of transistor T2 may be electrically connected to the power consumption device 10, the second terminal b2 of transistor T2 may be electrically connected to a signal source 20 to receive a first signal V1 provided by the signal source 20, and the control terminal b3 of transistor T2 may be electrically connected to the second terminal a2 of transistor T1 and capacitor Ca1. The first terminal a1 of transistor T1 may be electrically connected to one of the data lines D[1]~D[m], and the control terminal a3 of transistor T1 may be electrically connected to one of the scan lines G[1]~G[n].

[0068] Transistor T1 or transistor T2 can be used as a switching element. In one embodiment, transistor T1 or transistor T2 may be an N-type MOSFET (NMOS), a P-type MOSFET (PMOS), a bipolar junction transistor (BJT), or other types of transistors, and is not limited thereto. For ease of explanation, Figure 1 The transistors T1 and T2 in the example are based on an NMOS structure.

[0069] In one embodiment, the power-consuming device 10 may be, for example, an electrode, a light-emitting device, a heat-generating device, a sensing device, a touch device, or a display device, or other devices that consume power, and is not limited thereto. In one embodiment, the power-consuming device 10 may receive energy via transistor T2 and use that energy for power consumption. For example, the power-consuming device 10 may convert the received energy (e.g., at least a portion of the energy of the first signal V1) into heat energy, light energy, or a display image, thereby performing power consumption operations, and is not limited thereto.

[0070] In one embodiment, the signal source 20 may be, for example, various power supply devices, such as voltage sources or current sources, and is not limited thereto. In one embodiment, the signal source 20 may be, for example, a power source disposed outside the electronic device 1, and is not limited thereto. The signal source 20 may be electrically connected to the second terminal b2 of the transistor T2 in each array unit P, thereby providing a first signal V1 to each array unit P. The voltage value of the first signal V1 may be adjusted by the signal source 20 itself or by a control circuit connected to the signal source 20, and is not limited thereto.

[0071] In one embodiment, scan lines G[1]~G[n] can be electrically connected to the same or different scan drivers (not shown), wherein the scan drivers can be used to provide scan signals SS(1)~SS(n). For example, in row[1], the control terminal a3 of transistor T1 in each array cell P can receive scan signal SS(1) through scan line G[1], and in row[2], the control terminal a3 of transistor T1 in each array cell P can receive scan signal SS(2) through scan line G[2], and so on. Scan signals SS(1)~SS(n) can be used to turn transistor T1 on or off.

[0072] In one embodiment, data lines D[1] to D[m] can be electrically connected to the same or different data drivers (not shown), wherein the data drivers can be used to provide data signals DS(1) to DS(m). For example, in row col[1], the first terminal a1 of the transistor T1 of each array unit P can receive the data signal DS(1) through data line D[1], and in row col[2], the first terminal a1 of the transistor T1 of each array unit P can receive the data signal DS(2) through data line D[2], and so on. Furthermore, in one embodiment, the control terminal b3 of the transistor T2 of each array unit P can receive at least a portion of the energy of the data signals DS(1) to DS(m) via the transistor T1. The voltage value of the first signal V1 when it is transmitted to the power consumption device 10 after passing through the transistor T2 may be affected by the magnitude of the voltage value received by the control terminal b3. Therefore, it can be considered that the amount of power consumed by the power consumption device 10 is determined according to the data signals DS(1) to DS(m) received by the control terminal b3 of the transistor T2, and is not limited thereto.

[0073] Next, the driving process of each component in electronic device 1 will be explained. Figure 2A This corresponds to an embodiment of the present disclosure. Figure 1 The example shows the timing diagrams of the scan signals SS(1)~SS(N), data signals DS(1)~DS(m), and the first signal V1. Please also refer to... Figure 1 . Figure 2A Can be used to illustrate in Figure 1 In the illustration, the changes of the first signal V1, data signals DS(1)~DS(m) and scan signals SS(1)~SS(n) in at least one time frame Frame1 are shown. The "time frame Frame1" can be regarded as the time when the electronic device 1 performs a complete data update, but is not limited to this.

[0074] like Figure 2A As shown, time frame Frame1 may contain a write cycle P1 and an output cycle P0, where the output cycle P0 immediately follows the write cycle P1. The next time frame Frame2 may immediately follow the output cycle P0 of time frame Frame1, where time frame Frame2 may contain a write cycle P2 and an output cycle (not shown). Accordingly, the output cycle P0 of time frame Frame1 may be located between the write cycle P1 of time frame Frame1 and the write cycle P2 of time frame Frame2.

[0075] Please also refer to Figure 1 and Figure 2AIn one embodiment, during the write cycle P1 of the time frame Frame1, the scan signals SS(1) to SS(n) received by each column row[1] to row[n] can sequentially change from a low voltage level (e.g., labeled L) to a high voltage level (e.g., labeled H), and then sequentially change from a high voltage level to a low voltage level. During the write cycle P1, the data signals DS(1) to DS(m) received by each row col[1] to col[m] can synchronously change from a low voltage level (e.g., labeled L) to a high voltage level (e.g., labeled H), and then synchronously change from a high voltage level to a low voltage level, allowing sufficient charging time to fully charge the capacitor and improve data integrity. Furthermore, during the write cycle P1, the first signal V1 provided by the signal source 20 can maintain a low voltage level (e.g., labeled V1_L), and in one embodiment, the voltage value of the low voltage level V1_L of the first signal V1 can be, for example, zero, but is not limited thereto.

[0076] Further, in one embodiment, during the write cycle P1, columns row[1] to row[n] can sequentially receive scan signals SS(1) to SS(n), and the transistor T1 of the array unit P in each column row[1] to row[n] can receive its corresponding data signal DS(1) to DS(m). In one embodiment, during the write cycle P1, since the first signal V1 is maintained at a low voltage level V1_L, the power consumption device 10 does not receive the energy of the first signal V1 through the transistor T2. The data signals DS(1) to DS(m) received by each transistor T1 are stored in the capacitor Ca1 electrically connected to it. At this time, since the power consumption device 10 cannot obtain enough energy through the transistor T2, the power consumption device 10 will not perform power consumption operations, such as light emission, heat generation, or display screen, but not limited to these. Furthermore, in one embodiment, when all scan signals SS(1)~SS(n) have changed from low voltage level to high voltage level and then from high voltage level back to low voltage level, the energy stored in capacitor Ca1 in array unit P of all columns row[1]~row[n] can reach a threshold, and transistor T2 of array unit P of all columns row[1]~row[n] has been turned on. At this time, the operation of electronic device 1 can enter the output cycle P0, and the first signal V1 can change from low voltage level V1_L to high voltage level V1_H.

[0077] In one embodiment, during the output cycle P0, the scan signals SS(1)~SS(n) can be at a low voltage level, the data signals DS(1)~DS(m) can be at a low voltage level, the transistor T1 of each array unit P of row[1]~row[n] can be turned off, and the first signal V1 can be at a high voltage level V1_H. At this time, for each array unit P, the control terminal b3 of transistor T2 can receive the data signals DS(1)~DS(m) stored in capacitor Ca1. Therefore, transistor T2 can be turned on, and at least a portion of the energy of the first signal V1 can be transmitted to the power consumption device 10 via transistor T2. Therefore, the power consumption device 10 can use the received energy to perform power consumption operations. The magnitude of the energy (e.g., the voltage value of the first signal V1 after passing through transistor T2) can be determined according to the data signals DS(1)~DS(m) received by the control terminal b3 of transistor T2, and is not limited thereto.

[0078] In one embodiment, during the output period P0, the scan signals SS(1) to SS(n) may be at a low voltage level, and their voltage values ​​may be, for example, zero, but are not limited thereto. In one embodiment, during the output period P0, the data signals DS(1) to DS(m) may be at a low voltage level, and their voltage values ​​may be, for example, zero, but are not limited thereto.

[0079] Therefore, it can be seen that during the write cycle P1, the power consumption device 10 of each array unit P does not perform power consumption operations. Thus, this disclosure can improve the problem of uneven overall data updates caused by the influence of other array units P that have already performed power consumption on array units P that have not yet performed power consumption. Alternatively, during the output cycle P0, the transistor T2 of each array unit P can be synchronously turned on to transmit at least a portion of the energy of the first signal V1 to the power consumption device 10. Therefore, the power consumption devices 10 of each array unit P can perform power consumption operations simultaneously, thereby achieving delay-free overall data updates. Therefore, this disclosure can address the deficiencies of the prior art, and is not limited thereto.

[0080] Figure 2B This corresponds to another embodiment of the present disclosure. Figure 1 The example shows the timing diagrams of the scan signals SS(1)~SS(N), data signals DS(1)~DS(m), and the first signal V1. Please also refer to... Figure 1 and Figure 2A . Figure 2B The timing of the example scan signals SS(1)~SS(N) and the first signal V1 is roughly applicable. Figure 2A The example is not repeated here. The following mainly focuses on the timing of the data signals DS(1) to DS(m).

[0081] like Figure 2BAs shown, in the write cycle P1 of time frame Frame1, the data signals DS(1)~DS(m) can sequentially change from low voltage level (L) to high voltage level (H) and then sequentially change from high voltage level to low voltage level during the period when the corresponding scan signals SS(1)~SS(n) are at high voltage level (H). This reduces the probability of data signals coupling with each other. Under this design, similar to Figure 2A For example, each power-consuming device 10 may not perform energy consumption operations during the write cycle P1. Alternatively, each power-consuming device 10 may perform power consumption operations simultaneously during the output cycle P0.

[0082] Please refer to it again. Figure 2A and 2B In one embodiment, when the scan signals SS(1)~SS(n) and / or the data signals DS(1)~DS(m) transition from a low voltage level to a high voltage level, there may be a voltage rise time, during which the scan signals SS(1)~SS(n) and / or the data signals DS(1)~DS(m) may gradually rise from a low voltage level to a high voltage level. Furthermore, when the scan signals SS(1)~SS(n) and / or the data signals DS(1)~DS(m) transition from a high voltage level to a low voltage level, there may be a voltage fall time, during which the scan signals SS(1)~SS(n) and / or the data signals DS(1)~DS(m) may gradually fall from a high voltage level to a low voltage level.

[0083] Furthermore, in one embodiment, during the write cycle P1, the operation of the electronic device 1 will only enter the output cycle P0 when the scan signal SS(n) and / or the data signal DS(m) reach a first preset condition during the voltage drop period. The first preset condition is that the scan signal SS(n) and / or the data signal DS(m) have dropped to more than 90% of the high voltage level (voltage value ≤ 10% of the high voltage level), but is not limited to this. Additionally, in one embodiment, during the output cycle P0, the operation of the electronic device 1 will only enter the write cycle P2 of the next time frame frame 2 when the voltage rise period of the scan signal SS(n) and / or the data signal DS(m) reaches a second preset condition. The second preset condition is that the voltage value of the scan signal SS(n) and / or the data signal DS(m) has risen from a low voltage level to more than 90% of the high voltage level (voltage value ≥ 90% of the high voltage level), but is not limited to this.

[0084] In addition, according to Figure 2A and Figure 2B , Figure 1An array unit P of the electronic device 1 can be operated through an electronic device operation method according to an embodiment of the present disclosure, wherein the electronic device operation method may include the following steps:

[0085] Step A1: Provide transistor T2, which includes a first terminal b1 and a second terminal b2;

[0086] Step A2: Provide a power consumption device 10, which is electrically connected to the first terminal b1 of transistor T2;

[0087] Step A3: Provide signal source 20, electrically connect it to the second terminal b2 of transistor T2;

[0088] Step A4: In time frame Frame1 with write cycle P1 and output cycle P0, the signal source 20 provides a low voltage level V1_L during write cycle P1; and

[0089] Step A5: Make signal source 20 provide a high voltage level V1_H during output cycle P0.

[0090] In addition, in one embodiment, the electronic device operation method may further include step A6: providing a scan signal (e.g., SS(1)), wherein the voltage value of the scan signal (e.g., SS(1)) is zero at the voltage level of the output period P0. In one embodiment, the electronic device operation method may further include step A7: providing a data signal (e.g., DS(1)), wherein the voltage value of the data signal (e.g., DS(1)) is zero at the voltage level of the output period P0.

[0091] The order of steps A1 to A7 is not limited, as long as it is reasonable and feasible.

[0092] In addition, although Figure 1 The transistors T1 and T2 in the example are NMOS structures, but this disclosure may also have other implementations. For example, transistors T1 and T2 may be PMOS structures. In this case, transistors T1 and T2 can be turned on when the control terminals a3 and b3 receive a low voltage and turned off when the control terminals a3 and b3 receive a high voltage, and are not limited to this.

[0093] therefore, Figures 1 to 2B The example is already understandable.

[0094] The electronic device 1 disclosed herein also has different implementations. Figure 3 This is a schematic diagram of electronic device 1 according to another embodiment of the present disclosure. Figure 4A and Figure 4B This corresponds to an embodiment of the present disclosure. Figure 3 The example shows the timing diagrams for the scan signals SS(1)~SS(N), data signals DS(1)~DS(m), control signal EM, and high voltage level signal VDD. Please also refer to the following: Figures 1 to 2B For ease of explanation, Figure 3 This example uses the circuit structure of an array unit P as an illustration, and those skilled in the art can further explain it based on... Figure 1 and Figure 3 To infer multiple Figure 3 The way in which array elements P are arranged into an array.

[0095] like Figure 3 As shown, array unit P may include transistor T1, transistor T2, capacitor Ca1, and power consumption device 10, and array unit P may also include transistor T3. Transistor T2 may be electrically connected to a signal source 60. Transistor T3 may be electrically connected to a signal source 30. Transistor T3 has a first terminal c1, a second terminal c2, and a control terminal c3. Transistor T3 may have the same structure as transistors T1 and T2, for example, all of them may be NMOS structures, but is not limited thereto.

[0096] In one embodiment, the first terminal c1 of transistor T3 can be electrically connected to the first terminal b1 of transistor T2, the second terminal c2 of transistor T3 can be electrically connected to the power consumption device 10, and the control terminal c3 of transistor T3 can be electrically connected to the signal source 30, wherein the signal source 30 can be used to provide a control signal EM, and the control signal EM can be used to control transistor T3 to turn on or off. In addition, the second terminal b2 of transistor T2 can be electrically connected to the signal source 60, wherein the signal source 60 can be used to provide a high voltage level signal VDD, and the control terminal b3 of transistor T2 can be electrically connected to capacitor Ca1 and the second terminal a2 of transistor T1. The first terminal a1 of transistor T1 can be electrically connected to one of the data lines D[1]~D[m] (e.g., D[1]) to receive one of the data signals DS(1)~DS(m) (e.g., DS(1)), and the control terminal a3 of transistor T1 can be electrically connected to one of the scan lines G[1]~G[n] (e.g., G[1]) to receive one of the scan signals SS(1)~SS(m) (e.g., SS(1)).

[0097] like Figure 1 , Figure 3 and Figure 4AAs shown, in one embodiment, during the write cycle P1 of time frame Frame1, the scan signals SS(1)~SS(n) sequentially change from a low voltage level (e.g., marked L) to a high voltage level (e.g., marked H), and the data signals DS(1)~DS(m) synchronously change from a low voltage level (e.g., marked L) to a high voltage level (e.g., marked H). The transistors T1 in rows[1]~row[n] can be turned on sequentially and each receives the corresponding data signals DS(1)~DS(m). In one embodiment, during the write cycle P1, the signal source 60 provides a high voltage level signal VDD, and the control signal EM provided by the signal source 30 is a low voltage level EM_L. Therefore, the transistor T3 is turned off, and the data signals DS(1)~DS(m) received by each transistor T1 are stored in the capacitor Ca1 electrically connected to it. The power consumption device 10 does not receive energy. Therefore, during the write cycle P1, the power consumption device 10 does not perform power consumption operations.

[0098] Next, in one embodiment, during the output period P0 of time frame Frame1, the scan signals SS(1)~SS(n) are at a low voltage level, the data signals DS(1)~DS(m) are at a low voltage level, the signal source 60 continuously provides a high voltage level signal VDD, and the control signal EM provided by the signal source 30 changes to a high voltage level EM_H. At this time, for each array unit P, transistor T1 can be turned off, the control terminal b3 of transistor T2 receives the data signals DS(1)~DS(m) stored in capacitor Ca1 and turns on, and transistor T3 turns on because the control signal EM is at a high voltage level EM_H. Thus, at least a portion of the energy of the high voltage level signal VDD can be transmitted to the power consumption device 10 through each transistor T2 and transistor T3, so the power consumption device 10 can perform power consumption operation. In one embodiment, the amount of power consumed by the power consumption device 10 (i.e., the amount of energy received) can be adjusted by adjusting the voltage values ​​of the control signal EM and / or the data signals DS(1)~DS(m), and is not limited thereto.

[0099] therefore, Figure 3 and 4A Examples may have the same as Figures 1 to 2B Similar effects can solve problems with existing technologies.

[0100] Figure 4B The timing of the example scan signals SS(1)~SS(n), control signal EM, and high voltage level signal VDD is roughly applicable. Figure 4A The example is explained, and Figure 4BIn the example, during the period when the corresponding scan signals SS(1) to SS(n) in the write cycle P1 transition to a high voltage level, the data signals DS(1) to DS(m) sequentially transition from a low voltage level to a high voltage level, and then sequentially transition from a high voltage level to a low voltage level again. Therefore, Figure 4B Examples may have the same as Figure 4A Similar effects can be achieved by addressing the problems of existing technologies.

[0101] according to Figure 4A and 4B As can be seen from the example, Figure 3 An array unit P in the electronic device 1 can be operated through an electronic device operation method according to another embodiment of the present disclosure, wherein the electronic device operation method may include the following steps:

[0102] Step B1: Provide transistor T3, which includes a first terminal c1, a second terminal c2, and a control terminal c3;

[0103] Step B2: Provide a power consumption device 10, which is electrically connected to the second terminal C2 of transistor T3;

[0104] Step B3: Provide signal source 30 and electrically connect it to the control terminal c3 of transistor T3;

[0105] Step B4: In time frame Frame1, which has write cycle P1 and count cycle P0, the signal source 30 provides a low voltage level EM_L during write cycle P1; and

[0106] Step B5: Enable signal source 30 to provide a high voltage level EM_H during output cycle P0.

[0107] Furthermore, in one embodiment, the electronic device operation method may further include step B6: providing a scan signal (e.g., SS(1)), wherein the voltage value of the scan signal (e.g., SS(1)) is zero during the voltage level of the output cycle P0. In one embodiment, the electronic device operation method may further include step B7: providing a data signal (e.g., DS(1)), wherein the voltage value of the data signal (e.g., DS(1)) is zero during the voltage level of the output cycle P0. In one embodiment, the electronic device operation method may further include step B8: continuously providing a high voltage level signal VDD to the second terminal b2 of transistor T2 by signal source 20.

[0108] The order of steps B1 to B7 above is not limited, as long as it is reasonable and feasible.

[0109] Furthermore, as long as it is reasonable and feasible, Figure 4A and Figure 4B The timing details of each signal in the example are applicable. Figure 2A and Figure 2B The explanation in the example.

[0110] therefore, Figures 3 to 4B The example is now understandable.

[0111] The electronic device 1 disclosed herein also has different implementations. Figure 5 This is a schematic diagram of electronic device 1 according to another embodiment of the present disclosure. Figure 6A and Figure 6B This corresponds to an embodiment of the present disclosure. Figure 5 The example shows the timing diagrams of the scan signals SS(1)~SS(N), data signals DS(1)~DS(m), and the first signal V1. Please also refer to... Figures 1 to 4B For ease of explanation, Figure 5 This example uses the circuit structure of an array unit P as an illustration, and those skilled in the art can further explain it based on... Figure 1 and Figure 5 To infer multiple Figure 5 The way in which array elements P are arranged into an array.

[0112] like Figure 5 As shown, array unit P may include transistor T1, transistor T2, capacitor Ca1, and power consumption device 10, and may also include transistor T3 and capacitor Ca2. Transistor T3 has a first terminal c1, a second terminal c2, and a control terminal c3. Signal source 20 is used to provide a first signal V1. Furthermore, transistor T3 may have different structures from transistors T1 and T2; for example, transistor T3 may be a PMOS structure, while transistors T1 and T2 may be NMOS structures, and the configuration is not limited thereto.

[0113] In one embodiment, the first terminal b1 of transistor T2 can be electrically connected to power consumption device 10, and the second terminal b2 of transistor T2 can be electrically connected to signal source 20 to receive the first signal V1 provided by signal source 20. The control terminal b3 of transistor T2 can be electrically connected to capacitor Ca2 and the second terminal c2 of transistor T3. The first terminal c1 of transistor T3 can be electrically connected to capacitor Ca1 and the second terminal a2 of transistor T1, and the control terminal c3 of transistor T3 can be electrically connected to signal source 20 to receive the first signal V1. The first terminal a1 of transistor T1 can be electrically connected to one of the data lines D[1]~D[m] (e.g., D[1]) to receive one of the data signals DS(1)~DS(m) (e.g., DS(1)). The control terminal a3 of transistor T1 can be electrically connected to one of the scan lines G[1]~G[n] (e.g., G[1]) to receive one of the scan signals SS(1)~SS(m) (e.g., SS(1)).

[0114] like Figure 1 , Figure 5 and Figure 6AAs shown, in one embodiment, during the write cycle P1 of time frame Frame1, the scan signals SS(1)~SS(n) sequentially change from a low voltage level (e.g., marked L) to a high voltage level (marked H), and the data signals DS(1)~DS(m) synchronously change from a low voltage level (e.g., marked L) to a high voltage level (marked H). The transistors T1 in rows[1]~row[n] will turn on sequentially and each receive the data signals DS(1)~DS(m) corresponding to time frame Frame1. In addition, during the write cycle P1, the first signal V1 provided by the signal source 20 is a high voltage level V1_H. The control terminal c3 of the PMOS transistor T3 receives the high voltage level V1_H, so the transistor T3 is turned off. At this time, the data signals DS(1)~DS(m) corresponding to time frame Frame1 received by the transistor T1 will be stored in the capacitor Ca1. Furthermore, since transistor T3 is turned off, transistor T2 will not receive the data signals DS(1)~DS(m) corresponding to time frame Frame1. Therefore, the power consumption device 10 will not perform the power consumption operation corresponding to time frame Frame1 during the write cycle P1 of time frame Frame1.

[0115] In one embodiment, during the output period P0 of time frame Frame 1, the scan signals SS(1)~SS(n) are at a low voltage level, the data signals DS(1)~DS(m) are at a low voltage level, and the first signal V1 changes from a high voltage level V1_H to a low voltage level V1_L. At this time, for each array unit P, the PMOS transistor T3 can be turned on, and at least a portion of the energy of the data signals DS(1)~DS(m) corresponding to time frame Frame 1 stored in capacitor Ca1 can be stored in capacitor Ca2 via transistor T3. Furthermore, since the first signal V1 is at a low voltage level V1_L, the power consumption device 10 cannot receive the energy of the first signal V1 through transistor T2, so the power consumption device 10 will not perform power consumption operation during the output period P0 of time frame Frame 1.

[0116] In one embodiment, during the write cycle P2 of the next time frame Frame2, the scan signals SS(1)~SS(n) sequentially change from low voltage to high voltage, and the data signals DS(1)~DS(m) synchronously change from low voltage to high voltage. Therefore, the transistors T1 in rows[1]~row[n] will turn on sequentially and receive the data signals DS(1)~DS(m) of the corresponding time frame Frame2. In addition, the first signal V1 provided by the signal source 20 changes from low voltage V1_L to high voltage V1_H again. At this time, for each array unit P, the PMOS transistor T3 is turned off. The data signals DS(1)~DS(m) of the corresponding time frame Frame2 received by the transistor T1 will be stored in the capacitor Ca1. The control terminal b3 of the transistor T2 can receive at least a part of the energy of the data DS(1)~DS(m) of the corresponding time frame Frame1 stored in the capacitor Ca2. Therefore, the transistor T2 can be turned on, and at least a part of the energy of the first signal V1 can enter the power consumption device 10 through the transistor T2. In one embodiment, the amount of power consumed by the power consuming device 10 can be determined based on the magnitude of the data signals DS(1)~DS(m) of the corresponding time frame Frame1 received by the transistor T2, and is not limited thereto. Therefore, during the write cycle P2 of the time frame Frame2, the power consuming device 10 can perform the power consumption operation corresponding to the time frame Frame1.

[0117] In one embodiment, when transistor T3 is turned on, the amount of charge received by capacitors Ca1 and Ca2 can reach a balance (e.g., be equal), but is not limited thereto. In one embodiment, when the capacitance value of capacitor Ca1 is greater than or significantly greater than the capacitance value of capacitor Ca2 (e.g., differing by at least 2, 5, or 10 times, but not limited thereto), the data level (e.g., voltage value) at which capacitors Ca1 and Ca2 achieve charge balance can be adjusted by adjusting the capacitance value of capacitor Ca1, but is not limited thereto. In one embodiment, the capacitance value of capacitor Ca1 can also be equal to the capacitance value of capacitor Ca2, but is not limited thereto.

[0118] Therefore, each array unit P of electronic device 1 can synchronously update the data of the corresponding time frame Frame1 during the write cycle P2 of time frame Frame2. Figure 5 and 6A Examples of this technology can solve the problem of uneven data updates in existing technologies, or can achieve delay-free overall data updates. Alternatively, while performing overall data updates for the corresponding time frame Frame1, electronic device 1 can store the data signals DS(1)~DS(m) for the next time frame Frame2 into the capacitors Ca1 of each array unit P, which can improve the operating efficiency of electronic device 1, and is not limited thereto.

[0119] Please refer to the following: Figure 6B . Figure 6B The timing of the example scan signals SS(1)~SS(n) and the first signal V1 is roughly applicable. Figure 6A The example is explained, and Figure 6B During the writing cycle P1, when the scan signals SS(1) to SS(n) transition to a high voltage level, the data signals DS(1) to DS(m) can sequentially transition from a low voltage level to a high voltage level, and then sequentially transition from a high voltage level to a low voltage level again. Under this design, electronic device 1 can achieve... Figure 6A Examples of similar or identical effects can solve problems in existing technologies.

[0120] according to Figure 6A and Figure 6B Example, Figure 5 Each array unit P in the electronic device 1 can be operated through an electronic device operation method according to an embodiment of the present disclosure, wherein the electronic device operation method may include the following steps:

[0121] Step C1: Provide transistor T2, which includes a first terminal b1, a second terminal b2, and a control terminal b3;

[0122] Step C2: Provide a power consumption device 10, which is electrically connected to the first terminal b1 of transistor T2;

[0123] Step C3: Provide signal source 20, electrically connect it to the second terminal b2 of transistor T2, and electrically connect it to the control terminal c3 of transistor T3;

[0124] Step C4: In time frame Frame1 with write cycle P1 and output cycle P0, the signal source 20 provides a high voltage level V1_H during write cycle P1; and;

[0125] Step C5: Make signal source 20 provide a low voltage level V1_L during output cycle P0, and make signal source 20 provide a high voltage level V1_H during the write cycle P1 of the next time frame Frame2.

[0126] In addition, in one embodiment, the electronic device operation method may further include step C6: providing a scan signal (e.g., SS(1)), wherein the voltage value of the scan signal (e.g., SS(1)) is zero at the voltage level of the output period P0. In one embodiment, the electronic device operation method may further include step C7: providing a data signal (e.g., DS(1)), wherein the voltage value of the data signal (e.g., DS(1)) is zero at the voltage level of the output period P0.

[0127] The order of steps C1 to C7 is not limited, as long as it is reasonable and feasible.

[0128] Furthermore, as long as it is reasonable and feasible, Figure 6A and Figure 6B The detailed timing features of each signal in the example are applicable Figure 2A and Figure 2B Explanation of the example.

[0129] therefore, Figures 5 to 6B The example is now understandable.

[0130] The electronic device 1 disclosed herein also has different implementations. Figure 7 This is a schematic diagram of electronic device 1 according to another embodiment of the present disclosure. Figure 8A and Figure 8B This corresponds to an embodiment of the present disclosure. Figure 7 The timing diagrams for the scan signals SS(1)~SS(N), data signals DS(1)~DS(m), the first signal V1, and the second signal V2 are provided. Please also refer to the following: Figures 1 to 6B For ease of explanation, Figure 7 This example uses the circuit structure of an array unit P as an illustration, and those skilled in the art can further explain it based on... Figure 1 and Figure 7 To infer multiple Figure 7 The way array elements P are arranged into an array. Furthermore, Figure 7 The circuit structure of array cell P in the example is roughly applicable. Figure 5 As illustrated in the example, the following explanation will focus on the differences.

[0131] like Figure 7 As shown, each array unit P may include transistors T1, T2, and T3, capacitors Ca1 and Ca2, and a power consumption device 10, and may also include an inverter 40. The inverter 40 is electrically connected to a signal source 50. The inverter 40 has an input node n1 and an output node n2. In one embodiment, the inverter 40 may include transistors T4 and T5. Transistor T4 has a first terminal d1, a second terminal d2, and a control terminal d3, and transistor T5 has a first terminal e1, a second terminal e2, and a control terminal e3. Transistors T4 and T5 may have different structures; for example, transistor T4 may be a PMOS structure, and transistor T5 may be an NMOS structure, but are not limited thereto. Furthermore, signal source 20 can be used to provide a first signal V1, and signal source 50 can be used to provide a second signal V2. In one embodiment, the second signal V2 may be, for example, a high-voltage level signal VDD, but is not limited thereto.

[0132] In one embodiment, the first terminal b1 of transistor T2 is electrically connected to the power consumption device 10, and the second terminal b2 of transistor T2 is electrically connected to the signal source 20 to receive the first signal V1. The control terminal b3 of transistor T2 is electrically connected to capacitor Ca2 and the output node n2 of inverter 40. The input node n1 of inverter 40 is electrically connected to the second terminal c2 of transistor T3. The first terminal c1 of transistor T3 is electrically connected to capacitor Ca1 and the second terminal a2 of transistor T1, and the control terminal c3 of transistor T3 is electrically connected to the signal source 20 to receive the first signal V1. The first terminal a1 of transistor T1 can be electrically connected to one of the data lines D[1]~D[m] (e.g., D[1]) to receive one of the data signals DS(1)~DS(m) (e.g., DS(1)). The control terminal a3 of transistor T1 can be electrically connected to one of the scan lines G[1]~G[n] (e.g., G[1]) to receive one of the scan signals SS(1)~SS(m) (e.g., SS(1)). In addition, in one embodiment, the first terminal d1 of transistor T4 and the second terminal e2 of transistor T5 of inverter 40 can be electrically connected to output node n2. The second terminal d2 of transistor T4 can be electrically connected to signal source 50 to receive the second signal V2. The control terminal d3 of transistor T4 and the control terminal e3 of transistor T5 can be electrically connected to input node n1, and the first terminal e1 of transistor T5 can be electrically connected to a low voltage level or grounded (e.g., the voltage value can be zero).

[0133] like Figure 8A As shown, during the write cycle P1 of time frame Frame1, the scan signals SS(1)~SS(n) sequentially change from a low voltage level (labeled L) to a high voltage level (labeled H), and the data signals DS(1)~DS(m) synchronously change from a low voltage level (labeled L) to a high voltage level (labeled H). The first signal V1 is a high voltage level V1_H, and the second signal V2 is a high voltage level V2_H. At this time, for each array unit P, the PMOS transistor T3 is turned off, and the data signals DS(1)~DS(m) received by transistor T1 can be stored in capacitor Ca1. During the write cycle P1, the power consumption device 10 does not perform the power consumption operation corresponding to time frame Frame1.

[0134] During the output period P0 of time frame Frame1, the scan signals SS(1)~SS(n) are at low voltage, the data signals DS(1)~DS(m) are at low voltage, the first signal V1 is at low voltage V1_L, and the second signal V2 is at high voltage V2_H. At this time, for each array unit P, the PMOS transistor T3 is turned on, and at least a portion of the energy of the corresponding data signals DS(1)~DS(m) stored in capacitor Ca1 can be transferred to the input node n1 of inverter 40. The output node n2 of inverter 40 can output a high voltage (e.g., the second signal V2_H at the second terminal d2 of transistor T4) or a low voltage (e.g., the low voltage or zero voltage at the first terminal e1 of transistor T5) according to the magnitude of the data signals DS(1)~DS(m) received by the input node n1. Furthermore, since the first signal V1 is a low voltage level V1_L, the low or high voltage level output by the output node n2 of the inverter 40 can be stored in the capacitor Ca2, and the power consumption device 10 cannot obtain energy through the transistor T2 to perform the power consumption operation corresponding to the time frame Frame1. Therefore, during the output cycle P0, the power consumption device 10 will not perform the power consumption operation corresponding to the time frame Frame1.

[0135] In the write cycle P2 of the next time frame Frame2, the scan signals SS(1)~SS(n) are at high voltage, the data signals DS(1)~DS(m) are at high voltage, the first signal V1 is at high voltage V1_H, and the second signal V2 is at high voltage V2_H. At this time, for each array unit P, transistor T1 turns on again and receives the data signals DS(1)~DS(m) of the corresponding time frame Frame2, while transistor T3 turns off at the same time. Therefore, the data signals DS(1)~DS(m) of the corresponding time frame Frame2 received by transistor T1 will be stored in capacitor Ca1. In addition, the control terminal b3 of transistor T2 can receive the data stored in capacitor Ca2 in the output cycle P0. Therefore, transistor T2 turns on, and at least a portion of the energy of the first signal V1 (e.g., V1_H) can enter the power consumption device 10 through transistor T2, so that the power consumption device 10 performs the power consumption operation of the corresponding time frame Frame1. In one embodiment, the amount of power consumed by the power-consuming device 10 can be determined based on the data level (e.g., voltage value) received by the control terminal b3 of transistor T2, and is not limited thereto.

[0136] Therefore, each array unit P of electronic device 1 can synchronously update the data of the corresponding time frame Frame1 during the write cycle P2 of time frame Frame2. Figure 7 and 8AThe example can solve the problem of uneven data updates in the prior art, or can achieve a delay-free overall data update. Alternatively, while performing an overall data update of the corresponding time frame Frame1, the electronic device 1 can store the data signals DS(1)~DS(m) of the next time frame Frame2 into the capacitors Ca1 of each array unit P, thus improving the operating efficiency of the electronic device 1, and is not limited thereto.

[0137] also, Figure 8B The example is generally applicable. Figure 8A The difference in the example is that during the write cycle P1, the data signals DS(1)~DS(m) sequentially transition from low voltage to high voltage and then back to low voltage during the transition of the scan signals SS(1)~SS(n) to a high voltage level. With this design, electronic device 1 can achieve the same performance as... Figure 8A Examples of the same or similar effects.

[0138] according to Figure 8A and Figure 8B Example, Figure 7 Each array unit P in the electronic device 1 can be operated through an electronic device operation method according to an embodiment of the present disclosure, wherein the electronic device operation method may include the following steps:

[0139] Step D1: Provide transistor T2, which includes a first terminal b1, a second terminal b2, and a control terminal b3;

[0140] Step D2: Provide a power consumption device 10, which is electrically connected to the first terminal b1 of transistor T2;

[0141] Step D3: Provide signal source 20, electrically connect it to the second terminal b2 of transistor T2, and electrically connect it to the control terminal c3 of transistor T3;

[0142] Step D4: In time frame Frame1 with write cycle P1 and output cycle P0, the signal source 20 provides a high voltage level V1_H during write cycle P1; and;

[0143] Step D5: Make signal source 20 provide a low voltage level V1_L during output cycle P0, and make signal source 20 provide a high voltage level V1_H during the write cycle P1 of the next time frame Frame2.

[0144] In addition, in one embodiment, the electronic device operation method may further include step D6: providing a scan signal (e.g., SS(1)), wherein the voltage value of the scan signal (e.g., SS(1)) is zero at the voltage level of the output period P0. In one embodiment, the electronic device operation method may further include step D7: providing a data signal (e.g., DS(1)), wherein the voltage value of the data signal (e.g., DS(1)) is zero at the voltage level of the output period P0.

[0145] The order of steps D1 to D7 is not limited, as long as it is reasonable and feasible.

[0146] therefore, Figures 7 to 8B The example is now understandable.

[0147] The electronic device 1 disclosed herein may also have different implementations. Figure 9 This is a schematic diagram of electronic device 1 according to another embodiment of the present disclosure. Figure 10A and Figure 10B This corresponds to an embodiment of the present disclosure. Figure 9 The timing diagrams for the scan signals SS(1)~SS(N), data signals DS(1)~DS(m), control signal EM, and high voltage level signal VDD are provided. Please also refer to the following: Figures 1 to 8B For ease of explanation, Figure 9 This example uses the circuit structure of an array unit P as an illustration, and those skilled in the art can further explain it based on... Figure 1 and Figure 9 To infer multiple Figure 9 The way in which array cells P form an array column.

[0148] like Figure 9 As shown, the array unit P may include transistors T1, T2, and T3, capacitor Ca1, and power consumption device 10, and may also include transistors T6, T7, and T8. Transistor T6 has a first terminal f1, a second terminal f2, and a control terminal f3. Transistor T7 has a first terminal g1, a second terminal g2, and a control terminal g3. Transistor T8 has a first terminal h1, a second terminal h2, and a control terminal h3.

[0149] In one embodiment, the first terminal a1 of transistor T1 can be electrically connected to one end of capacitor Ca1, the first terminal h1 of transistor T8, and the control terminal b3 of transistor T2. The second terminal a2 of transistor T1 can be electrically connected to the start signal Vinit, and the control terminal a3 of transistor T1 can be electrically connected to the scan line (e.g., G[n-1]). The other end of capacitor Ca1 can be electrically connected to the high voltage level signal VDD and the second terminal f2 of transistor T6. The first terminal b1 of transistor T2 can be electrically connected to the second terminal c2 of transistor T3 and the second terminal h2 of transistor T8. The second terminal b2 of transistor T2 can be electrically connected to the first terminal f1 of transistor T6 and the second terminal g2 of transistor T7. The first terminal c1 of transistor T3 can be electrically connected to the power consumption device 10, and the control terminals c3 of transistor T3 and f3 of transistor T6 can be electrically connected to the signal source 30 to receive the control signal EM provided by the signal source 30. The first terminal g1 of transistor T7 can be electrically connected to a data line (e.g., D[m]), and the control terminal g3 of transistor T7 and the control terminal h3 of transistor T8 can be electrically connected to a scan line (e.g., G[n]).

[0150] also, Figure 9 The transistors T1, T2, T3, T6, T7, and T8 in the example are based on a PMOS structure. Therefore, when the control terminals a3, b3, c3, f3, g3, or h3 of transistors T1, T2, T3, T6, T7, or T8 receive a high potential, transistors T1, T2, T3, T6, T7, or T8 will be turned off, and when the control terminals a3, b3, c3, f3, g3, or h3 of transistors T1, T2, T3, T6, T7, or T8 receive a low potential, transistors T1, T2, T3, T6, T7, or T8 will be turned on. It should be noted that the structure of transistors T1, T2, T3, T6, T7, and T8 in this disclosure is not limited to this.

[0151] like Figure 1 , Figure 9 and Figure 10A As shown, during the write cycle P1 of time frame Frame1, the scan signals SS(1)~SS(n) sequentially change from high voltage level (marked as H) to low voltage level (marked as L), and then sequentially change from low voltage level to high voltage level. The data signals DS(1)~DS(m) sequentially change from high voltage level (marked as H) to low voltage level (marked as L), and then sequentially change from low voltage level to high voltage level. The control signal EM is high voltage level EM_H. During the output cycle P0 of time frame Frame1, for each array unit P, the control signal EM can change from high voltage level EM_H to low voltage level EM_L. At this time, at least a portion of the energy of the high voltage level signal VDD provided by the signal source 20 can enter the power consumption device 10 through transistors T2 and T3.

[0152] In one embodiment, for an array cell P, during the first stage of the write cycle P1 of time frame Frame 1, when the scan signal SS(n-1) changes from a high voltage level (H) to a low voltage level (L), the PMOS transistor T1 can be turned on. At this time, the voltage levels of the first terminal a1 of transistor T1, the first terminal h1 of transistor T8, and / or the control terminal b3 of transistor T2 can be, for example, the voltage value of the start signal Vinit, and the energy stored in capacitor Ca1 can be converted into a first voltage value v01, which can be, for example, the difference between the voltage value of the high voltage level signal VDD and the voltage value of the start signal Vinit (e.g., v01 = VDD - Vinit), and is not limited thereto. This stage can be regarded as the initialization period of the data compensation process of array cell P.

[0153] Next, in the second stage of the write cycle P1 of time frame Frame1, for array cell P, when the scan signal SS(n) changes from a high voltage level (H) to a low voltage level (L), and the scan signal SS(n-1) can change from a low level (L) to a high level (H), transistors T7 and T8 can be turned on. The voltage level received by the control terminal b3 of transistor T2 can be increased to the second voltage value v02 by the influence of transistors T7 and T8. The second voltage value can be, for example, the voltage value of the data signal DS(m) and the gate threshold voltage V of transistor T2. t,T2 The difference in voltage values ​​(e.g., v02 = DS(m) - |V t,T2 |), and not limited to this. Furthermore, the energy stored in capacitor Ca1 at this time can be converted into a third voltage value v03, where the third voltage value v03 can be the difference between the voltage value of the high-voltage flat signal VDD and the second voltage value (for example, v03 = VDD - (DS(m) - |V t,T2 This stage can be considered as the programming period of the data compensation process for array unit P.

[0154] Next, during the output period P0 of time frame Frame 1, for the array cell P, the control signal EM can change from high level EM_H to low level EM_L, and the scan signal SS(n) can change from low level (L) to high level (H). At this time, transistor T3 can be turned on, so that at least a portion of the energy of the high level signal VDD provided by the signal source 20 can enter the power consumption device 10 through transistors T2 and T3. This stage can be regarded as the output period of the data compensation process of the array cell P. In one embodiment, the energy entering the power consumption device 10 can be, for example, a first current value I. device The first current value Idevice It can be expressed as the following formula:

[0155] I device =k(V G,T2 -|V t,T2 |) 2 =k(VDD-(DS(m)-|V t,T2 |)-|V t,T2 |) 2 =k(VDD-DS(m)) 2 ;

[0156] Where k is, for example, a compensation parameter, and can be expressed as follows:

[0157] ;

[0158] ;

[0159] in, The thickness of the oxide layer of transistor T3. Where is the dielectric constant of the oxide layer, μ is the electron mobility, W is the width of the channel region of transistor T3, and L is the length of the channel region. The oxide layer mentioned above is, for example, the gate insulating layer in the transistor, and its material may include inorganic materials, but this disclosure is not limited thereto.

[0160] Therefore, it can be seen that during the write cycle P1, the power consumption device 10 does not perform power consumption operations, while during the output cycle P0, the power consumption devices 10 of each array unit P simultaneously perform power consumption operations. Thus, with this design, the electronic device 1 can achieve the same or similar effects as the aforementioned example, solving the problems of the prior art.

[0161] also, Figure 10B The example is generally applicable. Figure 10A The difference in the example is that during the write cycle P1, the data signals DS(1)~DS(m) sequentially transition from a high voltage level to a low voltage level, and then sequentially transition from a low voltage level to a high voltage level again, during the period when the scan signals SS(1)~SS(n) transition to a low voltage level. With this design, electronic device 1 can achieve the same performance as... Figure 10A Examples of the same or similar effects.

[0162] according to Figure 10A and Figure 10B Example, Figure 9 Each array unit P in the electronic device 1 can be operated through an electronic device operation method according to an embodiment of the present disclosure, wherein the electronic device operation method may include the following steps:

[0163] Step E1: Provide transistor T3, which includes a first terminal c1, a second terminal c2, and a control terminal c3;

[0164] Step E2: Provide a power consumption device 10, which is electrically connected to the first terminal c1 of transistor T3;

[0165] Step E3: Provide signal source 30, electrically connecting the control terminal c3 of transistor T3 and the control terminal f3 of transistor T6;

[0166] Step E4: In time frame Frame1 with write cycle P1 and output cycle P0, the signal source 30 provides a high voltage level EM_H during write cycle P1; and;

[0167] Step E5: Enable signal source 30 to provide a low voltage level EM_L during output cycle P0.

[0168] In addition, in one embodiment, the electronic device operation method may further include step E6: providing a scan signal (e.g., SS(1)), wherein the voltage value of the scan signal (e.g., SS(1)) is not zero during the voltage level of the output cycle P0. In one embodiment, the electronic device operation method may further include step E7: providing a data signal (e.g., DS(1)), wherein the voltage value of the data signal (e.g., DS(1)) is not zero during the voltage level of the output cycle P0. In one embodiment, the electronic device operation method may further include step E8: continuously providing a high voltage level signal VDD to the second terminal f2 of transistor T6.

[0169] The order of steps E1 to E8 is not limited, as long as it is reasonable and feasible.

[0170] therefore, Figures 9 to 10B The example is now understandable.

[0171] In one embodiment, this disclosure can determine whether a product falls within the scope of protection of this disclosure by at least the presence or absence of components, component configuration, structural observation and / or operation of the disputed product, but is not limited thereto.

[0172] Details or features of the various embodiments disclosed herein may be freely combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0173] By using the electronic device operation method disclosed herein, the electronic device of this disclosure can reduce the problem of uneven overall data updates, or can achieve the effect of zero-delay overall data updates.

[0174] The above embodiments are merely illustrative examples for ease of explanation. The scope of the claims asserted in this disclosure should be determined by the claims of the patent application, and not limited to the above embodiments.

Claims

1. A method for operating an electronic device, characterized in that, Includes the following steps: A first transistor is provided, comprising one end and another end; Provide a power-consuming device electrically connected to one end of the first transistor; and Provide a signal source, electrically connected to the other end of the first transistor; In the time graph frame having a write cycle and an output cycle, the signal source provides a high voltage level during the output cycle and a low voltage level during the write cycle.

2. The electronic device operation method according to claim 1, characterized in that, The voltage value of the low voltage level is zero.

3. The method for operating an electronic device according to claim 1, characterized in that, The first transistor further includes another end, and the other end of the first transistor is electrically connected to the second transistor.

4. The method for operating an electronic device according to claim 1, characterized in that, It also includes the step of: providing a data signal, wherein the voltage value of the data signal is zero at the voltage level of the output cycle.

5. The method for operating an electronic device according to claim 1, characterized in that, It also includes the step of: providing a scan signal, wherein the voltage value of the scan signal is zero at the voltage level of the output cycle.

6. The method of operating an electronic device according to claim 1, characterized in that, The first transistor further includes another end, which is electrically connected to one end of the second transistor and a capacitor, the other end of the second transistor is electrically connected to one end of the third transistor and another capacitor, the other end of the third transistor is electrically connected to a data line, and the other end of the third transistor is electrically connected to a scan line.

7. The method of operating an electronic device according to claim 1, characterized in that, The first transistor also includes another end, which is electrically connected to a node of an inverter and a capacitor. The other node of the inverter is electrically connected to one end of a second transistor. The other end of the second transistor is electrically connected to one end of a third transistor and another capacitor. The other end of the third transistor is electrically connected to a data line. The other end of the second transistor is electrically connected to the signal source, and the other end of the third transistor is electrically connected to a scan line.

8. The method of operating an electronic device according to claim 1, characterized in that, The electronic device 1 further includes a plurality of columns, each of the plurality of columns including a plurality of array units, wherein each of the plurality of array units includes one of a plurality of first transistors and one of a plurality of power-consuming devices.

9. The method of operating an electronic device according to claim 8, characterized in that, The output cycle is followed by the write cycle, and each column receives a scan signal, with each column receiving a high voltage level during the write cycle.

10. A method for operating an electronic device, characterized in that, Includes the following steps: A first transistor is provided, comprising one end and another end; Provide a power-consuming device electrically connected to one end of the first transistor; and Provide a signal source, electrically connected to the other end of the first transistor; In the time frame that includes the write cycle and the output cycle, the signal source provides a low voltage level during the output cycle and a high voltage level during the write cycle.

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