Signal driving circuit and method and electronic equipment

Abstract

The invention relates to a signal driving circuit and method and electronic equipment. A signal driving circuit includes: a first driving branch configured to be powered by a high voltage; a second driving branch configured to be powered by a low voltage; and the selection control circuit is configured to select the first driving branch or the second driving branch based on the amplitude of a driving signal and is used for performing power amplification processing on the driving signal.

Description

Technical Field

[0001] This invention relates to a signal driving circuit and a signal driving method, which have improved driving efficiency, thereby saving energy consumption. The invention also relates to electronic devices including this signal driving circuit. Background Technology

[0002] As portable electronic devices offer increasingly rich functionality, their power consumption inevitably rises, and battery life faces a serious challenge due to limitations in battery power. Therefore, how to reduce power consumption and save power to extend battery life while ensuring the normal functioning of electronic devices is a technical problem that needs to be solved. Summary of the Invention

[0003] In view of the above problems, the present invention is proposed.

[0004] One aspect of the present invention provides a signal driving circuit, comprising: a first driving branch configured to be powered by a high voltage; a second driving branch configured to be powered by a low voltage; and a selection control circuit configured to select the first driving branch or the second driving branch based on the amplitude of a driving signal, for performing power amplification processing on the driving signal.

[0005] According to one embodiment, the first driving branch includes a first driving transistor, one end of which is configured to receive the high voltage, and the other end is connected to an output node, with its gate connected to a gate driving circuit. The second driving branch includes a second switching transistor and a second driving transistor connected in series, one end of which is configured to receive the low voltage, and the other end is connected to the output node. The gate of the second switching transistor is connected to the selection control circuit, and the gate of the second driving transistor is connected to the gate driving circuit. The signal driving circuit further includes: at least one fourth driving transistor connected between the output node and ground potential, with its gate connected to the gate driving circuit; and a gate driving circuit configured to receive the driving signal and control the gate voltages of the first driving transistor, the second driving transistor, and the fourth driving transistor based on the driving signal. The selection control circuit selects either the first driving branch or the second driving branch based on the amplitude of the driving signal, and together with the at least one fourth driving transistor, performs power amplification processing on the driving signal.

[0006] According to one embodiment, when the amplitude of the driving signal is less than a first threshold, the selection control circuit selects the second driving branch to perform power amplification processing on the driving signal. When the amplitude of the driving signal is greater than or equal to the first threshold, the selection control circuit selects the first driving branch to perform power amplification processing on the driving signal.

[0007] According to one embodiment, the signal driving circuit further includes a third driving branch comprising a third switching transistor and a third driving transistor connected in series, one end of which is configured to receive a medium voltage, the medium voltage being between the low voltage and the high voltage, and the other end connected to the output node. The gate of the third switching transistor is connected to the selection control circuit, and the gate of the third driving transistor is connected to the gate driving circuit. The gate driving circuit is further configured to control the gate voltage of the third driving transistor based on the driving signal, and the selection control circuit is configured to select the first driving branch, the second driving branch, or the third driving branch based on the amplitude of the driving signal, together with the at least one fourth driving transistor, to perform power amplification processing on the driving signal.

[0008] According to one embodiment, when the amplitude of the driving signal is less than a first threshold, the selection control circuit selects the second driving branch to perform power amplification processing on the driving signal; when the amplitude of the driving signal is greater than or equal to the first threshold and less than a second threshold, the selection control circuit selects the third driving branch to perform power amplification processing on the driving signal; when the amplitude of the driving signal is greater than or equal to the second threshold, the selection control circuit selects the first driving branch to perform power amplification processing on the driving signal.

[0009] According to one embodiment, when the selection control circuit selects the second driving branch, the selection control circuit controls the gate voltages of the second and third switching transistors to turn on the second switching transistor and turn off the third switching transistor. The selection control circuit also provides a control signal to the gate driving circuit. In response to the control signal, the gate driving circuit provides a driving signal to the gate of the second driving transistor and controls the gate voltages of the first and third driving transistors to turn them off. When the selection control circuit selects the third driving branch, the selection control circuit controls the gate voltages of the second and third switching transistors to turn off the second switching transistor and turn on the third switching transistor. The selection control circuit also provides a control signal to the gate driving circuit. In response to the control signal, the gate driving circuit provides a driving signal to the gate of the third driving transistor and controls the gate voltages of the first and second driving transistors to turn them off. When the selection control circuit selects the first driving branch, the selection control circuit controls the gate voltages of the second and third switching transistors to make both the second and third switching transistors in a cutoff state. The selection control circuit also provides a control signal to the gate driving circuit. In response to the control signal, the gate driving circuit provides a driving signal to the gate of the first driving transistor and controls the gate voltages of the second and third driving transistors to make both the second and third driving transistors in a cutoff state.

[0010] According to one embodiment, the at least one fourth driving transistor includes a plurality of fourth driving transistors connected in parallel. The gate driving circuit is configured to provide a driving signal to the gate of the plurality of fourth driving transistors when the first driving branch is selected to perform power amplification processing, and to provide a driving signal to the gate of a portion of the plurality of fourth driving transistors when the second driving branch or the third driving branch is selected to perform power amplification processing, thereby keeping the remaining portions of the plurality of fourth driving transistors in a cutoff state.

[0011] According to one embodiment, the signal driving circuit further includes a third driving branch, comprising a third switching transistor and a third driving transistor connected in series with each other. The third driving branch is connected in parallel with the second driving branch, one end of which is configured to receive the low voltage, and the other end is connected to the output node. The gate of the third switching transistor is connected to the selection control circuit, and the gate of the third driving transistor is connected to the gate driving circuit. When the second driving branch is selected to perform power amplification processing, the selection control circuit and the gate driving circuit control the second driving branch and the third driving branch in the same manner, so that both the second driving branch and the third driving branch are used to perform power amplification processing on the driving signal.

[0012] According to one embodiment, when any drive branch includes two or more transistors of the same conductivity type connected in series, at least two transistors of the same conductivity type are connected in series in opposite directions.

[0013] Another aspect of the present invention provides an electronic device including any one of the signal driving circuits described above, and a playback device for playing a driving signal provided by the signal driving circuit.

[0014] According to one embodiment, the driving signal is an audio signal, and the playback device is a speaker.

[0015] According to one embodiment, the driving signal is a tactile signal, and the playback device is a vibration motor.

[0016] Another aspect of the present invention provides a signal driving method executed by a signal driving circuit, the signal driving circuit including a first driving branch configured to be powered by a high voltage and a second driving branch configured to be powered by a low voltage, the signal driving method including: detecting the amplitude of a driving signal; and selecting the first driving branch or the second driving branch based on the amplitude of the driving signal for performing power amplification processing on the driving signal.

[0017] According to one embodiment, the first driving branch includes a first driving transistor, one end of which is configured to receive the high voltage, and the other end is connected to an output node, with its gate connected to a gate driving circuit. The second driving branch includes a second switching transistor and a second driving transistor connected in series, one end of which is configured to receive the low voltage, and the other end is connected to the output node. The gate of the second switching transistor is connected to a selection control circuit, and the gate of the second driving transistor is connected to the gate driving circuit. The signal driving circuit further includes: at least one fourth driving transistor connected between the output node and ground potential, with its gate connected to the gate driving circuit; a gate driving circuit configured to receive the driving signal and control the gate voltages of the first driving transistor, the second driving transistor, and the fourth driving transistor based on the driving signal; and a selection control circuit configured to select either the first driving branch or the second driving branch based on the amplitude of the driving signal, and together with the at least one fourth driving transistor, to perform power amplification processing on the driving signal.

[0018] According to one embodiment, selecting either the first driving branch or the second driving branch based on the amplitude of the driving signal to perform power amplification processing on the driving signal includes: when the amplitude of the driving signal is less than a first threshold, the selection control circuit selects the second driving branch to perform power amplification processing on the driving signal; when the amplitude of the driving signal is greater than or equal to the first threshold, the selection control circuit selects the first driving branch to perform power amplification processing on the driving signal.

[0019] According to one embodiment, the signal driving circuit further includes a third driving branch, which includes a third switching transistor and a third driving transistor connected in series. One end of the third driving transistor is configured to receive a medium voltage, which is between the low voltage and the high voltage, and the other end is connected to the output node. The gate of the third switching transistor is connected to the selection control circuit, and the gate of the third driving transistor is connected to the gate driving circuit. The gate driving circuit is further configured to control the gate voltage of the third driving transistor based on the driving signal. Selecting either the first driving branch or the second driving branch based on the amplitude of the driving signal to perform power amplification processing on the driving signal includes: selecting the first driving branch, the second driving branch, or the third driving branch based on the amplitude of the driving signal, and using them together with the at least one fourth driving transistor to perform power amplification processing on the driving signal.

[0020] According to one embodiment, selecting a first driving branch, a second driving branch, or a third driving branch based on the amplitude of the driving signal includes: when the amplitude of the driving signal is less than a first threshold, the selection control circuit selects the second driving branch to perform power amplification processing on the driving signal; when the amplitude of the driving signal is greater than or equal to the first threshold and less than a second threshold, the selection control circuit selects the third driving branch to perform power amplification processing on the driving signal; and when the amplitude of the driving signal is greater than or equal to the second threshold, the selection control circuit selects the first driving branch to perform power amplification processing on the driving signal.

[0021] According to one embodiment, when the selection control circuit selects the second driving branch, the selection control circuit controls the gate voltages of the second and third switching transistors to turn on the second switching transistor and turn off the third switching transistor. The selection control circuit also provides a control signal to the gate driving circuit. In response to the control signal, the gate driving circuit provides a driving signal to the gate of the second driving transistor and controls the gate voltages of the first and third driving transistors to turn them off. When the selection control circuit selects the third driving branch, the selection control circuit controls the gate voltages of the second and third switching transistors to turn off the second switching transistor and turn on the third switching transistor. The selection control circuit also provides a control signal to the gate driving circuit. In response to the control signal, the gate driving circuit provides a driving signal to the gate of the third driving transistor and controls the gate voltages of the first and second driving transistors to turn them off. When the selection control circuit selects the first driving branch, the selection control circuit controls the gate voltages of the second and third switching transistors to make both the second and third switching transistors in a cutoff state. The selection control circuit also provides a control signal to the gate driving circuit. In response to the control signal, the gate driving circuit provides a driving signal to the gate of the first driving transistor and controls the gate voltages of the second and third driving transistors to make both the second and third driving transistors in a cutoff state.

[0022] The above and other features and advantages of the present invention will become clear and apparent from the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0023] Figure 1 A schematic diagram of an existing signal driving circuit is shown.

[0024] Figure 2 A schematic diagram of a signal driving circuit according to an embodiment of the present invention is shown.

[0025] Figure 3 A schematic diagram of a signal driving circuit according to another embodiment of the present invention is shown.

[0026] Figure 4 A schematic diagram of a signal driving circuit according to another embodiment of the present invention is shown.

[0027] Figure 5 A schematic diagram of a signal driving circuit according to another embodiment of the present invention is shown.

[0028] Figure 6 A schematic diagram of a drive branch in a signal drive circuit according to an embodiment of the present invention is shown.

[0029] Figure 7 A schematic diagram of an electronic device according to an embodiment of the present invention is shown.

[0030] Figure 8 A flowchart of a signal driving method according to an embodiment of the present invention is shown. Detailed Implementation

[0031] Some exemplary embodiments of the invention will now be described with reference to the accompanying drawings. To provide a clear and complete description of these exemplary embodiments, certain specific details are provided below. However, it should be understood that the invention should not be limited to these specific details of the exemplary embodiments. Rather, embodiments of the invention may be practiced without these specific details or by employing other alternative methods, without departing from the spirit and principles of the invention as defined in the claims.

[0032] Figure 1 A schematic diagram of a conventional signal driving circuit is shown. For ease of description, some embodiments of the present invention will be illustrated below using an audio signal driving circuit as an example. However, it should be understood that the embodiments of the present invention are not limited to audio signal driving circuits, and their principles can also be applied to driving circuits for other signals, such as, but not limited to, tactile signal driving circuits for driving vibration motors.

[0033] Reference Figure 1The signal driving circuit 10 may include a preamplifier circuit 12 and a power output stage 14. Depending on the type of signal driving circuit 10, the preamplifier circuit 12 may include various circuits. For example, the signal driving circuit 10 may be a Class A amplifier, a Class B amplifier, a Class AB amplifier, a Class D amplifier, etc. Taking a Class D amplifier as an example, the preamplifier circuit 12 may include a preamplifier, an integrating circuit, a pulse width modulation circuit, a level conversion circuit, a gate driving circuit, etc. If the signal driving circuit 10 is another type of driving circuit, the specific circuits included in the preamplifier circuit 12 may differ, and will not be listed here. The preamplifier circuit 12 receives the input audio signal Vin, processes it accordingly, and then provides it to the power output stage 14 for power amplification and output.

[0034] The power output stage 14 may include the industry-standard H-bridge. Figure 1 A half-bridge circuit is shown, but a full-bridge circuit could also be included. For example... Figure 1 As shown, the power output stage 14 includes a first PMOS transistor 15 and a second NMOS transistor 17, which are connected in series. The source of the PMOS transistor 15 is connected to the drive voltage ( Figure 1 The PMOS transistor 15 (PVDD) is connected to the drain of NMOS transistor 17 and serves as the output node to provide the output voltage Vout. The source of NMOS transistor 17 is grounded. The control gates of PMOS transistor 15 and NMOS transistor 17 receive the audio signal. When PMOS transistor 15 is turned on, NMOS transistor 17 is turned off, and the output signal Vout is high; when PMOS transistor 15 is turned off, NMOS transistor 17 is turned on, and the output signal Vout is low. The output signal Vout can be filtered and provided to the speaker to drive the speaker to play the audio signal.

[0035] Currently, the battery voltage Vbat used to power portable electronic devices is typically around 3 to 5 volts, insufficient to provide the voltage required to drive audio signals. Insufficient drive voltage can lead to truncated distortion, affecting sound quality and listening experience. To provide a sufficiently high drive voltage, a boost circuit 19 can be used to boost the battery voltage Vbat, generating a higher voltage PVDD to power the output stage 14. The battery voltage Vbat can then be used to power the preamplifier circuit 12. Examples of boost circuits 19 include, but are not limited to, DC-DC circuits, charge pump circuits, etc. Although... Figure 1 The boost circuit 19 is shown outside the signal drive circuit 10, but it can also be integrated within the signal drive circuit 10. For example, the signal drive circuit 10 can be formed as a driver chip, which may include the built-in boost circuit 19, or the boost circuit 19 can be formed outside the driver chip.

[0036] While the boost circuit 19 can generate a higher voltage PVDD to meet the high voltage requirement of the power output stage 14, this reduces the driving efficiency of the signal drive circuit 10, resulting in wasted power. For example, if the high voltage PVDD is set relatively high, such as around 12V, then when the audio signal is weak, such a high drive voltage is not required, resulting in wasted power consumption; on the other hand, if the high voltage PVDD is set relatively low, such as around 6 to 8V, then when the audio signal is strong, truncated distortion may occur.

[0037] To address the aforementioned issues, an adjustable boost circuit concept is proposed. Specifically, the audio signal can be sampled, and the boost voltage PVDD provided by the boost circuit 19 can be controlled based on the voltage level of the audio signal. When the audio signal voltage level is high, the voltage PVDD provided by the boost circuit 19 can be increased; when the audio signal voltage level is low, the voltage PVDD provided by the boost circuit 19 can be decreased. This achieves improved driving efficiency and reduced power consumption, thereby extending the battery life of electronic devices, while avoiding truncated distortion and ensuring sound quality.

[0038] However, for portable electronic devices such as mobile phones, the pursuit of saving power and extending battery life is endless. There is a desire to further improve the drive circuit to achieve higher drive efficiency and reduce wasted power, thereby further saving power. Based on this pursuit, after studying existing drive circuits, the inventors realized the following problem. Specifically, the high voltage PVDD output by commonly used boost circuits is above the battery voltage Vbat that powers the boost circuit; that is, the boost voltage PVDD is greater than or equal to the battery voltage Vbat. In this case, when the audio signal voltage level is very low, for example, close to the lowest volume, the drive voltage PVDD provided by the boost circuit 19 is still close to or equal to the battery voltage Vbat. Since the battery voltage Vbat may be much higher than the drive voltage required by the audio signal, the drive efficiency of the power output stage 14 is low, resulting in wasted power. There is still room for further improvement in existing drive circuits to address this problem.

[0039] One embodiment of the present invention provides a signal driving circuit that can further improve driving efficiency, thereby saving power consumption and extending the battery life of electronic devices. Another embodiment of the present invention also provides an electronic device including the signal driving circuit.

[0040] Figure 2A schematic diagram of a signal driving circuit according to an embodiment of the present invention is shown. It should be understood that the signal driving circuit of the present invention can be formed as an integrated circuit, such as a chip, or as a circuit on a printed circuit board, etc., and the present invention is not specifically limited in this regard. Furthermore, in the embodiments of the signal driving circuit described below, the power output stage and related control circuitry are mainly described, while other functional units that may be included in the signal driving circuit are omitted. For example, depending on the type of signal driving circuit, including but not limited to Class A amplifiers, Class B amplifiers, Class AB amplifiers, Class D amplifiers, etc., the signal driving circuit may also include various pre-amplifier circuits upstream of the power output stage, filter circuits downstream of the power output stage, and functional circuits such as overvoltage protection, undervoltage protection, temperature protection, etc.

[0041] Reference Figure 2 The signal driving circuit may include a first driving branch connected to a high voltage, such as PVDD, which includes a transistor, such as a PMOS transistor P1, and a second driving branch connected to a low voltage, which includes two transistors, such as PMOS transistors P2 and PMOS transistor P3, connected in series. It should be understood that the high and low voltages can be relative probabilities, i.e., the high voltage is higher than the low voltage, and the low voltage is lower than the high voltage. Depending on the specific application, the high and low voltages may have different voltage ranges. In one embodiment, the first driving branch may be connected to the high voltage rail of the electronic device to receive the high voltage, and the second driving branch may be connected to the low voltage rail of the electronic device to receive the low voltage. In another embodiment, the high voltage may be a high voltage provided by a boost circuit, obtained by boosting a power supply voltage, such as a battery voltage Vbat; the low voltage may be a low voltage provided by a buck circuit, obtained by bucking the power supply voltage Vbat. The boost and buck circuits may be part of the signal driving circuit of the present invention, for example, integrated together in a signal driving chip, or formed outside the signal driving chip, which has pins for receiving the high and low voltages. In one embodiment, the high voltage can be an adjustable voltage, for example, adjustable between the battery voltage Vbat and the maximum voltage based on the amplitude of the drive signal. The low voltage can be a fixed voltage. In one embodiment, the high voltage can be between the power supply voltage Vbat, for example, 3-5 volts, and the maximum voltage, for example, 12-15 volts, and the low voltage can be between, for example, 1.6-2.2 volts, such as in the range of 1.8-2.0 volts. In the following description, for simplicity and ease of understanding, 12 volts will be used as an example of a high voltage PVDD, 5 volts as an example of a power supply voltage or battery voltage Vbat, and 1.8 volts as an example of a low voltage; however, it should be understood that the principles of the invention are not limited to these specific voltage values ​​used as examples.

[0042] like Figure 2As shown, in the first driving branch, the source of PMOS transistor P1 receives a high voltage PVDD, and its drain is connected to the output node that provides the output voltage Vout. The control gate can be connected to the gate driving circuit 21. Multiple transistors, such as multiple NMOS transistors N1, can be placed between the output node Vout and ground. These transistors are connected in parallel, with their sources and drains connected between the output node Vout and ground. The control gate can be connected to the gate driving circuit 21. Thus, PMOS transistor P1 and NMOS transistor N1 form an H-bridge circuit structure, here a half-bridge for single-ended output. However, this invention can also be applied to a full-bridge for dual-ended / differential output, which will be described in detail below.

[0043] In the second drive branch, PMOS transistors P2 and P3 are connected in series, preferably in reverse series, which will be referred to later. Figure 6 Further detailed description. The drain of PMOS transistor P2 receives a low voltage, and its source is connected to the source of PMOS transistor P3. The drain of PMOS transistor P3 is connected to the output node that provides the output voltage Vout. PMOS transistor P2 can be used as a switching transistor, and its control gate can be connected to the selection control circuit 23. PMOS transistor P3 can be used as a driving transistor, and its control gate can be connected to the gate driving circuit 21. Thus, PMOS transistor P3 and NMOS transistor N1 also form an H-bridge circuit structure, here a half-bridge for single-ended output, but the invention can also be applied to a full-bridge suitable for dual-ended / differential output, which will be described in detail below. It should be understood that the positions of switching transistor P2 and driving transistor P3 can be interchanged; for example, driving transistor P3 can be located on the low-voltage side, and switching transistor P2 can be located on the output node side.

[0044] Continue to refer to Figure 2 The signal driving circuit may also include a sampling circuit 22, which can sample the driving signal and provide the sampled signal to the selection control circuit 23. Although Figure 2 The diagram shows sampling circuit 22 sampling the input drive signal Vin. However, sampling circuit 22 can also sample the output drive signal Vout, the amplitude of which corresponds to the product of the amplitude of the input signal Vin and the amplification factor (i.e., gain) of the signal drive circuit. It is understood that sampling circuit 22 can also sample the drive signal at any node between the input and output. Examples of sampling circuit 22 may include a resistor network or a power amplifier, etc. In some embodiments, sampling circuit 22 may be omitted, for example, the input drive signal may be directly connected to selection control circuit 23 via wiring.

[0045] The selection control circuit 23 can detect the amplitude of the drive signal and select either the first drive branch or the second drive branch based on the amplitude of the drive signal for power amplification processing of the drive signal. The selection control circuit 23 can also control the gate drive circuit 21 to provide the drive signal Vin to the selected drive branch for power amplification processing.

[0046] The following description Figure 2 The working principle of the signal driving circuit shown is as follows: The sampling circuit 22 samples the driving signal Vin and provides the sampled driving signal to the selection control circuit 23. The selection control circuit 23 detects the amplitude of the driving signal and selects the corresponding driving branch based on the amplitude. When the amplitude of the driving signal is large, for example, greater than or equal to a predetermined threshold, the selection control circuit 23 can determine that a high voltage is needed for driving. This predetermined threshold can be stored in a predetermined register of the driving circuit and can be adjusted through an interface circuit such as an I2C bus. When it is determined that a high voltage is needed for driving, the selection control circuit 23 can turn off the switching transistor P2 by controlling the gate voltage of the switching transistor P2, so that the second driving branch (i.e., the low voltage branch) cannot be turned on. The selection control circuit 23 can also control the gate driving circuit 21 to control the gate voltage of the driving transistor P3, so that the driving transistor P3 is in the off state, or the gate driving circuit 21 can prevent the driving signal from being provided to the control gate of the driving transistor P3, which can further save power consumption. In this way, the second driving branch (i.e., the low voltage branch) will not work. On the other hand, the selection control circuit 23 can control the gate drive circuit 21 to provide drive signals to the control gate of the drive transistor P1 in the first drive branch, and to the control gate of one or more drive transistors N1. In this way, drive transistors P1 and N1 form an H-bridge to amplify the drive signals. The operating principle of the H-bridge is well known in the industry and will not be elaborated here. At this point, using an adjustable high voltage PVDD, such as 5 volts to 12 volts, to amplify the drive signals with a large amplitude avoids truncation distortion and ensures good drive performance and efficiency.

[0047] It should be understood that, although Figure 2 The gate drive circuit 21 is shown as a block diagram, but it may also include multiple sub-circuits or sub-modules. For example, it may include a gate drive sub-module for driving transistor P1, a gate drive sub-module for driving transistor P3, and a gate drive sub-module for driving transistor N1. The gate drive circuit can perform level shifting and logic control on the input drive signal Vin to control the conduction and cutoff of the corresponding transistor.

[0048] When the amplitude of the drive signal is low, for example, less than a predetermined threshold, the selection control circuit 23 can determine that a low voltage is sufficient to amplify the drive signal for output. Therefore, the selection control circuit 23 can control the gate drive circuit 21 to apply a predetermined voltage to the control gate of the drive transistor P1, thus turning off the drive transistor P1 and preventing the high voltage PVDD from reaching the output node through the first drive branch (i.e., the high-voltage branch). On the other hand, the selection control circuit 23 can turn on the switching transistor P2 by controlling its gate voltage, thus enabling the second drive branch (i.e., the low-voltage branch). The selection control circuit 23 can also provide a control signal to the gate drive circuit 21, enabling it to provide the drive signal to the control gate of the drive transistor P3 in the second drive branch. In this way, the first drive branch (i.e., the high-voltage branch) is disabled, while the second drive branch (i.e., the low-voltage branch) is enabled. Furthermore, the selection control circuit 23 can also control the gate drive circuit 21 to provide the drive signal to the control gate of one or more drive transistors N1. Thus, drive transistors P3 and N1 form an H-bridge to amplify the drive signal for output. At this point, using a low voltage, such as 1.8 volts, to amplify the drive signal with a low amplitude is sufficient to avoid truncation distortion, achieve good driving effect, and ensure driving efficiency. Compared with using a high voltage to drive a small signal, this significantly saves power consumption.

[0049] As described above, the selection control circuit 23 can select the high-voltage branch or the low-voltage branch to perform the drive based on sampling of the drive signal, such as audio or tactile signal, thereby saving power consumption of the drive circuit while ensuring the driving effect. It can be understood that the selection control circuit 23 can easily control the on and off times of the high-voltage branch and the low-voltage branch, preventing them from conducting simultaneously, thus preventing the high voltage PVDD from reaching the low-voltage domain via transistors P1, P3, and P2, thereby affecting the operation of the low-voltage device.

[0050] exist Figure 2In the example shown, the high-voltage branch may only include the driving transistor P1, without any additional switching transistors, while the low-voltage branch includes both the driving transistor P3 and a dedicated switching transistor P2. This is because when a low voltage, such as 1.8 volts, reaches the output node Vout, its voltage value is low and will not affect the off state of the driving transistor P1 in the high-voltage branch. On the other hand, when a high voltage PVDD, such as 12 volts, reaches the output node Vout, it may affect the off state of the driving transistor P3 in the low-voltage branch, causing it to turn on unexpectedly. This would allow the high voltage PVDD to flow back into the low-voltage domain. Therefore, a dedicated switching transistor P2 is used to prevent the low-voltage branch from turning on unexpectedly. However, it is understood that a dedicated switching transistor can also be used in the high-voltage branch, although this would increase the area of ​​the circuit, such as the chip. Furthermore, as mentioned earlier, the positions of the switching transistor P2 and the driving transistor P3 can be interchanged. When the switching transistor P2 is located on the output node side and the driving transistor P3 is located on the low voltage side, by controlling the gate voltage of the switching transistor P2 to make it in the off state, the high voltage PVDD reaching the output node Vout cannot reach the low voltage domain through the low voltage branch, thereby ensuring the normal operation of electronic devices connected to the low voltage domain.

[0051] As described above, regardless of whether a high-voltage branch or a low-voltage branch is selected, it forms an H-bridge with the driving transistor N1 to perform power amplification output operation. Therefore, in some embodiments, the control signal generated by the selection control circuit 23 may not affect the control operation of the gate driving circuit 21 on the driving transistor N1. That is, regardless of whether the selection control circuit 23 selects to use a high-voltage branch or a low-voltage branch, the gate driving circuit 21 will provide a drive signal to the gates of one or more parallel driving transistors N1. In this case, the gate driving circuit 21 can provide the same drive signal to the gates of multiple parallel driving transistors N1, causing them to simultaneously turn on or off in response to the drive signal. The parallel state of multiple driving transistors N1 can reduce the equivalent resistance, thereby reducing power consumption. In other embodiments, the control signal generated by the selection control circuit 23 may also affect the control operation of the gate driving circuit 21 on the driving transistor N1. For example, when the selection control circuit 23 selects to use the high-voltage branch for driving, the larger current allows all driving transistors N1 to operate normally and participate in power amplification. When the selection control circuit 23 selects to use the low-voltage branch for driving, the smaller current allows the gate driving circuit 21 to control the gate voltage, causing some driving transistors N1 to be in the off state, while only a portion of driving transistors N1 can operate normally and participate in power amplification. In this case, the static power consumption of the transistors can be reduced, thereby saving driving losses, and the circuit impedance can be adjusted to achieve impedance matching with upstream and downstream circuits.

[0052] Figure 2 This diagram illustrates a driver circuit for single-ended output, where only one output signal, Vout, exists. In some applications, such as audio signal driving, for dual-ended / differential output scenarios—where an input signal Vin generates two differential output signals, Vout1 and Vout2—the output stage needs to perform power amplification on each signal separately. This can be achieved by performing power amplification on each signal individually. Figure 2 The circuit shown is an example of this. Figure 3 middle.

[0053] Reference Figure 3 The signal driving circuit includes, in addition to Figure 2 The circuit shown, in addition to amplifying the power of a single signal Vout1, also includes an output stage circuit with the same configuration for amplifying the power of the differential signal Vout2. Specifically, it includes a PMOS transistor P1a, whose source receives a high voltage PVDD, and whose drain is connected to the output node providing the output voltage Vout2. Its control gate can be connected to the gate drive circuit 21. Multiple NMOS transistors N1a can be disposed between the output node Vout2 and ground, connected in parallel, and their control gates can be connected to the gate drive circuit 21. PMOS transistors P2a and P3a are connected in series. The drain of PMOS transistor P2a receives a low voltage, and its source is connected to the source of PMOS transistor P3a. The drain of PMOS transistor P3a is connected to the output node providing the output voltage Vout2. PMOS transistor P2a can be used as a switching transistor, and its control gate can be connected to the selection control circuit 23. PMOS transistor P3a can be used as a driving transistor, and its control gate can be connected to the gate drive circuit 21. The positions of the switching transistor P2a and the driving transistor P3a can be interchanged. The control of the high-voltage branch containing transistor P1a and the low-voltage branches containing transistors P2a / P3a can be exactly the same as the control of the high-voltage and low-voltage branches described above, that is, the high-voltage branch or the low-voltage branch is used simultaneously to amplify the differential signals Vout1 and Vout2. This will not be repeated here. In one embodiment, the switching transistor P2a can be omitted, and the drain of the driving transistor P3a can be connected to the drain of the switching transistor P2. This reduces the number of components and saves circuit area.

[0054] In some embodiments, the high voltage PVDD can be adjustable, for example, adjusted between the power supply voltage Vbat and its maximum value according to the amplitude of the drive signal. Therefore, the high voltage branch can be used for power amplification of drive signals with a wide amplitude range. In other embodiments, such as in some low-cost electronic devices, to reduce costs, the boost circuit providing the high voltage PVDD may not have automatic conditional boost gain, and the generated high voltage PVDD has a fixed value. In this case, the high voltage PVDD may be around 12 volts, while the low voltage may be around 1.8 volts, a large gap that is not conducive to power amplification of drive signals, for example, those greater than 1.8 volts but much lower than 12 volts; that is, the driving efficiency for these signals is still relatively low, resulting in power waste. Therefore, in Figure 4 In the illustrated embodiment, three drive branches can be provided, namely, in addition to the aforementioned high-voltage branch and low-voltage branch, a medium-voltage branch can also be included, which can be connected to a medium voltage, such as power supply voltage or battery voltage, between the high voltage PVDD (e.g., 12 volts) and the low voltage (e.g., 1.8 volts), and can be in the range of 3 to 6 volts, for example, around 5 volts.

[0055] like Figure 4 As shown, the intermediate voltage branch may include a switching transistor P4 and a driving transistor P5 connected in series. The drain of the switching transistor P4 is connected to the intermediate voltage, and its source is connected to the source of the driving transistor P5. The drain of the driving transistor P5 is connected to the output node Vout. In some embodiments, the positions of the switching transistor P4 and the driving transistor P5 may be interchanged; for example, the driving transistor P5 may be located on the intermediate voltage side, while the switching transistor P4 may be located on the output node side. The control gate of the switching transistor P4 is connected to the selection control circuit 23, and the control gate of the driving transistor P5 is connected to the gate driving circuit 21.

[0056] Figure 4 The working principle of the three-branch drive circuit shown is the same as Figure 2The two branch drive circuits shown are similar and will only be briefly described here. When the selection control circuit 23 determines that the amplitude of the sampled signal is lower than the first threshold, the low-voltage branch can be selected to perform power amplification. At this time, the selection control circuit 23 can turn off the switching transistor P4 in the medium-voltage branch and provide a control signal to the gate drive circuit 21. In response to this control signal, the gate drive circuit 21 can turn off both drive transistors P5 and P1, so that neither the medium-voltage branch nor the high-voltage branch works. The selection control circuit 23 can turn on the switching transistor P2 in the low-voltage branch and provide a control signal to the gate drive circuit 21. In response to this control signal, the gate drive circuit 21 can provide a drive signal to the gate of the drive transistor P3 in the low-voltage branch, so that the low-voltage branch can work normally. Together with the drive transistor N1, it forms an H-bridge to perform power amplification on the drive signal.

[0057] When the selection control circuit 23 determines that the amplitude of the sampled signal is greater than or equal to a first threshold but lower than a second threshold, it can select to use the intermediate voltage branch to perform power amplification. In this case, the selection control circuit 23 can turn off the switching transistor P2 in the low-voltage branch and provide a control signal to the gate drive circuit 21. In response to this control signal, the gate drive circuit 21 can turn off both drive transistors P3 and P1, thus disabling both the low-voltage and high-voltage branches. The selection control circuit 23 can also turn on the switching transistor P4 in the intermediate voltage branch and provide a control signal to the gate drive circuit 21. In response to this control signal, the gate drive circuit 21 can provide a drive signal to the gate of the drive transistor P5 in the intermediate voltage branch, allowing the intermediate voltage branch to operate normally. Together with the drive transistor N1, it forms an H-bridge to amplify the drive signal.

[0058] When the selection control circuit 23 determines that the amplitude of the sampled signal is greater than or equal to the second threshold, it can select to use the high-voltage branch to perform power amplification. At this time, the selection control circuit 23 can turn off both the switching transistor P2 in the low-voltage branch and the switching transistor P4 in the medium-voltage branch, and provides a control signal to the gate drive circuit 21. In response to this control signal, the gate drive circuit 21 can turn off both drive transistors P3 and P5, thus disabling both the low-voltage and medium-voltage branches. In response to the control signal provided by the selection control circuit 23, the gate drive circuit 21 also provides a drive signal to the gate of the drive transistor P1 in the high-voltage branch, allowing the high-voltage branch to operate normally. Together with the drive transistor N1, it forms an H-bridge to amplify the drive signal.

[0059] Figure 4 Other aspects of the illustrated embodiments may be related to Figure 2The embodiments shown are the same or similar, and will not be described again here. It should be understood that... Figure 4 The illustrated embodiments can also be used as follows Figure 3 This forms a differential circuit used to provide differential signals, which will not be described again here.

[0060] based on Figure 2 and Figure 4 The illustrated embodiment can also be understood to allow for the setting of more drive branches, each corresponding to a different voltage range, depending on the voltage range required in the specific application. This enables finer selection of the drive voltage, resulting in higher drive efficiency and energy savings. In specific applications, the appropriate number of drive branches can be selected based on the required drive voltage range and factors such as cost. The selection and control of each drive branch can be referenced as described above. Figure 2 and Figure 4 As described.

[0061] As described above, the driving circuit of the present invention can be implemented as a chip. When applied to an electronic device, the chip pins can receive driving signal inputs from external circuits and multiple different driving voltages. Consider a specific case where the driving circuit of the present invention provides three driving branches, such as a low-voltage branch, a medium-voltage branch, and a high-voltage branch, but the electronic device only provides two voltages, such as a high voltage and a low voltage. In one embodiment, only the low-voltage branch and the high-voltage branch can be connected to their respective voltages, while the medium-voltage branch is left unused. The second threshold in the register of the driving circuit corresponding to the selection of the medium-voltage branch can be set to the same value as the first threshold corresponding to the low-voltage branch. In this case, when the amplitude of the sampled signal is lower than the first (and second) thresholds, the selection control circuit 23 can select the low-voltage branch for power amplification; when the amplitude of the sampled signal is greater than or equal to the first (and second) thresholds, the selection control circuit 23 can select the high-voltage branch for power amplification, thus the selection control circuit 23 will not select the medium-voltage branch.

[0062] In another embodiment, such as Figure 5 As shown, the medium-voltage branch can also be connected in parallel with the low-voltage branch, that is, the medium-voltage branch is also connected to the low-voltage branch, and the medium-voltage branch is operated using the same logic as the low-voltage branch. For example... Figure 5As shown, when the amplitude of the sampled signal is lower than the first (and second) thresholds, the selection control circuit 23 can select the low-voltage branch for power amplification. In this case, the selection control circuit 23 can control the switching transistors P2 and P4 to conduct simultaneously, and provide a control signal to the gate drive circuit 21, causing the gate drive circuit 21 to simultaneously provide a drive signal to the gates of driving transistors P3 and P5. In this embodiment, by connecting the low-voltage branch and the medium-voltage branch in parallel, the resistance can be reduced, thereby saving power consumption. When the amplitude of the sampled signal is greater than or equal to the first (and second) thresholds, the selection control circuit 23 can select the high-voltage branch for power amplification. In this case, the selection control circuit 23 can control the switching transistors P2 and P4 to deactivate simultaneously, and provide a control signal to the gate drive circuit 21, causing the gate drive circuit 21 to control the driving transistors P3 and P5 to be in the deactivated state, and simultaneously provide a drive signal to the gate of driving transistor P1, thereby using the high-voltage branch for power amplification. In some embodiments, the second threshold can be disabled, and only the first threshold is used to select the low-voltage branch (in this embodiment, a parallel circuit of a low-voltage branch and a medium-voltage branch) and the high-voltage branch.

[0063] In the embodiments described above, various transistors in the driving circuit, including switching transistors and driving transistors, are described based on specific conductivity types, such as PMOS and NMOS. However, it should be understood that the various transistors in the driving circuit of the present invention are not limited to the specific types described above. For example, these switching transistors and driving transistors can arbitrarily use NMOS transistors and PMOS transistors; the present invention does not impose any special restrictions on this, as long as the gate voltage of the transistor is controlled by the selection control circuit 23 and the gate driving circuit 21 to achieve the desired on and off states. Therefore, the appropriate transistor type can be selected as needed. For example, for the driving transistor in the high-voltage branch, because its source is connected to a high voltage, it is difficult to provide a higher voltage to its gate; therefore, a PMOS transistor can be selected, which can conduct when the voltage Vgs between its gate and source is below -0.7 volts. For the switching transistors in the low-voltage and medium-voltage branches, PMOS or NMOS transistors can be selected. NMOS transistors generally have a smaller area than PMOS transistors, which is beneficial for the miniaturization of the driving chip and is therefore preferred. For the driving transistors in the low-voltage and medium-voltage branches, either PMOS transistors or NMOS transistors can be arbitrarily selected.

[0064] Figure 6 This illustrates the connection of two transistors of the same conductivity type in a low-voltage or medium-voltage branch, using a PMOS transistor as an example, but the principle also applies to the case of two NMOS transistors. Figure 6As shown, when two transistors of the same conductivity type are used in a low-voltage or medium-voltage branch, these two transistors are preferably connected in series in opposite directions. Figure 6 The diagram shows transistors P2 and P3 with their sources connected to each other, the drain of transistor P2 connected to the low / medium voltage, and the drain of transistor P3 connected to the output node. This connection allows the parasitic diodes D2 and D3 of transistors P2 and P3 to be reverse-connected. This prevents the low / medium voltage from reaching the output node Vout via the parasitic diode path and affecting the output signal when the low / medium voltage circuit is not selected for power amplification. It also prevents the high voltage PVDD supplied to the output node Vout from flowing back into the low / medium voltage domain via the parasitic diode path, affecting the normal operation of other components, or even causing physical damage to them.

[0065] Figure 7 An electronic device 30 according to an embodiment of the present invention is shown, which may include a signal driving circuit 32 and a playback device 34. For example, the electronic device 30 may be a portable electronic device such as a mobile phone, and the signal driving circuit 32 may include the components described above. Figure 2-6 The described driving circuit allows the playback device 34 to play a driving signal provided by the signal driving circuit 32. In one embodiment, the driving signal may be, for example, an audio signal, the signal driving circuit 32 may be an audio power amplifier circuit, and the playback device 34 may be a speaker that plays the audio signal processed by the signal driving circuit 32, thereby providing voice functionality to the user. In another embodiment, the driving signal may be, for example, a tactile signal, the signal driving circuit 32 may be a tactile signal power amplifier circuit, and the playback device 34 may be, for example, a linear motor that plays the tactile signal processed by the signal driving circuit 32, thereby providing tactile feedback to the user.

[0066] Figure 8 A signal driving method according to an embodiment of the present invention is shown, which can be executed by any of the signal driving circuits described above. Since some details of the signal driving method executed by the signal driving circuits have already been described above, only a brief description of the signal driving method is given here.

[0067] like Figure 8As shown, the signal driving method may include: step 41, detecting the amplitude of the driving signal; and step 42, selecting a first driving branch or a second driving branch based on the amplitude of the driving signal, for performing power amplification processing on the driving signal. The signal driving circuit for executing this method has already been described in detail above, and will not be repeated here. In short, the amplitude of the driving signal can be detected by a selection control circuit, and a first driving branch or a second driving branch can be selected based on the amplitude of the driving signal, which, together with at least one fourth driving transistor, can be used to perform power amplification processing on the driving signal.

[0068] In one embodiment, selecting a first driving branch or a second driving branch based on the amplitude of the driving signal to perform power amplification processing on the driving signal may include: when the amplitude of the driving signal is less than a first threshold, the selection control circuit selects the second driving branch to perform power amplification processing on the driving signal; when the amplitude of the driving signal is greater than or equal to the first threshold, the selection control circuit selects the first driving branch to perform power amplification processing on the driving signal.

[0069] As mentioned earlier, the signal driving circuit may also include a third driving branch. In this case, the first, second, or third driving branch can be selected based on the amplitude of the driving signal, and used together with at least one fourth driving transistor to perform power amplification processing on the driving signal. For example, when the amplitude of the driving signal is less than a first threshold, the selection control circuit selects the second driving branch to perform power amplification processing on the driving signal; when the amplitude of the driving signal is greater than or equal to the first threshold and less than the second threshold, the selection control circuit selects the third driving branch to perform power amplification processing on the driving signal; when the amplitude of the driving signal is greater than or equal to the second threshold, the selection control circuit selects the first driving branch to perform power amplification processing on the driving signal. The control of each transistor when each driving branch is selected has been described in detail above, and will not be repeated here.

[0070] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0071] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0072] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0073] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0074] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A signal driving circuit, comprising: a first driving branch configured to be powered by a high voltage; a second driving branch configured to be powered by a low voltage; and a selection control circuit configured to select the first driving branch or the second driving branch for performing power amplification on a driving signal based on an amplitude of the driving signal. 2.The signal driving circuit of claim 1, wherein the first driving branch comprises a first driving transistor having one end configured to receive the high voltage, the other end connected to an output node, and a gate connected to a gate drive circuit; the second driving branch comprises a second switch transistor and a second driving transistor connected in series with each other, having one end configured to receive the low voltage, the other end connected to the output node, the gate of the second switch transistor connected to the selection control circuit, and the gate of the second driving transistor connected to the gate drive circuit; the signal driving circuit further comprises: at least one fourth driving transistor connected between the output node and a ground potential, having a gate connected to the gate drive circuit; and the gate drive circuit configured to receive the driving signal and control gate voltages of the first driving transistor, the second driving transistor, and the fourth driving transistor based on the driving signal, wherein the selection control circuit selects the first driving branch or the second driving branch, together with the at least one fourth driving transistor, for performing power amplification on the driving signal based on the amplitude of the driving signal. the selection control circuit selects the second driving branch for performing power amplification on the driving signal when the amplitude of the driving signal is less than a first threshold value, 3. The signal drive circuit of claim 2, wherein, the selection control circuit selects the first driving branch for performing power amplification on the driving signal when the amplitude of the driving signal is greater than or equal to the first threshold value. 4.The signal driving circuit of claim 2, further comprising: a third driving branch comprising a third switch transistor and a third driving transistor connected in series with each other, having one end configured to receive a medium voltage, the medium voltage being between the low voltage and the high voltage, the other end connected to the output node, the gate of the third switch transistor connected to the selection control circuit, and the gate of the third driving transistor connected to the gate drive circuit, wherein the gate drive circuit is further configured to control the gate voltage of the third driving transistor based on the driving signal, the selection control circuit is configured to select the first driving branch, the second driving branch, or the third driving branch, together with the at least one fourth driving transistor, for performing power amplification on the driving signal based on the amplitude of the driving signal. the selection control circuit selects the second driving branch for performing power amplification on the driving signal when the amplitude of the driving signal is less than a first threshold value, 5. The signal drive circuit of claim 4, wherein, ​ when the amplitude of the drive signal is greater than or equal to the first threshold value and less than a second threshold value, the selection control circuit selects the third drive branch for performing power amplification processing on the drive signal, when the amplitude of the drive signal is greater than or equal to the second threshold value, the selection control circuit selects the first drive branch for performing power amplification processing on the drive signal.

6. The signal drive circuit of claim 5, wherein, when the selection control circuit selects the second drive branch, the selection control circuit controls the gate voltages of the second switch transistor and the third switch transistor so that the second switch transistor is turned on and the third switch transistor is turned off, and the selection control circuit also provides a control signal to the gate drive circuit, and the gate drive circuit provides a drive signal to the gate of the second drive transistor in response to the control signal, and controls the gate voltages of the first drive transistor and the third drive transistor so that the first drive transistor and the third drive transistor are in an off state, when the selection control circuit selects the third drive branch, the selection control circuit controls the gate voltages of the second switch transistor and the third switch transistor so that the second switch transistor is turned off and the third switch transistor is turned on, and the selection control circuit also provides a control signal to the gate drive circuit, and the gate drive circuit provides a drive signal to the gate of the third drive transistor in response to the control signal, and controls the gate voltages of the first drive transistor and the second drive transistor so that the first drive transistor and the second drive transistor are in an off state, when the selection control circuit selects the first drive branch, the selection control circuit controls the gate voltages of the second switch transistor and the third switch transistor so that the second switch transistor and the third switch transistor are both in an off state, and the selection control circuit also provides a control signal to the gate drive circuit, and the gate drive circuit provides a drive signal to the gate of the first drive transistor in response to the control signal, and controls the gate voltages of the second drive transistor and the third drive transistor so that the second drive transistor and the third drive transistor are in an off state.

7. The signal drive circuit of claim 6, wherein, the at least one fourth drive transistor includes a plurality of fourth drive transistors connected in parallel, the gate drive circuit is configured to provide a drive signal to the gates of the plurality of fourth drive transistors when the first drive branch is selected for performing power amplification processing, and provide a drive signal to the gates of a portion of the plurality of fourth drive transistors and leave the remaining portion of the plurality of fourth drive transistors in an off state when the second drive branch or the third drive branch is selected for performing power amplification processing.

8. The signal drive circuit of claim 2, further comprising: a third drive branch comprising a third switch transistor and a third drive transistor connected in series with each other, the third drive branch being connected in parallel with the second drive branch, one end of the third drive branch being configured to receive the low voltage, the other end of the third drive branch being connected to the output node, a gate of the third switch transistor being connected to the selection control circuit, a gate of the third drive transistor being connected to the gate drive circuit, wherein, when the second drive branch is selected to perform the power amplification processing, the selection control circuit and the gate drive circuit control the second drive branch and the third drive branch in the same way, so that both the second drive branch and the third drive branch are used to perform the power amplification processing on the drive signal.

9. The signal driver circuit of any one of claims 1 to 8, wherein, When any drive branch comprises two or more transistors of the same conductivity type connected in series, at least two transistors of the same conductivity type are connected in series with each other in an opposite direction. 10.An electronic device comprising: the signal drive circuit of any one of claims 1 to 9; and a playing device configured to play the drive signal provided by the signal drive circuit.

11. The electronic device of claim 10, wherein, the drive signal is an audio signal, and the playing device is a loudspeaker, or the drive signal is a haptic signal, and the playing device is a vibration motor. 12.A signal drive method performed by a signal drive circuit, the signal drive circuit comprising a first drive branch configured to be powered by a high voltage and a second drive branch configured to be powered by a low voltage, the signal drive method comprising: detecting an amplitude of a drive signal; and selecting the first drive branch or the second drive branch to perform power amplification processing on the drive signal based on the amplitude of the drive signal. 13.The signal drive method of claim 12, wherein the first drive branch comprises a first drive transistor, one end of the first drive transistor being configured to receive the high voltage, the other end of the first drive transistor being connected to an output node, a gate of the first drive transistor being connected to a gate drive circuit; the second drive branch comprises a second switch transistor and a second drive transistor connected in series with each other, one end of the second drive branch being configured to receive the low voltage, the other end of the second drive branch being connected to the output node, a gate of the second switch transistor being connected to a selection control circuit, a gate of the second drive transistor being connected to the gate drive circuit; the signal drive circuit further comprises: at least one fourth drive transistor connected between the output node and a ground potential, a gate of the fourth drive transistor being connected to the gate drive circuit; the gate drive circuit is configured to receive the drive signal and control gate voltages of the first drive transistor, the second drive transistor and the fourth drive transistor based on the drive signal; and the selection control circuit is configured to select the first drive branch or the second drive branch to perform the power amplification processing on the drive signal with the at least one fourth drive transistor based on the amplitude of the drive signal. selecting the first drive branch or the second drive branch to perform the power amplification processing on the drive signal based on the amplitude of the drive signal comprises:

14. The signal drive method of claim 13, wherein, ​ when the amplitude of the driving signal is less than a first threshold, the second driving branch is selected by the selection control circuit for performing power amplification processing on the driving signal, when the amplitude of the driving signal is greater than or equal to the first threshold, the first driving branch is selected by the selection control circuit for performing power amplification processing on the driving signal.

15. The signal drive method of claim 13, wherein, The signal driving circuit further comprises a third driving branch comprising a third switch transistor and a third driving transistor connected in series with each other, one end of which is configured to receive a medium voltage between the low voltage and the high voltage, and the other end of which is connected to the output node, a gate of the third switch transistor being connected to the selection control circuit, and a gate of the third driving transistor being connected to the gate driving circuit, the gate driving circuit being further configured to control a gate voltage of the third driving transistor based on the driving signal, selecting the first driving branch or the second driving branch for performing power amplification processing on the driving signal based on the amplitude of the driving signal, comprises: selecting the first driving branch, the second driving branch or the third driving branch together with the at least one fourth driving transistor for performing power amplification processing on the driving signal based on the amplitude of the driving signal.

16. The signal drive method of claim 15, wherein, selecting the first driving branch, the second driving branch or the third driving branch based on the amplitude of the driving signal, comprises: when the amplitude of the driving signal is less than a first threshold, the second driving branch is selected by the selection control circuit for performing power amplification processing on the driving signal, when the amplitude of the driving signal is greater than or equal to the first threshold and less than a second threshold, the third driving branch is selected by the selection control circuit for performing power amplification processing on the driving signal, when the amplitude of the driving signal is greater than or equal to the second threshold, the first driving branch is selected by the selection control circuit for performing power amplification processing on the driving signal.

17. The signal drive method of claim 16, wherein, when the selection control circuit selects the second driving branch, the selection control circuit controls gate voltages of the second switch transistor and the third switch transistor to turn on the second switch transistor and turn off the third switch transistor, and the selection control circuit further provides a control signal to the gate driving circuit, the gate driving circuit provides a driving signal to a gate of the second driving transistor in response to the control signal, and controls gate voltages of the first driving transistor and the third driving transistor to turn off the first driving transistor and the third driving transistor, When the selection control circuit selects the third drive branch, the selection control circuit controls the gate voltages of the second switch transistor and the third switch transistor to make the second switch transistor be in an off state and the third switch transistor be in an on state, and the selection control circuit also provides a control signal to the gate drive circuit, and the gate drive circuit provides a drive signal to the gate of the third drive transistor in response to the control signal, and controls the gate voltages of the first drive transistor and the second drive transistor to make the first drive transistor and the second drive transistor be in off states, When the selection control circuit selects the first drive branch, the selection control circuit controls the gate voltages of the second switch transistor and the third switch transistor to make the second switch transistor and the third switch transistor be in off states, and the selection control circuit also provides a control signal to the gate drive circuit, and the gate drive circuit provides a drive signal to the gate of the first drive transistor in response to the control signal, and controls the gate voltages of the second drive transistor and the third drive transistor to make the second drive transistor and the third drive transistor be in off states.

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