LED display device based on multi-channel PWM constant current driving chip

Abstract

The application discloses a kind of LED display devices based on multi-channel PWM constant current drive chip, by setting controller, LED drive module and LED array unit, LED drive module includes first drive unit and second drive unit, second drive unit includes a plurality of series connection PWM constant current drive chip and respectively connect the power filter capacitor at the power input end and ground end of each PWM constant current drive chip, controller according to control instruction controls first drive unit and second drive unit drive LED array unit and carries out PWM display, adopts multi-channel low turn PWM constant current drive chip, chip maximum supports 16bit gray scale, high-precision current generating circuit is integrated in chip, so that the current error between chip is controllable, improve the display effect of LED display screen, improve the working stability of LED display screen to a certain extent.

Description

Technical Field

[0001] This invention belongs to the field of LED dot matrix display technology, and particularly relates to an LED display device based on a multi-channel PWM constant current drive chip. Background Technology

[0002] Dot matrix display is a common display technology widely used in electronic devices such as LED displays, electronic clocks, and billboards. It consists of multiple LEDs, and characters, numbers, or graphics are displayed by controlling the on / off state of each LED. A microcontroller is typically used as the microcontroller to program and control the content and effects of the dot matrix display. Dot matrix display modules usually consist of multiple LEDs arranged in a matrix. In a microcontroller system, operating on any register or a specific bit requires specifying its physical address. Since a register only has eight bits, the number of bits is eight times the number of registers. The microcontroller cannot encode all bits; therefore, only one of the eight registers is bit-addressable. For non-addressable registers, if only one bit needs to be operated on without affecting the others, logic gates are used for bit manipulation. However, in grayscale display applications, uncontrollable current errors can occur when using a microcontroller for PWM constant current driving, resulting in poor display quality. Therefore, there is an urgent need to provide an LED display device based on a multi-channel PWM constant current driver chip to solve the aforementioned technical problems. Summary of the Invention

[0003] In view of this, the present invention provides an LED display device based on a multi-channel PWM constant current drive chip. The chip adopts a multi-channel low-turn-off PWM constant current drive chip, which supports a maximum of 16-bit grayscale levels and integrates a high-precision current generation circuit on the chip, making the current error between chips controllable and improving the display effect of the LED display screen. The specific technical solution is as follows.

[0004] This invention provides an LED display device based on a multi-channel PWM constant current drive chip, the LED display device comprising a controller, an LED drive module, and an LED array unit;

[0005] The LED driving module includes a first driving unit and a second driving unit. The first driving unit is connected to a first end of the LED array unit, one end of the second driving unit is connected to a second end of the LED array unit, and the other end of the second driving unit is connected to the controller.

[0006] The second driving unit includes multiple PWM constant current driving chips connected in series and power filter capacitors connected to the input and output terminals of each PWM constant current driving chip respectively. The controller is used to receive control commands and control the first driving unit and the second driving unit to drive the LED array unit to perform PWM display according to the control commands.

[0007] As a preferred embodiment of the above technical solution, each of the PWM constant current drive chips includes a VDD pin, a GND pin, multiple OUT pins, an SDI pin, a CLK pin, an OE pin, an LE pin, an SDO pin, and multiple OUT pins. The power supply filter capacitor is connected to the VDD pin and the GND pin. The multiple OUT pins are connected to the second end of the LED array unit. The CLK pin, OE pin, and LE pin of each of the PWM constant current drive chips are respectively connected to the corresponding control pins.

[0008] The SDI pin of the first PWM constant current drive chip is connected to the SDI pin of the controller, the SDO pin of the first PWM constant current drive chip is connected to the SDI pin of the second PWM constant current drive chip, the first end is the row connection end of the LED array unit, and the second end is the group connection end of the LED array unit.

[0009] As a preferred embodiment of the above technical solution, the control commands of the controller include single-edge / dual-edge switching commands, ROW signal transmission mode, and PWM display mode.

[0010] As a preferred embodiment of the above technical solution, the rising edge of the CLK signal in single-edge mode samples SDI data, and both the rising and falling edges of the CLK signal in dual-edge mode sample SDI data. The CLK rising edge count is used to fix the OE signal width. The single-edge / dual-edge mode switching command needs to be sent once after power-on.

[0011] When it is necessary to enter single-edge mode after power-on, the controller sends more than or equal to 15 DCLK edges to set SDR, where the edges include rising edges and falling edges, DCLK is the pixel clock signal, and SDR is to enter single-edge mode.

[0012] When the SDR needs to enter dual-edge mode after power-on, the controller sends two rising edges of DCLK to set DDR, where DDR is to enter dual-edge mode.

[0013] When the CLK signal needs to switch from dual-edge mode to single-edge mode, the controller sends a dual-edge mode of more than or equal to 15 DCLK edges to set SDR.

[0014] When the SDR needs to enter dual-edge mode from single-edge mode, the controller sends two rising edges of DCLK in single-edge mode to set it to DDR.

[0015] As a preferred embodiment of the above technical solution, each of the PWM constant current drive chips is model HT2018. The PWM constant current drive chip integrates an on-chip GCLK generation circuit. The GCLK generation circuit is used to convert the OE signal into a ROW signal. The rising edge of the ROW signal is used to indicate the start of a row of display. The high-level width of the ROW signal includes W12 and W4. W12 indicates that the high-level width of the ROW signal is 12 DCLK widths, and W4 indicates that the high-level width of the ROW signal is 4 DCLK widths.

[0016] As a preferred embodiment of the above technical solution, the PWM display mode includes a general frame synchronization mode, a high grayscale data independent refresh synchronization mode, a high grayscale data independent refresh asynchronous mode, and a low grayscale high refresh mode.

[0017] As a preferred embodiment of the above technical solution, the execution process of the general frame synchronization mode includes:

[0018] Set the PWM display mode to general frame synchronization mode;

[0019] The DCLK data in each row are calculated according to the first preset formula;

[0020] Configure the number of display data groups, reg0x03[6:0]=refresh rate / frame rate-1, after VSYNC, display the first line of the first group, stop displaying after the data of the current frame is completed, until the next VSYNC arrives, where reg0x03[6:0] represents the number of PWM display groups, the number of PWM display groups = reg0x03[6:0]+1, the maximum number of groups supported is 128 groups, VSYNC represents the register instruction corresponding to update the display data.

[0021] As a preferred embodiment of the above technical solution, the execution process of the high-grayscale independent refresh synchronization mode includes:

[0022] Set the PWM display mode to high grayscale data independent refresh frame synchronization mode;

[0023] Calculate a set of display times = frame period / refresh rate or frame period / / frame frequency;

[0024] The display time for one row = display time for one set / number of rows;

[0025] The number of DCLKs in each row is calculated according to the formula. The second preset formula is satisfied by adjusting the number of gray levels in the row, the frequency of DCLKs, and the register reg0x6[1:0].

[0026] ROW is sent continuously at a fixed display frequency without interruption; the frequency of ROW is independent of VSYNC, and the frequency of the ROW signal = 1 / the display time of one line = 1 / the time between the rising edges of two ROW signals.

[0027] The 0th group, 0th row sends the ROW signal W12, and in other cases sends the ROW signal W4. For every first preset number of ROW signals, there is one W12, and this cycle continues. Here, VSYNC represents the instruction to update the register corresponding to the display data. The first preset number = number of groups * number of rows scanned.

[0028] As a preferred embodiment of the above technical solution, the execution process of the high-gray independent refresh asynchronous mode includes:

[0029] Set the PWM display mode to asynchronous mode with independent high grayscale data refresh;

[0030] The number of DCLKs in each row is calculated according to the third preset formula;

[0031] The number of display data groups is manually configured, with a default of 64 groups, reg0x03[6:0]=7'h3f, and a maximum of 128 groups. Here, reg0x03[6:0]=7'h3f represents the 64 groups of LED display data that are manually configured.

[0032] The frequency of the ROW signal = 1 / the display time of one line = 1 / the time between two rising edges of ROW;

[0033] The number of groups to be displayed in one frame = display refresh rate / frame rate. The number of groups to be displayed in one frame is greater than the number of data groups manually configured. The controller needs to send a second preset number of ROW signals in one frame. After sending, the display will be in an inter-frame black state until the next VSYNC. The second preset number = display refresh rate / frame rate * number of lines.

[0034] In group 0, row 0 sends the ROW signal W12; otherwise, it sends the ROW signal W4. Every third preset number of ROW signals, there is one W12 signal, and this cycle continues. Here, VSYNC represents the instruction to update the register corresponding to the displayed data. The refresh rate in asynchronous mode is greater than 7680. The third preset number = register configuration value * number of rows scanned.

[0035] As a preferred embodiment of the above technical solution, the execution process of the high-gray independent refresh asynchronous mode includes:

[0036] Set the PWM display mode to low grayscale high refresh rate mode;

[0037] The number of display groups is manually configured, with a default setting of 64 groups.

[0038] The number of DCLKs in each row is calculated according to the fourth preset formula, and the display time of each row is also calculated.

[0039] Calculate the display time for a set of rows = display time for one row * number of rows;

[0040] Calculate the display time for all groups = display time for one group * number of groups;

[0041] High refresh rate = frame period / display time of all groups;

[0042] A high refresh rate * number of display groups * number of scanned ROW signals needs to be sent between the two VSYNC signals;

[0043] After VSYNC, the first line of group 1 is displayed;

[0044] The display of the current frame stops after a high refresh rate of 10 times and continues until the next VSYNC.

[0045] Visual refresh rate = frame rate * number of data groups * refresh rate;

[0046] In the low grayscale high refresh rate mode, when the ROW signal needs to be changed, the grayscale level does not need to be adjusted. VSYNC indicates the instruction to update the register corresponding to the display data.

[0047] This invention provides an LED display device based on a multi-channel PWM constant current drive chip. The device comprises a controller, an LED drive module, and an LED array unit. The LED drive module includes a first drive unit and a second drive unit. The second drive unit includes multiple PWM constant current drive chips connected in series and power filter capacitors connected to the power input terminal and ground terminal of each PWM constant current drive chip. The controller controls the first and second drive units to drive the LED array unit for PWM display according to control commands. The device uses a multi-channel low-turn-off PWM constant current drive chip, which supports a maximum of 16-bit grayscale levels. It integrates a high-precision current generation circuit, making the current error between chips controllable, improving the display effect of the LED display screen, and to a certain extent enhancing the working stability of the LED display screen. Attached Figure Description

[0048] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a structural block diagram of the LED display device provided by the present invention;

[0050] Figure 2 Circuit diagram of the LED display device provided by the present invention;

[0051] Figure 3 A waveform diagram of ROW signal transmission provided by the present invention;

[0052] Figure 4 Waveform diagram of the universal frame synchronization mode provided by the present invention;

[0053] Figure 5 Waveform diagram of the high grayscale independent refresh synchronization mode provided by the present invention;

[0054] Figure 6 Waveform diagram of the high grayscale independent refresh asynchronous mode provided by the present invention;

[0055] Figure 7 The waveform diagram is for the low grayscale high refresh rate mode provided by this invention.

[0056] 100 - Controller; 110 - LED driver module; 111 - First driver unit; 112 - Second driver unit; 130 - LED array unit. Detailed Implementation

[0057] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0058] See Figure 1 and Figure 2 The present invention provides an LED display device based on a multi-channel PWM constant current drive chip, the LED display device including a controller 100, an LED drive module 110 and an LED array unit 130;

[0059] The LED driving module 110 includes a first driving unit 111 and a second driving unit 112. The first driving unit 111 is connected to the first end of the LED array unit 130, one end of the second driving unit 112 is connected to the second end of the LED array unit 130, and the other end of the second driving unit 112 is connected to the controller 100.

[0060] The second driving unit 112 includes a plurality of PWM constant current driving chips connected in series and power supply filter capacitors respectively connected to the input and output terminals of each PWM constant current driving chip. The controller 100 is used to receive control commands and control the first driving unit 111 and the second driving unit 112 to drive the LED array unit 130 to perform PWM display according to the control commands.

[0061] In this embodiment, each PWM constant current driver chip includes a VDD pin, a GND pin, multiple OUT pins, an SDI pin, a CLK pin, an OE pin, an LE pin, an SDO pin, and multiple OUT pins. The power supply filter capacitor is connected to the VDD pin and the GND pin. The multiple OUT pins are connected to the second end of the LED array unit. The CLK pin, OE pin, and LE pin of each PWM constant current driver chip are respectively connected to the corresponding control pins. Among them, the SDI pin of the first PWM constant current driver chip is connected to the SDI pin of the controller, and the SDO pin of the first PWM constant current driver chip is connected to the SDI pin of the second PWM constant current driver chip. The first end is the row connection end of the LED array unit, and the second end is the group connection end of the LED array unit. Each of the PWM constant current driver chips is model HT2018. The PWM constant current driver chip integrates an on-chip GCLK generation circuit. The GCLK generation circuit is used to convert the OE signal into a ROW signal. The rising edge of the ROW signal indicates the start of a row display. The first driving unit 111 is a row driver chip. The high-level width of the ROW signal includes W12 and W4. W12 indicates that the high-level width of the ROW signal is 12 DCLK widths, and W4 indicates that the high-level width of the ROW signal is 4 DCLK widths.

[0062] It should be noted that the control commands of the controller 100 include single-edge / dual-edge switching commands, ROW signal transmission mode, and PWM display mode. In single-edge mode, the rising edge of the CLK signal samples SDI data; in dual-edge mode, both the rising and falling edges of the CLK signal sample SDI data. The OE signal width is fixed using CLK rising edge counting. The single / dual-edge mode switching command needs to be sent once after power-on. When entering single-edge mode after power-on, the controller sends at least 15 DCLK edges to set SDR, where edges include rising and falling edges. DCLK is the pixel clock signal, and SDR indicates entering single-edge mode. When SDR needs to enter dual-edge mode after power-on, the controller 100 sends two DCLK rising edges to set DDR, where DDR indicates entering dual-edge mode. When the CLK signal is in dual-edge mode and needs to enter single-edge mode, the controller 100 sends at least 15 DCLK edges in dual-edge mode to set SDR. When SDR is in single-edge mode and needs to enter dual-edge mode, the controller 100 sends two DCLK rising edges in single-edge mode to set DDR.

[0063] The HT2018 is a common-anode 8-channel low-turn-off PWM constant current driver chip specifically designed for LED displays. It supports up to 16-bit grayscale levels and integrates high-precision current generation circuitry, ensuring current error between chips is controlled within 2.0%. It also incorporates several proprietary technologies to enhance the display effect of LED displays, providing further improvements. The LED display application circuit includes the power input voltage VCC and the power filter capacitor Cn. VCC is the input power voltage, with an allowable voltage range of 2.6–5.5V; its typical application voltage in display applications is 5.0V. Figure 2 Cn represents the system power supply filter capacitor, for example, 100nF. The HT2018 supports 1~32 scans; its tiny size fills the market gap for small-size chips in transparent screen applications, making it suitable for LED displays. When using the HT2018 in LED display designs, the current difference between channels and even between chips is extremely small, stemming from the HT2018's excellent constant current output characteristics. The maximum current between channels within the chip is less than ±2.0%, while the maximum current error between chips is less than ±2.0%. The stability of its output current remains unaffected by changes in the load voltage (Vout).

[0064] Specifically, the controller's register write process is as follows: first, PRE_ACT is sent, then WR_CFG is executed. LE is the width of 5 DCLKs. The first 8 bits input are the register address bits, and the last 8 bits input are the data bits of the corresponding register address. For example: {A7, A6, A5, A4, A3, A2, A1, A0} = 8'b0000_0111; {D7, D6, D5, D4, D3, D2, D1, D0} = 8'b1001_1101; that is, register 0x07 (8'b0000_0111) is set to 8'b1001_1101. Here, PRE_ACT indicates write enable, and WR_CFG indicates write register. The register signal transmission method is as follows: the order of sending instructions and data in each frame is: send VSYNC; send PRE_ACT; send WR_CFG to write register configuration (only one register address needs to be written per frame to save configuration time); send DAT_LAT several times to write display data in conjunction with SDI. Here, DAT_LAT indicates latching 16 bits of data to SRAM, GND indicates chip ground, CLK indicates serial clock input, LE indicates data and instruction latch, different LE lengths represent different instructions, OUT0-OUT7 indicate constant current output, ROW indicates line feed signal, SDO indicates serial data output, VDD indicates chip power supply, and SDI indicates serial data input.

[0065] It should be understood that, such as Figure 3 As shown, only the first row (Line 0) of Group 1 (Group 0) needs to send the ROW signal of W12; all other ROW signals are sent according to W4. By setting up a controller, LED driver module, and LED array unit, the LED driver module includes a first driver unit and a second driver unit. The second driver unit includes multiple PWM constant current driver chips connected in series and power filter capacitors connected to the power input terminal and ground terminal of each PWM constant current driver chip. The controller controls the first and second driver units to drive the LED array unit for PWM display according to control commands. Multi-channel low-turn-off PWM constant current driver chips are used, supporting a maximum of 16-bit grayscale levels. High-precision current generation circuits are integrated on-chip, making the current error between chips controllable, improving the display effect of the LED display screen, and to a certain extent improving the working stability of the LED display screen.

[0066] Optionally, the PWM display modes include a general frame synchronization mode, a high grayscale data independent refresh synchronization mode, a high grayscale data independent refresh asynchronous mode, and a low grayscale high refresh mode.

[0067] Specifically, the execution process of the general frame synchronization mode includes:

[0068] Set the PWM display mode to general frame synchronization mode;

[0069] The DCLK data in each row are calculated according to the first preset formula;

[0070] Configure the number of display data groups, reg0x03[6:0]=refresh rate / frame rate-1, after VSYNC, display the first line of the first group, stop displaying after the data of the current frame is completed, until the next VSYNC arrives, where reg0x03[6:0] represents the number of PWM display groups, the number of PWM display groups = reg0x03[6:0]+1, the maximum number of groups supported is 128 groups, VSYNC represents the register instruction corresponding to update the display data.

[0071] In this embodiment, as Figure 4 As shown, the number of display groups is automatically configured by the controller: Number of groups = Frame period / Display time of one group, Display time of one group = Display time of one line * Number of scan lines, Display time of one line - Line break time is the first preset formula, which is:

[0072] (2*(reg0x17[6]*16+reg0x05[7:4]+1)+2*(reg0x17 <4> *16+reg0x05[3:0]+1)+4*(reg0x14 <3> *128+reg0x04[6:0]+1)) / (reg0x06[2:0]+1) _DCLK_.

[0073] Specifically, the execution process of the high-gray independent refresh synchronization mode includes:

[0074] Set the PWM display mode to high grayscale data independent refresh frame synchronization mode;

[0075] Calculate a set of display times = frame period / refresh rate or frame period / frame frequency;

[0076] The display time for one row = display time for one set / number of rows;

[0077] The number of DCLKs in each row is calculated according to the formula. The second preset formula is satisfied by adjusting the number of gray levels in the row, the frequency of DCLKs, and the register reg0x6[1:0].

[0078] ROW is sent continuously at a fixed display frequency without interruption; the frequency of ROW is independent of VSYNC, and the frequency of the ROW signal = 1 / the display time of one line = 1 / the time between the rising edges of two ROW signals.

[0079] The 0th group, 0th row sends the ROW signal W12, and in other cases sends the ROW signal W4. For every first preset number of ROW signals, there is one W12, and this cycle continues. Here, VSYNC represents the instruction to update the register corresponding to the display data. The first preset number = number of groups * number of rows scanned.

[0080] In this embodiment, as Figure 5 As shown, the number of display groups is automatically configured by the controller: Number of groups = Frame period / Display time of one group, Display time of one group = Display time of one line * Number of scan lines, Display time of one line - Line break time is the second preset formula, and the second preset formula is:

[0081] (2*(reg0x17[6]*16+reg0x05[7:4]+1)+2*(reg0x17 <4> *16+reg0x05[3:0]+1)+4*(reg0x14 <3> *128+reg0x04[6:0]+1)) / (reg0x06[2:0]+1) _DCLK_.

[0082] Specifically, the execution process of the high-gray independent refresh asynchronous mode includes:

[0083] Set the PWM display mode to asynchronous mode with independent high grayscale data refresh;

[0084] The number of DCLKs in each row is calculated according to the third preset formula;

[0085] The number of display data groups is manually configured, with a default of 64 groups, reg0x03[6:0]=7'h3f, and a maximum of 128 groups supported. Here, reg0x03[6:0]=7'h3f represents the 64 groups of LED display data that are manually configured.

[0086] The frequency of the ROW signal = 1 / the display time of one line = 1 / the time between two rising edges of ROW;

[0087] The number of groups to be displayed in one frame = display refresh rate / frame rate. If the number of groups to be displayed in one frame is greater than the number of data groups manually configured, the controller needs to send a second preset number of ROW signals (display refresh rate / frame rate * number of lines) per frame. After sending, the display will remain in an inter-frame black state until the next VSYNC display.

[0088] The 0th row of group 0 sends the ROW signal W12, and the other rows send the ROW signal W4. Every third preset number of ROW signals (number of groups (according to register configuration value) * number of rows scanned) will result in one W12 signal, and this cycle continues. VSYNC indicates the instruction to update the register corresponding to the displayed data. The refresh rate in asynchronous mode is greater than 7680.

[0089] In this embodiment, as Figure 6 As shown, the number of display groups n is manually configured (the default configuration is 64 groups). The number of groups to be displayed in one frame = m + n = display refresh rate / frame rate. The display time of one group = the display time of one line * the number of scan lines. The display time of one line is the third preset formula, which is:

[0090] =(2*(reg0x17[6]*16+reg0x05[7:4]+1)+2*(reg0x17 <4> *16+reg0x05[3:0]+1)+4*(reg0x14 <3> *128+reg0x04[6:0]+1)) / (reg0x06[2:0]+1)+line break time. The main differences between the high grayscale data independent refresh frame synchronous mode and the asynchronous mode are: 1. High grayscale data independent refresh frame synchronous mode: the number of displayed data groups is automatically configured according to the display frame time; 2. High grayscale data independent refresh asynchronous mode: the number of displayed data groups can be manually configured.

[0091] Specifically, the execution process of the high-gray independent refresh asynchronous mode includes:

[0092] Set the PWM display mode to low grayscale high refresh rate mode;

[0093] The number of display groups is manually configured, with a default setting of 64 groups.

[0094] The number of DCLKs in each row is calculated according to the fourth preset formula, and the display time of each row is also calculated.

[0095] Calculate the display time for a set of rows = display time for one row * number of rows;

[0096] Calculate the display time for all groups = display time for one group * number of groups;

[0097] High refresh rate = frame period / display time of all groups;

[0098] A high refresh rate * number of display groups * number of scanned ROW signals needs to be sent between the two VSYNC signals;

[0099] After VSYNC, the first line of group 1 is displayed;

[0100] The display of the current frame stops after a high refresh rate of 10 times and continues until the next VSYNC.

[0101] Visual refresh rate = frame rate * number of data groups * refresh rate;

[0102] In the low grayscale high refresh rate mode, when the ROW signal needs to be changed, the grayscale level does not need to be adjusted. VSYNC indicates the instruction to update the register corresponding to the display data.

[0103] In this embodiment, as Figure 7 As shown, the display time for one row is the fourth preset formula, which is:

[0104] (2*(reg0x17[6]*16+reg0x05[7:4]+1)+2*(reg0x17 <4> *16+reg0x05[3:0]+1)+4*(reg0x14 <3> *128+reg0x04[6:0]+1)) / (reg0x06[2:0]+1)+line break time, the display time of a group = the display time of a line * the number of scanned lines, the number of display groups is manually configured (the default configuration is 64 groups), the display time of all groups = the display time of a group * the number of display groups; high refresh rate = frame period / the display time of all groups, a high refresh rate * the number of display groups * the number of scanned ROW signals needs to be sent before two Vsyncs ( Figure 7 (Taking a 2x higher refresh rate as an example).

[0105] It should be noted that HT2018 supports a maximum of 64 line scans, configured as reg0x02[5:0] = number of line scans - 1, reg0x14[3]*128+reg0x04[6:0] represents the PWM display length of one line, the PWM display length of one line = 4*(reg0x14[3]*128+reg0x04[6:0]+1); reg0x03[6:0] represents the number of PWM display groups, the number of PWM display groups = reg0x03[6:0]+1, and the maximum number of groups supported is 128. In frame synchronization mode, the number of PWM display groups = refresh rate / frame rate; in asynchronous mode, the PWM display groups can be configured independently (unrelated to the refresh rate); the number of display groups is less than or equal to the maximum number of groups. GL-08 supports two maximum number of groups, namely 128 and 64. Internal grayscale clock configuration: The HT2018 integrates a PLL to generate the grayscale clock GCLK. The relevant calculation formula is as follows: FGCLK=FDCLK*division coefficient.

[0106] In one feasible embodiment, the PWM grayscale level (maximum value) = row grayscale level * PWM display group. Gamma can be calculated and generated based on the PWM grayscale level (maximum value) (this part is generated by the control card manufacturer according to its own gamma generation formula). The chip grayscale level only supports a maximum of 16 bits. To optimize the heat dissipation of the package, the optimal operating range of the output voltage (VDS) is 0.3V to 1.0V (at this time, IOUT = 0.5 to 36mA). If VDS = VLED - VF and VLED = 5V, the excessively high output voltage (VDS) may cause PD(act) > PD(max). In this case, use the lowest possible VLED voltage, or use an external series resistor or Zener diode as VDROP. This results in VDS = (VLED - VF) - VDROP, achieving the effect of reducing the input voltage (VDS).

[0107] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0108] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0109] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. An LED display device based on a multi-channel PWM constant current drive chip, characterized in that, The LED display device includes a controller, an LED driver module, and an LED array unit; The LED driving module includes a first driving unit and a second driving unit. The first driving unit is connected to a first end of the LED array unit, one end of the second driving unit is connected to a second end of the LED array unit, and the other end of the second driving unit is connected to the controller. The second driving unit includes multiple PWM constant current driving chips connected in series and power filter capacitors connected to the power input terminal and ground terminal of each PWM constant current driving chip respectively. The controller is used to receive control commands and control the first driving unit and the second driving unit to drive the LED array unit to perform PWM display according to the control commands. The controller's control commands include single-edge / dual-edge switching commands, ROW signal transmission mode, and PWM display mode; In single-edge mode, the rising edge of the CLK signal samples SDI data, while in dual-edge mode, both the rising and falling edges of the CLK signal sample SDI data. The CLK rising edge count is used to fix the OE signal width. The single / dual-edge mode switching command needs to be sent once after power-on. When it is necessary to enter single-edge mode after power-on, the controller sends more than or equal to 15 DCLK edges to set SDR, where the edges include rising edges and falling edges, DCLK is the pixel clock signal, and SDR is to enter single-edge mode. When the SDR needs to enter dual-edge mode after power-on, the controller sends two rising edges of DCLK to set DDR, where DDR is to enter dual-edge mode. When the CLK signal needs to switch from dual-edge mode to single-edge mode, the controller sends a dual-edge mode of more than or equal to 15 DCLK edges to set SDR. When the SDR needs to enter dual-edge mode from single-edge mode, the controller sends two rising edges of DCLK in single-edge mode to set it to DDR.

2. The LED display device based on a multi-channel PWM constant current drive chip according to claim 1, characterized in that, Each of the PWM constant current driver chips includes a VDD pin, a GND pin, multiple OUT pins, an SDI pin, a CLK pin, an OE pin, an LE pin, an SDO pin, and multiple OUT pins. The power supply filter capacitor is connected to the VDD pin and the GND pin. The multiple OUT pins are connected to the second end of the LED array unit. The CLK pin, OE pin, and LE pin of each of the PWM constant current driver chips are respectively connected to the corresponding control pins. The SDI pin of the first PWM constant current drive chip is connected to the SDI pin of the controller, the SDO pin of the first PWM constant current drive chip is connected to the SDI pin of the second PWM constant current drive chip, the first end is the row connection end of the LED array unit, and the second end is the group connection end of the LED array unit.

3. The LED display device based on a multi-channel PWM constant current drive chip according to claim 1, characterized in that, Each of the PWM constant current driver chips is model HT2018. The PWM constant current driver chip integrates an on-chip GCLK generation circuit. The GCLK generation circuit is used to convert the OE signal into a ROW signal. The rising edge of the ROW signal indicates the start of a row of display. The high-level width of the ROW signal includes W12 and W4. W12 indicates that the high-level width of the ROW signal is 12 DCLK widths, and W4 indicates that the high-level width of the ROW signal is 4 DCLK widths.

4. The LED display device based on a multi-channel PWM constant current drive chip according to claim 3, characterized in that, The PWM display modes include general frame synchronization mode, high grayscale data independent refresh synchronization mode, high grayscale data independent refresh asynchronous mode, and low grayscale high refresh mode.

5. The LED display device based on a multi-channel PWM constant current drive chip according to claim 4, characterized in that, The execution process of the general frame synchronization mode includes: Set the PWM display mode to general frame synchronization mode; The DCLK data in each row are calculated according to the first preset formula; Configure the number of display data groups, reg0x03[6:0]=refresh rate / frame rate-1, after VSYNC, display the first line of the first group, stop displaying after the data of the current frame is completed, until the next VSYNC arrives, where reg0x03[6:0] represents the number of PWM display groups, the number of PWM display groups = reg0x03[6:0]+1, the maximum number of groups supported is 128 groups, VSYNC represents the register instruction corresponding to update the display data.

6. The LED display device based on a multi-channel PWM constant current drive chip according to claim 4, characterized in that, The execution process of the high-gray independent refresh synchronization mode includes: Set the PWM display mode to high grayscale data independent refresh frame synchronization mode; Calculate a set of display times = frame period / refresh rate or frame period / frame frequency; The display time for one row = display time for one set / number of rows; The number of DCLKs in each row is calculated according to the formula. The second preset formula is satisfied by adjusting the number of gray levels in the row, the frequency of DCLKs, and the register reg0x6[1:0]. ROW is sent continuously at a fixed display frequency without interruption; the frequency of ROW is independent of VSYNC, and the frequency of the ROW signal = 1 / the display time of one line = 1 / the time between the rising edges of two ROW signals. In group 0, row 0 sends the ROW signal W12; otherwise, it sends the ROW signal W4. A W12 signal exists for every first preset number of ROW signals, and this cycle continues. Here, VSYNC represents the instruction to update the register corresponding to the displayed data, and the first preset number equals the group number. Number of rows scanned.

7. The LED display device based on a multi-channel PWM constant current drive chip according to claim 4, characterized in that, The execution process of the high-gray independent refresh asynchronous mode includes: Set the PWM display mode to asynchronous mode with independent high grayscale data refresh; The number of DCLKs in each row is calculated according to the third preset formula; The number of display data groups is manually configured, with a default of 64 groups, reg0x03[6:0]=7'h3f, and a maximum of 128 groups. Here, reg0x03[6:0]=7'h3f represents the 64 groups of LED display data that are manually configured. The frequency of the ROW signal = 1 / the display time of one line = 1 / the time between two rising edges of ROW; The number of groups to be displayed in one frame = display refresh rate / frame rate. If the number of groups to be displayed in one frame is greater than the manually configured number of data groups, the controller needs to send a second preset number of ROW signals per frame. After sending, the display remains in an inter-frame black state until the next VSYNC. The second preset number = display refresh rate / frame rate. number of rows; In group 0, row 0 sends the ROW signal W12; otherwise, it sends the ROW signal W4. Every third preset number of ROW signals results in one W12 signal, and this cycle continues. Here, VSYNC represents the instruction to update the register corresponding to the displayed data. In asynchronous mode, the refresh rate is greater than 7680. The third preset number equals the register configuration value. Number of rows scanned.

8. The LED display device based on a multi-channel PWM constant current drive chip according to claim 4, characterized in that, The execution process of the high-gray independent refresh asynchronous mode includes: Set the PWM display mode to low grayscale high refresh rate mode; The number of display groups is manually configured, with a default setting of 64 groups. The number of DCLKs in each row is calculated according to the fourth preset formula, and the display time of each row is also calculated. Calculate the display time of a set = display time of a line number of rows; Calculate the display time for all groups = display time for one group Number of groups; High refresh rate = frame period / display time of all groups; A high refresh rate needs to be sent between two VSYNCs. Display group number Scan several ROW signals; After VSYNC, the first line of group 1 is displayed; The display of the current frame stops after a high refresh rate of 10 times and continues until the next VSYNC. Visual refresh rate = frame rate Number of data sets High refresh rate; In the low grayscale high refresh rate mode, when the ROW signal needs to be changed, the grayscale level does not need to be adjusted. VSYNC indicates the instruction to update the register corresponding to the display data.

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