Memory device and operating method thereof

Abstract

A memory device and a method of operating the memory device are provided. The memory device includes: a memory cell array including a first string disposed in a first layer, and a second string disposed in a second layer stacked on the first layer; a page buffer circuit including a first page buffer corresponding to a first string of the first layer and a second page buffer corresponding to a second string of the second layer; and a control logic circuit configured to independently control the first page buffer and the second page buffer in a core operation.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0113513, filed on August 23, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices. Background Technology

[0004] Memory devices are used to store data and can be classified as volatile or non-volatile memory devices. Examples of non-volatile memory devices include flash memory devices used in mobile phones, digital cameras, portable computer devices, fixed computer devices, or other devices. Because information communication devices support a variety of functions, high-capacity and highly integrated memory devices are required. Therefore, three-dimensional (3D) non-volatile memory devices, including those with multiple word lines stacked vertically on a substrate, are being developed. Furthermore, to provide 3D non-volatile memory devices, techniques are being developed to connect chips formed on different wafers using bonding methods. Summary of the Invention

[0005] One or more embodiments provide a memory device implemented by a joining method that has improved reliability of core operations.

[0006] According to one aspect of the embodiments, the memory device includes: a memory cell array including a first string disposed in a first layer and a second string disposed in a second layer stacked on the first layer; a page buffer circuit including a first page buffer corresponding to the first string in the first layer and a second page buffer corresponding to the second string in the second layer; and control logic circuitry configured to independently control the first page buffer and the second page buffer in core operations.

[0007] According to another aspect of the embodiments, the memory device includes: a first chip including a first page buffer and a second page buffer; a second chip stacked on the first chip, wherein a first string electrically connected to the first page buffer is disposed in the second chip; a third chip stacked on the second chip, wherein a second string electrically connected to the second page buffer is disposed in the third chip; and control logic circuitry configured to independently control the first page buffer and the second page buffer in core operation.

[0008] According to another aspect of the embodiments, a method is provided for operating a memory device including a memory cell array, the memory cell array including a first string disposed in a first layer and a second string disposed in a second layer stacked on the first layer. The method includes: entering a core operating mode; and independently controlling a first page buffer connected to the first string in the first layer and a second page buffer connected to the second string in the second layer based on characteristic differences between the first layer and the second layer. Attached Figure Description

[0009] The above and other aspects and features of this disclosure will become more clearly understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a data storage device according to an embodiment.

[0011] Figure 2 This is a block diagram illustrating a memory device according to an embodiment.

[0012] Figure 3 These are diagrams used to describe embodiments of a memory device according to an example.

[0013] Figure 4 It is a cross-sectional view used to conceptually describe an implementation of a memory device according to an embodiment.

[0014] Figure 5A It is shown that the formation according to the embodiment is in Figure 4 A circuit diagram of one of the multiple memory blocks in the first unit layer. Figure 5B It is shown that the formation according to the embodiment is in Figure 4 A circuit diagram of one of the multiple memory blocks in the second unit layer.

[0015] Figure 6 It is used to describe the embodiments. Figure 4 A diagram of the transmission transistor circuit.

[0016] Figure 7A This is a circuit diagram showing the first page buffer according to an embodiment.

[0017] Figure 7B This is a circuit diagram showing the second page buffer according to an embodiment.

[0018] Figure 8 This is a flowchart describing the core operations of a memory device according to an embodiment.

[0019] Figures 9 to 11 This is a diagram illustrating the operating conditions of pre-programmed operations that are set differently for each layer during an erasure operation, according to an embodiment.

[0020] Figure 12 This is a flowchart describing the pre-programming operations performed in an erase operation of a memory device according to an embodiment.

[0021] Figure 13 and Figure 14 This is a diagram illustrating the verification operation conditions set differently for each layer during the erasure operation according to an embodiment.

[0022] Figure 15 This is a flowchart describing the verification operations performed during an erase operation of a memory device according to an embodiment.

[0023] Figure 16 and Figure 17 It is a diagram used to describe the programming operation conditions that are set differently for each layer according to an embodiment.

[0024] Figure 18 This is a flowchart describing the programming operations of a memory device according to an embodiment.

[0025] Figure 19 and Figure 20 This is a diagram illustrating the verification operation conditions set differently for each layer in the programming verification operation according to an embodiment.

[0026] Figure 21 This is a flowchart describing the programming verification operation of a memory device according to an embodiment.

[0027] Figure 22 The diagram illustrates a timing diagram of applying hard core operating conditions to a first cell layer and soft core operating conditions to a second cell layer during a read operation, according to an embodiment.

[0028] Figure 23 This is a flowchart describing a read operation of a memory device according to an embodiment.

[0029] Figure 24 It is a cross-sectional view used to conceptually describe an implementation of a memory device according to an embodiment.

[0030] Figure 25 This is a diagram illustrating a transmission transistor circuit according to an embodiment.

[0031] Figure 26 This is a timing diagram illustrating an example of a gate-induced drain leakage (GIDL) erase operation according to an embodiment, in which the float time is changed to compensate for layer-specific characteristic differences.

[0032] Figure 27 This is a flowchart describing a read operation of a memory device according to an embodiment. Detailed Implementation

[0033] Hereinafter, embodiments will be described with reference to the accompanying drawings. The same components are denoted by the same reference numerals throughout the specification, and repeated descriptions thereof are omitted. It will be understood that when an element or layer is referred to as "on" another element or layer, "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as "directly on" another element or layer, "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. The embodiments described herein are exemplary embodiments, and therefore this disclosure is not limited thereto, and may be implemented in various other forms. Each exemplary embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment also provided herein or not provided herein but consistent with this disclosure.

[0034] [A data storage device that compensates for differences in characteristics between cells formed in different layers]

[0035] Figure 1 This is a block diagram illustrating a data storage device 1000 according to an embodiment.

[0036] The data storage device 1000 according to an embodiment may include a memory device 1100, and the memory cell array 1110 of the memory device 1100 may include memory cells formed in different layers. These layers may be formed using different wafers, and these layers may therefore have different characteristics from each other. To compensate for the differences in characteristics between the different layers, in core operation, the memory device 1100 may independently control the page buffer for each layer or may independently control the word lines of each layer other than the main word line. Therefore, the reliability of the core operation of the memory device 1100 can be improved.

[0037] Reference Figure 1 The data storage device 1000 may include a memory device 1100 and a memory controller 1200, and the memory device 1100 may include a memory cell array 1110, a page buffer circuit 1140 and a layer compensation circuit 1180.

[0038] The memory device 1100 can receive address signals, command signals, and user data from the memory controller 1200. The memory device 1100 can store user data based on the address signals and command signals. Furthermore, the memory device 1100 can perform an erase operation on the stored data. For example, the memory device 1100 can perform a gate-induced drain leakage (GIDL) erase operation in which an erase voltage is applied through a common-source line or a bit line.

[0039] The memory cell array 1110 may include a plurality of sub-memory cell arrays 1111 to 111n. Each of the plurality of sub-memory cell arrays 1111 to 111n may include a plurality of memory cells, and each of the plurality of memory cells may store data.

[0040] In this embodiment, the plurality of sub-memory cell arrays 1111 to 111n can be formed on different wafers. For example, the plurality of sub-memory cell arrays 1111 to 111n can be formed in different chips, and the chips in which the sub-memory cell arrays are formed can be interconnected by a bonding method. Therefore, the memory cell array 1110 can be formed to include multiple layers.

[0041] Page buffer circuit 1140 can be connected to memory cell array 1110 via bit lines. Page buffer circuit 1140 may include multiple page buffers, and each page buffer may temporarily store data to be programmed at the corresponding page or data read from the corresponding page.

[0042] In an embodiment, the page buffer circuit 1140 may include a plurality of subpage buffer circuits SPBC1 to SPBCn. The plurality of subpage buffer circuits SPBC1 to SPBCn may each correspond to a plurality of sub-memory cell arrays 1111 to 111n. In core operations, each of the plurality of subpage buffer circuits SPBC1 to SPBCn can be independently controlled and can independently execute core operations. In an embodiment, core operations may refer to at least one of erase operations, programming operations, verification operations, and read operations.

[0043] For example, the first subpage buffer circuit SPBC1 may include multiple page buffers, and the page buffers of the first subpage buffer circuit SPBC1 may be electrically connected to the bit lines of the first sub-memory cell array 1111, respectively. Furthermore, for example, the nth subpage buffer circuit SPBCn may include multiple page buffers, and the page buffers of the nth subpage buffer circuit SPBCn may be electrically connected to the bit lines of the nth sub-memory cell array 111n, respectively. In core operation, the first subpage buffer circuit SPBC1 and the nth subpage buffer circuit SPBCn can be controlled independently, and the operating conditions of the first subpage buffer circuit SPBC1 and the nth subpage buffer circuit SPBCn can be set to be different from each other.

[0044] The layer compensation circuit 1180 can be electrically connected to the page buffer circuit 1140 and / or the memory cell array 1110. Based on the cell characteristics of each layer, the layer compensation circuit 1180 can set different operating conditions for the core operation for each layer.

[0045] In this embodiment, the layer compensation circuit 1180 can independently control the subpage buffer circuits SPBC1 to SPBCn corresponding to each layer based on the cell characteristics of each layer. For example, the layer compensation circuit 1180 can set different core operating conditions (such as bit line voltage levels, bit line voltage application time, or sensing time) for each layer. Therefore, it is possible to compensate for the characteristic differences, word line load differences, and / or bit line load differences of memory cells formed on different layers.

[0046] Alternatively, in an embodiment, the layer compensation circuit 1180 can independently control the word lines of each layer, excluding the main word line, based on the cell characteristics of each layer. In an embodiment, the main word line can refer to the word line connected to the memory cell storing data, and the word lines other than the main word line can refer to gate-induced drain leakage (GIDL) lines, string select lines, ground select lines, pseudo word lines, etc., as described below. Therefore, in a GIDL erase operation, the float time of the string select lines, etc., can be set differently for each layer. Thus, differences in the characteristics of memory cells formed on different layers, differences in word line loads, and / or differences in bit line loads can be compensated.

[0047] As described above, in core operations, the memory device 1100 according to the embodiment can independently control the page buffer of each layer, or can independently control the word lines of each layer except for the main word line. Therefore, the reliability of the core operations of the memory device 1100 can be improved.

[0048] Figure 2 It is shown Figure 1 A block diagram of an example of a memory device 1100.

[0049] Reference Figure 2 The memory device 1100 may include a memory cell array 1110 and peripheral circuitry 1120. The peripheral circuitry 1120 may include an address decoder (i.e., an address decoder circuit) 1130, a page buffer circuit 1140, an input / output circuit 1150, a voltage generator (i.e., a voltage generation circuit) 1160, and control logic (i.e., control logic circuitry) 1170.

[0050] The memory cell array 1110 may include multiple memory blocks. Each memory block may have a two-dimensional or three-dimensional structure. Memory cells of a memory block with a two-dimensional structure (or horizontal (or planar) structure) may be formed in a direction parallel to the substrate. Memory cells of a memory block with a three-dimensional structure (or vertical structure) may be formed in a direction perpendicular to the substrate.

[0051] The memory cell array 1110 may include a plurality of sub-memory cell arrays 1111 to 111n. The plurality of sub-memory cell arrays 1111 to 111n may be formed on different wafers. For example, the plurality of sub-memory cell arrays 1111 to 111n may be formed in different chips, and the chips in which the sub-memory cell arrays are formed may be interconnected by a bonding method.

[0052] Address decoder 1130 can be connected to memory cell array 1110 via row lines RLs. Row lines RLs may include serial select lines, ground select lines, word lines, pseudo-word lines, and GIDL lines.

[0053] Page buffer circuit 1140 can be connected to memory cell array 1110 via bit lines BLs. Page buffer circuit 1140 can temporarily store data to be programmed at a selected page or data read from a selected page.

[0054] Page buffer circuit 1140 may include multiple subpage buffer circuits SPBC1 to SPBCn. The multiple subpage buffer circuits SPBC1 to SPBCn may correspond to multiple sub-memory cell arrays 1111 to 111n, respectively. In core operation, each of the multiple subpage buffer circuits SPBC1 to SPBCn can be independently controlled and can independently execute core operations. In an embodiment, to compensate for differences in layer characteristics, the operating conditions in the core operation of each page buffer circuit can be set differently.

[0055] The input / output circuit 1150 can be internally connected to the page buffer circuit 1140 via data lines DLs, and externally connected to the memory controller 1200 via input / output lines (see [link]). Figure 1 ).

[0056] Voltage generator 1160 can generate various voltages required for the operation of memory device 1100. For example, voltage generator 1160 can be configured to generate various voltages supplied to row lines RLs, bit lines BLs, or common source lines according to the operation of memory device 1100. For example, voltage generator 1160 can be configured to generate multiple programming voltages, multiple programming verification voltages, multiple transfer voltages, multiple read voltages, multiple read transfer voltages, and multiple erase voltages.

[0057] Control logic 1170 can control all operations of memory device 1100 in response to commands and addresses provided from memory controller 1200. Control logic 1170 may include layer compensation circuitry 1180 that sets different operating conditions for core operations for each layer.

[0058] The layer compensation circuit 1180 can be electrically connected to the page buffer circuit 1140 and / or the memory cell array 1110. Based on the cell characteristics of each layer, the layer compensation circuit 1180 can set different operating conditions for the core operation for each layer.

[0059] For example, the layer compensation circuit 1180 can independently control the subpage buffer circuits SPBC1 to SPBCn corresponding to each layer based on the characteristics of each layer. Alternatively, for example, the layer compensation circuit 1180 can independently control the word lines of each layer other than the main word lines based on the characteristics of each layer. Therefore, differences in layer characteristics can be compensated.

[0060] Figure 3 It is used to describe the embodiments. Figure 2 A diagram illustrating an embodiment of the memory device 1100. For ease of description, in Figure 3 In this context, it is assumed that the memory device 1100 is implemented by bonding three chips and the memory cell array is implemented using two chips.

[0061] Reference Figure 3 The memory device 1100 may include a first chip C1, a second chip C2, and a third chip C3 stacked in a vertical direction. The first chip C1 may include... Figure 2 The peripheral circuit 1120, the second chip C2 may include Figure 2 The first sub-memory cell array 1111, and the third chip C3 may include a second sub-memory cell array. The first chip C1 and the second chip C2 can be connected to each other by a bonding method, and the second chip C2 and the third chip C3 can be connected to each other by a bonding method.

[0062] The first chip C1 may include a circuit region, which includes a line decoder region DEC, a page buffer region PBA, and other circuit regions. Figure 2 The address decoder 1130 can be set to Figure 2 In the line decoder region DEC, and Figure 2 The page buffer circuit 1140 can be set in the page buffer region PBA. Furthermore, Figure 2 The control logic 1170, layer compensation circuit 1180, and / or voltage generator 1160 can be located in other circuit areas. For example... Figure 2 The input / output circuit 1150 can be located in other circuit areas.

[0063] The second chip C2 may include a memory cell array MCA. Figure 2 The first sub-memory cell array 1111 can be set in the memory cell array MCA of the second chip C2.

[0064] The third chip C3 may include a memory cell array (MCA). A second sub-memory cell array may be disposed within the memory cell array (MCA) of the third chip C3.

[0065] The first chip C1, the second chip C2, and the third chip C3 can be manufactured using different wafers and can be bonded together. For this reason, the cell characteristics of the memory cells in the second chip C2 can differ from those of the memory cells in the third chip C3. For example, the core operation speed of the memory cells in the second chip C2 can differ from the core operation speed of the memory cells in the third chip C3.

[0066] Furthermore, the length of the word line connecting the memory cell in the second chip C2 to the address decoder 1130 in the first chip C1 can be different from the length of the word line connecting the memory cell in the third chip C3 to the address decoder 1130 in the first chip C1. This difference in word line length may result in different load characteristics.

[0067] Furthermore, the length of the bit line connecting the memory cell in the second chip C2 to the page buffer circuit 1140 in the first chip C1 can be different from the length of the bit line connecting the memory cell in the third chip C3 to the page buffer circuit 1140 in the first chip C1. This difference in bit line length may result in different load characteristics.

[0068] To compensate for differences in chip-specific cell characteristics, chip-specific word line load characteristics, and / or chip-specific bit line load characteristics, the layer compensation circuit 1180 according to the embodiment can independently control the subpage buffer circuits SPBC1 to SPBCn corresponding to each layer, or can independently control the word lines of each layer except for the main word lines, based on the characteristics of each layer. Therefore, differences in the characteristics, word line loads, and / or bit line loads of memory cells formed on different layers can be compensated. This can improve the reliability of core operations.

[0069] In the embodiments, reference is made to Figure 3 A description of three chips being coupled together is given. However, this is provided as an example, and the embodiment is not limited thereto. According to the embodiment, “N” (N is a natural number of 3 or greater) different chips can be coupled together. For example, Figure 2 The memory cell array 1110 can be implemented by bonding three or more different chips. Alternatively, for example, Figure 2 The peripheral circuitry 1120 can be implemented by bonding two or more different chips. In this specification, for ease of description, it will be described as follows: Figure 3The embodiment shown combines three chips.

[0070] The following sections will first describe in detail an example of improving the reliability of kernel operations by independently controlling the page buffers of each layer. Next, they will describe in detail an example of improving the reliability of kernel operations by independently controlling the word lines of each layer, excluding the main word line.

[0071] [Page buffers controlled independently for each layer]

[0072] Figure 4 It is used to conceptually describe a memory device (such as...) according to an embodiment. Figure 2 A cross-sectional view of an embodiment of a memory device. (See reference...) Figure 3 In the above description, it is assumed that Figure 4 The memory device 1100A is implemented by bonding three chips, and the memory cell array is implemented using two chips. Furthermore, for ease of description, in Figure 4 The example shows one of the multiple strings in each cell region.

[0073] Reference Figure 4 When viewed in the vertical direction, the memory device 1100A may include an outer peripheral layer PL, a first cell layer CL1, and a second cell layer CL2.

[0074] The outer peripheral layer PL can be with Figure 3 The first chip C1 corresponds to, and Figure 2 The peripheral circuitry 1120 can be formed in the outer peripheral layer PL. For example, the transfer transistor circuit PTC, the first page buffer PB1, and the second page buffer PB2 can be formed in the outer peripheral layer PL. In an embodiment, the transfer transistor circuit PTC may be included in... Figure 2 The address decoder 1130. Additionally, the first page buffer PB1 may be included in... Figure 2 The first subpage buffer circuit SPBC1 is included. The second page buffer PB2 may be included in the second subpage buffer circuit. According to an embodiment, the outer peripheral layer PL may be referred to as the "peripheral circuit region PERI".

[0075] The outer peripheral layer PL and the first unit layer CL1 can be connected to each other by a bonding method. For example, a first bonding metal BM1 can be disposed on the upper part of the outer peripheral layer PL, and a second bonding metal BM2 can be disposed on the lower part of the first unit layer CL1. The outer peripheral layer PL and the first unit layer CL1 can be connected to each other by bonding the first bonding metal BM1 and the second bonding metal BM2.

[0076] The first unit layer CL1 can be with Figure 3 The second chip C2 corresponds to, and Figure 2The first sub-memory cell array 1111 can be formed in the first cell layer CL1. For example, the first sub-memory cell array 1111 may include a first string STR1_C1, and the first string STR1_C1 may be located in the first cell layer CL1 and may extend in the vertical direction.

[0077] The first string STR1_C1 of the first cell layer CL1 may include multiple transistors GDT1_C1, GDT2_C1, and SST_C1, and multiple memory cells MCa_C1 ("a" is an integer). The first end of the first string STR1_C1 of the first cell layer CL1 may be connected to the bit line BL_C1, and the second end of the first string STR1_C1 of the first cell layer CL1 may be connected to the common-source line CSL_C1. According to an embodiment, the first cell layer CL1 may be referred to as the "first cell region CELL1".

[0078] The first unit layer CL1 and the second unit layer CL2 can be connected to each other by a bonding method. For example, a third bonding metal BM3 can be disposed on the upper part of the first unit layer CL1, and a fourth bonding metal BM4 can be disposed on the lower part of the second unit layer CL2. The first unit layer CL1 and the second unit layer CL2 can be connected to each other by bonding the third bonding metal BM3 and the fourth bonding metal BM4.

[0079] The second unit layer CL2 can be with Figure 3 The third chip C3 corresponds to this, and the second sub-memory cell array can be formed in the second cell layer CL2. For example, the second sub-memory cell array may include a first string STR1_C2, and the first string STR1_C2 can be formed in the second cell layer CL2 and can extend in the vertical direction.

[0080] The first string STR1_C2 of the second cell layer CL2 may include multiple transistors GDT1_C2, GDT2_C2, and SST_C2, as well as multiple memory cells MCa_C2 ("a" being an integer). The first end of the first string STR1_C2 of the second cell layer CL2 may be connected to bit line BL_C2, and the second end of the first string STR1_C2 of the second cell layer CL2 may be connected to common source line CSL_C2. According to an embodiment, the second cell layer CL2 may be referred to as the "second cell region CELL2".

[0081] In this embodiment, the word lines of the first unit layer CL1 and the word lines of the second unit layer CL2 can be controlled simultaneously.

[0082] For example, the memory cell MCa_C1 of the first cell layer CL1 can be connected to the word line WLa_C1, and the word line WLa_C1 of the first cell layer CL1 can be connected to the transfer transistor circuit PTC of the outer peripheral layer PL. Furthermore, for example, the memory cell MCa_C2 of the second cell layer CL2 can be connected to the word line WLa_C2, and the word line WLa_C2 of the second cell layer CL2 can be connected to the transfer transistor circuit PTC of the outer peripheral layer PL. The transfer transistor circuit PTC of the outer peripheral layer PL can simultaneously drive the word line WLa_C1 of the first cell layer CL1 and the word line WLa_C2 of the second cell layer CL2.

[0083] In this situation, the word line WLa_C1 of the first cell layer CL1 and the word line WLa_C2 of the second cell layer CL2 cannot be controlled independently. Therefore, it is not possible to compensate for the differences in cell characteristics, word line load, and / or bit line load by controlling the word lines.

[0084] In this embodiment, bit line BL_C1 of the first unit layer CL1 can be connected to the first page buffer PB1, and bit line BL_C2 of the second unit layer CL2 can be connected to the second page buffer PB2. In this case, each of the first page buffer PB1 and the second page buffer PB2 can be controlled independently during core operations.

[0085] For example, the core operating conditions controlled by the first page buffer PB1 (such as the voltage level of bit line BL_C1 of the first cell layer CL1), the voltage application time of bit line BL_C1, or the sensing time can be set to differ from the core operating conditions controlled by the second page buffer PB2 (such as the voltage level of bit line BL_C2 of the second cell layer CL2), the voltage application time of bit line BL_C2, or the sensing time. Therefore, differences in cell characteristics, word line loads, and / or bit line loads between the first cell layer CL1 and the second cell layer CL2 can be compensated for during core operation.

[0086] Figure 5A It is shown that the formation according to the embodiment is in Figure 4 A circuit diagram of one of the multiple memory blocks in the first unit layer CL1. Figure 5B It is shown that the formation according to the embodiment is in Figure 4 A circuit diagram of one of the multiple memory blocks in the second unit layer CL2. For ease of description, assume that four strings are included in one memory block, and each string includes five memory cells.

[0087] Reference Figure 5AThe memory block BLK1_C1 of the first unit layer CL1 may include multiple strings STR1_C1 to STR4_C1 stacked vertically on the substrate. The multiple strings STR1_C1 to STR4_C1 may be arranged in a first direction (i.e., the X-axis direction) and a second direction (i.e., the Y-axis direction).

[0088] Strings belonging to the same column among multiple strings STR1_C1 to STR4_C1 can be connected to the same position line. For example, the first string STR1_C1 and the second string STR2_C1 can be connected to the first position line BL1_C1, and the third string STR3_C1 and the fourth string STR4_C1 can be connected to the second position line BL2_C1.

[0089] Each of the multiple strings STR1_C1 to STR4_C1 may include multiple unit transistors. Each of the multiple unit transistors may include a charge-trapping flash (CTF) memory cell, but the embodiment is not limited thereto. The multiple unit transistors may be stacked in a third direction (i.e., the Z-axis direction).

[0090] Multiple strings STR1_C1 to STR4_C1 can be connected together to the common-source line CSL_C1. For example, as follows Figure 5A As shown, the common source line CSL_C1 can be connected to the lower ends of multiple strings STR1_C1 to STR4_C1. However, this is provided as an example. It is sufficient if the common source line CSL_C1 is electrically connected to the lower ends of strings STR1_C1 to STR4_C1, and the embodiment is not limited to the case where the common source line CSL_C1 is physically located at the lower ends of strings STR1_C1 to STR4_C1. Hereinafter, for ease of description, the structure and construction of the strings will be described based on the first string STR1_C1.

[0091] Multiple unit transistors can be connected in series between the first bit line BL1_C1 and the common source line CSL_C1. For example, multiple unit transistors may include GIDL transistors GDT1_C1 and GDT2_C1, a string select transistor SST_C1, memory cells MC1_C1 to MC5_C1, a pseudo memory cell DMC_C1, and a ground select transistor GST_C1.

[0092] GIDL transistors GDT1_C1 and GDT2_C1 can be located at the lower and upper ends of string STR1_C1, respectively. For example, the first GIDL transistor GDT1_C1 can be connected to the common-source line CSL_C1 at the lower end of string STR1_C1. The second GIDL transistor GDT2_C1 can be connected to the first line BL1_C1 at the upper end of string STR1_C1. The gate of the first GIDL transistor GDT1_C1 can be connected to the first GIDL line GIDL1_C1, and the gate of the second GIDL transistor GDT2_C1 can be connected to the second GIDL line GIDL2_C1. However, this is provided as an example. According to embodiments, GIDL transistors can be located only at the upper end of string STR1_C1, or GIDL transistors can be located only at the lower end of string STR1_C1.

[0093] A string select transistor SST_C1 may be disposed between the fifth memory cell MC5_C1 and the second GIDL transistor GDT2_C1. The gate of the string select transistor SST_C1 may be connected to the string select line SSLa_C1. However, this is provided as an example. According to an embodiment, a plurality of string select transistors connected in series may be disposed between the fifth memory cell MC5_C1 and the second GIDL transistor GDT2_C1.

[0094] A ground selection transistor GST_C1 may be disposed between the pseudo memory cell DMC_C1 and the first GIDL transistor GDT1_C1. The gate of the ground selection transistor GST_C1 may be connected to the ground selection line GSLa_C1. However, this is provided as an example. According to an embodiment, a plurality of ground selection transistors connected in series may be disposed between the pseudo memory cell DMC_C1 and the first GIDL transistor GDT1_C1.

[0095] The first memory cell MC1_C1 to the fifth memory cell MC5_C1 can be connected in series between the serial select transistor SST_C1 and the pseudo memory cell DMC_C1. The gates of the first memory cell MC1_C1 to the fifth memory cell MC5_C1 can be connected to the first word line WL1_C1 to the fifth word line WL5_C1, respectively.

[0096] A pseudo-memory cell DMC_C1 may be disposed between the first memory cell MC1_C1 and the first GIDL transistor GDT1_C1. The gate of the pseudo-memory cell DMC_C1 may be connected to the pseudo-word line DWL_C1. However, this is provided as an example. According to an embodiment, multiple pseudo-memory cells connected in series may be disposed between the first memory cell MC1_C1 and the first GIDL transistor GDT1_C1. Alternatively, additional pseudo-memory cells may be disposed between the string select transistor SST_C1 and the fifth memory cell MC5_C1.

[0097] Reference Figure 5B The memory block BLK1_C2 of the second unit layer CL2 may include multiple strings STR1_C2 to STR4_C2 vertically stacked on the substrate. The construction and arrangement of each of the multiple strings STR1_C2 to STR4_C2 are consistent with reference to... Figure 5A Those descriptions are similar, and therefore, repeated descriptions will be omitted to avoid redundancy.

[0098] In an embodiment, the number of pseudo-word lines in the first unit layer CL1 can be equal to the number of pseudo-word lines in the second unit layer CL2.

[0099] In detail, due to the differences in the manufacturing processes of the first unit layer CL1 and the second unit layer CL2, the number of pseudo-character lines in the first unit layer CL1 may differ from the number of pseudo-character lines in the second unit layer CL2 for stable operation. For example, for stable operation, the first unit layer CL1 may require at least two pseudo-character lines, and the second unit layer CL2 may require at least three pseudo-character lines.

[0100] In this case, the number of pseudo-word lines in the first cell layer CL1 can be set to be equal to the number of pseudo-word lines in the second cell layer CL2, which has poor characteristics. That is, according to the embodiment, since the main word lines of the first cell layer CL1 and the second cell layer CL2 are connected to each other, the number of pseudo-word lines in the first cell layer CL1 can be set to be equal to the number of pseudo-word lines in the second cell layer CL2. Therefore, the memory device can operate stably regardless of the differences in cell characteristics between the first cell layer CL1 and the second cell layer CL2. Furthermore, according to the embodiment, each of the pseudo-word lines in the first cell layer CL1 and the second cell layer CL2 can be driven independently, and therefore, the memory device can operate stably regardless of the differences in cell characteristics between each layer.

[0101] Figure 6 It is used to describe the embodiments. Figure 4 A diagram of a PTC (Power Transistor) circuit. For convenience, please refer to... Figures 4 to 5BIn the above description, it is assumed that the first unit layer CL1 is connected to the first word line WL1_C1 to the fifth word line WL5_C1, and the second unit layer CL2 is connected to the first word line WL1_C2 to the fifth word line WL5_C2.

[0102] Reference Figures 4 to 6 The transmission transistor circuit PTC may include a first transmission transistor PT_WL1 to a fifth transmission transistor PT_WL5. The gates of the first transmission transistor PT_WL1 to the fifth transmission transistor PT_WL5 may be connected to the block word line BLKWL1.

[0103] A first terminal of the first transmission transistor PT_WL1 can be connected to the first word line WL1_C1 of the first cell layer CL1 and the first word line WL1_C2 of the second cell layer CL2. A second terminal of the first transmission transistor PT_WL1 can be connected to the first row line RL1. In response to the voltage level of the block word line BLKWL1, the first transmission transistor PT_WL1 can provide the voltage received from the voltage generator 160 to each of the first word lines WL1_C1 of the first cell layer CL1 and WL1_C2 of the second cell layer CL2.

[0104] As described above, the first terminal of the second transmission transistor PT_WL2 can be connected to the second word line WL2_C1 of the first cell layer CL1 and the second word line WL2_C2 of the second cell layer CL2. The second terminal of the second transmission transistor PT_WL2 can be connected to the second row line RL2. Similarly, the first terminal of the fifth transmission transistor PT_WL5 can be connected to the fifth word line WL5_C1 of the first cell layer CL1 and the fifth word line WL5_C2 of the second cell layer CL2. The second terminal of the fifth transmission transistor PT_WL5 can be connected to the fifth row line RL5.

[0105] Based on the above description, the word lines of the first cell layer CL1 and the corresponding word lines of the second cell layer CL2 can be driven simultaneously by the same transmission transistor. In this case, compared to driving the word lines of the first cell layer CL1 and the word lines of the second cell layer CL2 separately, the area used to implement the transmission transistor circuit can be reduced.

[0106] Because the word lines of the first cell layer CL1 and its corresponding second cell layer CL2 are driven simultaneously by the same transmission transistor, layer-specific characteristic differences cannot be compensated for by word lines. According to an embodiment, layer-specific characteristic differences can be compensated for by layer-specific independent control of the page buffer.

[0107] Figure 7A This illustrates an embodiment. Figure 4 The circuit diagram of the first page buffer PB1 is shown in the example. Figure 7BThis illustrates an embodiment. Figure 4 The circuit diagram for the second page buffer PB2 is shown in the example.

[0108] First, refer to Figure 7A The first page buffer PB1 can be electrically connected to the first bit line BL1_C1 of the first unit layer CL1.

[0109] The first page buffer PB1 may include multiple transistors NM1 to NM7 and a first latch L1.

[0110] The first transistor NM1 can be connected to the first bit line BL1_C1 of the first cell layer CL1. In response to the bit line cut-off signal BLSHF_C1, the first transistor NM1 can be electrically connected to or disconnected from the first bit line BL1_C1.

[0111] The second transistor NM2 can receive the power supply voltage VDD_C1. In response to the bit line clamping control signal BLCLAMP_C1, the second transistor NM2 can provide the power supply voltage VDD_C1 to the first bit line BL1_C1, or it can prevent the power supply voltage VDD_C1 from being provided to the first bit line BL1_C1. As described above, according to the embodiment, the voltage level and / or application time of the power supply voltage VDD_C1 can be changed according to the type of core operation, the cell characteristics of the relevant layer, etc.

[0112] The third transistor NM3 can be turned on or off in response to the bit line connection control signal CLBLK_C1. Therefore, a sensing operation can be performed. As described above, according to the embodiment, the application time of the bit line connection control signal CLBLK_C1 can be varied depending on the type of core operation, the cell characteristics of the relevant layer, etc.

[0113] The fourth transistor NM4 and the sixth transistor NM6 can be connected in series. The gate of the fourth transistor NM4 can be connected to the first terminal of the third transistor NM3, and the gate of the sixth transistor NM6 can be connected to the bit line reset signal RST_C1.

[0114] The fifth transistor NM5 and the seventh transistor NM7 can be connected in series. The gate of the fifth transistor NM5 can be connected to the bit line refresh signal REFRESH_C1, and the gate of the seventh transistor NM7 can be connected to the bit line set signal SET_C1.

[0115] During read or verification operations, the first latch L1 can store data to be stored in a memory cell via the first bit line BL1_C1, or the sensing result of a threshold voltage of the memory cell. Alternatively, according to an embodiment, during programming operations, the first latch L1 can be used to provide a bit line voltage or a programming disable voltage to the first bit line BL1_C1.

[0116] The following is for reference Figure 7B The second page buffer PB2 can be electrically connected to the first line BL1_C2 of the second unit layer CL2.

[0117] The second page buffer PB2 may include multiple transistors NM8 to NM14 and a second latch L2. The construction and operation of the second page buffer PB2 are similar to those of the first page buffer PB1, and therefore, repeated descriptions will be omitted to avoid redundancy.

[0118] In this embodiment, each of the first page buffer PB1 and the second page buffer PB2 can be controlled independently during core operations.

[0119] For example, in the same core operation, the application time and / or voltage level of at least one of the following signals to be provided to the first page buffer PB1—BLSHF_C1, BLCAMP_C1, VDD_C1, CLBLK_C1, SET_C1, RST_C1, and REFRESH_C1—may differ from the application time and / or voltage level of at least one of the following signals to be provided to the second page buffer PB2—BLSHF_C2, BLCAMP_C2, VDD_C2, CLBLK_C2, SET_C2, RST_C2, and REFRESH_C2.

[0120] In this case, according to the embodiment, each of the following two generators can be provided independently: a generator that generates the bit line cutoff signal BLSHF_C1, bit line clamp control signal BLCLAMP_C1, power supply voltage VDD_C1, bit line connection control signal CLBLK_C1, bit line set signal SET_C1, bit line reset signal RST_C1, or bit line refresh signal REFRESH_C1 to be provided to the first page buffer PB1; and a generator that generates the bit line cutoff signal BLSHF_C2, bit line clamp control signal BLCLAMP_C2, power supply voltage VDD_C2, bit line connection control signal CLBLK_C2, bit line set signal SET_C2, bit line reset signal RST_C2, or bit line refresh signal REFRESH_C2 to be provided to the second page buffer PB2.

[0121] As described above, in core operation, the reliability of the core operation of the memory device can be improved by independently controlling each of the first page buffer PB1 connected to the first cell layer CL1 and the second page buffer PB2 connected to the second cell layer CL2.

[0122] Figure 8 This is a flowchart describing the core operations of a memory device according to an embodiment.

[0123] During operation S110, the memory device can enter the core operation mode.

[0124] For example, a memory device can enter a mode for performing erase, program, verify, or read operations.

[0125] In operation S120, the memory device can independently control the page buffer corresponding to each layer based on layer-specific cell characteristic differences, layer-specific word line load differences, and / or layer-specific word line load differences.

[0126] For example, when the cell characteristics (such as the speed of the core operation of the memory cell) of the memory cell corresponding to the first layer are better than those of the memory cell corresponding to the second layer, the first page buffer corresponding to the first layer can be controlled by using hard core operation conditions, and the second page buffer corresponding to the second layer can be controlled by using soft core operation conditions.

[0127] In an embodiment, hard-core operating conditions can refer to conditions where the bit line voltage level or bit line application time is set such that erase, programming, verification, and read operations are performed relatively slowly. Soft-core operating conditions can refer to conditions where the bit line voltage level or bit line application time allows erase, programming, verification, and read operations to be performed relatively quickly. In this respect, erase, programming, verification, and read operations can be performed faster in soft-core operations than in hard-core operations.

[0128] As mentioned above, the reliability of core operations of a memory device can be improved by independently controlling the page buffers of each layer.

[0129] [Layer-specific control of pre-programmed operation conditions in erase operations]

[0130] Figures 9 to 11 This is a diagram illustrating the operating conditions of pre-programmed operations, which are set differently for each layer during an erasure operation according to an embodiment. In detail, Figure 9 This is a diagram illustrating an example of the differences in cell characteristics between the first cell layer CL1 and the second cell layer CL2. Figure 10 An example of a timing diagram is shown in which hard core operating conditions are applied to the first cell layer CL1 and soft core operating conditions are applied to the second cell layer CL2 in a pre-programmed operation. Figure 11This is a diagram illustrating an example of the channel voltage Vch when hard core operating conditions are applied to the first cell layer CL1 and soft core operating conditions are applied to the second cell layer CL2.

[0131] Reference Figure 9 The pre-programmed characteristics of the first cell layer CL1 and the second cell layer CL2, formed on different wafers, can be different. For example, as Figure 9 As shown, the memory cells of the first cell layer CL1 can be pre-programmed before the memory cells of the second cell layer CL2, and in this respect, they can have different threshold voltages. In this case, the reliability of the memory device operation may be reduced, or the performance of the memory device may be degraded.

[0132] To compensate for differences in specific layer characteristics, according to an embodiment, in a pre-programmed operation that is an erase operation, the first page buffer PB1 corresponding to the first unit layer CL1 can be controlled by using hard core operating conditions (see [link]). Figure 4 Furthermore, the second page buffer PB2 corresponding to the second unit layer CL2 can be controlled by using soft kernel operating conditions (see...). Figure 4 ).

[0133] In the embodiments, reference will be made to Figure 10 and Figure 11 A detailed description is provided. At time 0 t0, each of the string select line SSLa_C1, ground select line GSLa_C1, and first bit line BL1_C1 of the first unit layer CL1 can be set to ground (GND). Furthermore, each of the string select line SSLa_C2, ground select line GSLa_C2, and first bit line BL1_C2 of the second unit layer CL2 can be set to ground (GND). Additionally, all word lines of both the first and second unit layers CL1 and CL2 can be set to ground (GND).

[0134] At the first time point t1, both the string selection line SSLa_C1 of the first unit layer CL1 and the string selection line SSLa_C2 of the second unit layer CL2 can be converted into the string selection voltage VSSL. In this case, the first string STR1_C1 of the first unit layer CL1 can be selected (see...). Figure 4 ) and the first string STR1_C2 of the second unit layer CL2 (see Figure 4 Furthermore, at the first time point t1, all word lines of the first cell layer CL1 and the second cell layer CL2 can be converted to the first transmission voltage VPASS1.

[0135] At the second time point t2, the first line BL1_C1 of the first unit layer CL1 can be transformed into the first line voltage VBL1.

[0136] At the third time point t3, the selected word line among the word lines of the first cell layer CL1 and the second cell layer CL2 can be converted to the pre-programmed voltage VPPGM. In this case, refer to Figure 11 In the second cell layer CL2, the gate-source voltage VGS2 of the memory cell corresponding to the selected word lines WL1_C2 to WL3_C2 can correspond to the pre-programming voltage VPPGM. Conversely, the gate-source voltage VGS1 of the memory cell corresponding to the selected word lines WL1_C1 to WL3_C1 in the first cell layer CL1 can correspond to the voltage level obtained by subtracting the first line voltage VBL1 from the pre-programming voltage VPPGM.

[0137] Therefore, in the pre-programming operation, the memory cells of the second cell layer CL2, which has poor cell characteristics, can be pre-programmed relatively quickly, while the memory cells of the first cell layer CL1, which has good cell characteristics, can be pre-programmed relatively slowly.

[0138] As a result, the differences in cell characteristics between the first cell layer CL1 and the second cell layer CL2 can be compensated by applying different levels of bit line voltage to the first cell layer CL1 and the second cell layer CL2.

[0139] Continue to refer to Figure 10 At the fourth time point t4, the string selection lines SSLa_C1 and SSLa_C2 and word lines of the first unit layer CL1 and the second unit layer CL2, as well as the first bit line BL1_C1 of the first unit layer CL1, can be converted to ground GND, and thus, the preprogramming operation can be terminated.

[0140] exist Figure 10 The text describes how characteristic differences can be compensated by setting different bit line voltage levels for the first cell layer CL1 and the second cell layer CL2. However, this is provided as an example, and the embodiments are not limited thereto. According to the embodiments, in addition to the bit line voltage levels of the first cell layer CL1 and the second cell layer CL2, layer-specific characteristic differences can also be compensated by setting different application times for the bit line voltage levels. For example, during pre-programming operations, the bit line voltage can be applied to the first cell layer CL1, which has good cell characteristics, for a relatively long time, and the bit line voltage can be applied to the second cell layer CL2, which has poor cell characteristics, for a relatively short time.

[0141] Figure 12 This is a flowchart describing the pre-programming operations performed in an erase operation of a memory device according to an embodiment.

[0142] During operation S210, the memory device can enter the pre-programming mode during the erase operation.

[0143] In operation S220, the memory device can independently set at least one of the bit line voltage to be provided to each layer and the application time of the bit line voltage based on layer-specific memory cell characteristic differences, layer-specific word line load differences and / or layer-specific bit line load differences.

[0144] For example, the characteristics of the first layer can be relatively better than those of the second layer. In this case, a relatively large bit line voltage can be provided to the bit line corresponding to the first layer through the first page buffer, and a relatively small bit line voltage can be provided to the bit line corresponding to the second layer through the second page buffer. Therefore, layer-specific characteristic differences can be compensated for in pre-programming operations.

[0145] [Layer-specific control of verification operation conditions during erase operation]

[0146] Figure 13 and Figure 14 This is a diagram illustrating the verification operation conditions set differently for each layer during the erasure operation according to an embodiment. In detail, Figure 13 This is a diagram used to describe the problems in the verification operation caused by the difference in cell characteristics between the first cell layer CL1 and the second cell layer CL2. Figure 14 An example of a timing diagram is shown in which hard core operating conditions are applied to the first cell layer CL1 and soft core operating conditions are applied to the second cell layer CL2 during the erase verification operation.

[0147] Reference Figure 13 The erase operation characteristics of the first unit layer CL1 and the second unit layer CL2 formed on different wafers can be different. For example, as Figure 13 As shown, during the erase operation, the threshold voltage change width of the memory cell in the first cell layer CL1 can be greater than the threshold voltage change width of the memory cell in the second cell layer CL2.

[0148] In this scenario, to verify the erase operation, different verification voltages Vvfy1 and Vvfy2 should be applied to the memory cells of the first cell layer CL1 and the second cell layer CL2. Therefore, the verification operation must be performed twice, leading to a degradation in the performance of the memory device.

[0149] To compensate for differences in specific layer characteristics, according to an embodiment, in the erase verification operation mode, the first page buffer PB1 corresponding to the first unit layer CL1 can be controlled by using hard core operation conditions (see [link]). Figure 4 Furthermore, the second page buffer PB2 corresponding to the second unit layer CL2 can be controlled by using soft kernel operating conditions (see...). Figure 4 Therefore, the same verification voltage can be used to perform verification operations on both the first cell layer CL1 and the second cell layer CL2 simultaneously.

[0150] In the embodiments, reference will be made to Figure 7A , Figure 7B and Figure 14 A detailed description is provided: at time point t0, all of the serial select lines, ground select lines, and bit lines of the first unit layer CL1 and the second unit layer CL2 can be set to ground (GND). Furthermore, the first bit line connection control signal CLBLK_C1 to be provided to the first page buffer PB1 and the second bit line connection control signal CLBLK_C2 to be provided to the second page buffer PB2 can both be set to ground (GND).

[0151] At the first time point t1, the selected serial select line in the first unit layer CL1 and the second unit layer CL2 can be converted into the first read voltage VREAD1, and the unselected serial select line in the first unit layer CL1 and the second unit layer CL2 can be converted into the second read voltage VREAD2. The selected ground select line in the first unit layer CL1 and the second unit layer CL2 can be converted into the first read voltage VREAD1, and the unselected ground select line in the first unit layer CL1 and the second unit layer CL2 can be converted into the second read voltage VREAD2.

[0152] The word lines of the first cell layer CL1 and the second cell layer CL2 can be converted into the verification voltage Vvfy.

[0153] At the second time point t2, the unselected serial selection line among the serial selection lines of the first unit layer CL1 and the second unit layer CL2 can be converted to ground GND. The unselected ground selection line among the ground selection lines of the first unit layer CL1 and the second unit layer CL2 can be converted to ground GND.

[0154] Furthermore, at the second time point t2, the first bit line BL1_C1 of the first unit layer CL1 can be transformed into the first bit line voltage VBL1_C1, and the first bit line BL1_C2 of the second unit layer CL2 can be transformed into the second bit line voltage VBL1_C2. That is, the first bit line BL1_C1 of the first unit layer CL1 can be pre-charged with the first bit line voltage VBL1_C1, and the first bit line BL1_C2 of the second unit layer CL2 can be pre-charged with the second bit line voltage VBL1_C2.

[0155] In this case, the first bit line voltage VBL1_C1 provided to the first cell layer CL1 with good layer characteristics can be lower than the second bit line voltage VBL1_C2 provided to the second cell layer CL2 with poor layer characteristics. That is, hard verification operating conditions can be applied to the first cell layer CL1, and soft verification operating conditions can be applied to the second cell layer CL2.

[0156] Therefore, during the erase verification operation, a relatively small current can be generated in the string of the first cell layer CL1 with good layer characteristics, while a relatively large current can be generated in the string of the second cell layer CL2 with poor layer characteristics. Based on the above description, the same verification operation can be used to simultaneously perform the verification operation for the first cell layer CL1 with good characteristics and the verification operation for the second cell layer CL2 with poor characteristics.

[0157] Continue to refer to Figure 14 At the third time point t3, the first bit line BL1_C1 of the first unit layer CL1 can be transformed into the bit line voltage VBL2_C1, and at the fourth time point t4, the first bit line BL1_C2 of the second unit layer CL2 can be transformed into the bit line voltage VBL2_C2.

[0158] In this case, the application time of the first bit line voltage VBL1_C1 provided to the first cell layer CL1 with good layer characteristics can be shorter than the application time of the second bit line voltage VBL1_C2 provided to the second cell layer CL2 with poor layer characteristics. That is, hard verification operating conditions can be applied to the first cell layer CL1, and soft verification operating conditions can be applied to the second cell layer CL2.

[0159] Therefore, during the erase verification operation, a relatively small current can be generated in the string of the first cell layer CL1 with good characteristics, and a relatively large current can be generated in the string of the second cell layer CL2 with poor characteristics. Based on the above description, the same verification operation can be used to simultaneously perform the verification operation for the first cell layer CL1 with good characteristics and the verification operation for the second cell layer CL2 with poor characteristics.

[0160] At the fifth time point t5, each of the first bit line connection control signal CLBLK_C1 provided to the first page buffer PB1 of the first unit layer CL1 and the second bit line connection control signal CLBLK_C2 provided to the second page buffer PB2 of the second unit layer CL2 can be activated, and thus, sensing operation can be initiated.

[0161] At time point t6, the first bit line connection control signal CLBLK_C1 provided to the first page buffer PB1 of the first unit layer CL1 can be activated, and thus the sensing operation can be terminated. At time point t7, the second bit line connection control signal CLBLK_C2 provided to the second page buffer PB2 of the second unit layer CL2 can be activated, and thus the sensing operation can be terminated.

[0162] In this case, the sensing time T3 corresponding to the first unit layer CL1 with good layer characteristics can be shorter than the sensing time T4 corresponding to the second unit layer CL2 with poor layer characteristics. That is, hard verification operation conditions can be applied to the first unit layer CL1, and soft verification operation conditions can be applied to the second unit layer CL2. According to the above description, the verification operation for the first unit layer CL1 with good characteristics and the verification operation for the second unit layer CL2 with poor characteristics can be performed simultaneously using the same verification operation.

[0163] At time point t8, the serial select line, ground select line, word line, and bit line of the first unit layer CL1 and the second unit layer CL2 can be converted to ground GND, and the verification operation associated with the erase operation can be terminated.

[0164] For convenience, Figure 14 The present invention provides a complete description of methods for setting different bit line voltage levels for each layer, methods for setting different bit line voltage application times for each layer, and methods for setting different sensing times for each layer. However, this is provided as an example. According to embodiments, at least one of the above methods can be applied.

[0165] Figure 15 This is a flowchart describing the verification operations performed during an erase operation of a memory device according to an embodiment.

[0166] In operation S310, the memory device can enter verification mode during the erase operation.

[0167] In operation S320, the memory device can independently set at least one of the following: the bit line voltage applied to the bit line corresponding to each layer, the application time of the bit line voltage, and the sensing time, based on layer-specific cell characteristic differences, layer-specific word line load differences, and / or layer-specific bit line load differences.

[0168] For example, the characteristics of memory cells in the first layer can be relatively better compared to those in the second layer. In this case, the bit lines corresponding to the first layer can be precharged with a relatively low voltage compared to those corresponding to the second layer. Alternatively, the bit lines corresponding to the first layer can be precharged for a relatively short period of time compared to those corresponding to the second layer. Alternatively, the sensing time corresponding to the first layer can be relatively short compared to that corresponding to the second layer. Therefore, the differences in cell characteristics can be compensated for in the verification operation associated with the erase operation.

[0169] [Layer-specific control of programming operation conditions]

[0170] Figure 16 and Figure 17This is a diagram illustrating the programming operation conditions set differently for each layer according to an embodiment. In detail, Figure 16 This example illustrates a timing diagram in which hard core operating conditions are applied to the first cell layer CL1, which has good cell characteristics, and soft core operating conditions are applied to the second cell layer CL2, which has poor cell characteristics, during programming operations. Figure 17 This is a diagram illustrating an example of the channel voltage Vch when hard core operating conditions are applied to the first cell layer CL1 and soft core operating conditions are applied to the second cell layer CL2.

[0171] Refer to Figure 16 and Figure 17 The described programming operations and references Figures 9 to 11 The pre-programmed operations described are similar, and therefore, repeated descriptions will be omitted to avoid redundancy. For ease of description, it is hereby assumed that the bit line forced voltage is provided to both the first bit line BL1_C1 of the first cell layer CL1 and the first bit line BL1_C2 of the second cell layer CL2.

[0172] Reference Figure 16 At time 0 t0, each of the string select line SSLa_C1, ground select line GSLa_C1, and first bit line BL1_C1 of the first cell layer CL1 can be set to ground GND. Furthermore, each of the string select line SSLa_C2, ground select line GSLa_C2, and first bit line BL1_C2 of the second cell layer CL2 can be set to ground GND. Additionally, all word lines of the first cell layer CL1 and the second cell layer CL2 can be set to ground GND. Furthermore, a programming disable voltage VINHB can be provided to the bit line corresponding to the programming disabled string, and the bit line corresponding to the programming requested string can be set to ground GND.

[0173] At the first time point t1, both the string selection line SSLa_C1 of the first unit layer CL1 and the string selection line SSLa_C2 of the second unit layer CL2 can be converted into the string selection voltage VSSL. In this case, the first string STR1_C1 of the first unit layer CL1 can be selected (see...). Figure 4 ) and the first string STR1_C2 of the second unit layer CL2 (see Figure 4 Furthermore, at the first time point t1, unselected word lines in the word lines of the first cell layer CL1 and the second cell layer CL2 can be converted to the first transmission voltage VPASS1, and selected word lines in the word lines of the first cell layer CL1 and the second cell layer CL2 can be converted to the second transmission voltage VPASS2.

[0174] At the second time point t2, the first bit line BL1_C1 of the first unit layer CL1 can be transformed into the first bit line forced voltage VFC1, and the first bit line BL1_C2 of the second unit layer CL2 can be transformed into the second bit line forced voltage VFC2.

[0175] In this case, the first bit line forced voltage VFC1 provided to the first cell layer CL1, which has good layer characteristics, can be relatively higher than the second bit line forced voltage VFC2 provided to the second cell layer CL2, which has poor layer characteristics. That is, hard programming operating conditions can be applied to the first cell layer CL1, and soft programming operating conditions can be applied to the second cell layer CL2.

[0176] At the third time point t3, the selected word line can be converted to the programming voltage VPGM.

[0177] In this case, refer to Figure 17 Because the second bit-line forced voltage VFC2 is provided to the first bit line BL1_C2 of the second cell layer CL2, the gate-source voltage VGS2 of the memory cell corresponding to the selected word line WL3_C2 can correspond to the voltage level obtained by subtracting the second bit-line forced voltage VFC2 from the programming voltage VPGM. Because the first bit-line forced voltage VFC1 is provided to the first bit line BL1_C1 of the first cell layer CL1, the gate-source voltage VGS1 of the memory cell corresponding to the selected word line WL3_C1 can correspond to the voltage level obtained by subtracting the first bit-line forced voltage VFC1 from the programming voltage VPGM.

[0178] In this case, because the first bit forced voltage VFC1 is greater than the second bit forced voltage VFC2, a relatively low programming voltage can be provided to the selected memory cell of the first cell layer CL1 with good characteristics, and a relatively high programming voltage can be provided to the selected memory cell of the second cell layer CL2 with poor characteristics.

[0179] Based on the above description, the characteristic differences between the first unit layer CL1 and the second unit layer CL2 can be compensated by applying bit line forced voltages of different levels to the first unit layer CL1 and the second unit layer CL2.

[0180] At the fourth time point t4, the string selection lines SSLa_C1 and SSLa_C2 and word lines of the first unit layer CL1 and the second unit layer CL2, as well as the first bit line BL1_C1 of the first unit layer CL1, can be converted to ground GND, and thus, the programming operation can be terminated.

[0181] Figure 18 This is a flowchart describing the programming operations of a memory device according to an embodiment.

[0182] During operation S410, the memory device can enter the execution mode of programming operation.

[0183] In operation S420, the memory device can independently set at least one of the bit line forced voltage to be provided to each layer and the application time of the bit line forced voltage based on layer-specific cell characteristic differences, layer-specific word line load differences and / or layer-specific bit line load differences.

[0184] For example, the characteristics of memory cells in the first layer can be relatively better than those in the second layer. In this case, a relatively large bit line forced voltage can be provided to the bit lines corresponding to the first layer through the first page buffer, and a relatively small bit line forced voltage can be provided to the bit lines corresponding to the second layer through the second page buffer. Alternatively, the bit line forced voltage can be provided to the bit lines corresponding to the first layer through the first page buffer for a relatively long period of time, and the bit line forced voltage can be provided to the bit lines corresponding to the second layer through the second page buffer for a relatively short period of time. Therefore, the differences in cell characteristics can be compensated for during programming operations.

[0185] [Layer-specific control of validation operation conditions in programming validation operations]

[0186] Figure 19 and Figure 20 This is a diagram illustrating the verification operation conditions set differently for each layer in the programming verification operation according to an embodiment. In detail, Figure 19 This is a diagram used to describe the problem of programming verification operation caused by the difference in word line load between the first unit layer CL1 and the second unit layer CL2. Figure 20 An example of a timing diagram is shown in which hard core operating conditions are applied to the first unit layer CL1 and soft core operating conditions are applied to the second unit layer CL2 in a programming verification operation.

[0187] Refer to Figure 19 and Figure 20 The described programming verification operations and references Figure 13 and Figure 14 The erase verification operations described are similar, and therefore, repeated descriptions will be omitted to avoid redundancy.

[0188] Reference Figure 4 and Figure 19 The first unit layer CL1 can be stacked on the outer peripheral layer PL, and the second unit layer CL2 can be stacked on the first unit layer CL1. Therefore, the word line length corresponding to the first unit layer CL1 can be shorter than the word line length corresponding to the second unit layer CL2. In this respect, the word line load time corresponding to the first unit layer CL1 can be shorter than the word line load time corresponding to the second unit layer CL2.

[0189] In this case, such as Figure 19 As shown, at the first time point t1 when the sensing operation is terminated, the word lines of the first cell layer CL1, which has good word line load characteristics, can be loaded, but the word lines of the second cell layer CL2, which has poor word line load characteristics, may not be loaded. This leads to a decrease in the reliability of the memory device.

[0190] To compensate for differences in word line load characteristics specific to a layer, according to an embodiment, during the programming verification operation, the first page buffer PB1 corresponding to the first unit layer CL1 can be controlled using hard core operating conditions (see [link]). Figure 4 Furthermore, the second page buffer PB2 corresponding to the second unit layer CL2 can be controlled by using soft kernel operating conditions (see...). Figure 4 Therefore, the reliability of programming verification operations can be improved.

[0191] In the embodiments, reference will be made to Figure 7A , Figure 7B and Figure 20 A detailed description is provided. At time 0 t0, all word lines and bit lines of the first unit layer CL1 and the second unit layer CL2 can be set to ground (GND). Furthermore, the first bit line connection control signal CLBLK_C1 to be provided to the first page buffer PB1 and the second bit line connection control signal CLBLK_C2 to be provided to the second page buffer PB2 can both be set to ground (GND).

[0192] At the first time point t1, the unselected word lines in the word lines of the first cell layer CL1 and the second cell layer CL2 can be converted into the first read voltage VREAD1, and the selected word lines in the word lines of the first cell layer CL1 and the second cell layer CL2 can be converted into the verification voltage Vvfy.

[0193] At the second time point t2, the first bit line BL1_C1 of the first unit layer CL1 can be transformed into the first bit line voltage VBL1_C1, and the first bit line BL1_C2 of the second unit layer CL2 can be transformed into the second bit line voltage VBL1_C2. That is, the first bit line BL1_C1 of the first unit layer CL1 can be pre-charged with the first bit line voltage VBL1_C1, and the first bit line BL1_C2 of the second unit layer CL2 can be pre-charged with the second bit line voltage VBL1_C2.

[0194] In this case, the first bit line voltage VBL1_C1 provided to the first cell layer CL1, which has good word line load characteristics, can be lower than the second bit line voltage VBL1_C2 provided to the second cell layer CL2, which has poor word line load characteristics. That is, hard programming verification operation conditions can be applied to the first cell layer CL1, and soft programming verification operation conditions can be applied to the second cell layer CL2. Therefore, the reliability of programming verification operation can be improved.

[0195] Continue to refer to Figure 20 At the third time point t3, the first bit line BL1_C1 of the first unit layer CL1 can be transformed into the bit line voltage VBL2_C1, and at the fourth time point t4, the first bit line BL1_C2 of the second unit layer CL2 can be transformed into the bit line voltage VBL2_C2.

[0196] In this case, the application time T1 of the first bit line voltage VBL1_C1, which has good word line load characteristics, can be shorter than the application time T2 of the second bit line voltage VBL1_C2 provided to the second cell layer CL2, which has poor word line load characteristics. That is, hard programming verification operation conditions can be applied to the first cell layer CL1, and soft programming verification operation conditions can be applied to the second cell layer CL2. Therefore, the reliability of the programming verification operation can be improved.

[0197] At the fifth time point t5, each of the first bit line connection control signal CLBLK_C1 provided to the first page buffer PB1 of the first unit layer CL1 and the second bit line connection control signal CLBLK_C2 provided to the second page buffer PB2 of the second unit layer CL2 can be activated, and thus, coarse sensing operation can be initiated.

[0198] At time point t6, the first bit line connection control signal CLBLK_C1 provided to the first page buffer PB1 of the first unit layer CL1 can be activated, and thus, the coarse sensing operation on the first bit line BL1_C1 can be terminated. At time point t7, the second bit line connection control signal CLBLK_C2 provided to the second page buffer PB2 of the second unit layer CL2 can be activated, and thus, the coarse sensing operation can be terminated.

[0199] In this case, the coarse sensing time T3 corresponding to the first cell layer CL1 with good word line load characteristics can be shorter than the coarse sensing time T4 corresponding to the second cell layer CL2 with poor word line load characteristics. That is, hard programming verification operation conditions can be applied to the first cell layer CL1, and soft programming verification operation conditions can be applied to the second cell layer CL2. Therefore, the reliability of coarse programming sensing operation can be improved.

[0200] At the eighth time point t8, each of the first bit line connection control signal CLBLK_C1 provided to the first page buffer PB1 of the first unit layer CL1 and the second bit line connection control signal CLBLK_C2 provided to the second page buffer PB2 of the second unit layer CL2 can be activated, and thus, fine sensing operation can be initiated.

[0201] At time point t9, the first bit line connection control signal CLBLK_C1 provided to the first page buffer PB1 of the first unit layer CL1 can be activated, and thus, the fine sensing operation on the first bit line BL1_C1 can be terminated. At time point t10, the second bit line connection control signal CLBLK_C2 provided to the second page buffer PB2 of the second unit layer CL2 can be activated, and thus, the fine sensing operation on the first bit line BL1_C2 can be terminated.

[0202] In this case, the fine sensing time T5 corresponding to the first cell layer CL1 with good word line load characteristics can be shorter than the fine sensing time T6 corresponding to the second cell layer CL2 with poor word line load characteristics. That is, hard programming verification operation conditions can be applied to the first cell layer CL1, and soft programming verification operation conditions can be applied to the second cell layer CL2. Therefore, the reliability of fine programming sensing operation can be improved.

[0203] At time point 11, the string select line, ground select line, word line, and bit line of the first unit layer CL1 and the second unit layer CL2 can be converted to ground GND, and the programming verification operation can be terminated.

[0204] For convenience, Figure 20 The document provides a complete description of methods for applying different bit line voltage levels for each layer, methods for applying different bit line voltage application times for each layer, and methods for setting different coarse sensing times and fine sensing times for each layer. However, this is provided as an example. According to embodiments, at least one of the above methods can be applied.

[0205] Figure 21 This is a flowchart describing the programming verification operation of a memory device according to an embodiment.

[0206] In operation S510, the memory device can enter programming verification mode during programming operations.

[0207] In operation S520, the memory device can independently set at least one of the following: bit line voltage, bit line voltage application time, coarse sensing time, and fine sensing time corresponding to each layer, based on layer-specific cell characteristic differences, layer-specific word line load differences, and / or layer-specific bit line load differences.

[0208] Therefore, differences in word line load characteristics specific to a layer can be compensated for during programming verification operations.

[0209] [Layer-specific control over read operation conditions]

[0210] Figure 22 The diagram illustrates a timing diagram of applying hard core operating conditions to the first cell layer CL1 and soft core operating conditions to the second cell layer CL2 during a read operation, according to an embodiment.

[0211] Refer to Figure 22 The described read operation and reference Figure 19 and Figure 20 The described programming verification operations are similar, and therefore, repeated descriptions will be omitted to avoid redundancy.

[0212] As mentioned above, the reliability of read operations may be reduced due to differences in layer-specific word line load characteristics. To compensate for these differences, according to an embodiment, during a read operation, the first page buffer PB1 corresponding to the first unit layer CL1 can be controlled using hard core operating conditions (see [link to embodiment]). Figure 4 Furthermore, the second page buffer PB2 corresponding to the second unit layer CL2 can be controlled by using soft kernel operating conditions (see...). Figure 4 Therefore, the reliability of read operations can be improved.

[0213] In the embodiments, reference will be made to Figure 7A , Figure 7B and Figure 22 A detailed description is provided. At time 0 t0, all word lines and bit lines of the first unit layer CL1 and the second unit layer CL2 can be set to ground (GND). Furthermore, the first bit line connection control signal CLBLK_C1 to be provided to the first page buffer PB1 and the second bit line connection control signal CLBLK_C2 to be provided to the second page buffer PB2 can both be set to ground (GND).

[0214] At the first time point t1, the unselected word lines in the word lines of the first cell layer CL1 and the second cell layer CL2 can be converted into the first read voltage VREAD1, and the selected word lines in the word lines of the first cell layer CL1 and the second cell layer CL2 can be converted into the read voltage VRD.

[0215] At the second time point t2, the first bit line BL1_C1 of the first unit layer CL1 can be transformed into the first bit line voltage VBL1_C1, and the first bit line BL1_C2 of the second unit layer CL2 can be transformed into the second bit line voltage VBL1_C2. That is, the first bit line BL1_C1 of the first unit layer CL1 can be pre-charged with the first bit line voltage VBL1_C1, and the first bit line BL1_C2 of the second unit layer CL2 can be pre-charged with the second bit line voltage VBL1_C2.

[0216] In this case, the first bit line voltage VBL1_C1 provided to the first cell layer CL1, which has good word line load characteristics, can be lower than the second bit line voltage VBL1_C2 provided to the second cell layer CL2, which has poor word line load characteristics. Therefore, the reliability of the programming verification operation can be improved.

[0217] Continue to refer to Figure 22 At the third time point t3, the first bit line BL1_C1 of the first unit layer CL1 can be transformed into the bit line voltage VBL2_C1, and at the fourth time point t4, the first bit line BL1_C2 of the second unit layer CL2 can be transformed into the bit line voltage VBL2_C2.

[0218] In this case, the application time T1 of the first bit line voltage VBL1_C1, which has good word line load characteristics, can be shorter than the application time T2 of the second bit line voltage VBL1_C2 provided to the second cell layer CL2, which has poor word line load characteristics. Therefore, the reliability of the programming verification operation can be improved.

[0219] At the fifth time point t5, each of the first bit line connection control signal CLBLK_C1 provided to the first page buffer PB1 of the first unit layer CL1 and the second bit line connection control signal CLBLK_C2 provided to the second page buffer PB2 of the second unit layer CL2 can be activated, and thus, sensing operation can be initiated.

[0220] At time point t6, the first bit line connection control signal CLBLK_C1 provided to the first page buffer PB1 of the first unit layer CL1 can be activated, and thus, the sensing operation on the first bit line BL1_C1 can be terminated. At time point t7, the second bit line connection control signal CLBLK_C2 provided to the second page buffer PB2 of the second unit layer CL2 can be activated, and thus, the sensing operation can be terminated.

[0221] In this case, the sensing time T3 corresponding to the first cell layer CL1, which has good word line load characteristics, can be shorter than the sensing time T4 corresponding to the second cell layer CL2, which has poor word line load characteristics. Therefore, the reliability of the programmable sensing operation can be improved.

[0222] At time point t8, the serial select line, ground select line, word line, and bit line of the first unit layer CL1 and the second unit layer CL2 can be converted to ground GND, and the programming verification operation can be terminated.

[0223] For convenience, Figure 22 The present invention provides a complete description of a method for setting the voltage level of the precharge bit line voltage differently for each layer, a method for setting the application time of the precharge bit line voltage differently for each layer, and a method for setting the sensing time differently for each layer. However, this is provided as an example. According to embodiments, at least one of the above methods can be applied.

[0224] Figure 23 This is a flowchart describing a read operation of a memory device according to an embodiment.

[0225] In operation of S610, the memory device can enter read operation mode.

[0226] In operation S620, the memory device can independently set at least one of the following based on layer-specific cell characteristic differences, layer-specific word line load differences, and / or layer-specific bit line load differences: the bit line voltage corresponding to each layer, the bit line voltage application time, and the sensing time.

[0227] Therefore, during read operations, differences in layer-specific word line load characteristics can be compensated for.

[0228] exist Figures 4 to 23 Various embodiments for compensating for layer characteristic differences by independently controlling the page buffer for each layer are described herein. However, this is provided as an example, and the embodiments are not limited thereto. For example, in one embodiment, layer characteristic differences can be compensated for by independently controlling word lines other than the main word line for each layer. This will be explained in the following references. Figures 24 to 27 Describe in detail.

[0229] [Word lines other than the main word line, which are controlled independently for each layer]

[0230] Figure 24 It is used to conceptually describe the embodiments. Figure 2 A cross-sectional view of an embodiment of a memory device. As referenced above... Figure 4 In the given description, it is assumed that Figure 24 The memory device 1100B is implemented by bonding three chips, and the memory cell array is implemented using two chips. The bit line BL_C1 of the first cell layer CL1 is connected to the first page buffer PB1, and the bit line BL_C2 of the second cell layer CL2 is connected to the second page buffer PB2.

[0231] Figure 24 The structure of the memory device 1100B and Figure 4 The construction of the memory device 1100A is similar, and therefore, repeated descriptions will be omitted to avoid redundancy.

[0232] Reference Figure 24 When viewed in the vertical direction, the memory device 1100B may include an outer peripheral layer PL, a first cell layer CL1, and a second cell layer CL2.

[0233] The transfer transistor circuit PTC can be formed in the outer peripheral layer PL. The transfer transistor circuit PTC may include a first transfer transistor 11 to a fifth transfer transistor 15.

[0234] The first transmission transistor 11 can be connected to the word line WLa_C1 of the first cell layer CL1 and the word line WLa_C2 of the second cell layer CL2. Therefore, in core operation, the word line WLa_C1 of the first cell layer CL1 and the word line WLa_C2 of the second cell layer CL2 can be driven simultaneously.

[0235] The second transmission transistor 12 can be electrically connected to the second GIDL line GIDL2_C1 of the first cell layer CL1.

[0236] The third transmission transistor 13 can be electrically connected to the first GIDL line GIDL1_C1 of the first cell layer CL1.

[0237] The fourth transmission transistor 14 can be electrically connected to the second GIDL line GIDL2_C2 of the second unit layer CL2.

[0238] The fifth transmission transistor 15 can be electrically connected to the first GIDL line GIDL1_C2 of the second unit layer CL2.

[0239] In the core operation, the control of the first GIDL line GIDL1_C1 and the second GIDL line GIDL2_C1 of the first unit layer CL1, and the control of the first GIDL line GIDL1_C2 and the second GIDL line GIDL2_C2 of the second unit layer CL2, can be executed independently of each other. Therefore, for example, in the GIDL erase operation, the float time of the GIDL lines can be variable, and thus, layer-specific characteristic differences can be compensated for.

[0240] Figure 25 It is used to describe the embodiments. Figure 24 A diagram of the PTC (Power Transistor) circuit. For ease of description, in... Figure 25The following two types of transmission transistors are shown as examples: a transmission transistor connected to the first GIDL line GIDL1_C1 and the second GIDL line GIDL2_C1 of the first cell layer CL1 and the first GIDL line GIDL1_C2 and the second GIDL line GIDL2_C2 of the second cell layer CL2, and a transmission transistor that is connected to the third word line WL3_C1 of the first cell layer CL1 and the third word line WL3_C2 of the second cell layer CL2.

[0241] Reference Figure 25 The transfer transistor circuit PTC may include multiple transfer transistors PT_WL3, PT_GIDL1_C1, PT_GIDL2_C1, PT_GIDL1_C2, and PT_GIDL2_C2. The gates of the multiple transfer transistors PT_WL3, PT_GIDL1_C1, PT_GIDL2_C1, PT_GIDL1_C2, and PT_GIDL2_C2 may be connected to the block word line BLKWL.

[0242] The first terminal of the transfer transistor PT_WL3 can be connected to the third word line WL3_C1 of the first cell layer CL1 and the third word line WL3_C2 of the second cell layer CL2. The second terminal of the transfer transistor PT_WL3 can be connected to the third row line RL3. In response to the voltage level of the block word line BLKWL, the transfer transistor PT_WL3 can provide the voltage received from the voltage generator 160 to each of the third word lines WL3_C1 of the first cell layer CL1 and WL3_C2 of the second cell layer CL2 via the third row line RL3.

[0243] The first terminal of the transmission transistor PT_GIDL1_C1 can be connected to the first GIDL line GIDL1_C1 of the first cell layer CL1, and the second terminal of the transmission transistor PT_GIDL1_C1 can be connected to the row line RL_GIDL1_C1. The first GIDL line GIDL1_C1 of the first cell layer CL1 can be driven independently by the transmission transistor PT_GDIL1_C1.

[0244] As described above, the first terminal of the transmission transistor PT_GIDL2_C1 can be connected to the second GIDL line GIDL2_C1 of the first cell layer CL1, and the second terminal of the transmission transistor PT_GIDL2_C1 can be connected to the row line RL_GIDL2_C1. The first terminal of the transmission transistor PT_GIDL1_C2 can be connected to the first GIDL line GIDL1_C2 of the second cell layer CL2, and the second terminal of the transmission transistor PT_GIDL1_C2 can be connected to the row line RL_GIDL1_C2. The first terminal of the transmission transistor PT_GIDL2_C2 can be connected to the second GIDL line GIDL2_C2 of the second cell layer CL2, and the second terminal of the transmission transistor PT_GIDL2_C2 can be connected to the row line RL_GIDL2_C2. Each of the transmission transistors PT_WL3, PT_GIDL1_C1, PT_GIDL2_C1, PT_GIDL1_C2, and PT_GIDL2_C2 can independently drive its corresponding GIDL line.

[0245] According to an embodiment, layer-specific characteristic differences can be compensated for through layer-specific independent control of the GIDL line.

[0246] Figure 26 This is a timing diagram illustrating a GIDL erase operation according to an embodiment, where changing the float time compensates for differences in layer-specific characteristics. For ease of description, it is hereby assumed that the characteristics of the first cell layer CL1 are inferior compared to the second cell layer CL2.

[0247] Reference Figures 24 to 26 At time t0, bit lines, common source pole lines, GIDL lines, row lines, etc., can be set to ground (GND).

[0248] At the first time point t1, the voltage supplied through the common-source line CSL and the bit line BL can begin to increase. For example, the voltage supplied through the common-source line CSL and the bit line BL can be a gradually increasing voltage. For example, the voltage supplied through the common-source line CSL and the bit line BL can be a constantly increasing voltage.

[0249] At the second time point t2, the block word line BLKWL and the row line RL_GIDL1_C2 can be increased to the power supply voltage VDD. Therefore, the first GIDL line GIDL1_C2 of the second cell layer CL2 can be floated. When the voltage provided through the common source line CSL of the second cell layer CL2 increases to the erase voltage VERS, the voltage of the first GIDL line GIDL1_C2 of the second cell layer CL2 can also increase together. In this case, the voltage of the first GIDL line GIDL1_C2 can increase to a fourth voltage ΔV4. In an embodiment, the fourth voltage ΔV4 can correspond to the increment of the voltage level from the second time point t2 to the sixth time point t6.

[0250] At the third time point t3, the row line RL_GIDL1_C1 can be increased to the power supply voltage VDD. Therefore, the first GIDL line GIDL1_C1 of the first cell layer CL1 can be floated. When the voltage provided through the common source line CSL of the first cell layer CL1 increases to the erase voltage VERS, the voltage of the first GIDL line GIDL1_C1 of the first cell layer CL1 can also increase together. In this case, the voltage of the first GIDL line GIDL1_C1 can increase to the second voltage ΔV2. In an embodiment, the second voltage ΔV2 can correspond to the increment of the voltage level from the third time point t3 to the sixth time point t6.

[0251] As described above, at the fourth time point t4, the row line RL_GIDL2_C2 can be increased to the power supply voltage VDD. Therefore, the second GIDL line GIDL2_C2 of the second cell layer CL2 can be floated. When the voltage provided by the bit line BL of the second cell layer CL2 increases to the erase voltage VERS, the voltage of the second GIDL line GIDL2_C2 of the second cell layer CL2 can also increase together. In this case, the voltage of the second GIDL line GIDL2_C2 can increase to the third voltage ΔV3. In the embodiment, the third voltage ΔV3 can correspond to the increment of the voltage level from the fourth time point t4 to the sixth time point t6.

[0252] At the fifth time point t5, the row line RL_GIDL2_C1 can be increased to the power supply voltage VDD. Therefore, the second GIDL line GIDL2_C1 of the first cell layer CL1 can be floated. When the voltage provided by the bit line BL of the first cell layer CL1 increases to the erase voltage VERS, the voltage of the second GIDL line GIDL2_C1 of the first cell layer CL1 can also increase together. In this case, the voltage of the second GIDL line GIDL2_C1 can increase to the first voltage ΔV1. In an embodiment, the first voltage ΔV1 can correspond to the increment of the voltage level from the fifth time point t5 to the sixth time point t6.

[0253] At time point t6, the voltage supplied through the common-source line CSL or the bit line BL can be increased to the erase voltage VERS level. Therefore, the GIDL erase operation can be performed.

[0254] In this case, since the floating times of the GIDL lines GIDL1_C1 and GIDL2_C1 of the first unit layer CL1 and the GIDL lines GIDL1_C2 and GIDL2_C2 of the second unit layer CL2 are different from each other, the difference in the GIDL erasure speed of the layer can be compensated.

[0255] For example, when the first cell layer CL1 has relatively poor characteristics, as shown, the GIDL line of the first cell layer CL1 can float relatively slowly. For example, when the second cell layer CL2 has relatively good characteristics, the GIDL line of the second cell layer CL2 can float relatively quickly.

[0256] As mentioned above, since the float time of the GIDL line is variable for each layer, it can compensate for differences in layer-specific characteristics.

[0257] Figure 27 This is a flowchart describing a read operation of a memory device according to an embodiment.

[0258] In operation of S710, the memory device can enter GIDL erase operation mode.

[0259] In operation of S720, the memory device can independently control the float time of the GIDL line corresponding to each layer based on layer-specific cell characteristic differences, layer-specific word line load differences, and / or layer-specific address line load differences.

[0260] For example, GIDL lines corresponding to cell layers with relatively good characteristics can be floated quickly, while GIDL lines corresponding to cell layers with relatively poor characteristics can be floated slowly. This allows for compensation of differences in layer-specific characteristics.

[0261] The memory device according to this disclosure can be implemented by a bonding method and can improve the reliability of core operations.

[0262] Although various aspects of the embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: A memory cell array comprising a first string disposed in a first layer and a second string disposed in a second layer, the second layer being stacked on the first layer; Page buffer circuit, which includes a first page buffer corresponding to a first string of the first layer and a second page buffer corresponding to a second string of the second layer; as well as Control logic circuitry is configured to independently control the first page buffer and the second page buffer during core operations.

2. The memory device of claim 1, further comprising a first transmission transistor, the first transmission transistor including a first end connected to a first word line of the first string and a second word line of the second string, and a second end connected to a first row line.

3. The memory device according to claim 2, wherein, The control logic circuit is further configured to: in a pre-programmed operation mode, control the pre-programmed voltage to be applied to the first word line of the first string and the second word line of the second string, the first bit line voltage to be applied to the first bit line of the first string, and the second bit line voltage to be applied to the second bit line of the second string, and, The voltage levels of the first bit line voltage and the second bit line voltage are different from each other.

4. The memory device according to claim 2, wherein, The control logic circuit is further configured to: in the erase verification operation mode, control the verification voltage to be applied to the first word line of the first string and the second word line of the second string, the first bit line voltage to be applied to the first bit line of the first string, and the second bit line voltage to be applied to the second bit line of the second string, and The voltage levels of the first bit line voltage and the second bit line voltage are different from each other.

5. The memory device according to claim 4, wherein, The control logic circuit is further configured to: in the erase verification operation mode, control the first bit line voltage to be provided during a first time period and the second bit line voltage to be provided during a second time period different from the first time period.

6. The memory device according to claim 4, wherein, The first page buffer includes a first transistor configured to selectively connect the first bit of the first string to the first sensing node according to a first bit line connection control signal. The second page buffer includes a second transistor configured to selectively connect the second bit line of the second string and the second sensing node according to a second bit line connection control signal. The control logic circuit is further configured to: in the erase verification operation mode, control the activation time of the first bit line connection control signal to be different from the activation time of the second bit line connection control signal.

7. The memory device according to claim 2, wherein, The control logic circuit is further configured to: in a programming operation mode, control the programming voltage to be applied to the first word line of the first string and the second word line of the second string, the first bit line forced voltage to be applied to the first bit line of the first string, and the second bit line forced voltage to be applied to the second bit line of the second string, and The voltage levels of the first bit line forced voltage and the second bit line forced voltage are different from each other.

8. The memory device according to claim 2, wherein, The control logic circuit is further configured to: in the programming verification operation mode, control the verification voltage to be applied to the first word line of the first string and the second word line of the second string, the first bit line voltage to be applied to the first bit line of the first string, and the second bit line voltage to be applied to the second bit line of the second string, and, The voltage levels of the first bit line voltage and the second bit line voltage are different from each other.

9. The memory device according to claim 8, wherein, The control logic circuit is further configured to: in the programming verification operation mode, control the first bit line voltage to be provided during a first time period, and the second bit line voltage to be provided during a second time period different from the first time period.

10. The memory device according to claim 8, wherein, The first page buffer includes a first transistor configured to selectively connect the first bit of the first string to the first sensing node according to a first bit line connection control signal. The second page buffer includes a second transistor configured to selectively connect the second bit line of the second string and the second sensing node according to a second bit line connection control signal. The control logic circuit is further configured to, in the programming verification operation mode, control the sensing time when the first bit line connection control signal is activated to be different from the sensing time when the second bit line connection control signal is activated.

11. The memory device according to claim 10, wherein, The sensing time during which the first bit line connection control signal is activated includes a first coarse sensing time and a first fine sensing time. The sensing time during which the second bit line connection control signal is activated includes a second coarse sensing time and a second fine sensing time. The first coarse sensing time and the second coarse sensing time are different from each other, and the first fine sensing time and the second fine sensing time are also different from each other.

12. The memory device according to claim 2, wherein, The control logic circuit is further configured to: in a read operation mode, control the read voltage to be applied to the first word line of the first string and the second word line of the second string, the first bit line voltage to be applied to the first bit line of the first string, and the second bit line voltage to be applied to the second bit line of the second string, and The voltage levels of the first bit line voltage and the second bit line voltage are different from each other.

13. The memory device according to claim 12, wherein, The control logic circuit is further configured to: in the read operation mode, control the first bit line voltage to be provided during a first time period and the second bit line voltage to be provided during a second time period different from the first time period.

14. The memory device according to claim 13, wherein, The first page buffer includes a first transistor configured to selectively connect the first bit of the first string to the first sensing node according to a first bit line connection control signal. The second page buffer includes a second transistor configured to selectively connect the second bit line of the second string and the second sensing node according to a second bit line connection control signal. The control logic circuit is further configured to: in the read operation mode, control the sensing time when the first bit line connection control signal is activated to be different from the sensing time when the second bit line connection control signal is activated.

15. The memory device according to claim 2, further comprising: The second transmission transistor includes a first end connected to a first gate-drain leakage line of the first string and a second end connected to a second row line; as well as The third transmission transistor includes a first end connected to the second gate-drain leakage line of the second string and a second end connected to the third row line.

16. The memory device according to claim 15, wherein, In the erase operation mode, the first time point when the first gate-induced drain leakage line is floating and the second time point when the second gate-induced drain leakage line is floating are different from each other.

17. The memory device of claim 16, further comprising: The fourth transmission transistor includes a first end connected to the third gate-drain leakage line of the first string and a second end connected to the fourth row line; as well as The fifth transmission transistor includes a first terminal connected to the fourth gate-drain leakage line of the second string and a second terminal connected to the fifth row line. The control logic circuit is further configured to, in the erase operation mode, control the third time point when the third gate-drain leakage line is floating and the fourth time point when the fourth gate-drain leakage line is floating to be different from each other.

18. A memory device, comprising: The first chip includes a first page buffer and a second page buffer; A second chip, which is stacked on the first chip, wherein a first string electrically connected to the first page buffer is disposed in the second chip; A third chip, stacked on top of the second chip, wherein a second string electrically connected to the second page buffer is disposed within the third chip; and Control logic circuitry is configured to independently control the first page buffer and the second page buffer during core operations.

19. The memory device of claim 18, further comprising: A first transmission transistor includes a first end that is connected to a first word line of the first string and a second word line of the second string, and a second end that is connected to a first row line; The second transmission transistor includes a first end connected to a first gate-drain leakage line of the first string and a second end connected to a second row line; as well as The third transmission transistor includes a first terminal connected to the second gate-drain leakage line of the second string and a second terminal connected to the third row line. The control logic circuit is further configured to independently control the second transmission transistor and the third transmission transistor during the core operation.

20. A method of operating a memory device, the memory device comprising a memory cell array, the memory cell array including a first string disposed in a first layer and a second string disposed in a second layer stacked on the first layer, the method comprising: Enter core operation mode; as well as Based on the characteristic differences between the first layer and the second layer, the first page buffer of the first string connected to the first layer and the second page buffer of the second string connected to the second layer are independently controlled.

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