Memory device and method for adjusting signal transmission

Abstract

The memory device includes a stacked memory, a plurality of via holes, and a memory controller. The stacked memory includes a plurality of memory chips. Each memory chip comprises at least one memory cell array, a chip identification device and a signal path switch. The chip identification device is coupled to at least one memory cell array. The signal path switch is coupled to the chip identification device. The via hole penetrates through the stacked memory. The memory controller is coupled to the stacked memory. According to the memory device provided by the invention, each memory chip can be managed more easily, and the yield of the 3D stacked memory is improved.

Description

Technical Field

[0001] This invention relates to a memory device and a method for adjusting signal transmission. Background Technology

[0002] Multiple memory chips can be stacked to improve the integration of memory devices. Memory devices with three-dimensional (3D) structures can store and process large amounts of data. Various packaging technologies can be applied to semiconductor chips to form a three-dimensional structure (which can be referred to as 3D stacked memory, or stacked memory). Specifically, because through-silicon vias (TSVs) are suitable for achieving extremely high speeds of miniaturization in memory devices, they can be used to stack semiconductor chips.

[0003] 3D stacked memory may include coupling layers or packages of dynamic random-access memory (DRAM) memory elements, which may be referred to as a memory stack. Stacked memory can be used to provide a large amount of computer memory in a single device or package, which may also include certain system components such as memory controllers and central processing units (CPUs).

[0004] However, 3D stacked memory is significantly more expensive to manufacture than simpler memory components. In the construction of stacked memory devices, memory chips that are defect-free during manufacturing may develop defects during the packaging process of the 3D stacked memory. Summary of the Invention

[0005] One aspect of the present invention is to provide a memory device. The memory device includes a stacked memory, a plurality of vias, and a memory controller. The stacked memory includes a plurality of memory chips. Each memory chip includes at least one memory cell array, a chip identification device, and a signal path switch. The chip identification device is coupled to at least one memory cell array. The signal path switch is coupled to the chip identification device. The vias penetrate the stacked memory. The memory controller is coupled to the stacked memory.

[0006] According to one or more embodiments, the chip identification device includes an identification buffer.

[0007] According to one or more embodiments, the identification buffer includes a fuse, a one-time programmable memory, a non-volatile memory, or a combination thereof.

[0008] According to one or more embodiments, the memory chip is a non-volatile memory or a volatile memory.

[0009] According to one or more embodiments, non-volatile memory includes static random access memory, ferroelectric random access memory, read-only memory, flash memory, magnetoresistive random access memory, or combinations thereof.

[0010] According to one or more embodiments, volatile memory includes random access memory, dynamic random access memory, static random access memory, or a combination thereof.

[0011] According to one or more embodiments, the memory device further includes a plurality of bumps disposed between the vias and the memory controller.

[0012] According to one or more embodiments, the bump is a plurality of microbumps, a plurality of hybrid bumps, a plurality of bonding pads, or a combination thereof.

[0013] According to one or more embodiments, the memory device further includes a plurality of bumps or a plurality of bonding pads disposed between adjacent pairs of the memory chip.

[0014] According to one or more embodiments, each memory chip includes input / output circuitry coupled between a chip identification device and at least one memory cell array.

[0015] According to one or more embodiments, the memory device further includes a plurality of control circuits respectively coupled between a chip identification device and a memory controller of the memory chip.

[0016] Another aspect of the present invention provides a method for adjusting signal transmission. This method includes the following steps: Receiving a memory device, the memory device including a stacked memory, a plurality of vias penetrating the stacked memory, and a memory controller coupled to the stacked memory, wherein the stacked memory includes a plurality of memory chips, each memory chip including at least one memory cell array, a chip identification device coupled to the at least one memory cell array, and a signal path switch coupled to the chip identification device, and the vias respectively allow signal transmission. A first via for transmitting a first signal is detected to be damaged, wherein the damaged location of the first via is located within a first memory chip. The memory controller reads a first chip identification from the first memory chip. The transmission of the first signal is adjusted by the memory controller to transmit the first signal through a second via in the vias.

[0017] According to one or more embodiments, the method further includes setting a current reference value in a chip identification device in each memory chip. Detecting damage to a first via for transmitting a first signal in the via includes comparing an output current value of the first signal passing through the first via with a current reference value in the chip identification device of the first memory chip, wherein the output current value differs from the current reference value.

[0018] According to one or more embodiments, this method further includes setting a resistance reference value in a chip identification device in each memory chip. Detecting damage to a first via for transmitting a first signal in the via includes comparing the resistance value of the first via with a resistance reference value in the chip identification device of the first memory chip, wherein the resistance value differs from the resistance reference value.

[0019] According to one or more embodiments, this method further includes setting a voltage reference value in a chip identification device in each memory chip. Detecting damage to a first via for transmitting a first signal in the via includes comparing a voltage value of the first via with a voltage reference value in the chip identification device of the first memory chip, wherein the voltage value differs from the voltage reference value.

[0020] According to one or more embodiments, adjusting the transmission of a first signal by a memory controller to transmit the first signal through a second via in the via includes: closing the first via by a signal path switch corresponding to the first via; and opening the second via by a signal path switch corresponding to the second via.

[0021] According to one or more embodiments, the method further includes transmitting a second signal through a first via, wherein the second signal is transmitted to a second memory chip stacked between the first memory chip and the memory controller.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are intended to provide further illustration of the claimed invention. Attached Figure Description

[0023] The present invention can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings.

[0024] Figure 1 A schematic cross-sectional view is provided to illustrate the structure of a memory device according to some embodiments of the present invention.

[0025] Figure 2 This is a schematic diagram illustrating the relationship between a memory controller and a memory chip according to some embodiments of the present invention.

[0026] Figure 3 This is a schematic diagram illustrating signal transmission through a via in a memory device according to some embodiments of the present invention.

[0027] Figure 4 This is a schematic diagram illustrating signal transmission when a node in each memory chip fails, according to some embodiments of the present invention.

[0028] Figure 5 This is a schematic diagram illustrating signal transmission in a via when a node in one of the vias is damaged, according to some embodiments of the present invention.

[0029] Figure 6 This is a schematic diagram illustrating the signal transmission of an adjusted via according to some embodiments of the present invention. Detailed Implementation

[0030] Embodiments of the invention will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0031] The following are specific embodiments of the present invention, described in detail with reference to the accompanying drawings. The elements and designs of the following embodiments are for simplification and are not intended to limit the invention. The description mentions that a first structural feature is located on top of a second structural feature, including embodiments where the first and second structural features are in direct contact, and embodiments where there are other structural features between the first and second structural features, i.e., the first and second structural features are not in direct contact. Furthermore, the present invention may use repeated reference numerals and / or words in various embodiments. These repeated numerals or words are for simplification and clarity and are not intended to limit the various embodiments and / or the relationship between the structures.

[0032] Furthermore, for ease of explanation, spatially related terms such as "below," "under," "lower," "in lower text," and "higher" may be used in the text to describe the relationship between one element or feature shown in the figure and another. Spatially related terms are intended to encompass different orientations of the device during use or operation, in addition to those shown in the figure. The device may have other orientations (rotated 90 degrees or other orientations), therefore, spatially related terms used in the text can be interpreted in a similar manner.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the invention pertain. It should be understood that terms defined, for example, in common dictionaries, shall be interpreted as having the same meaning as they have in the relevant field and in the context of the invention, and shall not be construed as, or as having, an overly formal meaning unless expressly defined herein.

[0034] Figure 1 A schematic cross-sectional view is provided to illustrate the structure of a memory device 10 according to some embodiments of the present invention. Figure 2This is a schematic diagram illustrating the relationship between a memory controller and a memory chip according to some embodiments of the present invention. See also... Figures 1 to 2 The memory device 10 includes a stacked memory 100, a plurality of vias 300, and a memory controller 200. The stacked memory 100 includes a plurality of memory chips Ch1-Chn, the vias 300 pass through the stacked memory 100, and the memory controller 200 is coupled to the stacked memory 100. The three-dimensional (3D) memory device 10 realizes the vertical stacking of memory chips and achieves vertical interconnection of the memory chips through the vias 300. The vias 300 can also be referred to as "through electrodes" or "through silicon vias (TSVs)". In other words, the memory device 10 can be a stacked chip type memory or a stacked memory device that transmits data and control signals through the vias 300. That is, the vias 300 respectively allow signal transmission. According to one or more embodiments, the vias 300 include, for example, Figure 1 The four vias shown are TSV1-TSV4, but the invention is not limited thereto. According to other embodiments, via 300 may include more than four vias, such as ten vias, hundreds of vias, or even thousands of vias, depending on design requirements.

[0035] The memory controller 200 follows an instruction cycle. The instruction cycle is followed by the memory controller 200 to process instructions from the moment the computer is powered on until, for example, when the computer is powered off. The instruction cycle comprises three main phases: a fetch phase, a decode phase, and an execute phase. In some embodiments, the memory controller 200 may be referred to as a logic integrated circuit (logic IC) or a base die.

[0036] According to one or more embodiments, the memory controller 200 includes standard processors such as field-programmable gate arrays (FPGAs), graphics processing units (GPUs), central processing units (CPUs), application-specific standard parts (ASSPs), application-specific integrated circuits (ASICs), and micro control units (MCUs). However, the invention is not limited thereto. According to one or more embodiments, the memory controller 200 may include other suitable processing means.

[0037] According to one or more embodiments, the memory controller 200 includes logic circuitry having a control unit (CU) 210 and an arithmetic logic unit (ALU) 220, static random-access memory (SRAM) 230, and processing peripheral circuitry (PPC) 240.

[0038] In some embodiments, the control unit 210 is used to direct operations within the memory controller 200. According to one or more embodiments, the control unit 210 is used to direct the computer's logic units, memory, and input and output devices based on instructions received from a program.

[0039] In some embodiments, the arithmetic logic unit 220 is coupled to the control unit 210 and is used to perform bitwise operations and mathematical operations based on binary. The arithmetic logic unit 220 is the final element performing calculations in the memory controller 200. The arithmetic logic unit 220 performs operations on input data based on the received operands and codes. After the information has been processed by the arithmetic logic unit 220, the processed information is sent to the stacked memory 100.

[0040] In some embodiments, static random access memory 230 is coupled to control unit 210 and arithmetic logic unit 220, and serves as a cache for memory controller 200, wherein static random access memory 230 is a first-level cache. Where appropriate, static random access memory 230 may be referred to as a second semiconductor memory.

[0041] In some embodiments, the processing peripheral circuitry 240 serves as a communication interface for communication between the logic circuitry of the memory controller 200 and external electrical components, such as the stacked memory 100. Structurally, for example, the logic circuitry is not directly coupled to the stacked memory 100. Instead, the logic circuitry is directly coupled to the processing peripheral circuitry 240 and then indirectly coupled to the stacked memory 100 via the processing peripheral circuitry 240.

[0042] The stacked memory 100 is coupled to the memory controller 200 and is used to store instructions required in an instruction cycle, and serves as the main memory of the memory controller 200. Specifically, the stacked memory 100 includes multiple memory chips Ch1-Chn. Figure 1 As shown, the stacked memory 100 includes memory chips Ch1, Ch2, Ch3, ..., Chn, stacked sequentially above the memory controller 200 from bottom to top, where n is equal to or greater than 2. According to one or more embodiments, the memory device 10 also includes a plurality of bumps 400 disposed between the stacked memory 100 and the memory controller 200. In other words, these bumps 400 are disposed between the via 300 and the memory controller 200. In some embodiments, the bumps 400 may be microbumps, hybrid bumps, bonding pads, or combinations thereof. According to one or more embodiments, the memory device 10 also includes a plurality of bumps 500 or a plurality of bonding pads (not shown) disposed between two adjacent memory chips. In some embodiments, the bumps 500 are microbumps, hybrid bumps, bonding pads, or combinations thereof. The via 300 can be electrically connected to the bump 500 disposed between each memory chip Ch1-Chn, and can also be electrically connected to the bump 400 disposed between the first memory chip Ch1 and the memory controller 200. In other words, a segment of one of the multiple vias 300 in the memory chips Ch1-Chn can be electrically connected via the bump 500.

[0043] According to one or more embodiments, memory chips Ch1-Chn are nonvolatile memory chips or volatile memory chips. According to one or more embodiments, nonvolatile memory chips include dynamic random-access memory (DRAM), static random-access memory (SRAM), ferroelectric random-access memory (FRAM), read-only memory (ROM), or combinations thereof. According to other embodiments, nonvolatile memory chips include magnetoresistive random-access memory (MRAM), resistive random-access memory (ReRAM), bridged-conductor memory (CBM), phase-change memory (PCM), nanotube rain (NRAM), ferroelectric field-effect transistor (FeFET) memory, 3D Xpoint (3DXP) memory, flash memory, or combinations thereof. According to one or more embodiments, volatile memory includes dynamic random-access memory (DRAM), random-access memory, static random-access memory, or a combination thereof.

[0044] Please see Figure 1 and Figure 2 More specifically, each memory chip Ch1-Chn includes at least one memory cell array 1101, a chip identification device 120, and a signal path switch 130. For example... Figure 2 As shown, each memory chip Ch1-Chn may include one or more memory cell arrays 1101 to 110 n Where n is equal to or greater than 2, but is not limited thereto. According to one or more embodiments, at least one memory cell array 1101 to 110... nEach of the memory chips Ch1-Chn includes multiple word lines (not shown), multiple bit lines (not shown), and multiple memory cells (not shown). The memory cells are arranged in columns and rows. The memory cells are located at the intersection of each word line and bit line, and are used to store data in digital two-word form. The memory cells include, for example, a memory device for storing data and a memory transistor for performing unit selection. In an embodiment where the memory chips Ch1-Chn are DRAM, the memory includes capacitors. In another embodiment where the memory chips Ch1-Chn are MRAM, the memory device includes a magnetic tunneling junction (MJT) transistor.

[0045] Chip identification device 120 and signal path switch 130 are part of memory peripheral circuit (MPC), which are used in at least one memory cell array 1101 to 110 n A communication interface for communication with electronic components such as a memory controller 200 external to the memory chips Ch1-Chn. Structurally, for example, there is at least one memory cell array 1101 to 110. n Not directly coupled to memory controller 200. Instead, at least one memory cell array 1101 to 110 n It is directly coupled to the MPC, and then indirectly coupled to the memory controller 200 via the MPC. Additionally, the MPC is used to control at least one memory cell array 1101 to 1100. n According to one or more embodiments, the MPC may further include, for example, a decoder (such as a row decoder and a column decoder), an address buffer (not shown), input / output (I / O) circuitry, a clock generator (not shown), a direct-current (DC) generator (not shown), and a sense amplifier (S / A) (not shown). According to one or more embodiments, the input / output circuitry is coupled to the chip identification device 120 and at least one memory cell array 1101 to 1102. n between.

[0046] Chip identification device 120 is coupled to at least one memory cell array 1101 to 110 nThis is used to access the identification (or identifier) ​​of the corresponding memory chip. According to one or more embodiments, the chip identification device 120 includes an identification register 122. For example, the identification register 122 includes a fuse, one-time programmable memory, or nonvolatile memory. It is understood that each memory chip Ch1-Chn and each memory cell array 1101 to 110... n The identification (or identification code) is independent. According to one or more embodiments, the identification (or identification code) can be modified. By configuring the chip identification device 120, the location of damage can be clearly identified in the event of signal transmission failure.

[0047] It should be noted that a conventional DRAM chip can be used as the chip identification device 120 without modification. In other words, when the chip identification device 120 of the present invention is attached to a DRAM chip, a portion of the memory cell region may be sufficient for the chip identification device 120, and therefore no additional cost is required in manufacturing. The bit capacity of the identification device region may be much smaller than that of general-purpose memory and DRAM.

[0048] The signal path switch 130 is coupled to the chip identification device 120 and is used to turn on or off the via 300 in the stacked memory.

[0049] Please see Figure 1 and Figure 2 Operationally, the memory controller 200 generates and provides data signals (Data), address signals (ADD), and memory control signals (Control) to the MPC to access at least one memory cell array 1101 to 1102. n In some embodiments, the memory control signal Control includes a command signal. However, the invention is not limited thereto. In some embodiments, the memory control signal Control includes other suitable signals. According to one or more embodiments, the memory device 10 may further include control circuitry 160, which is respectively coupled between the chip identification device 122 and the memory controller 200 of the memory chips Ch1-Chn.

[0050] More specifically, each of the memory chips Ch1-Chn also includes an address decoder 140. The chip identification device 120 is sequentially coupled to at least one memory cell array 1101 to 110 via a signal path switch 130 and the address decoder 140.n The address decoder 140 receives the address ADD from an external device (e.g., memory controller 200) and performs the decoding of the address ADD under the control of the control circuit 160.

[0051] Another aspect of the present invention provides a method for adjusting signal transmission. The method includes the following operations: First, receiving a memory device, such as... Figures 1 to 2 The memory device 10 is shown. Then, it is detected whether a first via for transmitting a first signal among the plurality of vias is damaged, wherein the damaged location of the first via is located within a first memory chip. Next, the memory controller reads a first chip identifier of the first memory chip. Subsequently, the memory controller adjusts the transmission of the first signal to transmit the first signal through a second via among the vias. The method for adjusting signal transmission is described below according to one or more embodiments of the present invention.

[0052] Figure 3 This is a schematic diagram illustrating signal transmission through a via in a memory device according to some embodiments of the present invention. Figure 4 This is a schematic diagram illustrating signal transmission when a node in each memory chip fails, according to some embodiments of the present invention. Figure 5 This is a schematic diagram illustrating signal transmission in a via when a node in one of the vias is damaged, according to some embodiments of the present invention. Figure 6 This is a schematic diagram illustrating the signal transmission of an adjusted via according to some embodiments of the present invention.

[0053] See Figures 3 to 6 The original transmission path of the first signal SL1 is shown as a thick solid line, the original transmission path of the second signal SL2 is shown as a thin solid line, the adjusted transmission path of the first signal SL1' is shown as a thick dashed line, and the adjusted transmission path of the second signal SL2' is shown as a thin dashed line.

[0054] According to one or more embodiments, a first via TSV1 in via 300 is used to transmit a first signal SL1, and a second via TSV2 in via 300 is used to transmit a second signal SL2. The invention is not limited thereto. According to other embodiments, the first signal SL1 can be transmitted through the second via TSV2 or the third via TSV3 in via 300, while the second signal SL2 can be transmitted through the first via TSV1 or the fourth via TSV4 in via 300. It is worth noting that the transmission paths of the first signal SL1 and the second signal SL2 are independent of each other and do not interfere with each other.

[0055] In one embodiment, due to problems that may occur in the manufacturing process, one or more memory cell arrays may be bad or damaged memory cell arrays (e.g., Figure 4 The fault memory cell array FT(1101) in the memory chip Chn is shown. In another embodiment, due to problems such as manufacturing processes, one or more circuits in each memory chip may fail or disconnect (e.g., ...). Figure 4 The faulty circuit FP in the memory chip Chn shown. In other embodiments, one or more of the vias 300 may be defective or damaged vias due to problems that may occur in the manufacturing process (e.g., Figure 5 The upper node DL of the memory chip Ch2 in the via TSV1 shown is not functioning properly. This causes the first signal SL1, intended to be sent to the memory chip Ch3, to be interrupted at the memory chip Ch2. At this time, the chip identification device 120 of the memory chip Ch2 (such as...) Figure 2 As shown, the chip identification corresponding to memory chip Ch2 can be transmitted to memory controller 200, so that memory controller 200 knows that the damaged location is located in memory chip Ch2.

[0056] According to one or more embodiments, the method for adjusting signal transmission may further include a chip identification device 120 (e.g., for each memory chip Ch1-Chn) Figure 2 A current reference value is set in the diagram. Here, the current reference value represents the ideal current value of the signal. During the transmission of the first signal SL1 through the via TSV1, each memory chip Ch1-Chn can calculate or generate a corresponding output current value. Each output current value is compared with the chip identification device 120 (e.g., for each memory chip Ch1-Chn). Figure 2 The current value is compared with the current reference value shown in the figure. If the output current value does not reach or is different from the current reference value, the memory chip Ch2 is considered to be damaged.

[0057] According to one or more embodiments, the method for adjusting signal transmission may further include a chip identification device 120 (e.g., for each memory chip Ch1-Chn) Figure 2 A resistance reference value is set in the diagram. Here, the resistance reference value represents the ideal resistance value for transmitting signals through the via. During the transmission of the first signal SL1 through the via TSV1, each memory chip Ch1-Chn can calculate the resistance of the corresponding segment of the via TSV1 through which the first signal SL1 is transmitted. Each resistance is compared with the chip identification device 120 (e.g., as shown) of each memory chip Ch1-Chn. Figure 2 The resistance is compared with the reference value shown in the figure. If the resistance does not reach or is different from the reference value, the memory chip Ch2 is considered to be damaged.

[0058] According to one or more embodiments, the method for adjusting signal transmission may further include a chip identification device 120 (e.g., for each memory chip Ch1-Chn) Figure 2 The voltage reference value is set in the diagram. Each voltage is compared with the chip identification device 120 (e.g., shown) for each memory chip Ch1-Chn. Figure 2 The voltage is compared with the voltage reference value shown in the figure. If the voltage does not reach or is different from the voltage reference value, the memory chip Ch2 is considered to be damaged.

[0059] After the memory controller 200 reads the chip identification corresponding to memory chip Ch2, the memory controller 200 can send an instruction to each memory chip Ch1-Chn to adjust the transmission path of the first signal SL1. Specifically, the instruction to adjust the transmission path of the first signal SL1 can be that the memory controller 200 adjusts the transmission of the first signal SL1 to transmit the first signal SL1 through normally functioning vias TSV2, TSV3, or TSV4. For example, the memory controller 200 might adjust the transmission of the first signal SL1 by transmitting the first signal SL1 through the conductive via TSV2. Figure 6 In the diagram, the transmission path of the adjusted first signal SL1' is shown by the thick dashed line.

[0060] According to one or more embodiments, when the memory controller 200 issues an instruction to adjust the transmission of the first signal SL1 to transmit the first signal SL1 through the conductive via TSV2, the signal path switch 130 (e.g., via the corresponding via TSV1) switches through the corresponding via TSV1. Figure 2 (As shown) to shut off via TSV1, and switch 130 (as shown) via the signal path corresponding to via TSV2. Figure 2 (As shown) Connect the via hole TSV2.

[0061] According to one or more embodiments, the method for adjusting signal transmission may further include a second signal SL2 that needs to be transmitted to memory chip Ch1. When the via TSV2, which was initially used to transmit the second signal SL2, is used to transmit the first signal SL1, the second signal SL2 can be adjusted to be transmitted through the via TSV1. It should be noted that the second signal SL2 is transmitted to memory chip Ch1, which is stacked between memory chip Ch2, which has the damaged location of the via TSV1, and memory controller 200. In other words, when the target memory chip Ch1 that the second signal SL2 needs to reach is lower than the location of memory chip Ch2 at the damaged location of the via TSV1, the first signal SL1, which was originally transmitted through the via TSV1, can be adjusted to transmit the second signal SL2 through the via TSV2, and the second signal SL2, which was originally transmitted through the via TSV2, can be adjusted to transmit the second signal SL2 through the via TSV1.

[0062] The above embodiments offer various advantages. The methods and configurations described above allow for easier management of each memory chip and improve the yield of 3D stacked memories. Furthermore, when a damaged via is detected, additional metal wiring or redistribution layers (RDLs) may be needed for memory chips in different stacking layers to conduct to other functioning vias. Therefore, the methods and configurations of this invention can reduce manufacturing costs. Additionally, damaged vias can be effectively utilized, thereby reducing the use of redundant vias, further reducing the number of redundant vias, and lowering the proportion of redundant vias in the memory device.

[0063] Although the invention has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0064] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the invention falling within the appended claims.

[0065] [Symbol Explanation]

[0066] 10: Memory devices

[0067] 100: Stacked Memory

[0068] 1101: Memory Cell Array

[0069] 110 n : Memory cell array

[0070] 120: Chip recognition device

[0071] 122: Identify the cache

[0072] 130: Signal path switch

[0073] 140: Address Decoder

[0074] 160: Control Circuit

[0075] 200: Memory controller

[0076] 210: Control Unit

[0077] 220: Arithmetic Logic Unit

[0078] 230: Static Random Access Memory

[0079] 240: Handling peripheral circuits

[0080] 300: Through hole

[0081] 400: Bump

[0082] 500: Bump

[0083] ADD: address

[0084] Control: Memory control signal

[0085] Ch1: Memory Chips

[0086] Ch2: Memory Chips

[0087] Ch3: Memory Chips

[0088] Chn: Memory chip

[0089] Data: Data signal

[0090] DL: Upper Node

[0091] FT(1101): Fault Memory Cell Array

[0092] FP: Faulty Circuit

[0093] SL1: First signal

[0094] SL1': First signal

[0095] SL2: Second signal

[0096] SL2': Second signal

[0097] TSV1: Through Hole

[0098] TSV2: Through Hole

[0099] TSV3: Through Hole

[0100] TSV4: Through hole.

Claims

1. A memory device, characterized in that, include: A stacked memory includes multiple memory chips, wherein each memory chip comprises: At least one storage cell array; A chip identification device is coupled to the at least one memory cell array; and A signal path switch is coupled to the chip identification device; Multiple vias penetrate the stacked memory; and A memory controller is coupled to the stacked memory.

2. The memory device according to claim 1, wherein the chip identification device includes an identification cache.

3. The memory device of claim 2, wherein the identification buffer comprises a fuse, a one-time programmable memory, a non-volatile memory, or a combination thereof.

4. The memory device according to claim 1, wherein the plurality of memory chips are a plurality of non-volatile memories or a plurality of volatile memories.

5. The memory device of claim 4, wherein the plurality of non-volatile memories comprises a plurality of static random access memories, a plurality of ferroelectric random access memories, a plurality of read-only memories, a plurality of flash memories, a plurality of magnetoresistive random access memories, or combinations thereof.

6. The memory device of claim 4, wherein the plurality of volatile memories comprises a plurality of random access memories, a plurality of dynamic random access memories, a plurality of static random access memories, or a combination thereof.

7. The memory device according to claim 1, wherein, It further includes a plurality of bumps disposed between the plurality of vias and the memory controller.

8. The memory device of claim 7, wherein the plurality of bumps are a plurality of microbumps, a plurality of hybrid bumps, a plurality of bonding pads, or a combination thereof.

9. The memory device according to claim 1, wherein, It further includes multiple bumps or multiple bonding pads disposed between two adjacent memory chips.

10. The memory device of claim 1, wherein each of the memory chips includes input / output circuitry coupled between the chip identification device and the at least one memory cell array.

11. The memory device according to claim 1, wherein, It further includes multiple control circuits respectively coupled between the multiple chip identification devices of the multiple memory chips and the memory controller.

12. A method for adjusting signal transmission, characterized in that, The method includes: A receiving memory device, the memory device including a stacked memory, a plurality of vias penetrating the stacked memory, and a memory controller coupled to the stacked memory, wherein the stacked memory includes a plurality of memory chips, each memory chip including at least one memory cell array, a chip identification device coupled to the at least one memory cell array, and a signal path switch coupled to the chip identification device, and the plurality of vias respectively allow signal transmission; The first via used for transmitting the first signal among the plurality of vias was detected to be damaged, wherein the damaged location of the first via is located in the first memory chip among the plurality of memory chips; The memory controller reads the first chip identifier from the first memory chip; and The memory controller adjusts the transmission of the first signal to be transmitted through the second of the plurality of vias.

13. The method according to claim 12, wherein, Further includes: A current reference value is set in the chip identification device of each of the memory chips, wherein the first via used to transmit the first signal among the plurality of vias is detected to be damaged, including: The output current value of the first signal passing through the first via is compared with the current reference value in the chip identification device of the first memory chip, wherein the output current value is different from the current reference value.

14. The method according to claim 12, wherein, Further includes: A resistance reference value is set in the chip identification device of each of the memory chips, wherein the detection of damage to the first via for transmitting the first signal among the plurality of vias includes: The resistance value of the first via is compared with the resistance reference value in the chip identification device of the first memory chip, wherein the resistance value is different from the resistance reference value.

15. The method according to claim 12, wherein, Further includes: A voltage reference value is set in the chip identification device of each of the memory chips, wherein the detection of damage to the first via for transmitting the first signal among the plurality of vias includes: The voltage value of the first via is compared with the voltage reference value in the chip identification device of the first memory chip, wherein the voltage value is different from the voltage reference value.

16. The method of claim 12, wherein adjusting the transmission of the first signal via the memory controller to transmit the first signal through the second via of the plurality of vias comprises: The first via is closed by the signal path switch corresponding to the first via; as well as The second via is turned on by the signal path switch corresponding to the second via.

17. The method according to claim 12, wherein, Further includes: A second signal is transmitted through the first via, wherein the second signal is transmitted to a second memory chip stacked between the first memory chip and the memory controller.

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