Interface chip and test system including same

Abstract

An interface chip and a test system including the same are provided. The interface chip includes: a first interface circuit connected to a test device, the first interface circuit providing an interface for a first non-return-to-zero (NRZ) signal and a sideband signal for the test device; a second interface circuit connected to a device under test (DUT), the second interface circuit providing an interface for a second NRZ signal and a pulse amplitude modulation (PAM) signal for the DUT; and a conversion circuit connected to the first and second interface circuits, the conversion circuit providing a conversion between the first NRZ signal and the second NRZ signal and a conversion between the first NRZ signal and the PAM signal based on the sideband signal, generating a pass / fail (P / F) signal based on the PAM signal received from the DUT, and transmitting the P / F signal to a test device.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0114587, filed on August 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Some example embodiments relate to interface chips and test systems that include interface chips. Background Technology

[0003] Memory devices can send signals (such as commands, addresses, and data) to or receive signals (such as commands, addresses, and data) from external devices. Signaling methods can be used to enhance the efficiency of the input / output interface of memory devices.

[0004] Memory devices can be tested as devices under test (DUTs). This testing may lead to compatibility issues between the test equipment used to test the memory device and the memory device using signaling methods. Summary of the Invention

[0005] Some example embodiments provide interface chips for providing an interface connection between a test apparatus and a device under test (DUT), as well as test systems including interface chips.

[0006] Some exemplary embodiments of the inventive concept provide an interface chip comprising: a first interface circuit connected to a test apparatus, the first interface circuit providing an interface to the test apparatus for a first non-return-to-zero (NRZ) signal and a sideband signal; a second interface circuit connected to a device under test (DUT), the second interface circuit providing an interface to the DUT for a second NRZ signal and a pulse amplitude modulation (PAM) signal; and a conversion circuit connected to the first interface circuit and the second interface circuit, and configured to provide conversion between the first NRZ signal and the second NRZ signal based on the sideband signal, and conversion between the first NRZ signal and the PAM signal, generate a pass / fail (P / F) signal based on the PAM signal received from the DUT, and send the P / F signal to the test apparatus.

[0007] Some exemplary embodiments of the inventive concept also provide an interface chip, including: a command address (CA) conversion circuit that receives a setup signal and a plurality of first CA signals as non-return-to-zero (NRZ) signals from a test device, demultiplexes the plurality of first CA signals based on the setup signal, and outputs a second CA signal to a device under test (DUT) in response to the demultiplexing by the CA conversion circuit; and a data conversion circuit that sends an error flag signal and a first data signal corresponding to the first CA signal to the test device, or receives a first data signal, an error flag signal, and an instantaneous (OTF) signal from the test device, wherein the first data signal is an NRZ signal, sends a second data signal corresponding to the plurality of first CA signals to the DUT, or receives a second data signal from the DUT, wherein the second data signal is a pulse amplitude modulation (PAM) signal, and provides conversion between the first data signal, the error flag signal, and the second data signal based on the OTF signal.

[0008] Some exemplary embodiments of the inventive concept also provide a test system comprising: a test apparatus that transmits or receives a first non-return-to-zero (NRZ) signal for testing and transmits a sideband signal for setting an operating mode; a device under test (DUT) that transmits or receives a second NRZ signal and a pulse amplitude modulation (PAM) signal; and an interface chip connected to the test apparatus and the DUT, the interface chip providing conversion between the first NRZ signal and the second NRZ signal, and conversion between the first NRZ signal and the PAM signal based on the sideband signal, generating a pass / fail (P / F) signal based on the PAM signal received from the DUT, and transmitting the P / F signal to the test apparatus. Attached Figure Description

[0009] Figure 1 This is a block diagram of an interface chip according to some example embodiments.

[0010] Figure 2 This is a diagram illustrating an interface chip according to some example embodiments.

[0011] Figure 3 This illustrates some example embodiments. Figure 2 A diagram of the CA (command address) conversion circuit.

[0012] Figure 4 This is a diagram illustrating a CA conversion operation in a 2:1 mode according to some example embodiments.

[0013] Figure 5 This is a diagram illustrating a CA conversion operation in 1:1 mode according to some example embodiments.

[0014] Figure 6 This is a diagram illustrating a data conversion circuit according to some example embodiments.

[0015] Figure 7 and Figure 8 This is a diagram illustrating the conversion operation of a data conversion circuit according to some example embodiments.

[0016] Figure 9 This is a diagram illustrating a data conversion circuit according to some example embodiments.

[0017] Figure 10 This is a block diagram of a conversion circuit according to some example embodiments.

[0018] Figure 11A This is a diagram illustrating a first training circuit according to some example embodiments.

[0019] Figure 11B This is a diagram illustrating a second training circuit according to some example embodiments.

[0020] Figure 12 This is a block diagram of a conversion circuit according to some example embodiments.

[0021] Figure 13 This illustrates some example embodiments. Figure 12 The waveform diagram shows an example operation of the error switching circuit.

[0022] Figure 14 This is a block diagram of a conversion circuit according to some example embodiments.

[0023] Figure 15 This is a block diagram of a first clock conversion circuit according to some example embodiments.

[0024] Figure 16 This is a flowchart illustrating a method for converting CA signals of an interface chip according to some example embodiments.

[0025] Figure 17 This is a flowchart illustrating a method for converting write data signals of an interface chip according to some example embodiments.

[0026] Figure 18 This is a flowchart illustrating a method for converting read data signals from an interface chip according to some example embodiments.

[0027] Figure 19 This is a block diagram of a conversion circuit according to some example embodiments.

[0028] Figure 20 This illustrates some example embodiments. Figure 19 A diagram illustrating the operation of the self-training circuit.

[0029] Figure 21 This is a diagram illustrating a test system according to some example embodiments.

[0030] Figure 22 Based on some example embodiments Figure 21 The flowchart of the training operation on the DUT side of the test system.

[0031] Figure 23 This is a diagram illustrating the open-circuit test operation of a test system according to some example embodiments.

[0032] Figure 24 and Figure 25 This is a diagram illustrating the signal level adjustment operation of a test system according to some example embodiments. Detailed Implementation

[0033] In the following description, some exemplary embodiments will be described with reference to the accompanying drawings.

[0034] When used in the specification, the following terms, such as “at least one of A, B and C” and similar language (e.g., “at least one selected from the group consisting of A, B and C”), may be interpreted as only A, only B, only C, or any combination of two or more of A, B and C (e.g., ABC, AB, BC and AC).

[0035] Figure 1 This is a block diagram of an interface chip according to some example embodiments.

[0036] Reference Figure 1 According to some example embodiments, the interface chip 1000 may include a first interface circuit 1100, a second interface circuit 1200, and a conversion circuit 1300. According to some example embodiments, the interface chip 1000 may be implemented as a semiconductor chip (such as, for example, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or an application processor (AP)).

[0037] The first interface circuit 1100 can be connected to a test apparatus and is configured to provide an interface for a first non-return-to-zero (NRZ) signal and one or more sideband signals SBS to the test apparatus. For example, the first interface circuit 1100 can be configured to provide an interface for signals that can be sent or received between the test apparatus and the interface chip 1000.

[0038] In this application, the test apparatus can be defined as an apparatus that provides test functions for a device under test (DUT) connected to the second interface circuit 1200. The test apparatus can apply various signals to the DUT through the interface chip 1000 to test the DUT, and examples of the applied signals may include one or more first NRZ signals NS1 and one or more sideband signals SBS.

[0039] One or more first NRZ signals NS1 are NRZ modulated signals and therefore may have two signal levels. In this application, "first NRZ signal" may refer to a signal that is NRZ modulated and transmitted or received between the test device and the interface chip 1000. Similarly, "second NRZ signal" may refer to a signal that is NRZ modulated and transmitted or received between the DUT and the interface chip 1000.

[0040] One or more sideband signals (SBS) can be defined as signals applied from the test apparatus to the interface chip 1000 to control or operate the interface chip 1000. One or more sideband signals (SBS) can be applied only to the interface chip 1000 and are distinguished from other signals that can be converted in any way by the conversion circuit 1300 and applied from the test apparatus to the DUT and vice versa. In this application, all signals defined as having the above-mentioned purpose (signals applied only to the interface chip 1000 to control or operate the interface chip 1000) can be classified as one or more sideband signals (SBS).

[0041] According to some example embodiments, the first interface circuit 1100 may include a plurality of pins for sending signals to or receiving signals from the test apparatus. Figure 1 For the sake of simplicity in the accompanying drawings, only one pin is shown for each of the one or more first NRZ signals NS1 and one or more sideband signals SBS, but multiple pins may be set depending on the number of the corresponding one or more first NRZ signals NS1 or one or more sideband signals SBS.

[0042] In addition to multiple pins, the first interface circuit 1100 may also include analog elements (such as drivers for sending signals to or receiving signals from the test device).

[0043] The second interface circuit 1200 can be connected to the DUT and configured to provide an interface for one or more second NRZ signals NS2 and pulse amplitude modulation (PAM) signals to the DUT. For example, the second interface circuit 1200 can be configured to provide an interface for signals that can be sent or received between the DUT and the interface chip 1000.

[0044] In this application, DUT can be defined as a target device tested by a test apparatus.

[0045] One or more PAM signals PS can be PAM-X (or PAMX) modulated signals, where X is a positive integer greater than or equal to 3. For example, when X=3, one or more PAM signals PS can be PAM-3 modulated signals. PAM-X modulated signals can have X signal levels.

[0046] According to some example embodiments, the second interface circuit 1200 may include multiple pins for sending signals to or receiving signals from the DUT. Figure 1 For the sake of simplicity in the accompanying diagram, only one pin is shown for each of the one or more second NRZ signals NS2 and one or more PAM signals PS, but multiple pins may be set depending on the number of the corresponding one or more second NRZ signals NS2 or one or more PAM signals PS.

[0047] According to some example embodiments, each pin in the second interface circuit 1200 can be configured to transmit or receive NRZ signals and / or PAM signals according to the register settings of the conversion circuit. For example, it can be configured to transmit or receive... Figure 1 One or more pins of the second NRZ signal NS2 can be configured to transmit or receive one or more PAM signals PS, or both one or more second NRZ signals NS2 and one or more PAM signals PS, depending on register settings. Similarly, they can be configured to transmit or receive... Figure 1 The pins of the PAM signal can be configured to send or receive one or more second NRZ signals NS2, or one or more second NRZ signals NS2 and one or more PAM signals PS, depending on the register settings.

[0048] For example, for ease of description, Figure 1 The pins shown are configured only to correspond to each signal. According to the above embodiment, each pin can transmit or receive NRZ signals and / or PAM signals according to register settings.

[0049] In addition to multiple pins, the second interface circuit 1200 may also include one or more analog elements (such as drivers for sending signals to or receiving signals from the DUT, and / or elements for applying delays for synchronization (e.g., triggers, multiplexers, etc.)).

[0050] The test device can apply various signals to the DUT through the interface chip 1000 to test the DUT, and examples of the applied signals may include one or more first NRZ signals NS1 and one or more sideband signals SBS.

[0051] The conversion circuit 1300 can be connected to the first interface circuit 1100 and the second interface circuit 1200, and is configured to provide conversion operations for transmitting or receiving various signals between the test apparatus and the DUT. In this application, the "conversion operations" provided by the conversion circuit 1300 may include data rate adjustment and / or signal modulation of the signal data rate.

[0052] According to some example embodiments, the conversion circuit 1300 may be configured to provide conversion between one or more first NRZ signals NS1 and one or more second NRZ signals NS2, or between one or more first NRZ signals NS1 and one or more PAM signals PS, based on one or more sideband signals SBS. For example, the conversion circuit 1300 may be configured to provide bidirectional conversion between a test apparatus and a DUT. One or more sideband signals SBS may be used for conversion, and the sideband signals "used for conversion between NRZ signals" may be defined separately from the sideband signals "used between NRZ signals and one or more PAM signals PS".

[0053] According to some example embodiments, the conversion circuit 1300 can upconvert the data rate of one or more first NRZ signals NS1 based on one or more sideband signals SBS, and provide the converted NRZ signal as one or more second NRZ signals NS2. Optionally, the conversion circuit 1300 can downconvert the data rate of one or more second NRZ signals NS2 based on one or more sideband signals SBS, and provide the converted NRZ signal as one or more first NRZ signals NS1. Optionally, the conversion circuit 1300 can provide conversion of modulation schemes between one or more first NRZ signals NS1 and one or more PAM signals PS.

[0054] According to some example embodiments, the test apparatus may be configured to support or require a data rate relatively lower than that supported or required by the DUT, or to support or require a modulation scheme different from that of the DUT. Therefore, a conversion circuit 1300 may be disposed between the test apparatus and the DUT to convert the signal to the required speed and / or modulation scheme on each side, thereby realizing a bidirectional interface between the test apparatus and the DUT.

[0055] According to the above embodiments, the interface chip 1000 can provide a bidirectional interface between the test device and the DUT that supports or requires different data rates and / or modulation schemes, so that the DUT can be tested even when using test devices with different standards.

[0056] Figure 2 This is a diagram illustrating an interface chip according to some example embodiments.

[0057] Reference Figure 2According to some example embodiments, the first interface circuit 1100 may be configured to receive a plurality of first CA (command address) signals CA1_1 to CA1_N classified as first NRZ signals, and to transmit or receive a first data signal DQ1 and an error flag signal EF classified as first NRZ signals. The first interface circuit 1100 may be configured to receive a set signal SET and an on-the-fly (OTF) signal classified as sideband signals. The first interface circuit 1100 may include a plurality of pins for transmitting or receiving the aforementioned signals.

[0058] Each first CA signal can be considered as a signal sent from the test device through a single CA channel. The CA pins on the test device side can be classified into two CA channels. For example, there may be a CA channel mapped to CA pins that are "including even-numbered CA pins" and a CA channel mapped to CA pins that are "odd-numbered CA pins".

[0059] Despite Figure 2 Only one first data signal DQ1 is shown, but in some example embodiments, similar to the first CA signal, multiple first data signals DQ1 can be transmitted or received through multiple channels. For example, the channel through which the data signal is transmitted or received may correspond to the most significant bit (MSB) or the least significant bit (LSB).

[0060] Each channel used to send or receive each signal can send or receive a signal of a number of bits corresponding to the number of pins included in the channel.

[0061] The second interface circuit 1200 can be configured to transmit a second CA signal CA2 classified as a second NRZ signal. The second interface circuit 1200 can also be configured to transmit or receive a second data signal DQ2 classified as a PAM signal. The second interface may include multiple pins for transmitting or receiving the aforementioned signals. In one embodiment, the first data signal DQ1 and the second data signal DQ2 may correspond to multiple first CA signals CA1_1 to CA1_N.

[0062] According to some example embodiments, the first interface circuit 1100 and the second interface circuit 1200 can send or receive CA signals via the CA pin, send or receive data signals via the DQ pin, and send or receive error flag signals EF via the DQE pin.

[0063] The conversion circuit 1300a may include a CA conversion circuit 1310 and a data conversion circuit 1320 connected to the first interface circuit 1100 and the second interface circuit 1200.

[0064] CA conversion circuit 1310 can perform conversion operations on CA signals and internal setting operations for the conversion operations. A setting signal SET, classified as a sideband signal, can be applied from the test device to CA conversion circuit 1310 to perform a setting operation. The setting signal SET can be a signal used to set or determine whether to output a second CA signal CA2 through the second interface circuit 1200.

[0065] When the test device attempts to provide the CA signal to the DUT to perform a test, the test device may provide a SET signal with a first logic value (e.g., logic low or logic high) to the interface chip 1000. Optionally, when the test device intends to set the interface chip 1000, the test device may provide a SET signal with a second logic value (e.g., logic high or logic low) to the interface chip 1000.

[0066] When a set signal SET with a second logic value is provided to interface chip 1000, interface chip 1000 does not output the second CA signal CA2. CA conversion circuit 1310 may perform a setting operation based on register setting values. Examples of setting operations according to some example embodiments may include a mode setting operation for setting how the second CA signal CA2 is provided. In the mode setting operation, when the test apparatus cannot provide the CA signal to the DUT at a data rate supported by the test apparatus (e.g., when it is difficult to meet the data rate required by the DUT), CA conversion circuit 1310 may operate to output the second CA signal CA2 using multiple first CA signals CA1_1 to CA1_N.

[0067] Optionally, during mode setup operation, when the test apparatus can provide CA signals to the DUT at the data rate required by the DUT (e.g., when the data rate required by the DUT can be met), the CA conversion circuit 1310 can operate to output a second CA signal CA2 using at least a portion of a plurality of first CA signals CA1_1 to CA1_N. At least a portion of the first CA signals can be transmitted through at least a portion of a plurality of CA channels, and the plurality of first CA signals CA1_1 to CA1_N are transmitted from the test apparatus through the plurality of CA channels.

[0068] When multiple first CA signals CA1_1 to CA1_N are used, the CA conversion circuit 1310 can upconvert the data rate of the CA signals to be supplied from the test apparatus to the DUT. For example, the second CA signal CA2 can have a higher data rate than the first CA signal.

[0069] When at least a portion of the multiple first CA signals CA1_1 to CA1_N are used, the CA conversion circuit 1310 can maintain the data rate of the CA signals as is. For example, the second CA signal CA2 can have the same data rate as the first CA signal.

[0070] In some example embodiments, the test apparatus may support speeds of, for example, 8 Gbps, and the data rate of each first CA signal is 5 Gbps. When the speed required by the memory device is higher than 8 Gbps, the CA conversion circuit 1310 may perform a conversion operation using multiple first CA signals CA1_1 to CA1_N via a mode setting operation. Alternatively, when the speed required by the memory device is 8 Gbps or less, the CA conversion circuit 1310 may perform a conversion operation using at least a portion of the first CA signals via a mode setting operation.

[0071] According to some example embodiments, the data conversion circuit 1320 may perform a conversion operation on a data signal based on an OTF signal classified as a sideband signal. The OTF signal may be applied from a test device and may be used to convert the data signal. In some example embodiments, the data conversion circuit 1320 may provide a conversion between a first data signal DQ1, an error flag signal EF, and a second data signal DQ2 based on the OTF signal.

[0072] In some example embodiments, the data conversion circuit 1320 may receive a first data signal DQ1 from the test apparatus, convert the first data signal DQ1 into a second data signal DQ2, and output the second data signal DQ2 to the DUT. For example, the data conversion circuit 1320 may extend the first data signal DQ1 based on the OTF signal OTF. The extension of the first data signal DQ1 can be used to prepare a data signal for encoding the required number of symbols for the DUT.

[0073] Data conversion circuit 1320 generates a cyclic redundancy check (CRC) (e.g., a CRC code) for the first data signal DQ1 and provides the second data signal DQ2 to the second interface circuit 1200 based on encoding the extended first data signal E_DQ1, the error flag signal EF, and the CRC. Encoding represents the conversion of a bit-wise signal into a symbol-wise signal, and the NRZ signal can be modulated into a PAM signal through encoding. Encoding can be performed using an encoding scheme defined for each signal.

[0074] In some example embodiments, the data conversion circuit 1320 may receive a second data signal DQ2 from the DUT, convert the second data signal DQ2 into a first data signal DQ1, and output the first data signal DQ1 to the test apparatus. For example, the data conversion circuit 1320 may decode the second data signal DQ2 and select a specific position from some decoded signals based on the OTF signal OTF. Through this selection, only the data signal with the required number of bits for the test apparatus can be provided to the test apparatus.

[0075] The data conversion circuit 1320 can generate a pass / fail (PF) signal by performing a CRC comparison on some decoded signals. The data conversion circuit 1320 can output the PF signal to the test device through the first interface circuit 1100.

[0076] The data conversion circuit 1320 can output some decoding signals corresponding to the error flag to the test device through the first interface circuit 1100.

[0077] Decoding involves converting a symbol-level signal into a bit-level signal. Through this decoding, a PAM signal can be modulated into an NRZ signal. Decoding can be performed using a decoding scheme defined for each signal.

[0078] According to some of the above example embodiments, the interface chip 1000 can convert signals from the test apparatus in response to the data rate or modulation scheme required by the DUT, or can convert signals from the DUT in response to the data rate or modulation scheme required by the test apparatus. As a result, interface constraints for testing can be resolved and / or mitigated, and / or the utilization of existing equipment can be increased and / or investment in new equipment can be reduced.

[0079] Figure 3 This illustrates some example embodiments. Figure 2 A diagram of the CA conversion circuit.

[0080] Reference Figure 3 According to some example embodiments, the CA conversion circuit 1310 may include a demultiplexer 1311, a register 1312, and a multiplexer 1313.

[0081] Demultiplexer 1311 can be configured to demultiplex a plurality of first CA signals CA1_1 to CA1_N based on a setting signal SET classified as a sideband signal, and in response to demultiplexing, provide a second CA signal CA2 classified as a second NRZ signal to the second interface circuit 1200. Demultiplexer 1311 can perform demultiplexing based on a demultiplexing setting.

[0082] According to some example embodiments, through demultiplexing, multiple first CA signals CA1_1 to CA1_N are converted into continuous (e.g., serialized) signals. Therefore, the second CA signal CA2 output by demultiplexing can have a higher speed than the first CA signals. The demultiplexer 1311 performs serialization and can therefore also be referred to as a serializer.

[0083] As an example, in some example embodiments, the plurality of first CA signals CA1_1 to CA1_N include two first CA signals.

[0084] Demultiplexer 1311 demultiplexes a first CA signal received from two CA channels to output a single second CA signal CA2. For example, demultiplexer 1311 can be implemented as a 2:1 structure performing demultiplexing on two input channels and one output channel. The output second CA signal CA2 can have a higher data rate than the first CA signal. For example, when the data rate of the first CA signal is k (where k is a real number greater than 0), the data rate of the second CA signal CA2 can be twice that (or 2k).

[0085] According to some example embodiments, demultiplexer 1311 may be implemented to perform demultiplexing greater than 2:1 (e.g., N:1 (where N is a positive integer and is the number of CA channels and the number of multiple first CA signals CA1_1 to CA1_N)).

[0086] Demultiplexer 1311 can output the second CA signal CA2 to register 1312 and multiplexer 1313.

[0087] Register 1312 can perform various settings for the operation of the interface chip. A second CA signal CA2 can be applied to register 1312 for setting, or register 1312 can enter a setting mode based on the power-on and initialization and / or configuration of the interface chip, or the settings of register 1312 can be executed. The CA signal applied to register 1312 may include commands and addresses for setting register 1312.

[0088] According to some example embodiments, register 1312 can perform the above-described mode setting operation based on a second logic value indicated by the SET signal. Register 1312 can set demultiplexing through the mode setting operation.

[0089] For example, register 1312 can set the demultiplexing performed by demultiplexer 1311 to 1:1 mode based on the data rate required by the second CA signal CA2 being less than K (where K is a real number greater than 0). Alternatively, register 1312 can set the demultiplexing performed by demultiplexer 1311 to N:1 mode based on the data rate required by the second CA signal CA2 being greater than or equal to K. For example, register 1312 can consider the data rate required by the DUT to set whether to operate demultiplexing in 1:1 or N:1 mode. When the test apparatus determines that a single CA channel cannot support the data rate required by the DUT, register 1312 can set the demultiplexing to N:1 mode.

[0090] Multiplexer 1313 can be configured to select one of a No Operation (NOP) signal and a second CA signal CA2 corresponding to demultiplexing, and output the selected signal (SEL).

[0091] According to some example embodiments, the multiplexer 1313 may receive a setting signal SET as a signal for selection, select the NOP signal NOP for the command DUT to operate in the idle state based on the setting signal SET indicating a second logic value, and provide the NOP signal NOP to the second interface circuit 1200.

[0092] Optionally, according to some example embodiments, the multiplexer 1313 may select the second CA signal CA2 based on the setting signal SET indicating a first logic value, and provide the second CA signal CA2 to the second interface circuit 1200.

[0093] According to the above embodiments, although register 1312 has been described as being included in CA conversion circuit 1310, register 1312 may be separately disposed in other components within conversion circuit 1300a, or disposed in conversion circuit 1300a, first interface circuit 1100 and / or second interface circuit 1200, instead of being disposed in CA conversion circuit 1310.

[0094] In addition to the mode settings for demultiplexing described above, register 1312, according to some example embodiments, can perform various settings for the interface chip. For example, register 1312 can set the first interface circuit 1100 and / or the second interface circuit 1200, or it can set training operations, latency and delays associated with the interface chip, and various analog elements included in the interface chip, which will be described later.

[0095] Register 1312 can generate register signals for controlling and / or setting the operation of components associated with the interface chip.

[0096] According to some example embodiments, the CA conversion circuit 1310 can provide a CA signal with increased speed to the DUT by demultiplexing multiple CA channels. NRZ modulation can be used to modulate the CA signal; NRZ modulation is commonly used in test equipment and the DUT. For example, conversion of the modulation scheme used for the CA signal may not be necessary. The CA conversion circuit 1310 can flexibly configure the demultiplexing to take into account the data rate required by the DUT.

[0097] Figure 4 This is a diagram illustrating a CA conversion operation in a 2:1 mode according to some example embodiments, and Figure 5 This is a diagram illustrating CA conversion operations in 1:1 mode according to some example embodiments. Figure 4 and Figure 5 In this context, when the aforementioned SET signal indicates the first logic value, the CA conversion operation can be considered as the operation of the demultiplexer.

[0098] Reference Figure 4 When demultiplexing is set to 2:1 mode, demultiplexer 1311 can demultiplex two first CA signals CA0 and CA1 received from two CA channels. The second CA signal CA2 output as a result of demultiplexing can be a signal obtained by serializing the two first CA signals CA0 and CA1. Therefore, the second CA signal CA2 can have a speed twice that of the first CA signal.

[0099] Reference Figure 5 When demultiplexing is set to 1:1 mode, demultiplexer 1311 can select one of two first CA signals, CA0 and CA1 (e.g., CA0), received from the two CA channels and output the selected CA signal as is. For example, the second CA signal CA2 is the same as one of the first CA signals. The single first CA signal to be selected can also be CA1 in addition to CA0 shown. When all the first CA signals have the same speed, any first CA signal can be selected in 1:1 mode to meet the speed required by the DUT.

[0100] For example, the two first CA signals CA0 and CA1 can be mapped to even-numbered CA pins and odd-numbered CA pins, respectively.

[0101] Figure 6 This is a diagram illustrating a data conversion circuit according to some example embodiments.

[0102] Reference Figure 6 According to some example embodiments, the data conversion circuit 1320a may include a DQ extension circuit 1321a, a first encoder 1322a, a second encoder 1323a, a CRC circuit 1324a, and a third encoder 1325a. Figure 6The data conversion circuit 1320a can be configured for operation in the direction of the DUT in the test apparatus (e.g., from the test apparatus toward the DUT) (e.g., during a data write operation).

[0103] The DQ expansion circuit 1321a can be configured to receive an OTF signal (OTF) and a first data signal DQ1 as an NRZ signal from a test apparatus, and to expand the first data signal DQ1 based on the OTF signal (OTF). For example, the DQ expansion circuit 1321a can expand the number of bits of the first data signal DQ1 by either copying the first data signal DQ1 based on the OTF signal (OTF) or inverting the first data signal based on the OTF signal (OTF). The DQ expansion circuit 1321a can apply copying and / or inversion to specific bits of the first data signal DQ1, or it can apply copying or inversion to all bits. In addition to copying or inversion, the DQ expansion circuit 1321a can perform expansion through various operations for increasing the number of bits of the signal.

[0104] The DQ expansion circuit 1321a can expand the number of bits of the first data signal DQ1 to "compensate for the number of bits required for encoding by the first encoder 1322a", and output the expanded first data signal E_DQ1.

[0105] The first encoder 1322a can encode the extended first data signal E_DQ1 to output the first encoded signal ES1.

[0106] The second encoder 1323a can receive an error flag signal EF from the test device and encode the error flag signal EF to output a second encoded signal ES2. For example, the error flag signal EF can be a poison / severity (P / S) signal supported by double data rate (DDR). The error flag signal EF can consist of 2 bits and can indicate whether an error has occurred in the memory device and the severity of the error.

[0107] The first encoded signal ES1 and the second encoded signal ES2 can be provided together to the CRC circuit 1324a. The CRC circuit 1324a can generate a CRC from the first encoded signal ES1.

[0108] The third encoder 1325a can encode the CRC to output the third encoded signal ES3.

[0109] Finally, the second data signal DQ2 output by the data conversion circuit 1320a may include the first encoded signal ES1 to the third encoded signal ES3.

[0110] Each of the first encoders 1322a to the third encoder 1325a can encode predefined bits in the target signal into a predefined number of symbols. For each encoder, the predefined number of bits and the predefined number of symbols can be set to be the same or different. The target signal can be encoded symbol by symbol, thereby converting from an NRZ signal to a PAM signal. Therefore, the first encoded signal ES1 to the third encoded signal ES3 can be signals in symbol-based units.

[0111] Some example embodiments based on the data rate required by the memory device are provided. In some example embodiments, GDDR7, as a graphics-oriented DDR, can be cited as an example of the Joint Electronic Equipment Committee (JEDEC) standard. GDDR7 may require a data rate of 32 Gbps or higher.

[0112] In some example embodiments with data speeds less than 32 Gbps, the test apparatus can transmit and receive 128 bits over eight unit intervals (UI). The test apparatus can transmit a 32-bit OTF signal (OTF) from two channels via the OTF pin and can transmit and receive a 2-bit error flag signal (EF) via the DQE pin.

[0113] The DQ extension circuit 1321a can extend the 128-bit first data signal DQ1 to 256 bits. The OTF signal used for extension can be 32 bits. The size of the OTF signal can be set differently depending on the number of bits to be extended. The first encoder 1322a can output a first encoded signal ES1 of 163 symbols through 11b7s encoding. In the following, "xbys" in this application can be defined as an encoding method that maps x bits to y symbols.

[0114] The second encoder 1323a can output a second encoded signal ES2, which consists of one symbol, through 2b1s encoding. The CRC circuit 1324a can generate an 18-bit CRC from the first encoded signal ES1, and the third encoder 1325a can output a third encoded signal ES3, consisting of 12 symbols, through 3b2s encoding. Finally, the data conversion circuit 1320a can output a second data signal DQ2, consisting of a first encoded signal ES1 with 163 symbols, a second encoded signal ES2 with one symbol, and a third encoded signal ES3 with 12 symbols. The second data signal DQ2 can be modulated from the NRZ signal to a PAM signal through the above encoding.

[0115] In some example embodiments with data speeds of 32 Gbps or higher, the test apparatus can transmit and receive 64 bits during 4 UI. The test apparatus receives 48 bits of OTF signal (OTF) from 6 channels via the OTF pin.

[0116] The DQ extension circuit 1321a can extend the 64-bit first data signal DQ1 to 256 bits. The OTF signal used for extension can be 48 bits. The size of the OTF signal can be set differently depending on the number of bits to be extended. The first encoder 1322a can output a first encoded signal ES1 of 163 symbols through 11b7s encoding. Then, similar to some example embodiments with data rates less than 32Gbps, the first encoder 1322a to the third encoder 1325a can perform encoding, and the CRC circuit 1324a can generate a CRC. Therefore, the data conversion circuit 1320a can output a second data signal DQ2 of 176 symbols.

[0117] Figure 7 and Figure 8 This is a diagram illustrating the conversion operation of the data conversion circuit according to an example scenario. Figure 7 The document provides some example implementations of data rates less than 32Gbps in GDDR7. Figure 8 The document provides some example implementations of data rates of 32Gbps or higher in GDDR7.

[0118] Reference Figure 7 Through the data conversion circuit 1320 according to the above embodiment, the first data signal DQ1 can be expanded into a first data signal E_DQ1 based on the OTF signal OTF. The expanded first data signal E_DQ1 may include the original first data signals (D0 and D1) and the first data signal DQ1 (D0) copied (and / or inverted) based on the OTF signals F0 and F1 corresponding to the two channels (or pins). F0 and D1 F1 ).

[0119] The extended first data signal E_DQ1 can be encoded into a second data signal DQ2 (PAM signal) via ENC encoding. The second data signal DQ2 can be a PAM3 modulated signal and has three voltage levels.

[0120] Reference Figure 8 The extended first data signal E_DQ1, extended by the data conversion circuit 1320 according to the above embodiment, may include the original first data signals (D0 and D1) and the first data signal DQ1 (D0) copied (and / or inverted) based on the OTF signals F0 to F5 corresponding to the six channels (or pins). F0 D0 F2 D0 F4 D1 F1 D1 F3 and D1 F5At data rates of 32Gbps or higher, the first data signal DQ1 received from the test device is 64 bits, thus requiring more OTF signals and extensions.

[0121] According to the above embodiments, the data conversion circuit 1320 can provide compatibility for writing data signals between a test device and a memory device with different modulation schemes NRZ / PAM, different data rates, and / or different pin numbers.

[0122] Figure 9 This is a diagram illustrating a data conversion circuit according to some example embodiments.

[0123] Reference Figure 9 According to some example embodiments, the data conversion circuit 1320b may include a first decoder 1321b, a DQ selection circuit 1322b, a CRC circuit 1323b, and a second decoder 1324b. Figure 9 The data conversion circuit can be configured for operation from the DUT toward the test apparatus (e.g., testing during a data readout operation).

[0124] The first decoder 1321b can decode multiple first symbols S1 from the second data signal DQ2 to obtain a first decoded signal DS1. The second data signal DQ2 is a PAM signal and is in symbol units. The multiple first symbols S1 can be the first symbols excluded from the second data signal DQ2, excluding multiple second symbols S2 and multiple third symbols S3 that are "symbols associated with errors". The first decoder 1321b can output the first decoded signal DS1 to the DQ selection circuit 1322b.

[0125] The DQ selection circuit 1322b can select a specific bit from the first decoded signal DS1 based on the OTF signal OTF and output the specific bit as the first data signal DQ1. Unlike the test operation in the data write operation, the specifications of the data read from the DUT may be incompatible with the specifications required by the test apparatus. For example, it may be difficult to use the DQ pins provided in the test apparatus to receive the read data. Therefore, considering the number of DQ pins, the DQ selection circuit 1322b can select only a specific bit from the first decoded signal DS1. The number of bits selected can vary depending on the number of DQ pins.

[0126] The DQ selection circuit 1322b can repeatedly output the selected specific bit, so that the first decoded signal DS1 can be fully output even when the number of DQ pins of the test device is incompatible.

[0127] The CRC circuit 1323b generates and outputs the PF signal P / F by performing CRC comparisons on multiple second symbols S2. The PF signal P / F indicates whether there are errors in the data verified by the CRC. When the PF signal P / F indicates success, it verifies that "there are no errors in the received signal," while when the PF signal P / F indicates failure, there are errors in the received signal.

[0128] The second decoder 1324b can decode the third symbol S3 corresponding to the error flag from the second data signal DQ2 to obtain the second decoded signal DS2, and output the obtained second decoded signal DS2.

[0129] Finally, the data conversion circuit 1320b can output a signal including the PF signal P / F output from the CRC circuit 1323b and the second decoding signal DS2 output from the second decoder 1324b as an error flag signal EF.

[0130] As described above, the first decoder 1321b to the second decoder 1324b can decode predefined symbols from the target signal into a predefined number of bits. For each decoder, the predefined number of symbols and the predefined number of bits can be set to be the same or different. Since encoding is performed bit by bit, the target signal can be converted from a PAM signal to an NRZ signal. Therefore, the first decoded signal DS1 and the second decoded signal DS2 can be bit-based signals.

[0131] As described above, some example implementations based on a data rate of 32Gbps can be considered.

[0132] In some example embodiments with data rates less than 32 Gbps, the data conversion circuit 1320b can provide a second data signal DQ2 of 176 symbols. The first decoder 1321b can use "7s11b decoding" to decode 163 of the 176 symbols (first symbol S1) and output a 256-bit first decoded signal DS1. In this application, "xsyb" is defined as a decoding method that maps x symbols to y bits.

[0133] The CRC circuit 1323b can perform CRC comparison based on 12 symbols (second symbol S2) out of 176 symbols, and can output a 1-bit PF signal P / F based on the comparison result. The second decoder 1324b can decode the remaining 1 symbol (third symbol S3) out of 176 symbols through "1s2b decoding", and output a 2-bit second decoded signal DS2.

[0134] The DQ selection circuit 1322b can select 128 bits from the 256 bits of the first decoded signal DS1 based on the OTF signal OTF. The OTF signal used for selection can be a 32-bit signal. The DQ selection circuit 1322b can output the 128 bits twice. The test device can read the 128 bits of data twice.

[0135] Finally, the data conversion circuit 1320b can output a 128-bit first data signal DQ1, a 2-bit error flag signal EF, and a 1-bit PF signal P / F. The first data signal DQ1 can be converted from PAM to NRZ modulation through the above decoding.

[0136] In some example embodiments with data rates of 32 Gbps or higher, the DQ selection circuit 1322b can select 64 bits from the 256 bits of the first decoded signal DS1 based on the OTF signal OTF. The OTF signal used for selection can be a 48-bit signal. Therefore, the data conversion circuit 1320b can output a 64-bit first data signal DQ1. The data conversion circuit 1320b can output 64 bits four times. The test device can read the 64-bit data four times.

[0137] According to the above embodiments, the data conversion circuit 1320b can provide compatibility for data signal reading operations between test devices and memory devices with different modulation schemes NRZ / PAM, different data rates, and / or different pin numbers.

[0138] According to some example embodiments, Figure 6 and Figure 9 Each component of the data conversion circuits 1320 (1320a and 1320b) can be configured or implemented to perform two conversion operations based on write and read operations. For example, the DQ extension circuit 1321a and the DQ selection circuit 1322b can be configured in an integrated manner, the first encoder 1322a and the first decoder 1321b can be configured as a single unit, and the third encoder 1325a and the second decoder 1324b can be configured as a single unit. The CRC circuit 1323b can be configured to perform both CRC generation and CRC comparison.

[0139] Figure 10 This is a block diagram of a conversion circuit according to some example embodiments.

[0140] Reference Figure 10 In addition to the embodiments described above (e.g., Figures 2 to 9 In addition to the CA conversion circuit 1310 and the data conversion circuit 1320, the conversion circuit 1300b according to some example embodiments may also include a first training circuit 1330a and a second training circuit 1330b (collectively referred to as training circuit 1330).

[0141] According to some example embodiments, the first training circuit 1330a and the second training circuit 1330b can be configured separately from the CA conversion circuit 1310 and the data conversion circuit 1320. According to the above embodiments, the CA conversion circuit 1310 can convert a first CA signal CA1 (unidirectional signal) into a second CA signal CA2. The data conversion circuit 1320 can convert between a first data signal DQ1 and a second data signal DQ2 (bidirectional signal).

[0142] The first training circuit 1330a can be configured to perform training on the test device side.

[0143] The first training circuit 1330a can receive a first CA training signal CA_T1, defined as a training signal for CA, from the test device, and perform training on the CA signal based on the received signal. The first training circuit 1330a can also perform training on a data signal when sending or receiving a first data training signal DQ_T1 from the test device, where the first data training signal DQ_T1 is defined as a training signal for data. The first training circuit 1330a can also perform training on an error detection signal by generating a first error training signal ERR_T1, defined as a training signal for error detection, and providing the first error training signal ERR_T1 to the test device.

[0144] In this application, training can be defined as the operation of synchronizing at least two signals (or matching the skewness of at least two signals), and can be performed before normal operation is performed by the test apparatus according to the above embodiments.

[0145] The second training circuit 1330b can be configured to perform training on the DUT side.

[0146] The second training circuit 1330b can be configured to convert the first CA training signal CA_T1 into a second CA training signal CA_T2, and to perform conversion between the first data training signal DQ_T1 and the second data training signal DQ_T2. The second training circuit 1330b can also be configured to receive a second error training signal ERR_T2, defined as a training signal for error detection, from the DUT, and convert the second error training signal ERR_T2 into the first error training signal ERR_T1.

[0147] The first CA training signal CA_T1 and the second CA training signal CA_T2 can be sent or received on the same CA pin used for sending or receiving the first CA signal CA1 and the second CA signal CA2. The first data training signal DQ_T1 and the second data training signal DQ_T2 can be sent or received on the same DQ pin used for sending or receiving the first data signal DQ1 and the second data signal DQ2. The first error training signal ERR_T1 and the second error training signal ERR_T2 can be sent or received on the same pin used for sending or receiving error detection signals.

[0148] According to the above embodiment, the conversion circuit 1300b may include a first training circuit 1330a and a second training circuit 1330b, which are used for training to synchronize signals and are separate from circuits 1310 and 1320 used for normal operation (such as the conversion of CA signals and data signals for testing). The training circuits can perform synchronization via hardware different from that used in normal operation. Training may require operations involving a load (such as random data generation). However, when the first training circuit 1330a and the second training circuit 1330b are configured separately, both normal operation and training can be performed effectively.

[0149] Figure 11A This is a diagram illustrating a first training circuit according to some example embodiments.

[0150] Reference Figure 11A According to some example embodiments, the first training circuit 1330a may include a first CA training path 1331a for CA training, a first write training path 1332a for writing training, a first read training path 1333a for reading training, and a first error training path 1334a.

[0151] According to some example embodiments, each training path may be connected to one or more pins corresponding to the training signal, including pins in the first interface circuit 1100 and the second interface circuit 1200. For example, the first CA training path 1331a may be connected to one or more first CA pins CA1_P, and the first write training path 1332a and the first read training path 1333a may be connected to one or more first DQ pins DQ1_P. The first error training path 1334a may be connected to one or more first error pins ERR1_P.

[0152] The first CA training path 1331a can be configured to perform training on the test device based on the CA training signal provided from the test device.

[0153] The first write training path 1332a and the first read training path 1333a can be connected to the switch SW. The pins connected to the training paths can be mapped via the switch SW.

[0154] The switch SW can be connected to one or more first DQ pins DQ1_P to provide a write training signal from one or more first DQ pins DQ1_P to the first write training path 1332a, or to provide a read training signal from the first read training path 1333a to one or more first DQ pins DQ1_P.

[0155] The first write training path 1332a can receive write training signals from one or more first DQ pins DQ1_P and perform write training according to the switching of switch SW, and the first read training path 1333a can send read training signals to one or more first DQ pins DQ1_P and perform read training according to the switching of switch SW.

[0156] The first error training path 1334a can generate a first error training signal and provide the first error training signal to the first interface circuit through one or more first error pins ERR1_P.

[0157] Figure 11B This is a diagram illustrating a second training circuit according to some example embodiments.

[0158] Reference Figure 11B According to some example embodiments, the second training circuit 1330b may include a second CA training path 1331b for CA training, a second write training path 1332b for writing training, a second read training path 1333b for reading training, and a second error training path 1334b.

[0159] According to some example embodiments, each training path may be connected to one or more pins corresponding to the training signal, including pins in the first interface circuit 1100 and the second interface circuit 1200. For example, the second CA training path 1331b may be connected to one or more first CA pins CA1_P and one or more second CA pins CA2_P, and the second write training path 1332b and the second read training path 1333b may be connected to one or more first DQ pins DQ1_P and one or more second DQ pins DQ2_P.

[0160] The second CA training path 1331b can be a path that provides training signals for CA, which are provided in one direction from one or more first CA pins CA1_P to one or more second CA pins CA2_P. The CA training signals can be provided to the DUT via the second CA training path 1331b instead of the CA conversion circuit 1310 according to some example embodiments.

[0161] The second write training path 1332b and the second read training path 1333b can be connected to the first switch SW1b and the second switch SW2b. The pins connected to each training path can be mapped via the first switch SW1b and the second switch SW2b.

[0162] The first switch SW1b can be connected to one or more first DQ pins DQ1_P to provide a write training signal from one or more first DQ pins DQ1_P to the second write training path 1332b, or to provide a read training signal from the second read training path 1333b to one or more first DQ pins DQ1_P.

[0163] The second switch SW2b can be connected to one or more second DQ pins DQ2_P to provide the read training signal from one or more second DQ pins DQ2_P to the second read training path 1333b, or to provide the write training signal from the second write training path 1332b to one or more second DQ pins DQ2_P.

[0164] The second write training path 1332b can receive a write training signal classified as a first NRZ signal through a first interface circuit 1100 including pins, and expand the write training signal to "the number of bits required to map to the DUT". The second write training path 1332b can map the expanded write training signal into I groups (where I is a positive integer) and symbols, and provide the mapped write training signal to the second interface circuit 1200.

[0165] I groups can be defined for multiple pins (e.g., second DQ pins) included in the second interface circuit 1200, and the I groups can be mapped to write training signals. For example, multiple second DQ pins can be grouped into I groups.

[0166] The testing setup may have a limit on the number of channels allocated. In this regard, grouping can be applied to apply a large amount of training data at once. For example, when there are 11 second DQ pins, the 11 pins can be grouped into 4 groups, and the same write training signal can be applied to each group.

[0167] The size of the write training signal applied to each group can be defined as the product of the number of groups, the burst length BL, and the number of bits mapped to a single symbol. The size defined by the product can be equal to the size of the write training signal applied to the test device. For example, when the number of groups is 4, the burst length is 16, and 2 bits are mapped to 1 symbol, a 128-bit write training signal can be applied to each group.

[0168] The second read training path 1333b can receive read training signals classified as PAM signals through a second interface circuit 1200 including pins, and provide the received read training signals to the first interface circuit 1100 by reading the read training signals J times (where J is a positive integer). The number of reads J can be set or defined based on the bit size of the read training signals and / or the number of pins mapped for training on the first DQ pin.

[0169] The second error training path 1334b can receive a second error training signal generated from the DUT for training through one or more second error pins ERR2_P, and convert the second error training signal into a first error training signal. The second error training path 1334b can provide the first error training signal to the first interface circuit through one or more first error pins ERR1_P.

[0170] As an example, some exemplary embodiments of receiving a read training signal of 160 symbols from the DUT are shown. A second switch SW2b maps one or more second DQ pins DQ2_P to a second read training path 1333b, and a first switch SW1b maps one or more first DQ pins DQ1_P to the second read training path 1333b. The second read training path 1333b can convert the 160 symbols into 320 bits, split the 320 bits, and provide the split bits to one or more mapped first DQ pins DQ1_P by J times.

[0171] According to some of the example embodiments described above, the second training circuit 1330b can enable the test device to perform training operations more efficiently by providing a path and mapping for training signals separately from normal operation.

[0172] Figure 12 This is a block diagram of a conversion circuit according to some example embodiments.

[0173] Reference Figure 12 In addition to the above example embodiments (e.g., Figures 2 to 9 In addition to the CA conversion circuit 1310 and the data conversion circuit 1320, the conversion circuit 1300c according to some example embodiments may also include an error conversion circuit 1340 for converting the error detection signal.

[0174] Error conversion circuit 1340 can be implemented according to some of the example embodiments described above (e.g., Figure 1 and Figure 2 The second interface circuit 1200 receives a first error detection signal ERR1, classified as a PAM signal. The first error detection signal ERR1 can be configured to indicate the presence of an error in at least one of the CA signal CA2 and the data signal DQ2. The first error detection signal ERR1 can be a signal generated and provided from the DUT when an error is detected in the DUT through testing.

[0175] Error conversion circuit 1340 can convert the first error detection signal ERR1 into a second error detection signal ERR2 classified as a first NRZ signal. According to some example embodiments, error conversion circuit 1340 can convert a PAM-modulated signal into an NRZ-modulated signal to output the second error detection signal ERR2.

[0176] Optionally, when the speed of the first error detection signal ERR1 on the DUT side is lower than the speed required by the test device, the error conversion circuit 1340 can upconvert the speed of the first error detection signal ERR1 and output a signal with the upconverted speed as the second error detection signal ERR2.

[0177] Figure 13 This illustrates some example embodiments. Figure 12 The waveform diagram shows an example operation of the error switching circuit.

[0178] Reference Figure 13 The test apparatus according to some of the above example embodiments can operate based on a first write clock WCK1, a first clock CK1, a CA signal CA, and a second error detection signal ERR2, and the DUT can operate based on a second write clock WCK2, a second clock CK2, and a first error detection signal ERR1. As an example, in some example embodiments where the test apparatus operates at a relatively low speed compared to the DUT, the first write clock WCK1 and the first clock CK1 are shown to have a lower speed (or lower frequency) than the second write clock WCK2 and the second clock CK2. The frequency of each signal is only set as an example.

[0179] When an example is provided where the first error detection signal ERR1 is modulated by PAM3, the first error detection signal ERR1 may have three logic levels (first level LV1, second level LV2, and third level LV3) as shown. When an example is provided where the second error detection signal ERR2 is modulated by NRZ, the second error detection signal ERR2 may have two logic levels (fourth level LV4 and fifth level LV5) as shown.

[0180] When an error is detected in the CA signal CA, the DUT may send a first error detection signal ERR1 at time t1. The first error detection signal ERR1 may drop from a third level to a first level within a specific period starting from time t1. An example of the first level of the first error detection signal ERR1 representing CA parity check (CAPAR) is provided.

[0181] The error conversion circuit 1340 can receive the first error detection signal ERR1 of PAM3 and convert the received first error detection signal ERR1 into the second error detection signal ERR2 of NRZ. As a result, the test device can receive the second error detection signal ERR2 with two levels (fourth level and fifth level) and two bits at time t2.

[0182] Then, when an error is detected in the written data, a first error detection signal ERR1 is transmitted at time t3. The first error detection signal ERR1 may drop from a third level to a second level during a specific period starting from time t3. An example is provided where the second level of the first error detection signal ERR1 represents a written CRC (WRCRC).

[0183] The error conversion circuit 1340 can receive the first error detection signal ERR1 of PAM3 and convert the received first error detection signal ERR1 into the second error detection signal ERR2 of NRZ. As a result, the test device can receive the second error detection signal ERR2 with two levels (fourth level and fifth level) and two bits at time t4.

[0184] According to some of the example embodiments described above, the error conversion circuit 1340 can convert the error detection signal based on the test and provide the converted error detection signal according to the data rate and modulation scheme required by the test apparatus. As a result, the error conversion circuit 1340 can provide interface functionality for the error detection signal.

[0185] Figure 14 This is a block diagram of a conversion circuit according to some example embodiments.

[0186] Reference Figure 14 In addition to the CA conversion circuit 1310, data conversion circuit 1320 and training circuit 1330 according to some of the above example embodiments, the conversion circuit 1300d according to some example embodiments may also include a first clock conversion circuit 1350 and a second clock conversion circuit 1360.

[0187] The first clock conversion circuit 1350 can be configured to provide a conversion operation for the write clock supplied to the DUT from the test apparatus. The first clock conversion circuit 1350 can receive a first write clock WCK1 from the test apparatus and upconvert the speed of the first write clock WCK1 to match the data speed required by the DUT. Therefore, a second write clock WCK2 having the upconverted speed by the first clock conversion circuit 1350 can be output to the DUT.

[0188] The second clock conversion circuit 1360 can be configured to provide a conversion operation for the read clock supplied from the DUT to the test apparatus. The second clock conversion circuit 1360 can receive a first read clock RCK1 from the DUT and down-convert the speed of the first read clock RCK1 to match the data speed required by the test apparatus. Therefore, a second read clock RCK2 with the down-converted speed by the second clock conversion circuit 1360 can be output to the test apparatus.

[0189] According to the above embodiment, the conversion circuit 1300d can provide write and read clocks for testing the test apparatus, the write and read clocks being converted to match the data speeds required by the test apparatus and the DUT. As a result, the conversion circuit 1300d can provide an interface function for the test clock.

[0190] Figure 15 This is a block diagram of a first clock conversion circuit according to some example embodiments.

[0191] Reference Figure 15 According to some example embodiments, the first clock conversion circuit 1350 may include a phase-locked loop (PLL) circuit 1351, a multiplexer 1352, and a suspension circuit 1353.

[0192] PLL circuit 1351 receives a first write clock WCK1 from the test apparatus and multiplies and fixes the frequency of the first write clock WCK1 to a target frequency. According to some example embodiments, the target frequency based on the multiplication can be set differently depending on the write clock speed required by the DUT. The speed of the first write clock WCK1 can be up-converted and provided to the DUT via PLL circuit 1351.

[0193] Multiplexer 1352 may be connected between PLL circuit 1351 and pause circuit 1353. Multiplexer 1352 may receive a first write clock WCK1 applied to PLL circuit 1351 and may be configured to perform a bypass function on PLL circuit 1351. Therefore, the first write clock WCK1 may have a speed converted by PLL circuit 1351, or the first write clock WCK1 may be applied to pause circuit 1353 as the original signal through multiplexer 1352 without modification.

[0194] Based on Figure 3 The settings of register 1312 shown above control multiplexer 1352. According to some example embodiments, multiplexer 1352 may be omitted.

[0195] The pause circuit 1353 can be configured to support a pause function for enabling control during test operations (or training operations) through the test apparatus. For example, the pause circuit 1353 can support a pause function to fix the second write clock signal WCK2 at a logic high (or low) level.

[0196] The second write clock WCK2 can be output to the DUT via the pause circuit 1353. The second write clock WCK2 can be up-converted via the PLL circuit 1351. When the write clock is disabled according to the pause function, the second write clock WCK2 can be output at a fixed specific level.

[0197] Figure 16 This is a flowchart illustrating a method for converting CA signals of an interface chip according to some example embodiments.

[0198] Reference Figure 16 In operation S110, the interface chip can receive multiple first CA signals classified as first NRZ signals and setting signals classified as sideband signals from the test device. For example, the interface chip can receive multiple first CA signals through N channels.

[0199] In operation S120, the interface chip can demultiplex multiple first CA signals based on a setting signal. A second CA signal, classified as a second NRZ signal, can be generated in response to the demultiplexing. According to some example embodiments, when the setting signal indicates a second logic value, the interface chip can internally set the demultiplexing mode operation based on a register. Then, the interface chip can perform demultiplexing based on the set mode.

[0200] During operation of S130, the interface chip can check the logic state of the setting signal.

[0201] When the setting signal indicates the first logic value, the process proceeds to operation S140. In operation S140, the interface chip can send the second CA signal to the DUT.

[0202] Optionally, when the setting signal indicates the second logic value, the process proceeds to operation S150, in which the interface chip can send the NOP signal to the DUT. The interface chip can be configured to demultiplex the mode.

[0203] Figure 17 This is a flowchart illustrating a method for converting write data signals of an interface chip according to some example embodiments.

[0204] Reference Figure 17 In operation S210, the interface chip can receive a first data signal (e.g., write data) and an error flag signal classified as a first NRZ signal from the test device.

[0205] In operation S220, the interface chip can extend the first data signal based on the OTF signal classified as a sideband signal. In operation S220, the data can be copied and / or reversed for extension.

[0206] In operation S230, the interface chip can encode the extended first data signal.

[0207] In operation of S240, the interface chip can encode error flag signals. For example, the encoding can map each signal bit to a symbol based on xbys.

[0208] In operation S250, the interface chip can generate a CRC for the extended first data signal. For example, operations S230 and S250 can be executed in parallel with operation S240, which encodes the error flag signal.

[0209] In operation S260, the interface chip can generate a second data signal based on CRC encoding. The second data signal may include the encoded first data signal, the encoded error flag signal, and the encoded CRC.

[0210] In operation of S270, the interface chip can send the second data signal to the DUT.

[0211] Figure 18 This is a flowchart illustrating a method for converting read data signals from an interface chip according to some example embodiments.

[0212] Reference Figure 18 In operation S310, the interface chip can receive a second data signal from the DUT (e.g., read data).

[0213] In operation of S320, the interface chip can decode the second data signal to generate a first decoded signal and a second decoded signal. For example, decoding can be based on xsyb, mapping each signal symbol to a bit.

[0214] In operation of S330, the interface chip can select some bits of the first decoded signal based on the OTF signal classified as a sideband signal.

[0215] In operation of S340, the interface chip can generate a PF signal by comparing it with the CRC of some symbols (e.g., a second symbol).

[0216] In operation of S350, the interface chip can send the selected bit, PF signal and second decode signal to the test device.

[0217] Figure 19 This is a block diagram of a conversion circuit according to some example embodiments.

[0218] Reference Figure 19 In addition to the CA conversion circuit 1310, data conversion circuit 1320 and error conversion circuit 1340 according to the above embodiments, the conversion circuit 1300e according to some example embodiments may also include a self-training circuit 1370.

[0219] The self-training circuit 1370 can be configured to perform training autonomously. The term "autonomously" can mean that signal training can be performed without controlling the test apparatus.

[0220] According to some example embodiments, the self-training circuit 1370 may operate based on a register set signal R_SET. The register set signal R_SET can be generated using registers according to the above example embodiments. The register set signal R_SET may include various setting / control signals for self-training operations.

[0221] The self-training circuit 1370 can perform and control phase interpolation (PI) for data shifting and phase adjustment of various signals converted by the interface chip, and can autonomously determine the pass or failure state of timing errors. When a "failure" occurs, the self-training circuit 1370 can continue to perform data shifting and / or phase adjustment until a "pass" occurs.

[0222] The self-training circuit 1370 can generate a delay setting signal DLY_SET based on data shifting and / or phase adjustment. The delay setting signal DLY_SET can include the amount of data shifting and / or phase adjustment to be applied to each signal (e.g., CA signals CA1 and CA2, data signals DQ1 and DQ2, error flag signals, and error detection signals ERR1 and ERR2, etc.).

[0223] According to the above embodiment, the self-training circuit 1370 can reduce timing errors by identifying the optimal delay to ensure "pass" and applying the optimal delay to the signal.

[0224] Figure 20 This illustrates some example embodiments. Figure 19 A diagram illustrating the operation of the self-training circuit.

[0225] Reference Figure 20 According to some example embodiments, the self-training circuit 1370 may include a shift circuit 1371, a multiplexer 1372, and a PI 1373.

[0226] The shift circuit 1371 can be configured to receive input data IN (e.g., a bit sequence) and shift the input data IN in units of UI. For example, the shift circuit 1371 can be configured as follows: Figure 20 The diagram shows the input data IN shifted by 4 UI bits, and the output shifted data S_IN. Each number in the input data IN represents the index of each bit, and the shift can involve, for example, shifting bit 0 to bit 4 and shifting bit 1 to bit 5.

[0227] Multiplexer 1372 can receive shifted data S_IN and can select at least a portion of the shifted data S_IN and output it to driver DRV. Driver DRV may be included in the first interface circuit 1100 and / or the second interface circuit 1200 according to the above embodiments, and can be configured to drive the final data and output the driven data to the test apparatus or DUT.

[0228] PI 1373 can be configured to adjust the phase of the data applied to the driver DRV. At least a portion of the shifted data S_IN is applied to the driver DRV via multiplexer 1372, such that PI 1373 can adjust the phase of the shifted data S_IN in units of at least some cells.

[0229] Figure 21 This is a diagram illustrating a test system according to some example embodiments.

[0230] Reference Figure 21 According to some example embodiments, the test system 2000 may include a test apparatus 2100, a DUT 2200, and an interface chip 2300.

[0231] The test apparatus 2100 may include a test interface circuit 2110 for sending signals to and receiving signals from the interface chip 2300. The test interface circuit 2110 may include multiple pins for sending signals to and receiving signals from the interface chip 2300. The test apparatus 2100 may be connected to the interface chip 2300 via multiple wires to send and receive signals for testing.

[0232] According to some example embodiments, the test interface circuit 2110 may send or receive one or more first NRZ signals NS1 modulated by NRZ, or send one or more sideband signals SBS generated in the test apparatus 2100 to control the interface chip 2300.

[0233] The testing apparatus 2100 can generate signals with test modes for testing (e.g., CA signal, write data signal, etc.), and can use the generated signals to perform tests. The testing apparatus 2100 can receive signals based on the test results.

[0234] DUT 2200 may include DUT interface circuitry 2210 for transmitting signals to and receiving signals from interface chip 2300. According to some example embodiments, DUT interface circuitry 2210 may transmit or receive one or more second NRZ signals NS2 modulated by NRZ, or transmit or receive one or more PAM signals PS modulated by PAM from DUT 2200.

[0235] DUT 2200 may include a variety of semiconductor devices. For example, DUT 2200 may be volatile memory (such as static random access memory (SRAM) or dynamic random access memory (DRAM)) or non-volatile memory (such as flash memory or resistive random access memory (RRAM)).

[0236] The DUT 2200 can be subjected to various signals for testing via the interface chip 2300, and signals corresponding to the test results can be applied via the interface chip 2300 (e.g., applying or sending signals corresponding to the test results to the interface chip 2300).

[0237] Interface chip 2300 can be configured or operated according to the above embodiments. According to some example embodiments, interface chip 2300 can transmit or receive one or more first NRZ signals NS1 via first interface circuit 2310, or receive one or more sideband signals SBS via first interface circuit 2310. Furthermore, interface chip 2300 can transmit or receive one or more second NRZ signals NS2 and one or more PAM signals PS via second interface circuit 2320. Interface chip 2300 can provide conversion between one or more first NRZ signals NS1 and one or more second NRZ signals NS2, or conversion between one or more first NRZ signals NS1 and one or more PAM signals PS via conversion circuit 2330.

[0238] According to the above embodiments, the test system 2000 can provide a bidirectional interface between the test apparatus 2100 and the DUT 2200 that support or require different data rates and / or modulation schemes, thereby allowing the DUT 2200 to be tested even when using test apparatus 2100 with different specifications.

[0239] Figure 22 Based on some example embodiments Figure 21 The flowchart of the training operation on the DUT side of the test system.

[0240] Reference Figure 22In operation S410, the test system can perform training between the test device and the interface chip. In operation S410, the test device and the interface chip can participate in training to synchronize signals with training regarding signals from the test device to the interface chip. According to some example embodiments, in operation S410, CA training, CSP (Command Start Point) setting, write training, read training, and error training can be performed on the test device.

[0241] In operation S420, the test system can initialize the DUT. Initialization can be performed to set the initial settings of the DUT before training it. In operation S420, the DUT can have its power, initialization-related parameters, and registers set.

[0242] In operation of S430, the test system can train the CA signal of the DUT.

[0243] In operating the S440, the test system can set the command start point (CSP) (the start point of the clock signal used for commands).

[0244] In operation of S450, the test system can perform error detection signal training (ERR training) on ​​the DUT.

[0245] In operation S460, the test system can perform read training on the DUT. For example, the test system can perform read training according to the embodiments described above (e.g., Figures 10 to 11B The training circuit is used to synchronize signals related to read operations on the DUT.

[0246] In operation S470, the test system can perform write training on the DUT. For example, the test system can perform write training according to the embodiments described above (e.g., Figures 10 to 11B The training circuit is used to synchronize signals related to write operations on the DUT.

[0247] During operation S480, the test system can perform normal operations. After synchronizing the signals via operations S410 to S470, the test system can perform normal testing operations according to the above embodiment.

[0248] For example, based on the normal operation used for testing in operation S480, and based on the test, the conversion circuit 2330 sends the error flag signal EF (e.g., see [link]) through the first interface circuit 2310. Figure 9When provided to test apparatus 2100, test apparatus 2100 can determine that the DUT 2200 associated with the error flag signal EF can be classified and / or upgraded and / or downgraded. For example, based on the error flag signal EF, some DUTs can be recalled; alternatively, based on the error flag signal EF, some DUTs can be provided to some customers but not to others. Optionally or additionally, DUTs can be disposed of based on the error flag signal EF. For example, based on the error flag signal EF, DUTs can be graded and / or discarded or upgraded and / or disposed of to a specific product or application. Optionally or additionally, in some example embodiments, this can be achieved through repeated... Figure 22 Steps S410 to S470 are used to retrain the DUT, and the normal operations for testing can be performed on the DUT again, so that a "pass" test result can be obtained due to retraining. The example embodiment is not limited thereto.

[0249] Figure 23 This is a diagram illustrating the open-circuit test operation of a test system according to some example embodiments.

[0250] Reference Figure 23 According to some example embodiments, the second interface circuit 2320 (see, for example, see...) Figure 21 The DUT interface circuit 2210 may include a current source IS, a driver DRV, and a comparator COMP. The DUT interface circuit 2210 may include a first diode d1 and a second diode d2, wherein the first diode d1 corresponds to a pull-up diode with VDDQ applied, and the second diode d2 corresponds to a pull-down diode connected to ground.

[0251] The current source IS and driver DRV can be configured to apply a test signal for open-circuit testing to one side of the DUT interface circuit 2210 via the first node n1. A voltage level corresponding to the applied test signal can be presented at the second node n2, where the anode of the first diode d1 and the cathode of the second diode d2 are connected. The voltage level can be applied to the input of the comparator COMP via the first node n1, and the comparator COMP can compare the voltage level with a reference level.

[0252] The comparator COMP determines pass or fail based on the result of comparing the voltage level with a reference level. When the test passes, the DUT pins are in normal contact. When the test fails, there is a contact problem.

[0253] Figure 24 and Figure 25 This is a diagram illustrating the signal level adjustment operation of a test system according to some example embodiments.

[0254] Reference Figure 24 and Figure 25According to some example embodiments, the test system can adjust the voltage level of the NRZ modulated signal and / or PAM modulated signal through each interface circuit (e.g., the first interface circuit, the second interface circuit, the test interface circuit, and / or the DUT interface circuit according to the above embodiments). Although Figure 24 Based on PAM3 signals, but some example embodiments are not limited to this.

[0255] PAM3 signals can have the following characteristics: Figure 24 The three voltage levels shown are illustrated, and two reference voltages, VREFDH and VREFDL, can be defined. The NRZ signal can have the following characteristics: Figure 25 The two voltage levels shown are illustrated, and a single reference voltage VREF can be defined.

[0256] For example, the test system can control the voltage levels of the NRZ and PAM signals by controlling the high voltage level VIDH relative to the pull-up (or pull-down) terminals. Alternatively, the test system can proportionally control the medium voltage level VIDM and / or the low voltage level VIDL relative to the high voltage level VIDH based on the terminal conditions.

[0257] As described above, according to some example embodiments, an interface chip for providing an interface connection between a test apparatus and a device under test (DUT), and a test system including the interface chip, can be provided.

[0258] One or more of the elements disclosed above may include processing circuitry (such as hardware including logic circuitry; a hardware / software combination (such as a processor executing software); or a combination thereof), or may be implemented in processing circuitry (such as hardware including logic circuitry; a hardware / software combination (such as a processor executing software); or a combination thereof). For example, processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0259] While some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. An interface chip, comprising: A first interface circuit is connected to the test device, and the first interface circuit is configured to provide an interface to the test device for a first non-return-to-zero signal and a sideband signal. The second interface circuit is connected to the device under test and is configured to provide an interface for the device under test for a second non-return-to-zero signal and a pulse amplitude modulation signal. as well as A conversion circuit, connected to a first interface circuit and a second interface circuit, is configured to provide conversion between a first non-return-to-zero (NRZ) signal and a second NRZ signal based on a sideband signal, as well as conversion between the first NRZ signal and a pulse amplitude modulation (PWM) signal.

2. The interface chip as described in claim 1, wherein, The first interface circuit is configured to receive a plurality of first command address signals provided as a first non-return-to-zero signal, and The conversion circuit is configured to demultiplex the plurality of first command address signals based on a setting signal received as a sideband signal, and in response to the demultiplexing by the conversion circuit, to provide a second command address signal as a second non-return-to-zero signal to the second interface circuit.

3. The interface chip as described in claim 2, wherein, The conversion circuit is configured as follows: Based on the setting signal indicating the first logic value, the second command address signal is provided to the second interface circuit. Based on the setting signal indicating the second logic value, a no-operation signal, commanding the device under test to operate in an idle state, is provided to the second interface circuit, and Configure the demultiplexing settings.

4. The interface chip as described in claim 3, wherein, The conversion circuit is configured as follows: Based on the fact that the data rate required by the second command address signal is less than K, the demultiplexing is set to a 1:1 mode, where K is a real number greater than 0, and Based on the data rate being greater than or equal to K, the demultiplexing is set to an N:1 mode, where N is the number of the plurality of first command address signals.

5. The interface chip as described in claim 1, wherein, The first interface circuit is configured to send a first data signal as a first non-return-to-zero signal to the test device or receive a first data signal as a first non-return-to-zero signal from the test device, and to send an error flag signal to the test device or receive an error flag signal from the test device. The second interface circuit is configured to send the second data signal as a pulse amplitude modulation signal to the device under test or to receive the second data signal as a pulse amplitude modulation signal from the device under test.

6. The interface chip as described in claim 5, wherein, The conversion circuit is configured as follows: Based on the instantaneous signal received as a sideband signal, the first data signal received from the test device is expanded to generate an expanded first data signal. A cyclic redundancy check code is generated for the first data signal received from the test device, and The second data signal is provided to the second interface circuit by encoding the extended first data signal, the error flag signal received from the test device, and the cyclic redundancy check code.

7. The interface chip as described in claim 5, wherein, The conversion circuit is configured as follows: Decode multiple first symbols of the second data signal received from the device under test to obtain a first decoded signal. Based on the instantaneous signal received as a sideband signal, a portion of the bits in the first decoded signal is selected to generate the selected portion of the bits, and Provide a portion of the selected bit to the first interface circuit.

8. The interface chip as described in claim 7, wherein, The conversion circuit is configured as follows: A pass / fail signal is generated by performing a cyclic redundancy check comparison on multiple second symbols of the second data signal received from the device under test. The pass / fail signal is provided to the first interface circuit.

9. The interface chip as described in claim 8, wherein, The conversion circuit is configured as follows: The third symbol corresponding to the error flag signal in the second data signal received from the device under test is decoded to obtain the second decoded signal, and The second decoded signal is provided to the first interface circuit.

10. The interface chip according to any one of claims 1 to 9, further comprising: The training circuit is configured to provide a write training path for write training of the device under test and a read training path for read training of the device under test.

11. The interface chip as described in claim 10, wherein, The training path is configured as follows: The first interface circuit receives the written training signal as the first non-return-to-zero signal. The write training signal is expanded and mapped to the number of bits required by the device under test to provide the expanded write training signal, and The expanded write training signals are mapped into I groups to provide the mapped write training signals to the second interface circuit, where I is a positive integer, and The I groups are defined for multiple pins included in the second interface circuit and are mapped to write training signals.

12. The interface chip as described in claim 10, wherein, The training path is configured as follows: The training signal is received and read as a pulse amplitude modulation signal through the second interface circuit, and The training signal is provided to the first interface circuit by reading the training signal J times, where J is a positive integer.

13. The interface chip according to any one of claims 1 to 9, wherein, The second interface circuit is configured to receive a first error detection signal from the device under test as a pulse amplitude modulation signal. The first error detection signal is configured to indicate whether an error has been detected in at least one of the command address signal and data signal received from the device under test, and The conversion circuit is configured to convert the first error detection signal into a second error detection signal classified as a first non-return-to-zero signal.

14. An interface chip, comprising: The command address conversion circuit is configured to receive a setting signal and a plurality of first command address signals as non-return-to-zero signals from the test device, demultiplex the plurality of first command address signals based on the setting signal, and output a second command address signal to the device under test in response to the demultiplexing by the command address conversion circuit. as well as The data conversion circuit is configured as follows: The error flag signal and the first data signal corresponding to the plurality of first command address signals are sent to the testing device, or the first data signal, the error flag signal, and the instant signal are received from the testing device. The first data signal is a non-return-to-zero signal. The second data signal corresponding to the plurality of first command address signals is sent to the device under test, or received from the device under test. The second data signal is a pulse amplitude modulation signal. The conversion between the first data signal, the error flag signal, and the second data signal is provided based on real-time signals.

15. The interface chip as described in claim 14, wherein, The command address translation circuit includes: The demultiplexer is configured to output a second command address signal based on the demultiplexing; and The multiplexer is configured to select a second command address signal based on a first logic value indicated by a setting signal, and to select a no-operation signal that commands the device under test to operate in an idle state as the output of the command address translation circuit to the device under test based on the second logic value indicated by the setting signal.

16. The interface chip as described in claim 15, further comprising: The register is configured to receive a setting signal and to set the demultiplexing based on a second logic value indicated by the setting signal.

17. The interface chip as described in claim 16, wherein, The register is configured as follows: Based on the fact that the data rate required by the second command address signal is less than K, the demultiplexing is set to a 1:1 mode, where K is a real number greater than 0, and Based on the data rate being greater than or equal to K, the demultiplexing is set to an N:1 mode, where N is the number of the plurality of first command address signals.

18. The interface chip according to any one of claims 14 to 17, wherein, The data conversion circuit is configured as follows: The first data signal received from the test device is extended based on the instantaneous signal to provide an extended first data signal. Generate a cyclic redundancy check code for the first data signal, and The second data signal is output by encoding the extended first data signal, the error flag signal received from the test device, and the cyclic redundancy check code.

19. The interface chip according to any one of claims 14 to 17, wherein, The data conversion circuit is configured as follows: Decoding multiple first symbols of the second data signal received from the device under test yields a first decoded signal. Based on the instantaneous signal, a portion of the bits in the first decoded signal is selected to generate the selected portion of the bits, and Output a portion of the selected bit to the test device.

20. A testing system, comprising: The testing device is configured to send or receive a first non-return-to-zero signal for testing, and to send a sideband signal for setting the operating mode; The device under test is configured to transmit or receive a second non-return-to-zero signal and a pulse amplitude modulation signal; as well as An interface chip, connected to a test device and a device under test, is configured to provide conversion between a first non-return-to-zero (NRZ) signal and a second NRZ signal, as well as conversion between the first NRZ signal and a pulse amplitude modulation (PWM) signal, based on sideband signals.

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