Novel indium phosphide-based vertical plane emitting laser

Abstract

The invention, which relates to the technical field of the laser, discloses a novel indium phosphide-based vertical surface emitting laser comprising an InP-based epitaxial layer, a two-dimensional material layer and a GaAs-based epitaxial layer. The InP-based epitaxial layer comprises an InP substrate, a bottom N-type DBR, an N-type doped layer, an active region and a first P-type doped layer; the GaAs-based epitaxial layer comprises an oxidation limiting layer, a second P-type doping layer and a top P-type DBR; the two-dimensional material layer is used for realizing heterogeneous integration of the InP-based epitaxial layer and the GaAs-based epitaxial layer, and the two-dimensional material layer and the GaAs-based epitaxial layer form a top two-dimensional heat dissipation channel. According to the indium phosphide-based vertical plane emitting laser, the technical bottleneck limited by a material system is broken through, and the high-aluminum-component AlGaAs oxidation limiting layer and the Al < x > Ga < 1-x > As / Al < y > Ga < 1-y > As DBR are grown on the InP-based epitaxial layer through the two-dimensional material layer, so that the preparation of the indium phosphide-based vertical plane emitting laser with high power, low power consumption and low cost is realized.

Description

Technical Field

[0001] This invention relates to the field of laser technology, and in particular to a novel indium phosphide-based vertical surface emitting laser. Background Technology

[0002] With the rapid development of the data communication era, Vertical Cavity Surface Emitting Laser (VCSEL) chips have been widely used in optical communication fields, such as optical interconnects, optical sensing, and optical storage, due to their excellent characteristics, such as small chip size, circular output spot, low operating threshold, high coupling efficiency, and easy integration. Application scenarios include short-range communication in data centers, 5G base stations, and HDMI ultra-high-definition video transmission. VCSELs offer good economic efficiency, practicality, and reliability, bringing great convenience to information exchange in various industries.

[0003] In VCSELs, the distinction between long-wavelength and short-wavelength VCSELs is primarily based on industry-standard optoelectronic bands. Short-wavelength VCSELs typically refer to the 650-1100nm band, mainly based on GaAs / AlGaAs materials, while long-wavelength VCSELs typically refer to the 1200-1650nm band, mainly based on InP / InGaAsP or GaInNAs / GaAs materials. Among long-wavelength VCSELs, indium phosphide (IP)-based VCSELs are compatible with the mainstream InP-based fiber and detector materials used in optical communication, and exhibit more stable luminescence performance at key communication wavelengths (1310nm or 1550nm), making them a preferred solution for achieving long-distance, low-loss optical interconnects. However, due to differences in material systems, manufacturing complexity, and performance requirements, long-wavelength VCSELs, especially IPT-based VCSELs, face significantly more technical challenges than short-wavelength VCSELs.

[0004] The core challenge for long-wavelength VCSELs, especially indium phosphide (IP)-based VCSELs, is the lack of mature oxide confinement layer technology, as seen in short-wavelength VCSELs. The ability to confine current and optical field is a key factor determining VCSEL performance, and oxide confinement layer technology is a mature technology for achieving this. Specifically, oxide confinement layer technology involves selectively oxidizing a specific AlGaAs layer to form an insulating ring oxide layer, thereby achieving concentrated current injection and optical field confinement. It offers advantages such as high current confinement efficiency, good optical field confinement effect, and mature and low-cost processing. However, due to the significant lattice mismatch between indium phosphide and the AlGaAs layer, high-density dislocations and defects are generated during the direct epitaxial growth of the AlGaAs layer, resulting in poor AlGaAs layer quality and making it difficult to form a uniform and reliable alumina confinement layer through wet oxidation. Because of the inability to use oxide confinement layers, existing IPT-based VCSELs have had to adopt other alternatives, but these solutions all have significant shortcomings, directly affecting their performance and commercialization progress.

[0005] Another challenge facing long-wavelength VCSELs is the lack of high-performance GaAs-based semiconductor DBR materials suitable for short-wavelength VCSELs. The DBR mirror is a crucial component of the VCSEL's optical resonator, and its performance directly determines the laser's emission efficiency and threshold current. Short-wavelength VCSELs rely on high-reflectivity GaAs-based semiconductor DBR materials (such as GaAs / AlGaAs) for efficient optical feedback; however, these GaAs-based semiconductor DBR materials exhibit significant lattice mismatch with the material system of long-wavelength VCSELs. Using low-reflectivity semiconductor DBR materials leads to many insurmountable shortcomings in practical applications for long-wavelength VCSELs. For example, with a 1550nm indium phosphide-based VCSEL, if lattice-matched semiconductor materials InGaAsP / InP or InAlGaAs / InAlAs are used, to achieve 99% reflectivity, the thickness of the top semiconductor DBR needs to reach 8μm. However, the greater the thickness of the semiconductor DBR, the greater the light absorption loss, which is more likely to cause problems such as high threshold current and high insertion loss. At the same time, excessive thickness of semiconductor DBR can also cause problems such as high series resistance and poor heat dissipation of the chip. Moreover, semiconductor DBR has a large number of film layers, and the requirements for film layer thickness and composition are relatively strict, which leads to high device fabrication difficulty and production difficulties.

[0006] In summary, overcoming the technical bottlenecks limited by long-wavelength VCSEL material systems and applying mature oxide confinement layer technology and high-performance GaAs-based semiconductor DBR materials from short-wavelength VCSELs to long-wavelength VCSELs, thereby enabling long-wavelength VCSELs to meet the demands for high power, low power consumption, and low-cost mass production, is a crucial research direction for long-wavelength VCSELs to escape the performance and cost dilemmas. Summary of the Invention

[0007] This invention provides a novel indium phosphide-based vertical surface-emitting laser. Its main purpose is to achieve the growth of an oxide confinement layer of GaAs-based material system and a top P-type DBR of GaAs-based material system on an InP-based epitaxial layer, thereby realizing the fabrication of a high-power, low-power indium phosphide-based vertical surface-emitting laser.

[0008] The present invention adopts the following technical solution: A novel indium phosphide-based vertical-plane emitting laser includes an InP-based epitaxial layer, a two-dimensional material layer, and a GaAs-based epitaxial layer. The InP-based epitaxial layer comprises, from bottom to top, an InP substrate, a bottom N-type DBR, an N-type doped layer, an active region, and a first P-type doped layer. The GaAs-based epitaxial layer comprises, from bottom to top, an oxide confinement layer, a second P-type doped layer, and a top P-type DBR. The two-dimensional material layer is graphene, disposed between the InP-based and GaAs-based epitaxial layers, for heterogeneous integration of the InP-based and GaAs-based epitaxial layers. Furthermore, the two-dimensional material layer and the GaAs-based epitaxial layer form a top two-dimensional heat dissipation channel with high lateral thermal conductivity and low longitudinal thermal resistance.

[0009] Furthermore, a resonant cavity is formed between the bottom N-type DBR and the top P-type DBR, and the two-dimensional material layer is disposed at the standing wave node within the resonant cavity.

[0010] Furthermore, the first P-type doped layer is a P-type InGaAsP.

[0011] Furthermore, the top P-type DBR is an AlGaAs material system.

[0012] Furthermore, the bottom N-type DBR is an InAlGaAs material system.

[0013] Furthermore, the active region is a multi-quantum-well active region of InGaAsP / InGaAsP or InGaAsP / InAlGaAs material system, and the wavelength of the active region is 1-2 μm.

[0014] Furthermore, the oxidation confinement layer is formed by a wet oxidation process from an oxidation confinement preform of an AlGaAs material system.

[0015] A novel method for fabricating an indium phosphide-based vertical-plane emitting laser, characterized by comprising the following steps: (1) The bottom N-type DBR, N-type doped layer, active region and first P-type doped layer are grown sequentially on the InP substrate to complete the preparation of the InP-based epitaxial layer; (2) A two-dimensional material layer is prepared on the first p-type doped layer; (3) An oxide-confined prefabricated layer, a second P-type doped layer and a top P-type DBR are grown sequentially on a two-dimensional material layer, and the oxide-confined prefabricated layer is oxidized by a wet oxidation process to form an oxide-confined layer, thereby completing the preparation of the GaAs-based epitaxial layer. (4) A P-type electrode is fabricated on the surface of the second P-type doped layer, and an N-type electrode is fabricated on the surface of the bottom N-type DBR.

[0016] Furthermore, the two-dimensional material layer is graphene. In step (2), the CVD-grown monolayer graphene is transferred from the copper foil to the first P-type doped layer.

[0017] Furthermore, the graphene transfer process includes the following steps: (2.1) Polymethyl methacrylate (PMMA) is spin-coated onto graphene on copper foil and baked at a specified temperature to obtain a PMMA support layer; (2.2) Immerse the graphene in FeCl3 copper etching solution until the copper foil is completely dissolved, and wash it with deionized water to remove the residual FeCl3 solution, thereby obtaining the graphene-PMMA layer. (2.3) First, the graphene-PMMA layer is transferred to the surface of the first P-type doped layer and dried at a specified temperature. Then, it is immersed in acetone solution to dissolve the PMMA support layer. (2.4) Anneal the epitaxial wafer.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention breaks through the technical bottleneck of material system limitations. It achieves heterogeneous integration of InP-based epitaxial layers and GaAs-based epitaxial layers through two-dimensional material layers. This allows the application of mature oxide confinement layer technology and high-performance GaAs-based semiconductor DBR materials in short-wavelength VCSELs to InP-based long-wavelength VCSELs. This enables the growth of an oxide confinement layer of GaAs-based material system and a top P-type DBR of GaAs-based material system on the InP-based epitaxial layer, thereby realizing the fabrication of a high-power, low-power indium phosphide-based vertical surface emission laser.

[0019] 2. This invention fully utilizes the high thermal conductivity of two-dimensional material layers and deeply integrates them into the core of the chip architecture. Through the three-layer action of "source heat reduction - lateral heat dissipation - vertical heat dissipation", a significant synergistic heat dissipation effect is generated, systematically solving the heat dissipation problem of InP-based long-wavelength VCSELs, thus laying a solid foundation for manufacturing high-performance, high-power, and high-reliability devices.

[0020] 3. This invention simultaneously applies the mature oxide confinement layer technology and GaAs-based semiconductor DBR technology from existing short-wavelength VCSELs to the fabrication process of InP-based long-wavelength VCSELs. This maximizes the use of existing process equipment and production lines, simplifies the fabrication process of InP-based long-wavelength VCSELs, reduces production costs, and improves production efficiency. It is conducive to large-scale industrial production and opens up a new path for the mass production of high-performance, low-cost InP-based long-wavelength VCSELs, which is of great significance to fields such as optical communication and sensing. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the present invention.

[0022] In the figure: 1-InP-based epitaxial layer; 11-InP substrate; 12-bottom N-type DBR; 13-N-type doped layer; 14-active region; 15-first P-type doped layer; 16-N-type electrode; 2-two-dimensional material layer; 3-GaAs-based epitaxial layer; 31-oxidation confinement layer; 32-second P-type doped layer; 33-top P-type DBR; 34-P-type electrode. Detailed Implementation

[0023] Specific embodiments of the present invention will now be described with reference to the accompanying drawings. Many details are described below to provide a comprehensive understanding of the invention; however, those skilled in the art will be able to implement the invention without these details.

[0024] like Figure 1As shown, this embodiment provides a novel indium phosphide-based vertical-plane emitting laser, comprising, from bottom to top, an InP-based epitaxial layer 1, a two-dimensional material layer 2, and a GaAs-based epitaxial layer 3. The InP-based epitaxial layer 1, from bottom to top, includes an InP substrate 11, a bottom N-type DBR 12, an N-type doped layer 13, an active region 14, and a first P-type doped layer 15. The GaAs-based epitaxial layer 3, from bottom to top, includes an oxide confinement layer 31, a second P-type doped layer 32, and a top P-type DBR 33. The core innovation of this embodiment lies in achieving heterogeneous integration of the InP-based epitaxial layer 1 and the GaAs-based epitaxial layer 3, thereby applying the mature oxide confinement layer technology and high-performance GaAs-based semiconductor DBR material from short-wavelength VCSELs to InP-based long-wavelength VCSELs. To more clearly illustrate the design principle of this embodiment, the structure of each epitaxial layer is described in detail below: InP substrate 11: InP substrate 11 is used to provide mechanical support and crystal growth template. In this embodiment, N-type doped InP substrate 11 is preferred.

[0025] Bottom N-type DBR12: The bottom N-type DBR12 and the top P-type DBR33 form the resonant cavity of the laser, providing the main optical feedback. Since the bottom N-type DBR12 is grown on a lattice-matched InP substrate 11, a lattice-matched InAlGaAs material system, such as an InAlGaAs / InAlAs material pair, is required. Specifically, in this embodiment, the bottom N-type DBR12 is In... 0.52 Al 0.24 Ga 0.24 As / In 0.52 Al 0.48 As has a lattice constant that perfectly matches that of the InP substrate 11. To ensure sufficient high reflectivity, it has 40-50 layers, with each layer having an optical thickness of λ / 4.

[0026] The N-type doped layer 13 serves three purposes: (1) efficiently transporting electrons to the active region 14 to ensure carrier injection; (2) connecting the bottom N-type DBR 12 with the active region 14 to reduce the interface barrier; and (3) acting as a current spreading layer, together with the InP substrate 11 and the bottom N-type DBR 12, constructing a complete, low-loss electrical path from the N-type electrode 16 to the active region 14 to ensure uniform current distribution. The material selection for the N-type doped layer 13 must match the lattice constant of the InP substrate 11 and meet the requirements of carrier transport and device function. InP-based semiconductor materials are selected as the core.

[0027] Active Region 14: Active Region 14 is the core functional region of the VCSEL, responsible for carrier recombination to generate stimulated emission and emit laser light. Since Active Region 14 is grown on a lattice-matched InP substrate 11, multi-quantum-well active regions 14 of InGaAsP / InGaAsP or InGaAsP / InAlGaAs material systems are typically selected, such as InP / InGaAsP, InP / InAlGaAs, or InGaAsP / InAlGaAs, and the wavelength of Active Region 14 is 1-2 μm.

[0028] First P-type doped layer 15: In this embodiment, the first P-type doped layer 15 has the following two functions: (1) Electrical contact and current spread: As an important component of the P-type side, it works with the upper P-type electrode 34 to inject holes downward into the active region 14; (2) Growth substrate of two-dimensional material layer 2: This is its most critical special function, providing a flat, clean substrate with suitable electrical properties for the subsequently transferred two-dimensional material layer 2. For the InP-based epitaxial layer 1 structure, the first P-type doped layer 15 is usually P-type doped InP or P-type doped InGaAsP. In order to form a better ohmic contact with the two-dimensional material layer 2 and reduce the contact resistance, an InP-based semiconductor material with a work function close to that of the two-dimensional material layer 2 should be preferred.

[0029] Oxidation confinement layer 31: Since the two-dimensional material layer 2 can achieve heterogeneous integration of InP-based epitaxial layer 1 and GaAs-based epitaxial layer 3, this embodiment can apply the mature oxidation confinement layer technology in short-wavelength VCSELs to long-wavelength VCSELs. Specifically, the oxidation confinement layer 31 is formed by a wet oxidation process of an oxidation confinement prefabricated layer of AlGaAs material system. By selectively oxidizing the aluminum-rich regions in the AlGaAs material, insulating alumina pores are formed, thereby confining the current and optical field and improving laser efficiency. The oxidation confinement prefabricated layer must be made of AlGaAs with a high aluminum content, typically >90%, such as Al 0.98 Ga 0.02 As, the thickness of the oxide confinement layer 31 is typically between 15-50 nm. After wet oxidation, the outer ring oxide region of the oxide confinement layer 31 is Al2O3, and the unoxidized region in the middle is Al. 0.98 Ga 0.02 As.

[0030] The second P-type doped layer 32: In this embodiment, the functions of the second P-type doped layer 32 include the following three points: (1) efficiently transporting holes to the active region 14, ensuring the continuity of carrier injection; (2) connecting the oxide confinement layer 31 and the top P-type DBR 33, reducing the interface barrier and defects, and forming a low-resistance current path; (3) together with the oxide confinement layer 31 and the P-type DBR 33, forming a GaAs-based epitaxial layer 3 with a gradually changing refractive index, thereby achieving better optical field confinement, and the optical path length of the resonant cavity can be optimized by controlling its thickness, thereby optimizing the optical performance of the resonant cavity. In this embodiment, the second P-type doped layer 32 is preferably a P-type AlGaAs material with medium to high Al composition (such as Al 0.5 Ga 0.5 As).

[0031] Top P-type DBR33: The top P-type DBR33 and the bottom N-type DBR12 form a resonant cavity. Since the two-dimensional material layer 2 can achieve heterogeneous integration of the InP-based epitaxial layer 1 and the GaAs-based epitaxial layer 3, this embodiment can apply the high-performance GaAs-based semiconductor DBR material used in short-wavelength VCSELs to InP-based long-wavelength VCSELs. Specifically, the top P-type DBR33 is an AlGaAs material system. Due to the high refractive index contrast of the AlGaAs material system, high reflectivity is achieved with a small number of layer pairs, thereby significantly reducing series resistance and optical loss. Preferably, the top P-type DBR33 is made of Al... x Ga 1-x As / Al y Ga 1-y The periodic structure made of As material has 10-20 layers, and the optical thickness of each layer is still λ / 4.

[0032] Two-dimensional material layer 2: The full name of two-dimensional material layer 2 is two-dimensional atomic crystal material, and in this embodiment, graphene is preferred. In this embodiment, the role of graphene mainly includes the following three points: (1) Lattice mismatch buffer layer: Graphene has an atomically flat surface without dangling bonds, which allows the oxidation restriction prefabrication layer of GaAs-based epitaxial layer 3 to grow on it through van der Waals forces rather than chemical bonds, thereby isolating the lattice mismatch between InP-based epitaxial layer 1 and GaAs-based epitaxial layer 3, and realizing the epitaxy of high-quality GaAs-based epitaxial layer 3; (2) Current transport layer: There is a vertical current transport between the first P-type doped layer 15 and the second P-type doped layer 32, and graphene itself is an excellent conductor, so it can improve the uniformity of current distribution, thereby helping to improve the overall performance of the device. During the oxidation process, the conductivity of graphene helps to maintain the electrical path and avoid current accumulation or leakage; (3) As an embedded heat diffusion layer between InP-based epitaxial layer 1 and GaAs-based epitaxial layer 3, graphene together with GaAs-based epitaxial layer 3 forms a new low thermal resistance top heat dissipation channel, which solves the heat dissipation problem of traditional InP-based long-wavelength VCSEL.

[0033] like Figure 1 As shown, in this embodiment, the two-dimensional material layer 2 is not an independent, passive insertion layer. Its parameters are profoundly and multidimensionally interdependent with the selection of the entire epitaxial structure. This interaction directly determines the feasibility of the scheme and the performance of the final device. Therefore, the two-dimensional material layer 2 should be designed and optimized in conjunction with other epitaxial structures during the design process. The following section analyzes the design key points of the two-dimensional material layer 2 in detail, starting from several core parameters: 1. Number of layers: The number (thickness) of the two-dimensional material layer 2 is one of the most critical parameters, mainly affecting the lattice mismatch buffering effect and electrical / optical properties. As a preferred option, the number of graphene layers in this embodiment is preferably 1-2 layers, and the following three factors are considered: (1) Constraints of the first p-type doped layer 15: The epitaxial growth characteristics of the two-dimensional material layer 2 depend on the shielding effect on the substrate charge density, which is directly determined by the thickness. With 1-2 layers of graphene, the weak van der Waals potential allows the substrate to interact with the epitaxial layer, thus supporting epitaxial growth. Conversely, if the number of graphene layers increases (e.g., 3-5 layers), its strong van der Waals potential will shield the substrate charge density, making epitaxial growth impossible. Therefore, 1-2 layers of graphene are the best choice for achieving high-quality epitaxial growth. In practical applications, the surface flatness of the first p-type doped layer 15 should be ensured to reach the atomic level to guarantee the continuity of graphene and the high quality of epitaxial growth.

[0034] (2) Constraints on Current Transport: Graphene is an excellent conductor. Single-layer graphene has extremely low in-plane resistance, benefiting from its high electron mobility and two-dimensional structure, resulting in strong lateral current expansion capability. Simultaneously, single-layer graphene has low out-of-plane resistance, with less restriction on vertical electron migration, leading to high injection efficiency. As the number of layers increases, the in-plane resistance increases slightly, mainly due to enhanced interlayer interactions leading to electron scattering; the out-of-plane resistance increases significantly because the interlayer van der Waals forces are weak, hindering electron migration in the vertical direction. Therefore, in design, 1-2 layers of graphene should be preferred to obtain the best current expansion and injection efficiency.

[0035] (3) Constraints related to optical properties: There is a close relationship between the transmittance of graphene and the number of layers. In the 1-2 μm band, monolayer graphene has a light absorption rate of about 2.3% and a high transmittance, making it suitable for applications in this band. As the number of layers increases, light absorption and transmittance gradually deteriorate. Therefore, monolayer graphene performs best in this band and is the ideal choice for achieving good optical performance.

[0036] 2. Work Function: The work function of the two-dimensional material layer 2 mainly affects the electrical contact with adjacent semiconductor layers. Ideally, it should form an ohmic contact or a low Schottky barrier with the first P-type doped layer 15 and the second P-type doped layer 32 to facilitate hole injection. Especially for the first P-type doped layer 15, which is in direct contact with the two-dimensional material layer 2, selecting a material with a better work function match is crucial. The work function of graphene is approximately 4.5-4.7 eV; therefore, the first P-type doped layer 15 is preferably P-type InGaAs. By adjusting the ratio of Ga to As, for example, lattice-matched In... 0.53 Ga 0.47 The work function of As is typically in the range of 4.8-5.0 eV, a value very close to that of graphene, making it an ideal choice for forming low-barrier contacts. In addition, the first p-type doped layer 15 and the second p-type doped layer 32 must be heavily doped (doping concentration > 1 × 10⁻⁶). 18 cm -3 The doping concentration is insufficient, which will form an excessively high Schottky barrier at the graphene-semiconductor interface, severely hindering current transport and resulting in high device voltage and severe heat generation.

[0037] 3. Position: The optical properties of the two-dimensional material layer 2 primarily affect the optical loss within the resonant cavity, making its position within the epitaxial structure particularly crucial. For example, even a single layer of graphene absorbs approximately 2.3% of infrared light; therefore, placing it within the laser resonant cavity introduces additional optical loss. In optical design, the two-dimensional material layer 2 must be precisely placed at the standing wave nodes (the weakest points of light intensity) of the resonant cavity's optical field to minimize its absorption loss. This, in turn, constrains the thickness of the first p-type doped layer 15 and the position of the entire active region 14 relative to the two-dimensional material layer 2, as these parameters collectively determine the distribution of the optical field within the cavity.

[0038] like Figure 1 As shown, this embodiment utilizes the van der Waals epitaxial properties of the two-dimensional material layer 2 to solve the lattice mismatch problem in growing a GaAs-based epitaxial layer 3 on an InP-based epitaxial layer 1, thereby breaking through the limitations of traditional materials and providing a new direction for the fabrication of InP-based long-wavelength VCSELs. Specifically, the mechanism by which the two-dimensional material layer 2 acts as a lattice mismatch buffer layer is as follows: Taking graphene as an example, its atomically flat surface, chemical inertness, and absence of dangling bonds make it suitable as a lattice mismatch buffer layer, allowing GaAs-based epitaxial layer 3 to be grown on graphene via van der Waals epitaxy. The oxide confinement layer 31, the second P-type doped layer 32, and the top P-type DBR 33 in GaAs-based epitaxial layer 3 are all AlGaAs materials, thus essentially forming a monolithic AlGaAs layer. The interaction between the AlGaAs layer and graphene is primarily achieved through weak van der Waals forces rather than traditional chemical bonding. This significantly reduces strain and defects caused by lattice mismatch, enabling the AlGaAs layer to grow on InP-based epitaxial layer 1 with low defect density, thereby obtaining a high-quality AlGaAs crystal structure. This provides essential technical support for the application of oxide confinement layer technology and GaAs-based semiconductor DBR materials in InP-based long-wavelength VCSELs.

[0039] like Figure 1 As shown, although graphene's high thermal conductivity is a recognized advantage, in this embodiment, graphene does not exist as an isolated heat sink. Instead, it is deeply integrated into the core of the chip architecture, leveraging its high thermal conductivity to achieve a synergistic heat dissipation effect of 1+1>2 through a three-layer process of "heat reduction at the source, lateral heat dissipation, and vertical heat dissipation." This systematically solves the heat dissipation problem of InP-based long-wavelength VCSELs, thus laying a solid foundation for manufacturing high-performance, high-power, and high-reliability devices. The following is a detailed analysis of the heat dissipation principle of graphene: (1) Heat Reduction at the Source: In this embodiment, graphene is used as a lattice mismatch buffer layer. The oxide confinement layer 31 and GaAs-based semiconductor DBR material are simultaneously applied to the InP-based long-wavelength VCSEL. On the one hand, the use of oxide confinement layer 31 is conducive to achieving better current and optical field confinement, enabling more electrical energy to be converted into laser light and improving electro-optical conversion efficiency, thereby reducing the generation of useless heat at the source. On the other hand, the resistance of GaAs-based semiconductor DBR material is much lower than that of InP-based epitaxial layer 1 semiconductor DBR material. Therefore, using GaAs-based semiconductor DBR material as the top P-type DBR 33 can significantly reduce the series resistance of the device, thereby reducing Joule heating. It can be seen that the introduction of graphene can indirectly reduce the total heat required for device heat dissipation, thus alleviating the heat dissipation burden at the source.

[0040] (2) Lateral heat dissipation: The active region 14 is the heat-generating center of the VCSEL. In this embodiment, an oxide confinement layer 31 of AlGaAs material is introduced above the active region 14 of the InP-based epitaxial layer 1. Although the oxidized Al2O3 has excellent optical properties, its thermal conductivity is extremely poor, which will form a local hot spot near the active region 14. Therefore, compared with the traditional InP-based long-wavelength VCSEL, the InP-based long-wavelength VCSEL with oxide confinement layer 31 provided in this embodiment also has a potential thermal bottleneck, and the heat dissipation situation is more complicated. Graphene is disposed between the first P-type doped layer 15 and the second P-type doped layer 32 above the active region 14, precisely located between the heat-generating center (active region 14) and the potential thermal bottleneck (oxide confinement layer 31). The in-plane thermal conductivity of graphene is as high as 2000-5000 W / mK, so it can act like a fan to quickly diffuse the heat transferred upward from the active region 14 laterally and disperse it to a larger area. After lateral diffusion, heat can bypass the Al2O3 pores with extremely poor thermal conductivity in the outer ring and continue to be transferred upwards from the central, unoxidized AlGaAs semiconductor region with better thermal conductivity, thus avoiding the formation of fatal local high temperatures below the oxidized pores. Therefore, the graphene embedded between the InP-based epitaxial layer 1 and the GaAs-based epitaxial layer 3 can play a role in localized lateral heat dissipation.

[0041] (3) Vertical heat dissipation: Traditional InP-based semiconductor DBR materials have low refractive index contrast and a large thickness of the top P-type DBR33, resulting in very low lateral and vertical thermal conductivity and poor heat dissipation. However, the lattice mismatch buffering effect of graphene allows the high-contrast GaAs-based semiconductor DBR material to be compatible with the InP-based epitaxial layer 1, significantly reducing the number of top P-type DBR33 layers and significantly improving thermal conductivity. Therefore, graphene can synergistically provide multiple heat dissipation effects, forming a top two-dimensional heat dissipation channel with "high lateral thermal conductivity + low vertical thermal resistance" together with the GaAs-based epitaxial layer 3, significantly improving the heat dissipation performance of InP-based long-wavelength VCSELs.

[0042] like Figure 1 As shown in the figure, this embodiment also provides a novel method for fabricating an indium phosphide-based vertical-plane emitting laser, comprising the following steps: (1) The bottom N-type DBR12, N-type doped layer 13, active region 14 and first P-type doped layer 15 are sequentially grown on the InP substrate 11 using MOCVD or MBE process, thereby completing the preparation of the InP-based epitaxial layer 1.

[0043] (2) A two-dimensional material layer 2 is prepared on the first P-type doped layer 15. In this embodiment, the two-dimensional material layer 2 is preferably graphene. This step involves transferring the CVD-grown monolayer graphene from the copper foil to the first P-type doped layer 15. The CVD-grown monolayer graphene is synthesized on the copper foil by low-pressure chemical vapor deposition (LPCVD), and its preparation process is existing technology and will not be described in detail here. The graphene transfer process includes the following steps: (2.1) Polymethyl methacrylate (PMMA) is spin-coated onto graphene on copper foil and baked at a specified temperature. Preferably, the PMMA-coated graphene is baked at 80°C for 10 minutes to obtain a PMMA support layer.

[0044] (2.2) Immerse the graphene in FeCl3 copper etching solution until the copper foil is completely dissolved, and wash it with deionized water to remove the residual FeCl3 solution, thereby obtaining the graphene-PMMA layer; preferably, the immersion time is 15 minutes.

[0045] (2.3) First, the graphene-PMMA layer is transferred to the surface of the first P-type doped layer 15 and dried at a specified temperature. Then, it is immersed in acetone solution to dissolve the PMMA support layer. Preferably, the drying temperature is 80°C and the drying time is 10 minutes.

[0046] (2.4) Annealing the epitaxial wafer; specifically, the epitaxial wafer is transferred to a specified 350°C environment and annealed in a hydrogen atmosphere for 30 minutes to remove process residues on the interface and improve the adhesion of graphene.

[0047] (3) An oxide-confined prefabricated layer, a second P-type doped layer 32, and a top P-type DBR 33 are sequentially grown on the two-dimensional material layer 2 using MOCVD or MBE processes. The oxide-confined prefabricated layer is then oxidized using a wet oxidation process to form an oxide-confined layer 31, thereby completing the fabrication of the GaAs-based epitaxial layer 3. Before oxidation, photolithography and inductively coupled plasma etching techniques are used to etch cylindrical or square mesa structures downwards from the epitaxial wafer. Since graphene is chemically inert, it will hinder the wet oxidation process. Therefore, during mesa etching, it is necessary to ensure that the etching depth completely penetrates the graphene so that the oxidant (water vapor) can laterally penetrate from the sidewalls into the oxide-confined prefabricated layer that needs to be oxidized.

[0048] (4) A P-type electrode 34 is fabricated on the surface of the second P-type doped layer 32, and an N-type electrode 16 is fabricated on the surface of the bottom N-type DBR12. The electrode fabrication method is existing technology and will not be described in detail here.

[0049] From a fabrication process perspective, simultaneously applying the mature oxide confinement layer technology and GaAs-based semiconductor DBR technology from existing short-wavelength VCSELs to InP-based long-wavelength VCSELs can maximize the use of existing process equipment and production lines, simplify the fabrication process of InP-based long-wavelength VCSELs, reduce production costs, and improve production efficiency. This is conducive to large-scale industrial production and opens up a new path for the mass production of high-performance, low-cost InP-based long-wavelength VCSELs, which is of great significance to fields such as optical communication and sensing.

[0050] The above are merely specific embodiments of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using the design concept shall be considered an infringement of the protection scope of the present invention.

Claims

1. A novel indium phosphide-based vertical-plane emitting laser, characterized in that: Including InP-based epitaxial layers, two-dimensional material layers, and GaAs-based epitaxial layers; The InP-based epitaxial layer comprises, from bottom to top, an InP substrate, a bottom N-type DBR, an N-type doped layer, an active region, and a first P-type doped layer; The GaAs-based epitaxial layer comprises, from bottom to top, an oxide confinement layer, a second P-type doped layer, and a top P-type DBR; The two-dimensional material layer is graphene, which is disposed between the InP-based epitaxial layer and the GaAs-based epitaxial layer to achieve heterogeneous integration of the InP-based epitaxial layer and the GaAs-based epitaxial layer. The two-dimensional material layer and the GaAs-based epitaxial layer form a top two-dimensional heat dissipation channel with high lateral thermal conductivity and low longitudinal thermal resistance.

2. The novel indium phosphide-based vertical-plane emitting laser as described in claim 1, characterized in that: The bottom N-type DBR and the top P-type DBR form a resonant cavity, and the two-dimensional material layer is disposed at the standing wave node within the resonant cavity.

3. A novel indium phosphide-based vertical-plane emitting laser as described in claim 1, characterized in that: The first P-type doped layer is P-type InGaAsP.

4. A novel indium phosphide-based vertical-plane emitting laser as described in claim 1, characterized in that: The top P-type DBR is an AlGaAs material system.

5. A novel indium phosphide-based vertical-plane emitting laser as described in claim 1, characterized in that: The bottom N-type DBR is an InAlGaAs material system.

6. A novel indium phosphide-based vertical-plane emitting laser as described in claim 1, characterized in that: The active region is a multi-quantum well active region of InGaAsP / InGaAsP or InGaAsP / InAlGaAs material system, and the wavelength of the active region is 1-2 μm.

7. A novel indium phosphide-based vertical-plane emitting laser as described in claim 1, characterized in that: The oxidation confinement layer is formed by a wet oxidation process from an oxidation confinement prefabrication layer of AlGaAs material system.

8. A method for fabricating a novel indium phosphide-based vertical-plane emitting laser, characterized in that: Includes the following steps: (1) The bottom N-type DBR, N-type doped layer, active region and first P-type doped layer are grown sequentially on the InP substrate to complete the preparation of the InP-based epitaxial layer; (2) A two-dimensional material layer is prepared on the first p-type doped layer; (3) An oxide-confined prefabricated layer, a second P-type doped layer and a top P-type DBR are grown sequentially on a two-dimensional material layer, and the oxide-confined prefabricated layer is oxidized by a wet oxidation process to form an oxide-confined layer. (4) A P-type electrode is fabricated on the surface of the second P-type doped layer, and an N-type electrode is fabricated on the surface of the bottom N-type DBR.

9. The method for fabricating a novel indium phosphide-based vertical-plane emitting laser as described in claim 8, characterized in that: The two-dimensional material layer is graphene. In step (2), the CVD-grown monolayer graphene is transferred from the copper foil to the first P-type doped layer.

10. The method for fabricating a novel indium phosphide-based vertical-plane emitting laser as described in claim 9, characterized in that: The graphene transfer process includes the following steps: (2.1) Polymethyl methacrylate is spin-coated onto graphene and baked at a specified temperature to obtain a PMMA support layer; (2.2) Graphene is immersed in FeCl3 copper etching solution until the copper foil is completely dissolved to obtain a graphene-PMMA layer; (2.3) First, the graphene-PMMA layer is transferred to the surface of the first P-type doped layer and dried at a specified temperature. Then, it is immersed in acetone solution to dissolve the PMMA support layer. (2.4) Anneal the epitaxial wafer.

Images