Antenna three-axis servo driving system based on single-chip dual-core DSP

Abstract

The invention relates to the technical field of servo drive control, and discloses an antenna three-axis servo drive system based on a single-chip dual-core DSP. A dual-core DSP (Digital Signal Processor) is adopted as a main controller, an FPGA (Field Programmable Gate Array) or other processors are not needed, and high-precision synchronous control on a permanent magnet synchronous motor with three servo axes (such as an azimuth axis, a pitch axis and a polarization axis) is realized. By using a dual-core task allocation architecture, efficient management of system communication, trajectory planning, task scheduling and a three-axis motor real-time servo control algorithm is realized. The three-axis control task is efficiently managed in a single chip through a time slice rotation and interruption priority scheduling mechanism, a multi-stage fault protection mechanism is designed, the integration level, reliability and control precision of the system are remarkably improved, and the system is particularly suitable for the servo control field of antennas and the like.

Description

Technical Field

[0001] This invention relates to the field of motor motion control technology, and in particular to a three-axis drive control system based on a single-chip dual-core digital signal processor (DSP). Background Technology

[0002] In the field of multi-axis motion control, such as industrial robots, CNC machine tools, and antenna servo control, high-precision synchronous coordination control of multi-axis servo motors is typically required. Traditional solutions mainly fall into the following categories: 1. Multi-controller architecture: Each motor axis is configured with an independent controller (such as MCU or DSP). This solution is complex, costly, and bulky, and the inter-axis synchronization performance depends on the communication bus, making it difficult to guarantee real-time performance and synchronization accuracy.

[0003] 2. Main Processor + FPGA / Dedicated Motion Control Chip Architecture: This architecture utilizes the main processor for upper-level planning, and an FPGA or dedicated motion control chip generates multiple synchronous PWM signals and processes encoder or Hall feedback. While this approach improves performance, it increases system complexity, design difficulty, and cost.

[0004] 3. High-performance multi-core processor architecture: Employing processors that integrate multiple cores or powerful peripherals. For example, TI's TMS320F28379 is a dual-core DSP integrating dual C28x cores, high-resolution PWM, rich encoder interfaces, and Σ-Δ filters. While existing technologies include applications using dual-core DSPs to control dual motors, they typically do not address solutions for achieving high-precision synchronous servo drive control of three axes using a single dual-core DSP. Especially without relying on an FPGA, a key technical challenge is how to rationally allocate dual-core resources within a single DSP to efficiently and reliably implement three complete servo control loops while ensuring strict synchronization between the three axes.

[0005] Therefore, there is an urgent need for a cost-effective, highly integrated, and highly precise three-axis synchronous servo drive control solution that can achieve high performance without adding an extra coprocessor. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a highly integrated three-axis servo drive control system based on a single-chip dual-core DSP. Through dual-core task division, refined peripheral resource configuration, and efficient time scheduling strategies, independent or synchronous precision control of the three-axis servo motors is achieved on a single DSP chip, aiming to significantly reduce system complexity and cost while ensuring real-time performance, accuracy, and reliability of control.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: A three-axis servo drive system for antennas based on a single-chip dual-core DSP includes: a dual-core DSP main controller, a three-channel power drive module, a three-axis actuator motor, and a sensor feedback module; The dual-core DSP main controller has core a for system communication, three-axis trajectory planning and task scheduling, and core b for real-time servo control algorithm calculation for the three-axis motor. The dual-core DSP main controller communicates with the host computer at high speed via the EtherCAT bus. Core a receives the target angle command from the host computer, performs trajectory planning and velocity look-ahead processing, and sends the target position of the three axes to core b via IPC. Core b runs the current loop at high frequency, sequentially reads the current sampling values ​​of the three ADCs and the actual position feedback from the three encoders, executes three sets of FOC algorithms, updates the values ​​of the three sets of ePWM registers, and drives three servo motors. A cross-coupled control algorithm is used to calculate and compensate for the synchronization error between the azimuth and pitch axes in real time, ensuring the accuracy and stability of the antenna beam pointing.

[0008] Furthermore, the core b of the dual-core DSP main controller is responsible for running three sets of three-closed-loop servo control algorithms for servo motors in parallel: the current loop adopts field-oriented control, and the speed loop and position loop operate at corresponding frequencies according to performance requirements; the core b reads sensor feedback, performs PID adjustment and coordinate transformation, and updates the control quantity in real time.

[0009] Furthermore, the peripherals of the dual-core DSP main controller include: The enhanced PWM module has a total of 9 modules, which are used to generate three three-phase PWM waveforms. After passing through the logic chip-based shoot-through protection circuit, they directly control the half-bridge driver chip, thereby driving the power inverter bridge of the three servo motors. The enhanced PWM module supports high resolution, dead-time programming, and synchronous triggering with the ADC. The high-precision ADC module utilizes its multiple ADC channels to synchronously sample the phase currents of three servo motors, providing feedback for the current loop; the startup of the high-precision ADC module is precisely triggered by the SOC signal of the enhanced PWM module. Enhanced encoder pulse module: It has three sets, which are used to capture the position and speed feedback signals of the photoelectric encoder or magnetoelectric encoder on the four servo motors; The comparator subsystem, configured on each servo axis, is used for hardware-level overcurrent and overvoltage protection. When the sampled current exceeds the set threshold, the comparator subsystem directly shuts off the output of the corresponding enhanced PWM module within nanoseconds.

[0010] Compared with the prior art, the beneficial effects of the present invention include: 1. High integration and low cost: Three-axis servo control is achieved using only one DSP chip, which greatly simplifies the hardware structure and reduces the cost of system components and PCB area.

[0011] 2. High real-time performance and high precision: Dual-core division of labor ensures that real-time control tasks are not affected by non-real-time tasks; abundant on-chip peripherals ensure the accuracy of control signal generation and acquisition, enabling high-precision control.

[0012] 3. High reliability: The system is robust due to the combination of hardware-level protection and multi-level software protection.

[0013] 4. Flexibility and scalability: It can be easily adapted to different control algorithms and synchronization requirements through software configuration. Attached Figure Description

[0014] Figure 1 : A block diagram of the single-chip hardware architecture of the system of this invention.

[0015] Figure 2 Flowchart of dual-core task scheduling and three-axis servo control.

[0016] Figure 3 Flowchart of multi-level fault protection mechanism. Detailed Implementation

[0017] Example: Three-axis servo drive control applied to satellite communication antennas I. System Hardware Architecture The core lies in the minimum system of a single-chip dual-core DSP and its interface design with three sets of servo drive units. The system mainly includes: the DSP minimum hardware system, three-channel power drive modules, a shoot-through detection and protection module, a three-axis servo motor, a sensor feedback module (encoder, Hall effect sensor, current sensor, etc.), a communication interface module, and a power management module.

[0018] Dual-core DSP main controller: As the sole main controller, its dual-core functions are as follows: Kernel a: Handles non-real-time or weak real-time tasks. This mainly includes: communicating with the host computer via EtherCAT, CAN, or UART to receive motion commands; performing complex trajectory planning for three axes; dynamic task scheduling and management; and system status monitoring and fault diagnosis. This kernel sends control commands to kernel b through the IPC (inter-core communication) module.

[0019] Kernel b: Dedicated to high real-time control tasks. Responsible for running the three-closed-loop servo control algorithm for three servo motors in parallel. Current loop (innermost loop): Employs field-oriented control (FOC) with a high operating frequency to ensure rapid torque response.

[0020] Speed ​​and position loops: Based on performance requirements, the speed and position loops operate at corresponding frequencies. Kernel b reads sensor feedback, performs PID control, coordinate transformation (Clarke / Park transformation), and updates control variables in real time.

[0021] Key On-Chip Peripherals and Their Allocation: The abundant on-chip peripherals of the dual-core DSP are key to achieving three-axis control on a single chip.

[0022] Enhanced PWM Module (ePWM): Nine independent ePWM modules (e.g., ePWM1A / B, ePWM2A / B, ePWM3A / B) are allocated to generate three three-phase PWM waveforms. After passing through a logic chip-based shoot-through protection circuit, these waveforms directly control the half-bridge driver chip, thereby driving the power inverter bridge of three servo motors. The ePWM module supports high resolution, programmable dead time, and can be synchronously triggered with the ADC.

[0023] High-precision ADC module: Utilizing its multiple ADC channels, it synchronously samples the phase currents of three servo motors, providing feedback for the current loop. The ADC can be precisely triggered by the SOC (Start-of-Conversion) signal of the ePWM module.

[0024] Enhanced Encoder Pulse Module (eQEP): Three sets of eQEP modules are allocated to capture the position and speed feedback signals of the photoelectric encoders or magnetoelectric encoders on the four servo motors.

[0025] Comparator Subsystem (CMPSS): Each servo axis is configured with a CMPSS for hardware-level overcurrent and overvoltage protection. When the sampled current exceeds a set threshold, the CMPSS can directly shut down the corresponding ePWM output within nanoseconds, providing the highest level of safety.

[0026] Σ-Δ filter module (SDFM): can be used for digital filtering of high-precision current sampling data.

[0027] l Power drive and sensor module: Power drive module: includes three sets of three-phase inverter bridges and their gate drive circuits.

[0028] Sensor inverse module: includes incremental encoder signal processing circuit, Hall signal digital logic shaping circuit, MOSFET drive and protection circuit, current sampling circuit (such as sampling resistor + isolation operational amplifier), temperature sampling circuit (such as thermistor + isolation operational amplifier), and voltage sampling circuit.

[0029] Straight-through detection and protection module: To prevent short circuits caused by shoot-through of the upper and lower bridge arms of the inverter, a shoot-through detection and protection circuit based on a logic chip is added. When the control signals of the upper and lower bridge arms are both high, the circuit will remain in the off state, realizing hardware interlocking of the PWM control signals.

[0030] II. Software and Control Methods The core of the software and control method of this invention lies in the implementation of a real-time scheduling strategy with dual-core collaboration and an efficient three-axis servo control algorithm.

[0031] Dual-core task allocation and real-time scheduling: Task scheduling on kernel a: Kernel a runs a real-time operating system (RTOS) or a timer-interrupt-based scheduler. It is responsible for communication parsing, trajectory planning, and sending the target instructions for the three axes to kernel b via IPC.

[0032] Real-time control loop on kernel b: Kernel b handles the core control calculations. It employs a strategy combining time-slice round-robin and high-priority interrupts. A high-priority timer interrupt (e.g., 20kHz) triggers the current loop calculation. Within the interrupt service routine (ISR), three sets of FOC algorithms are sequentially completed through looping and computational optimization. The velocity loop and position loop algorithms run in the main loop.

[0033] l Three-axis synchronous control strategy: Precise synchronous motion between the three axes can be achieved through software by employing strategies such as electronic gear / electronic cam or cross-coupling control.

[0034] Multi-level fault protection mechanism: Level 1 (Hardware Level): Hardware protection based on CMPSS, with the fastest response speed.

[0035] Level 2 (Software Real-Time Level): In the current loop ISR of kernel b, current, position error, etc. are checked in real time. Once an abnormality is found, the PWM is immediately blocked by software.

[0036] Level 3 (System Level): Kernel a runs fault diagnosis tasks, handles communication timeouts, and executes system safety shutdown procedures.

[0037] Take the three-axis motion control (azimuth axis Az, elevation axis E1, polarization axis Po) of a satellite communication antenna as an example.

[0038] 1. Hardware connection: The main controller is a dual-core DSP.

[0039] All three axes use low-inertia permanent magnet synchronous servo motors, and each motor is equipped with an incremental encoder.

[0040] The current sampling uses a high-precision sampling circuit (sampling resistor + isolation operational amplifier).

[0041] The dual-core DSP communicates with the host computer at high speed via the EtherCAT bus to meet the requirements of real-time antenna pointing control.

[0042] The inverter used for power drive is a three-phase full-bridge inverter based on MOSFET devices, and the drive signal is generated by a half-bridge drive chip.

[0043] 2. Workflow: The core logic of this system lies in converting abstract motion commands from the host computer into electrical energy to drive the precise movement of three motors through a series of precisely timed and interconnected hardware and software processes, forming a closed, high-precision autonomous control system. Its implementation logic can be divided into the following key stages: Phase 1: Instruction parsing and trajectory planning (executed in kernel a)

[0044] Command reception and parsing: Kernel a receives target angle commands (e.g., azimuth 45°, pitch 30°, polarization 0°) from the host computer via high real-time industrial buses such as EtherCAT. Kernel a runs the communication protocol stack, parses data packets, and extracts constraints such as the final target position, maximum speed, and acceleration for each axis.

[0045] Kernel A's trajectory planner generates a smooth, time-parameterized motion trajectory curve based on constraints. This process converts discrete "point commands" into a continuous "time-position-velocity" reference sequence. Simultaneously, the velocity look-ahead function analyzes the upcoming path and plans acceleration and deceleration in advance, ensuring smoothness and accuracy in the motion process.

[0046] Generate a series of instantaneous three-axis target position commands that are uniformly distributed over time.

[0047] The planned target location instructions are transmitted to kernel b in real time via the IPC mechanism.

[0048] Phase Two: Real-time Closed-Loop Control (Executed in Kernel b)

[0049] This is the core, lowest-level control logic of the system, executed cyclically based on a high-priority timer interrupt (e.g., 20kHz). Its logical sequence is as follows: Interrupt triggering and data acquisition: Logical clock: A hardware timer periodically generates interrupts, forcing the CPU to pause its current task and jump to the current loop interrupt service routine. This ensures the strict periodicity of the control loop and is the cornerstone of high-performance servo control.

[0050] The SOC signal of the PWM module synchronously triggers the ADC to synchronously sample the phase currents of the three motors. This eliminates the phase error caused by sampling delay.

[0051] At the ISR input, kernel b immediately reads the current sampling results of all ADCs and the pulse counts of the three encoders, converting them into the actual position of the motor.

[0052] Three-axis cyclic control calculation: Within the same interrupt cycle, kernel b executes the complete FOC algorithm sequentially for each of the three motor axes. The logic flow is identical for each axis, forming three parallel control pipelines: a. Position loop calculation: The target position issued by kernel a is compared with the actual position fed back by the encoder to obtain the position error. The target velocity is then calculated via a position PID controller.

[0053] b. Speed ​​loop calculation: The target speed is compared with the actual speed obtained by the encoder differential to obtain the speed error. The target torque current (Iq) is then calculated via a speed PID controller.

[0054] c. Current loop calculation (FOC core): Clarke / Park transformation: Transforms the sampled three-phase stationary coordinate system currents (Ia, Ib, Ic) into direct-axis currents (Id) and quadrature-axis currents (Iq) in a two-phase rotating coordinate system.

[0055] PID control: The transformed (Id, Iq) values ​​are compared with their target values ​​(Iq comes from the speed loop, and Id is usually set to 0 to achieve maximum torque output). The error is passed through the PID controller to calculate the voltage vector (Vd, Vq) that needs to be applied in the rotating coordinate system.

[0056] Inverse Park transformation: Transforms (Vd, Vq) back to a two-phase stationary coordinate system.

[0057] SVPWM generation: Based on the voltage vector in the stationary coordinate system, calculate and update the comparison register value of the ePWM module to generate six PWM waves to drive the three-phase inverter bridge.

[0058] Synchronization error compensation logic: During the calculation of the position or velocity loop, the cross-coupling control algorithm intervenes in real time. This algorithm continuously monitors (for example) the actual position or velocity of the azimuth and pitch axes, calculates the difference between them as a synchronization error, and then multiplies this error by a coupling coefficient to form a compensation amount, which is then superimposed on the input or output of the position or velocity loops of the two axes, respectively.

[0059] If one axis lags due to load disturbance, the algorithm will slightly slow down the other axis while speeding up the lagging axis, thereby dynamically maintaining the synchronization between the two axes and ensuring the stability of the antenna beam pointing.

[0060] Phase 3: Power Drive and Hardware Protection (Executed automatically in hardware)

[0061] The ePWM module outputs six PWM waveforms based on the updated register values ​​from kernel b.

[0062] These waveforms are hardware-interlocked by the shoot-through detection and protection circuit to ensure that the upper and lower bridge arms do not conduct simultaneously.

[0063] The safety PWM signal drives the half-bridge driver chip, which in turn controls the switching of the MOSFET three-phase inverter bridge, converting the DC bus voltage into on-demand three-phase AC power to drive the permanent magnet synchronous motor to rotate.

[0064] Hardware protection logic: Continuous monitoring: The comparator subsystem continuously compares the current sample value with a preset hardware threshold.

[0065] Asynchronous action: Once the current in a certain phase exceeds the limit, the comparator will immediately and unconditionally pull the corresponding ePWM output low (block) within nanoseconds, without waiting for the CPU to respond. This is the highest priority and fastest response safety logic.

[0066] Phase 4: System Monitoring and Fault Handling (Dual-Core Collaboration)

[0067] Real-time monitoring of kernel b: In the current loop ISR, in addition to executing the control algorithm, real-time fault judgment is also performed (such as position error exceeding the limit, software current limit). Once an abnormality is detected, the PWM is immediately blocked by software.

[0068] System monitoring in kernel a: Kernel a runs a watchdog task to monitor whether communication with the host computer times out and receives fault information reported by kernel b. It is responsible for performing more complex fault diagnosis and system-level safe shutdown procedures.

Claims

1. A three-axis servo drive system for an antenna based on a single-chip dual-core DSP, characterized in that, include: Dual-core DSP main controller, three-channel power drive module, three-axis actuator motor, sensor feedback module; The dual-core DSP main controller has core a for system communication, three-axis trajectory planning and task scheduling, and core b for real-time servo control algorithm calculation for the three-axis motor. The dual-core DSP main controller communicates with the host computer at high speed via the EtherCAT bus. Core a receives the target angle command from the host computer, performs trajectory planning and velocity look-ahead processing, and sends the target position of the three axes to core b via IPC. Core b runs the current loop at high frequency, sequentially reads the current sampling values ​​of the three ADCs and the actual position feedback from the three encoders, executes three sets of FOC algorithms, updates the values ​​of the three sets of ePWM registers, and drives three servo motors. A cross-coupled control algorithm is adopted to calculate and compensate for the synchronization error between the azimuth and pitch axes in real time, ensuring the accuracy and stability of the antenna beam pointing.

2. The antenna three-axis servo drive system of a single-chip dual-core DSP according to claim 1, characterized in that, The core b of the dual-core DSP main controller is responsible for running three sets of three-closed-loop servo control algorithms for servo motors in parallel: the current loop adopts field-oriented control, and the speed loop and position loop operate at corresponding frequencies according to performance requirements; the core b reads sensor feedback, performs PID adjustment and coordinate transformation, and updates the control quantity in real time.

3. The antenna three-axis servo drive system of a single-chip dual-core DSP according to claim 1, characterized in that, The peripherals of the dual-core DSP main controller include: The enhanced PWM module has a total of 9 modules, which are used to generate three three-phase PWM waveforms. After passing through the logic chip-based shoot-through protection circuit, they directly control the half-bridge driver chip, thereby driving the power inverter bridge of the three servo motors. The enhanced PWM module supports high resolution, dead-time programming, and synchronous triggering with the ADC. The high-precision ADC module utilizes its multiple ADC channels to synchronously sample the phase currents of three servo motors, providing feedback for the current loop; the startup of the high-precision ADC module is precisely triggered by the SOC signal of the enhanced PWM module. Enhanced encoder pulse module: It has three sets, which are used to capture the position and speed feedback signals of the photoelectric encoder or magnetoelectric encoder on the four servo motors; The comparator subsystem, configured on each servo axis, is used for hardware-level overcurrent and overvoltage protection. When the sampled current exceeds the set threshold, the comparator subsystem directly shuts off the output of the corresponding enhanced PWM module within nanoseconds.

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