An ultra-low spurious X / Ku broadband downconverter circuit and its implementation method

Abstract

This invention discloses an ultra-low spurious X / Ku broadband downconversion circuit and its implementation method, belonging to the field of radar communication technology. The circuit includes a reference clock, a first power divider, a second power divider, an input frequency measurement circuit, a phase-locked loop (PLL), a third power divider, a mixer-filter circuit, and an FPGA control unit. The frequency measurement module accurately measures the frequency of the external input signal, and the PLL dynamically adjusts the local oscillator frequency, effectively avoiding mixing intermodulation spurious signals. The final output signal is 1.8 GHz ± 500 MHz, with spurious suppression ≥ 75 dBc. This application achieves ultra-low spurious X / Ku broadband downconversion, significantly superior to traditional solutions (spurious suppression approximately 50 dBc), meeting the requirements of modern broadband radar systems.

Description

Technical Field

[0001] This invention belongs to the field of radar communication technology, specifically, it relates to an ultra-low spurious X / Ku broadband downconversion circuit and its implementation method. Background Technology

[0002] In modern information warfare, the demand for battlefield awareness capabilities is increasing, and radar, as a key sensor, plays an indispensable role in target detection, identification, and tracking. With the development of radar technology, broadband radar has attracted widespread attention due to its superior performance. Broadband radar features a large bandwidth, providing strong anti-jamming capabilities, stealth target detection capabilities, extremely high range resolution, and excellent target identification and ultra-short-range detection capabilities. These characteristics give broadband radar significant advantages in complex electromagnetic environments. However, the design of broadband radar also faces many challenges, especially in the design of the transceiver system. Because broadband radar typically uses a large time-width product to transmit signals, its absolute and relative bandwidths are large, thus placing higher demands on the instantaneous bandwidth of the signal, system sensitivity, signal-to-noise ratio, and real-time processing capabilities.

[0003] Currently, many research institutions and universities require transceiver systems with an instantaneous bandwidth of 1 GHz to meet experimental and application needs in their research on broadband systems. However, traditional 1 GHz instantaneous bandwidth downconversion receivers have significant shortcomings, particularly in spurious suppression, typically only reaching around 50 dBc. This spurious suppression capability is insufficient to meet the high-purity signal requirements of modern broadband radar systems, becoming a key bottleneck restricting system performance improvement. Furthermore, traditional downconversion schemes are prone to generating intermodulation spurious signals during the mixing process. These spurious signals may fall into the passband of the target signal, further degrading system performance. Although filters can suppress out-of-band spurious signals to some extent, they are difficult to effectively filter out spurious signals falling within the passband, thus limiting the spurious suppression capability of the output signal.

[0004] like Figure 1 As shown, this is a conventional downconversion circuit. Its mixer has a spurious rejection ratio (SCR) of 52dBc for the second-order intermediate frequency (IF). Therefore, mixing an 8GHz-13GHz signal with a 30GHz-35GHz signal produces a 22GHz±500MHz signal with SCR ≥ 52dBc. Mixing a 12GHz-18GHz signal with a 35GHz-40GHz signal produces a 22GHz±500MHz signal; no mixing intermodulation spurious signals fall within the 22GHz±500MHz bandpass filter. Mixing a 22GHz±500MHz signal with a 20.2GHz signal produces a 1.8GHz±500MHz signal; no mixing intermodulation spurious signals fall within the 1.8GHz±500MHz bandpass filter. Therefore, the final output spurious signal of the frequency converter is ≥ 52dBc.

[0005] To address the aforementioned issues, there is an urgent need for a broadband downconversion technology capable of achieving ultra-low spurious emissions in order to meet the requirement of high spurious emissions suppression under 1GHz instantaneous bandwidth conditions. Summary of the Invention

[0006] The purpose of this invention is to provide an ultra-low spurious X / Ku broadband downconversion circuit and its implementation method, mainly to solve the problem of insufficient spurious suppression performance in existing broadband downconversion schemes.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] An ultra-low spurious X / Ku broadband downconverter circuit includes: a reference clock, a first power divider, a second power divider, an input frequency measurement circuit, a phase-locked loop, a third power divider, a mixer filter circuit, and an FPGA control unit.

[0009] The output of the reference clock is connected to the input of the first power divider, and the two outputs of the first power divider are respectively connected to the phase-locked loop and the input of the second power divider.

[0010] The two output terminals of the second power divider output two reference clock signals, one for the FPGA control unit and the other for the input frequency measurement circuit.

[0011] The input frequency measurement circuit is used to measure the frequency of the external input signal to obtain the accurate frequency of the external input signal, and feed the signal back to the FPGA control unit;

[0012] The phase-locked loop receives a reference clock signal from the first power divider and a control signal from the FPGA control unit, and outputs an RF signal to the third power divider.

[0013] The third power divider splits the RF signal output from the phase-locked loop into two paths: one path serves as the loopback signal of the phase-locked loop, and the other path serves as the local oscillator signal for the mixing and filtering circuit.

[0014] The mixing and filtering circuit receives the local oscillator signal output from the third power divider and the external input signal, mixes and filters them, and then outputs a down-converted signal.

[0015] The FPGA control unit dynamically adjusts the operating state of the phase-locked loop based on the frequency measurement results of the input frequency measurement circuit to ensure that the local oscillator frequency matches the input signal frequency.

[0016] Furthermore, in this invention, the input frequency measurement circuit includes a fourth power divider and a frequency measurement module. The fourth power divider divides the external input signal into two paths: one path is input to the frequency measurement module for frequency measurement, and the other path serves as the radio frequency input signal for the mixing and filtering circuit.

[0017] Furthermore, in this invention, the phase-locked loop includes a loop filter and a voltage-controlled oscillator (VCO); the loop filter consists of a phase detector, capacitor C1, resistor R1, capacitor C2, resistor R2, capacitor C3, resistor R3, capacitor C4, and an operational amplifier; the phase detector receives a reference clock signal from the first power divider and a loopback signal provided by the third power divider, and its output is connected to capacitor C1 and resistor R1. The other end of capacitor C1 is grounded, and the other end of resistor R1 is connected to the inverting input of the operational amplifier. Resistor R2 and capacitor C3 are connected in series between the inverting input and output of the operational amplifier, and capacitor C2 is connected between the inverting input and output of the operational amplifier; one end of resistor R3 is connected to the output of the operational amplifier and the other end is connected to the input of the VCO; one end of capacitor C4 is connected to the input of the VCO and the other end is grounded; the VCO outputs a radio frequency signal to the third power divider.

[0018] Furthermore, in this invention, the mixing and filtering circuit includes an amplifier, a mixer, and a bandpass filter; wherein, the amplifier amplifies the voltage-controlled oscillator output signal after power division by the third power divider to the local oscillator drive power of the mixer; the mixer mixes the external input signal after power division by the fourth power divider with the local oscillator signal to generate an intermediate frequency signal; and the bandpass filter filters out mixing intermodulation spurious signals from the intermediate frequency signal before outputting the target signal.

[0019] Furthermore, in this invention, the FPGA control unit dynamically adjusts the operating state of the phase-locked loop to ensure that the local oscillator frequency output by the voltage-controlled oscillator matches the input signal frequency.

[0020] Based on the above circuit, the present invention also provides an ultra-low spurious X / Ku broadband downconversion implementation method, executed by the FPGA control unit, comprising the following steps:

[0021] S1. Reference clock distribution: The reference clock signal is divided into two paths by the first power divider. One path is directly supplied to the phase detector as the reference clock; the other path enters the second power divider and is divided into two paths: one path is supplied to the FPGA control unit as the control clock, and the other path is supplied to the frequency measurement module as the frequency measurement reference clock.

[0022] S2. External input signal preprocessing: The external input signal is split into two paths by the fourth power divider. One path enters the frequency measurement module for accurate measurement of the input signal frequency; the other path is directly used as the RF input signal of the mixer.

[0023] S3. Frequency Measurement and Phase-Locked Loop Control: After the frequency measurement module completes the frequency measurement of the input signal, it feeds back the result to the FPGA control unit; the FPGA control unit sends a control command to the phase detector based on the frequency measurement result to adjust the output frequency of the phase-locked loop.

[0024] S4. Phase-locked loop generates precise local oscillator signal: The phase detector compares the phase difference between the reference clock and the voltage-controlled oscillator loopback signal, and outputs an error signal; the loop filter removes high-frequency spurious signals and noise from the error signal, and outputs a stable control voltage to regulate the voltage-controlled oscillator; the voltage-controlled oscillator output signal is divided into two paths by the third power divider, one path is sent back to the phase detector as the loopback signal, and the other path is amplified by the amplifier to the local oscillator drive power required by the mixer, serving as the local oscillator input signal of the mixer;

[0025] S5. Mixing to generate intermediate frequency signal: The mixer receives the RF input signal from the fourth power divider and the precise local oscillator signal from the amplifier; after mixing, it generates an intermediate frequency signal.

[0026] S6. Filtered output of ultra-low spurious signal: The intermediate frequency signal after mixing is filtered by a bandpass filter to remove out-of-band mixing intermodulation spurious signals, and finally outputs a target signal with spurious suppression ≥75dBc, completing the ultra-low spurious broadband downconversion.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] (1) This invention uses an input frequency measurement circuit to accurately measure the frequency of the external input signal, and combines this with an FPGA control unit to dynamically adjust the local oscillator frequency of the phase-locked loop, ensuring that the local oscillator frequency is precisely matched with the input signal frequency, effectively avoiding mixing intermodulation spurious signals falling into the passband of the target intermediate frequency signal. Experimental verification shows that the spurious suppression of this scheme is ≥75dBc, which is far superior to the approximately 50dBc of the traditional scheme. This solves the core problem of insufficient spurious suppression in traditional broadband downconversion, and meets the stringent requirements of modern broadband radar for high-purity signals.

[0029] (2) The phase-locked loop of this invention uses a loop filter composed of a multi-stage RC network and an operational amplifier, which can efficiently filter out high-frequency spurious signals and noise in the error signal, and output a stable control voltage-regulated voltage-controlled oscillator (VCO) to ensure the frequency stability and phase purity of the local oscillator signal. At the same time, the VCO output signal is fed back to the phase detector through a power divider to form a closed-loop control, which further improves the accuracy of the local oscillator signal, provides a high-quality local oscillator input for the mixing process, and reduces nonlinear distortion.

[0030] (3) This invention supports wideband input signals of 8GHz-18GHz. Through the coordinated operation of an amplifier, a high-performance mixer (such as HMC773LC3B), and a high-order bandpass filter in the mixing and filtering circuit: the amplifier ensures the local oscillator signal reaches the mixer's driving power; the mixer reduces nonlinear distortion; and the bandpass filter removes out-of-band spurious signals, ultimately achieving efficient down-conversion with a 1GHz instantaneous bandwidth. This solution is adaptable to wideband radar systems in complex electromagnetic environments, possessing advantages such as strong anti-interference capability and high range resolution, providing reliable technical support for applications such as battlefield awareness and target identification. Attached Figure Description

[0031] Figure 1 This is a structural diagram of a downconverter circuit in the prior art;

[0032] Figure 2 This is a structural diagram of the downconversion circuit of the present invention. Detailed Implementation

[0033] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0034] like Figure 2 As shown, this invention discloses an ultra-low spurious X / Ku broadband downconversion circuit, comprising a reference clock, a first power divider (i.e., power divider 1), a second power divider (i.e., power divider 2), an input frequency measurement circuit, a phase-locked loop (PLL), a third power divider (i.e., power divider 3), a mixer-filter circuit, and an FPGA control unit. The input frequency measurement circuit consists of a fourth power divider (i.e., power divider 4) and a frequency measurement module. The PLL consists of a loop filter and a voltage-controlled oscillator (VCO). The mixer-filter circuit includes an amplifier, a mixer, and a bandpass filter. This circuit is used to complete the downconversion process from an external input signal to a 1.8GHz±500MHz intermediate frequency (IF) signal, achieving the technical goal of ultra-low spurious suppression ≥75dBc.

[0035] First, the reference clock provides a stable clock signal for the entire system. The output signal of the reference clock is split into two paths by power divider 1: one path supplies the phase-locked loop as the reference clock signal, and the other path enters power divider 2. Power divider 2 further splits the reference clock signal into two paths: one path supplies the FPGA control unit, and the other path supplies the input frequency measurement circuit.

[0036] The externally input 8GHz-18GHz signal is split into two paths by a power divider. One path enters the frequency measurement module for frequency measurement, while the other path serves as the RF input signal for the mixer. The frequency measurement module accurately measures the frequency of the external input signal, obtains the precise frequency, and transmits the measurement result to the FPGA control unit. The FPGA control unit dynamically adjusts the operating state of the phase-locked loop (PLL) based on the measurement result, ensuring that the local oscillator frequency output by the VCO matches the input signal frequency to achieve optimal mixing performance. The frequency measurement module employs a high-precision frequency measurement algorithm, enabling it to quickly and accurately acquire the frequency information of the input signal and avoid mixing intermodulation spurious problems caused by frequency measurement errors.

[0037] In this embodiment, the loop filter consists of a phase detector, capacitor C1, resistor R1, capacitor C2, resistor R2, capacitor C3, resistor R3, capacitor C4, and an operational amplifier. The phase detector receives a reference clock signal from the first power divider and a loopback signal from the third power divider. Its output terminal (CPo) is connected to capacitor C1 and resistor R1. The other end of capacitor C1 is grounded, and the other end of resistor R1 is connected to the inverting input of the operational amplifier. Resistor R2 and capacitor C3 are connected in series between the inverting input and output of the operational amplifier. Capacitor C2 is connected between the inverting input and output of the operational amplifier. One end of resistor R3 is connected to the output of the operational amplifier, and the other end is connected to the input of the voltage-controlled oscillator (VCO). One end of capacitor C4 is connected to the input of the VCO, and the other end is grounded. The loop filter aims to stabilize the output of the phase-locked loop (PLL) and adjusts the VCO by controlling the voltage Vt to ensure that the output frequency range of the VCO is 9.8 GHz to 16.2 GHz. The VCO selected is IVO-1020-CQ4. Its output signal is split into two paths by a power divider: one path serves as the loopback signal for the phase detector, and the other path is amplified by an amplifier to serve as the local oscillator signal for the mixer. The amplifier ensures that the VCO output signal can achieve the local oscillator drive power required by the mixer.

[0038] The mixer selected is the HMC773LC3B, which mixes the externally input 8GHz-18GHz signal with a 9.8GHz-16.2GHz local oscillator signal to generate an intermediate frequency (IF) signal of 1.8GHz ± 500MHz. The mixer employs high-performance mixing technology, effectively reducing nonlinear distortion during the mixing process and thus minimizing mixing intermodulation spurious signals. A bandpass filter filters the mixed signal, removing out-of-band mixing intermodulation spurious signals and ensuring that the output signal has a spurious rejection ratio (SCR) ≥ 75dBc. The bandpass filter uses high-order filtering technology, effectively filtering out out-of-band spurious signals while maintaining signal integrity within the passband.

[0039] This invention achieves broadband ultra-low spurious downconversion technology through the following steps.

[0040] S1: The output signal of the reference clock is split into two paths by power divider 1. One path is supplied to the phase detector, and the other path is sent to power divider 2. Power divider 2 further splits the reference clock signal into two paths. One path is supplied to the FPGA control unit, and the other path is supplied to the frequency measurement module.

[0041] S2: The externally input 8GHz-18GHz signal is split into two paths by a power divider. One path enters the frequency measurement module for frequency measurement, and the other path serves as the RF input signal for the mixer.

[0042] S3: The frequency measurement module performs accurate frequency measurement on the external input signal, obtains the accurate frequency of the input signal, and transmits the frequency measurement result to the FPGA control unit.

[0043] S4: The FPGA control unit dynamically adjusts the working state of the phase-locked loop based on the frequency measurement results to ensure that the local oscillator frequency output by the VCO matches the input signal frequency.

[0044] S5: The 9.8GHz-16.2GHz signal output by the VCO is split into two paths by a power divider. One path serves as the loopback signal for the phase detector, and the other path is amplified by an amplifier to serve as the local oscillator signal for the mixer.

[0045] S6: The mixer mixes the externally input 8GHz-18GHz signal with the 9.8GHz-16.2GHz local oscillator signal to generate an intermediate frequency signal of 1.8GHz±500MHz.

[0046] S7: The bandpass filter filters the mixed signal to remove out-of-band mixing intermodulation spurious signals and ensure that the spurious suppression of the output signal is ≥75dBc.

[0047] Specifically, this invention achieves dynamic adjustment of the local oscillator frequency through the coordinated operation of the frequency measurement module and the phase-locked loop (PLL). When the frequency measurement module measures the input signal frequency to be 8GHz-9GHz, the PLL outputs 10.3GHz as the local oscillator signal (LO); when the frequency measurement module measures the input signal (RFin) frequency to be 9GHz-10GHz, the PLL outputs 11.3GHz as the local oscillator signal; when the frequency measurement module measures the input signal frequency to be 10GHz-11GHz, the PLL outputs 12.3GHz as the local oscillator signal; when the frequency measurement module measures the input signal frequency to be 11GHz-12GHz, the PLL outputs 13.3GHz as the local oscillator signal; and when the frequency measurement module measures the input signal frequency to be 12GHz-13GHz, the PLL outputs 14.3GHz as the local oscillator signal. The phase-locked loop (PLL) outputs a local oscillator (LO) signal of 11.7 GHz when the frequency measurement module detects an input signal frequency of 13 GHz-14 GHz; 12.7 GHz when the frequency measurement module detects an input signal frequency of 14 GHz-15 GHz; 13.3 GHz when the frequency measurement module detects an input signal frequency of 15 GHz-16 GHz; 14.7 GHz when the frequency measurement module detects an input signal frequency of 16 GHz-17 GHz; and 15.7 GHz when the frequency measurement module detects an input signal frequency of 17 GHz-18 GHz. This dynamic adjustment mechanism ensures that no mixing intermodulation spurious signals fall within the 1.8 GHz ± 500 MHz filter band during the mixing process, ultimately achieving a spurious signal suppression of ≥75 dBc for the output signal.

[0048] In practical applications, the technical solution of this invention can be widely used in the field of radar communication, especially in modern broadband radar systems. For example, in information warfare where battlefield awareness is crucial, radar, as a sensor, needs to possess strong anti-jamming capabilities, the ability to detect concealed targets, and high range resolution. This invention, by precisely controlling the local oscillator frequency, avoids the intermodulation spurious signals generated by the mixing of the 4th-order radio frequency and the 4th-order local oscillator signals falling within the 1.8GHz±500MHz filter band, significantly improving the system's spurious suppression performance. Furthermore, this invention supports broadband input signals from 8GHz to 18GHz and can achieve downconversion with an instantaneous bandwidth of 1GHz, meeting the requirements of modern broadband radar systems.

[0049] To verify the technical effectiveness of this invention, experimental tests were conducted. The test results show that when the input signal frequency is 8GHz-9GHz, the phase-locked loop outputs 10.3GHz as the local oscillator signal, and the spurious suppression of the generated 1.8GHz±500MHz signal after mixing is ≥75dBc; when the input signal frequency is 9GHz-10GHz, the phase-locked loop outputs 11.3GHz as the local oscillator signal, and the spurious suppression of the generated 1.8GHz±500MHz signal after mixing is ≥75dBc; when the input signal frequency is 10GHz-11GHz, the phase-locked loop outputs 12.3GHz... As the local oscillator signal, the spurious suppression of the generated 1.8GHz±500MHz signal after mixing is ≥75dBc; when the input signal frequency is 11GHz-12GHz, the phase-locked loop outputs 13.3GHz as the local oscillator signal, and the spurious suppression of the generated 1.8GHz±500MHz signal after mixing is ≥75dBc; when the input signal frequency is 12GHz-13GHz, the phase-locked loop outputs 14.3GHz as the local oscillator signal, and the spurious suppression of the generated 1.8GHz±500MHz signal after mixing is ≥75dBc. c; When the input signal frequency is 13GHz-14GHz, the phase-locked loop outputs 11.7GHz as the local oscillator signal, and the spurious rejection of the generated 1.8GHz±500MHz signal after mixing is ≥75dBc; when the input signal frequency is 14GHz-15GHz, the phase-locked loop outputs 12.7GHz as the local oscillator signal, and the spurious rejection of the generated 1.8GHz±500MHz signal after mixing is ≥75dBc; when the input signal frequency is 15GHz-16GHz, the phase-locked loop outputs 13.3GHz as... The local oscillator signal, after mixing, achieves spurious suppression of ≥75dBc for the 1.8GHz±500MHz signal. When the input signal frequency is 16GHz-17GHz, the phase-locked loop outputs 14.7GHz as the local oscillator signal, and the resulting 1.8GHz±500MHz signal after mixing also exhibits spurious suppression of ≥75dBc. When the input signal frequency is 17GHz-18GHz, the phase-locked loop outputs 15.7GHz as the local oscillator signal, and the resulting 1.8GHz±500MHz signal after mixing also exhibits spurious suppression of ≥75dBc. Experimental results demonstrate that the technical solution of this invention can significantly improve the spurious suppression performance of the system, meeting the requirements of modern broadband radar systems.

[0050] In summary, this invention achieves a broadband, ultra-low spurious downconversion with a 1GHz instantaneous bandwidth by utilizing the coordinated operation of a frequency measurement module and a phase-locked loop (PLL). The frequency measurement module accurately measures the frequency of the external input signal, providing a basis for dynamic adjustment of the PLL. The FPGA dynamically adjusts the PLL's operating state to ensure the local oscillator frequency matches the input signal frequency. A high-precision VCO and amplifier ensure the stability and driving capability of the local oscillator signal. A bandpass filter filters the mixed signal, removing out-of-band mixing intermodulation spuriouss. These techniques work together to achieve spurious suppression of the output signal ≥75dBc, significantly superior to traditional downconversion schemes.

[0051] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. An ultra-low spurious X / Ku broadband downconverter circuit, characterized in that, include: Reference clock, first power divider, second power divider, input frequency measurement circuit, phase-locked loop, third power divider, mixer and filter circuit and FPGA control unit; The output of the reference clock is connected to the input of the first power divider, and the two outputs of the first power divider are respectively connected to the phase-locked loop and the input of the second power divider. The two output terminals of the second power divider output two reference clock signals, one for the FPGA control unit and the other for the input frequency measurement circuit. The input frequency measurement circuit is used to measure the frequency of the external input signal to obtain the accurate frequency of the external input signal, and feed the signal back to the FPGA control unit; The phase-locked loop receives a reference clock signal from the first power divider and a control signal from the FPGA control unit, and outputs an RF signal to the third power divider. The third power divider splits the RF signal output from the phase-locked loop into two paths: one path serves as the loopback signal of the phase-locked loop, and the other path serves as the local oscillator signal for the mixing and filtering circuit. The mixing and filtering circuit receives the local oscillator signal output from the third power divider and the external input signal, mixes and filters them, and then outputs a down-converted signal. The FPGA control unit dynamically adjusts the operating state of the phase-locked loop based on the frequency measurement results of the input frequency measurement circuit to ensure that the local oscillator frequency matches the input signal frequency.

2. The ultra-low spurious X / Ku broadband downconverter circuit according to claim 1, characterized in that, The input frequency measurement circuit includes a fourth power divider and a frequency measurement module. The fourth power divider splits the external input signal into two paths: one path is input to the frequency measurement module for frequency measurement, and the other path serves as the radio frequency input signal for the mixer-filter circuit.

3. The ultra-low spurious X / Ku broadband downconverter circuit according to claim 2, characterized in that, The phase-locked loop includes a loop filter and a voltage-controlled oscillator (VCO). The loop filter consists of a phase detector, capacitor C1, resistor R1, capacitor C2, resistor R2, capacitor C3, resistor R3, capacitor C4, and an operational amplifier. The phase detector receives a reference clock signal from the first power divider and a loopback signal from the third power divider. Its output is connected to capacitor C1 and resistor R1. The other end of capacitor C1 is grounded. The other end of resistor R1 is connected to the inverting input of the operational amplifier. Resistor R2 and capacitor C3 are connected in series between the inverting input and output of the operational amplifier. Capacitor C2 is connected between the inverting input and output of the operational amplifier. One end of resistor R3 is connected to the output of the operational amplifier, and the other end is connected to the input of the VCO. One end of capacitor C4 is connected to the input of the VCO, and the other end is grounded. The VCO outputs an RF signal to the third power divider.

4. The ultra-low spurious X / Ku broadband downconverter circuit according to claim 3, characterized in that, The mixing and filtering circuit includes an amplifier, a mixer, and a bandpass filter; wherein, the amplifier amplifies the voltage-controlled oscillator output signal after power division by the third power divider to the local oscillator drive power of the mixer; the mixer mixes the external input signal after power division by the fourth power divider with the local oscillator signal to generate an intermediate frequency signal; the bandpass filter filters out mixing intermodulation spurious signals from the intermediate frequency signal and outputs the target signal.

5. The ultra-low spurious X / Ku broadband downconverter circuit according to claim 4, characterized in that, The FPGA control unit dynamically adjusts the operating state of the phase-locked loop to ensure that the local oscillator frequency output by the voltage-controlled oscillator matches the input signal frequency.

6. A method for implementing ultra-low spurious X / Ku broadband downconversion, characterized in that, The ultra-low spurious X / Ku broadband downconversion circuit based on claim 5, executed by the FPGA control unit, includes the following steps: S1. Reference clock distribution: The reference clock signal is divided into two paths by the first power divider. One path is directly supplied to the phase detector as the reference clock; the other path enters the second power divider and is divided into two paths: one path is supplied to the FPGA control unit as the control clock, and the other path is supplied to the frequency measurement module as the frequency measurement reference clock. S2. External input signal preprocessing: The external input signal is split into two paths by the fourth power divider. One path enters the frequency measurement module for accurate measurement of the input signal frequency; the other path is directly used as the RF input signal of the mixer. S3. Frequency Measurement and Phase-Locked Loop Control: After the frequency measurement module completes the frequency measurement of the input signal, it feeds back the result to the FPGA control unit; the FPGA control unit sends a control command to the phase detector based on the frequency measurement result to adjust the output frequency of the phase-locked loop. S4. Phase-locked loop generates precise local oscillator signal: The phase detector compares the phase difference between the reference clock and the voltage-controlled oscillator loopback signal, and outputs an error signal; the loop filter removes high-frequency spurious signals and noise from the error signal, and outputs a stable control voltage to regulate the voltage-controlled oscillator; the voltage-controlled oscillator output signal is divided into two paths by the third power divider, one path is sent back to the phase detector as the loopback signal, and the other path is amplified by the amplifier to the local oscillator drive power required by the mixer, serving as the local oscillator input signal of the mixer; S5. Mixing to generate intermediate frequency signal: The mixer receives the RF input signal from the fourth power divider and the precise local oscillator signal from the amplifier; after mixing, it generates an intermediate frequency signal. S6. Filtered output of ultra-low spurious signal: The intermediate frequency signal after mixing is filtered by a bandpass filter to remove out-of-band mixing intermodulation spurious signals, and finally outputs a target signal with spurious suppression ≥75dBc, completing the ultra-low spurious broadband downconversion.

Images