Bidirectional switch for semiconductor device

Abstract

The invention discloses a bidirectional switch for a semiconductor device, and the semiconductor device comprises a first control end which is used for receiving a first control signal; the second control end is used for receiving a second control signal; and a bidirectional power transistor comprising a first gate terminal, a second gate terminal, a first terminal, and a second terminal, the first gate terminal and the second gate terminal being located between the first terminal and the second terminal, the first terminal and the second terminal are used for operating as a source terminal or a drain terminal of the bidirectional power transistor. The semiconductor device further includes an interface circuit monolithically integrated with the bidirectional power transistor and operably connected with the first control terminal, the second control terminal, the first gate terminal and the second gate terminal, the interface circuit being an actively switchable circuit, the interface circuit to: regulate a first voltage at the first gate terminal; and a second voltage at the second gate terminal.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. In particular, but not limited to, a bidirectional III-V high electron mobility transistor (HEMT) and its associated sensing, protection, and regulation circuitry. Background Technology

[0002] Gallium nitride (GaN) is a wide bandgap material, and its properties make it a suitable candidate material for many applications that require solid-state devices, such as radio frequency electronics, optoelectronics, and power electronics.

[0003] GaN technology facilitates the design of transistors with high electron mobility and high saturation velocity. These properties make GaN an ideal candidate material for various high-power and high-temperature applications, such as microwave applications like radar and cellular communication systems. As the number of system users and capacity requirements increase, there is growing interest in improving operating frequencies and power. Higher signal frequencies carry more information (i.e., larger bandwidth) and enable smaller antennas to achieve extremely high gain.

[0004] Furthermore, GaN's wide bandgap has the potential to achieve light emission at higher frequencies (such as the green, blue, violet, and ultraviolet portions of the electromagnetic spectrum).

[0005] Over the past decade, GaN has increasingly been recognized as a promising material for power devices, with applications spanning portable consumer electronics, solar inverters, electric vehicles, and power supplies. Its wide bandgap (Eg = 3.39 eV) enables a large critical electric field (Ec = 3.3 MV / cm), allowing for the design of devices with shorter drift regions and consequently lower on-resistance compared to silicon-based devices with the same breakdown voltage.

[0006] In addition, when using aluminum gallium nitride (AlGaN) / GaN heterostructures, extremely high mobility (e.g., μ = 2000 cm⁻¹) can be achieved at the hetero interface. 2 The electron density of the AlGaN / GaN heterostructure is approximately 1 × 10⁻⁶ (V·s), making it easier to form a two-dimensional electron gas (2DEG). Furthermore, the piezoelectric polarization charge in the AlGaN / GaN heterostructure results in a high electron density (e.g., 1 × 10⁻⁶) in the 2DEG layer. 13 cm -2 These characteristics make the performance parameters of the developed high electron mobility transistors (HEMTs) and Schottky barrier diodes highly competitive. Currently, a significant amount of research has been invested in the development of power devices with AlGaN / GaN heterostructures.

[0007] With the development of power applications such as electric vehicles, renewable energy generation, vehicle-to-vehicle communication, and energy storage, the demand for bidirectional switches is increasing. These switches can efficiently control bidirectional energy flow, ensuring safe and reliable operation under various operating conditions. Some emerging topologies may require power switches to have AC isolation capabilities, further increasing the demand for bidirectional switches. Examples of such topologies include:

[0008] 1. Three-level converter topologies such as T-type neutral point clamp (NPC) converters used in power factor correction (PFC) and inverter applications, high-power data center power supplies with three-phase input, and on-board chargers (OBC) / inverters for electric vehicles equipped with 800V batteries all require high-voltage switches (VDS>650V) with bidirectional AC isolation capability.

[0009] 2. AC / AC converters such as AC matrix converters or frequency converters also require AC isolation functionality.

[0010] 3. Solid-state circuit breakers (SSCBs) inherently require AC isolation functionality and are primarily used for bidirectional switching.

[0011] Traditionally, such applications have used back-to-back MOSFETs. Monolithic bidirectional switches based on wide-bandgap technology enable high power conversion efficiency and are increasingly being accepted as the industry standard for power electronics applications. Monolithic switches reduce material costs and improve efficiency.

[0012] Because there is no pn junction diode, GaN lateral devices are inherently bidirectional. Current flows from the source to the drain, or from the drain to the source, in a similar manner under the applied potential at the junction. However, the blocking capability of such devices depends on their gate-drain pitch, which limits their use in bidirectional applications. Existing methods to address this issue involve making the gate-drain pitch equal to the source-gate pitch, thus maintaining the same voltage across the device. The drawback of this method is that it increases the cell spacing. In another bidirectional switching design approach, the cell spacing is minimized by employing a dual-gate structure. To achieve this design, two devices are typically connected back-to-back. Because there are two gates instead of a single gate, this method also allows for more flexible gate control.

[0013] However, in certain situations, this method requires setting up two isolated sets of gate power supplies and two isolated gate drivers. Therefore, the applicant recognized the need for a more efficient monolithic solution, namely a bidirectional semiconductor device capable of being used in high-current, low-resistance, and high-voltage applications while reducing the number of devices. Summary of the Invention

[0014] The purpose of this invention is to provide a bidirectional semiconductor device that integrates sensing, protection, and regulation circuits.

[0015] According to a first aspect of this disclosure, a semiconductor device is provided, comprising:

[0016] A first control terminal for receiving a first control signal;

[0017] The second control terminal is used to receive the second control signal;

[0018] A bidirectional power transistor includes a first gate terminal, a second gate terminal, a first terminal, and a second terminal, wherein the first gate terminal and the second gate terminal are located between the first terminal and the second terminal. During use, the first terminal and the second terminal are used as either the source or drain terminals of the bidirectional power transistor.

[0019] An interface circuit, monolithically integrated with the bidirectional power transistor and operably connected to the first control terminal, the second control terminal, the first gate terminal, and the second gate terminal, is an actively switchable circuit comprising one or more transistors. This interface circuit is used for:

[0020] Adjusting the first voltage at the first gate terminal of the bidirectional power transistor; and

[0021] Adjust the second voltage at the second gate terminal of the bidirectional power transistor.

[0022] Compared to existing discrete device solutions, the device disclosed herein offers all or some of the following advantages:

[0023] 1. Compared to two discrete chips, it is smaller in size and has better on-resistance (i.e., resistance multiplied by area, which represents the chip area occupied by the device to achieve the target resistance).

[0024] 2. Based on a single VDD and a single adjustment circuit, the external voltage rail (VDD) can be adjusted to match the internal VDD voltage.

[0025] 3. It can, for example, meet the gate overvoltage, overcurrent, and short-circuit protection requirements of automotive power modules. In a specific implementation, the short-circuit protection mechanism can provide protection when any part of the device reaches saturation.

[0026] 4. Simplifies gate driver design, thereby reducing manufacturing costs and design constraints. For example, a specific implementation of the device may have only a floating power supply with its ground terminal referenced to the Kelvin connection voltage, thereby reducing or eliminating problems related to substrate potential.

[0027] This bidirectional power transistor can be a bidirectional III-V HEMT.

[0028] The gate of an enhancement-mode HEMT (i.e., an HEMT with a positive threshold voltage) may include a p-type GaN gate, which may include, for example, a magnesium-doped GaN region grown on an AlGaN layer (e.g., used as a p-type semiconductor). The gate may further include a Schottky or ohmic metallization layer in contact with or in direct contact with the p-type GaN region.

[0029] The gate of a depletion-type HEMT (i.e., a HEMT with a negative threshold voltage) may include Schottky metal deposited directly on an AlGaN layer.

[0030] It should be understood that other suitable enhancement-mode and depletion-mode HEMT gate structures may also be used in conjunction with the devices disclosed herein.

[0031] Both enhancement-mode and depletion-mode HEMTs can be used as high-voltage transistors, for example, by increasing the gate-drain spacing used to withstand voltage in isolation mode. Alternatively, the gate-drain terminals can be protected by providing a field plate, thereby reducing or maximizing the reduction of the electric field peak across the gate-drain terminals, respectively.

[0032] The first and second threshold voltage levels can be selected according to the needs and design requirements of the semiconductor device and / or its required function or application. Preferably, the threshold voltage is selected as a voltage whose difference between the maximum and minimum input voltages is large enough to prevent the gate from turning on or off due to signal noise or dV / dt events. For example, the threshold voltage can be in the range of 1.5 to 5V.

[0033] The interface circuit can be partially or completely monolithically integrated with the bidirectional transistor. This interface circuit can provide a variety of integrated sensing, protection, and regulation functions. In various embodiments, the interface circuit includes any one or more of the following:

[0034] Logic circuits;

[0035] Inverter;

[0036] Current source;

[0037] Capacitor;

[0038] Two-dimensional carrier gas (2DEG) or metallic resistor;

[0039] Voltage limiter;

[0040] Voltage regulator;

[0041] Level converter;

[0042] Short circuit detection and protection circuit;

[0043] Clamping circuit;

[0044] Electrostatic discharge (ESD) circuit;

[0045] Current sensing transistor;

[0046] Overcurrent detection circuit; and / or

[0047] Over-temperature detection circuit.

[0048] Such circuits and / or components may employ low-power or low-voltage enhancement-mode and depletion-mode HEMTs, resistors based on two-dimensional electron gases (2DEGs) or metals, and capacitors with insulating materials as dielectrics and parallel electrode plates with different conductive layers. Enhancement-mode low-power / low-voltage HEMTs may employ p-type GaN gates similar to high-voltage / high-power HEMTs. Depletion-mode low-power / low-voltage HEMTs may employ Schottky-type HEMTs (as described above for high-voltage depletion-mode HEMTs).

[0049] In a specific embodiment, the bidirectional power transistor may include a third terminal located between the first gate terminal and the second gate terminal. This third terminal is operatively connected to the interface circuit and serves to provide a reference voltage for both the first and second gate terminals. It should be understood that, unlike a back-to-back structure, the third terminal does not provide either charge carriers (providing electrons) or, conversely, charge carriers (consuming electrons) during the steady-state conduction of this bidirectional switch, and therefore is not used as a source or drain terminal. The third terminal can be used to provide a reference voltage. This connection can be used as a Kelvin connection and may be referred to as a voltage reference connection or an intermediate reference connection.

[0050] In a specific embodiment, the metallization area of ​​each of the first and second terminals is at least five times larger than the metallization area of ​​the third terminal. For example, the lengths of the first and second terminals can be 5 to 10 micrometers, while the length of the third terminal can be 1 to 2 micrometers. This is due to the fact that the third terminal does not carry current in a steady state, thus preventing contact resistance or electromigration caused by excessively high current density within the metallization layer from becoming a significant problem for the operation of the device.

[0051] The third terminal can be a Schottky junction. That is, the metallization layer of the third terminal can form a Schottky contact that contacts the 2DEG layer below the junction. Alternatively, the metallization layer can also form an ohmic contact that contacts the 2DEG layer below the third terminal. As another alternative, the third terminal may include a metallization layer disposed on a p-type GaN region, and the configuration can be similar to one or more of the gate junction structures described above.

[0052] In a specific embodiment, the third terminal is operatively connected to a Kelvin connection (or a Kelvin reference terminal), wherein the first and second control terminals are biased relative to the Kelvin connection. The semiconductor device may be configured such that the steady-state current flowing through the third terminal is zero or approximately zero (that is, such that the current is zero, or contains only a relatively small leakage current).

[0053] The bidirectional power transistor may include a substrate, which includes one or more of the following:

[0054] silicon;

[0055] Silicon carbide;

[0056] sapphire;

[0057] Diamond;

[0058] quartz;

[0059] Gallium nitride; and / or

[0060] Semi-insulating silicon carbide.

[0061] Optionally, the bidirectional power transistor may further include a substrate metallization layer, wherein the substrate metallization layer is operatively connected to the third terminal.

[0062] The interface circuit may include:

[0063] A first Miller-clamp transistor operably connected between the first gate terminal and the third terminal; and

[0064] A second Miller clamp transistor operatively connected between the second gate terminal and the third terminal.

[0065] In a specific embodiment, the first and second terminals of the bidirectional power transistor can be separated from each other along a first dimension, and

[0066] The third terminal may include multiple third terminal regions, which are separated from each other along a second dimension perpendicular to the first dimension.

[0067] As an additional or alternative embodiment, the third terminal may extend above the surface of the bidirectional power transistor and / or extend into or below the surface of the bidirectional power transistor toward the substrate layer. In one embodiment, the first and second terminals may extend along the second dimension, while the third terminal may extend along a third dimension perpendicular to the first and second dimensions. In such cases, the maximum length dimension of the first and second terminals may be located in the second dimension, while the maximum length dimension of the third terminal may be located in the third dimension.

[0068] In a specific embodiment, the interface circuit may include one or more gate interface circuits. The interface circuit may, for example, include:

[0069] A first auxiliary gate interface circuit, which can be used to adjust the voltage applied to the first control terminal so that the voltage applied to the first control terminal is operably matched with the first gate terminal, the first auxiliary gate interface circuit comprising:

[0070] A first low-voltage auxiliary HEMT, the first low-voltage auxiliary HEMT including a first auxiliary HEMT source terminal, a first auxiliary HEMT drain terminal, and a first auxiliary HEMT gate connection terminal; and

[0071] A first voltage limiter operably connected to the gate connection of the first auxiliary HEMT.

[0072] The first auxiliary HEMT source is operatively connected to the first gate terminal.

[0073] The first auxiliary HEMT drain terminal is operatively connected to the first control terminal.

[0074] The first voltage limiter is operatively connected to the third terminal and to the first auxiliary HEMT gate connection terminal, and the voltage limiter can be used to limit the voltage between the first gate terminal and the third terminal; and

[0075] A second auxiliary gate interface circuit, which can be used to adjust the voltage applied to the second control terminal so that the voltage applied to the second control terminal is operatively matched with the second gate terminal, the second auxiliary gate interface circuit comprising:

[0076] A second low-voltage auxiliary HEMT, comprising a second auxiliary HEMT source terminal, a second auxiliary HEMT drain terminal, and a second auxiliary HEMT gate connection terminal; and

[0077] A second voltage limiter operably connected to the gate connection of the second auxiliary HEMT.

[0078] The second auxiliary HEMT source is operatively connected to the second gate terminal.

[0079] The second auxiliary HEMT drain terminal is operatively connected to the second control terminal.

[0080] The second voltage limiter is operatively connected to the third terminal and to the second auxiliary HEMT gate connection terminal, and the voltage limiter can be used to limit the voltage between the second gate terminal and the third terminal.

[0081] In a specific embodiment, the gate connection of the transistor can be referenced to the first or second terminal (i.e., the source or drain terminal), rather than the center connection terminal (i.e., the third terminal). It should be understood that such a structure may omit the center third terminal. In such a structure, the first and second terminals of the device may each be provided with corresponding interface circuits. Accordingly, in such an embodiment, the interface circuit may include:

[0082] A first interface circuit, the first interface circuit being used to adjust a first voltage at the first gate terminal of the bidirectional power transistor; and

[0083] A second interface circuit is used to adjust the second voltage at the second gate terminal of the bidirectional power transistor.

[0084] In this structure, the first terminal can be used to provide a reference voltage to the first gate terminal, and the second terminal can be used to provide a reference voltage to the second gate terminal. Therefore, optionally, the first interface circuit includes a first Miller clamp transistor operably connected between the first gate terminal and the first terminal, and the second interface circuit includes a second Miller clamp transistor operably connected between the second gate terminal and the second terminal.

[0085] When the first and second interface circuits are configured, each interface circuit may include an auxiliary gate interface circuit. For example, the first interface circuit may include a first auxiliary gate interface circuit, which can be used to adjust the voltage applied to the first control terminal so that the voltage applied to the first control terminal is operably matched with the first gate terminal. The first auxiliary gate interface circuit includes:

[0086] A first low-voltage auxiliary HEMT, the first low-voltage auxiliary HEMT including a first auxiliary HEMT source terminal, a first auxiliary HEMT drain terminal, and a first auxiliary HEMT gate connection terminal; and

[0087] A first voltage limiter operably connected to the gate connection of the first auxiliary HEMT.

[0088] The first auxiliary HEMT source is operatively connected to the first gate terminal.

[0089] The first auxiliary HEMT drain terminal is operatively connected to the first control terminal.

[0090] The first voltage limiter is operatively connected to the first terminal and to the first auxiliary HEMT gate connection, and the voltage limiter can be used to limit the voltage between the first gate and the first terminal.

[0091] The second interface circuit may include a second auxiliary gate interface circuit, which can be used to adjust the voltage applied to the second control terminal so that the voltage applied to the second control terminal is operably matched with the second gate terminal. The second auxiliary gate interface circuit includes:

[0092] A second low-voltage auxiliary HEMT, comprising a second auxiliary HEMT source terminal, a second auxiliary HEMT drain terminal, and a second auxiliary HEMT gate connection terminal; and

[0093] A second voltage limiter operably connected to the gate connection of the second auxiliary HEMT.

[0094] The second auxiliary HEMT source is operatively connected to the second gate terminal.

[0095] The second auxiliary HEMT drain terminal is operatively connected to the second control terminal.

[0096] The second voltage limiter is operatively connected to the second terminal and to the second auxiliary HEMT gate connection, and the voltage limiter can be used to limit the voltage between the second gate terminal and the second terminal.

[0097] When a substrate is disposed, the substrate metallization layer can be operatively connected to the first or second source terminal, or floated between these two terminals. Optionally, the semiconductor device may further include: a first substrate transistor operatively connected between the substrate metallization layer and the first terminal; and a second substrate transistor operatively connected between the substrate metallization layer and the second terminal. The first and second substrate transistors can be used to selectively connect the substrate metallization layer to the first terminal and the second terminal, respectively.

[0098] In both of the above structures (one with a reference connection and one without), the interface circuit can be used to receive an external voltage rail (VDD) for operation of the integrated sensing, protection, and regulation circuitry within the interface circuit. Alternatively, the interface circuit may include a startup circuit for generating an external voltage rail (VDD) for operation of the integrated sensing, protection, and regulation circuitry within the interface circuit, based on the control connection or the high-voltage connection (or both). For example, the externally applied VDD voltage level can be 8–20V, while the regulated maximum voltage level for internal use in the semiconductor device can be 7V.

[0099] In either of the above scenarios, the interface circuit may optionally include a regulating circuit for adjusting the control connection voltage for the first and second gate terminals. For example, the regulating circuit may be used to reduce the input voltage (e.g., 0–20V) of either control connection terminal to an internal voltage level (e.g., 0–7V) acceptable to the gate (e.g., p-type GaN gate) of the bidirectional transistor.

[0100] When multiple interface circuits are set up, these interface circuits may include the same voltage rail, or they may each include their own voltage rail.

[0101] The semiconductor device may include additional terminals (such as a fourth connection terminal) for reporting a fault signal when the interface circuit detects one or more of (i) a short-circuit event, (ii) an overcurrent event, and / or (iii) an overtemperature event.

[0102] According to a second aspect of the present invention, an inverter is provided, which includes at least one of the semiconductor devices described in the first aspect. This inverter can be used in a range of applications, including but not limited to electric vehicles (EVs), electric motors, data centers, etc.

[0103] Accordingly, an electric vehicle may be provided, comprising: at least one semiconductor device of the first aspect described above; and / or an electric motor comprising at least one semiconductor device of the first aspect described above. Attached Figure Description

[0104] The contents of this disclosure can be more fully understood with reference to the accompanying drawings. The drawings are for illustrative and understanding purposes only and should not be construed as limiting this disclosure to the specific embodiments shown.

[0105] Figure 1 The image shows an example of a bidirectional switch.

[0106] Figure 2 The image shows another example of a bidirectional switch.

[0107] Figure 3 The image shows another example of a bidirectional switch.

[0108] Figure 4 The figure shows an example current flowing through a bidirectional switch with a center reference connection.

[0109] Figure 5 The figure shows an example current flowing through a discrete bidirectional switch.

[0110] Figure 6 Here is a top view of an example bidirectional switch.

[0111] Figure 7This is a top view illustrating another example of a bidirectional switch.

[0112] Figure 8 The example shown is a bidirectional switch with an integrated sensing / protection / regulation interface.

[0113] Figure 9 This is an example circuit diagram of a bidirectional switch with an integrated sensing / protection / regulation interface.

[0114] Figure 10 The diagram shows an example bidirectional switch employing an exemplary integrated sensing / protection / regulation interface structure.

[0115] Figure 11 The example shown is a bidirectional switch employing another exemplary integrated sensing / protection / regulation interface structure.

[0116] Figure 12 The example shown is a bidirectional switch employing yet another example of an integrated sensing / protection / regulation interface structure.

[0117] Figure 13 The example shown is a bidirectional switch employing yet another example of an integrated sensing / protection / regulation interface structure.

[0118] Figure 14 The diagram shows the bidirectional transistor output characteristics in the first operating mode.

[0119] Figure 15 The diagram shows the bidirectional transistor output characteristics in the second operating mode.

[0120] Figure 16 The diagram shows a bidirectional transistor in the third operating mode.

[0121] Figure 17 The diagram shows the bidirectional transistor output characteristics in the third operating mode.

[0122] Figure 18 Another example circuit diagram of a bidirectional switch with an integrated sensing / protection / regulation interface.

[0123] Figure 19 This is a circuit diagram of an integrated sensing / protection / regulation interface with fault detection functionality.

[0124] Figure 20 The diagram shows an example of a bidirectional switch without a central reference connection, which has an example of an integrated sensing / protection / regulation interface structure.

[0125] Figure 21 The diagram shows another example of a bidirectional switch without a central reference connection, which has an example of an integrated sensing / protection / regulation interface structure. Detailed Implementation

[0126] Although the gate is referred to as the third terminal in various embodiments described herein, it should be understood that the gate may also be referred to directly as the first terminal and the second terminal, respectively. It should be understood that in each embodiment described herein, the connection terminal referred to as the source or source end may be replaced with the drain or drain end, and vice versa.

[0127] Figure 1 The diagram illustrates one embodiment of a bidirectional switch 101, which includes an enhancement-mode III-V high electron mobility transistor (HEMT) switch. The HEMT switch includes a first gate terminal (G1), a second gate terminal (G2), a first terminal (T1) serving as either a source or a drain, and a second terminal (T2) serving as either a drain or a source, all disposed on the same (common) substrate 4. The first and second terminals are separated from each other along a first dimension. The enhancement-mode HEMT switch also includes a third terminal T3 (also referred to as a "middle connection" or "center connection") disposed between the two gates. Connections T1 and T2 can serve as source and drain, or drain and source, respectively, depending on the polarity of the bias voltage applied to these terminals. The third terminal T3 provides a reference voltage to the gate connections G1 and G2. T3 does not serve as a source-drain structure for electrodes; therefore, the steady-state current flowing through T3 is almost zero.

[0128] In switch 101, substrate 4 is connected to the third terminal T3, for example, via a back substrate connection or a metallization layer. Alternatively, substrate 4 may have no metallization layer on its back side and may not be connected to the substrate connection. Substrate 4 may comprise, or be made of, any suitable dielectric, insulating, or semi-insulating material. Suitable substrate materials may include, for example, but are not limited to, silicon, sapphire, diamond, quartz, gallium nitride (GaN), silicon carbide (SiC), and / or semi-insulating silicon carbide.

[0129] A heterojunction is formed at the interface between AlGaN layer 1 and GaN layer 2 above substrate 4, thereby realizing a high-electron-density two-dimensional carrier gas (2DEG). Optionally, a transition layer may be provided between substrate 4 and heterojunction layers 1 and 2.

[0130] HEMT switch 101 may include multiple finger-like structures or segments of first terminals and second terminals T1, T2. The finger-like structures of the first and second terminals can be arranged such that the terminals are alternately arranged along a first dimension or a second dimension perpendicular to the first dimension, like interlacing ten fingers.

[0131] In one embodiment, connection T3 may include a Schottky contact. This Schottky contact may resemble the Schottky gate structure commonly used in depletion-type HEMTs. The Schottky contact can provide a precise reference voltage for the gate connections G1 and G2, and can minimize the leakage current of connection T3 (in some embodiments, make the leakage current almost zero). In another embodiment, one or more of connections T1, T2, and T3 may include ohmic contacts.

[0132] Figure 2 The diagram shows a second exemplary embodiment of the bidirectional switch 101a. Switch 101a and... Figure 1 Similar to switch 101, but in switch 101a, the connection terminal T3 includes a gate contact similar to the structure of gates G1 and G2. In one embodiment, the gate contact may include a p-type GaN layer.

[0133] It should be understood that in all the above embodiments, the function of the connection terminal T3 is to serve as a reference connection terminal to bias the gate connection terminal or otherwise provide a reference voltage to the gate connection terminal. This third terminal is not used as a source / drain structure for charge carriers (electrons).

[0134] Figure 3 The diagram shows a bidirectional switch 101b. Switch 101b and... Figure 1 The switch 101 shown is similar, but in switch 101b, a single common field plate (preferably connected to T3) is provided above G1 and G2 to protect the two gate connection terminals (G1 and G2). It should be understood that, as an additional or alternative, a common field plate may also be provided for connection terminals T1 and / or T2.

[0135] Figure 4 The diagram illustrates an example current path 300 within a device such as switch 101. Assuming the voltage T2 is higher than the voltage T1, and both gates (G1, G2) are conducting, current flows from the first terminal (T1) through the metallization layer of terminal T1, the continuous 2DEG, and the metallization layer of the second terminal (T2) to the second terminal T2. For this current flow, the first terminal T1 serves as the source terminal, and the second terminal T2 serves as the drain terminal. It should be understood that since switch 101 is a bidirectional switch, current 300 can also flow in the reverse direction, i.e., from terminal T2 to terminal T1 (that is, the voltage of T1 is higher than the voltage of T2). In this reverse flow case, the first terminal T1 is used as the drain terminal instead, and the second terminal T2 serves as the source terminal. Therefore, it should be understood that T1 and T2 can be interchanged as source / drain terminals depending on the direction of the current flowing through the switch. It should also be understood that all other embodiments described herein are the same.

[0136] A very small part of the above current can also flow longitudinally through the third terminal T3, but almost no current (ideally, no current at all) flows vertically through the metallization layer of the connection terminal T3. That is to say, the connection terminal T3 is not used to conduct current, but only to set the reference potential of the first and second gate terminals (G1 and G2). Therefore, the connection terminal T3 can be used as a reference connection terminal to bias the gate connection terminal or otherwise provide a reference voltage for the gate connection terminal.

[0137] In the illustrated embodiment, the substrate 4 is connected to the connection terminal T3 via a backside metallization layer. Since no current flows vertically through the metallization layer of the connection terminal T3, the length (B) of the connection terminal T3 can be much smaller than the length (A) of the connection terminal T1 or T2. For example, the length A of each connection terminal T1, T2 can be 5 - 10 μm, while the length B of the connection terminal T3 can be 1 - 2 μm. More generally, as long as B << A, B and A can be of any size. For example, the metallization area of the connection terminal T3 can be at least 5 times smaller than the metallization area of either of the connection terminals T1 / T2.

[0138] Figure 5 An exemplary substrate segmentation structure of an existing bidirectional switch 400 is shown. The switch 400 includes two back-to-back HEMTs, and these two HEMTs include first and second source terminals (S1 and S2) separated from each other, and can be formed on separated substrate layers or have different active regions (with different 2DEG layers). The current path 402 from the connection terminal D1 to the connection terminal D2 is shown in the figure.

[0139] This discrete approach implements a scheme to simply form a bidirectional switch, for example, by connecting two existing transistors back-to-back. However, compared with the switch 101, the current path 402 of this structure is more tortuous, resulting in a larger on-resistance. The current path 402 flows through the metallization layer of the connection terminal D1, the 2DEG between D1 and the first source terminal (S1), the metallization layer of S1, the electrical connection structure between S1 and the second source terminal (S2), the metallization layer of the connection terminal S2, and the 2DEG formed between S2 and D2. That is to say, different from the current path 300, current flows vertically through the metallization layer of the connection terminal S1 and returns to the 2DEG by flowing vertically through the metallization layer of the connection terminal S2. Therefore, in order to reduce the resistance variation in the current path and facilitate the flow of current, it is necessary to enlarge the metallization areas of the source terminal and the drain terminal to similar sizes. For this reason, compared with Figure 1 switches such as the illustrated switch that use a common substrate, the discrete approach adopted by the switch 400 will result in an increase in size and / or an increase in on-resistance.

[0140] Figure 6 and Figure 7 is a top view of the bidirectional switch of the present disclosure. As Figure 6and Figure 7 As shown, optionally, the third terminal T3 may include a series of regions, finger structures, or island structures. Such island structures are spaced apart from each other along a second dimension perpendicular to the direction (i.e., the first dimension) that separates the connecting terminals T1 / T2 from each other.

[0141] exist Figure 6 In this structure, gate connection terminals G1 and G2 are continuous structures surrounding multiple island-shaped structures on the outside of connection terminal T3. For example... Figure 6 As shown, T1 and T2 are separated from each other along the first dimension, and G1 and G2 are also separated from each other along the first dimension.

[0142] exist Figure 7 In the middle, the gate connection terminals G1 and G2 intersect each other around the island-shaped structure of the connection terminal T3.

[0143] As an additional or alternative solution, connection terminal T3 can be formed as multiple island-shaped structures located at the center of the bidirectional switch, and its length is perpendicular to the lengths of connection terminals T1 and T2. That is, the third terminal and / or the third terminal island-shaped structure can extend along a third dimension perpendicular to the first and second dimensions. For example, as... Figure 6 and Figure 7 As shown, the first and second terminals may extend along a second dimension such that their maximum length dimension is located in this second dimension. In contrast, the third terminal and / or the third terminal island structure may extend "downward" into the surface of the bidirectional switch, or extend "upward" away from the surface of the bidirectional switch, such that the maximum length dimension of the third terminal and / or the third terminal island structure is located in this third dimension.

[0144] It should be understood that in other embodiments of the switch disclosed herein, the connection terminal T3 may include a single (continuous) region, rather than multiple island-like structures or regions separated from each other.

[0145] Figure 8 The illustration shows an example power integrated circuit (IC) 100 according to an embodiment of this disclosure. This power IC 100 can be a GaN power IC and may be referred to as a semiconductor device. The power IC 100 includes a high-voltage lateral bidirectional transistor (such as a III-V group HEMT, also referred to as a "power HEMT" or "bidirectional HEMT"), which includes two terminals T1 and T2 (also referred to as "first terminals and second terminals"), two external gate electrodes C1 and C2 (also referred to as "first and second external control terminals"), and a single reference electrode T3 (also referred to as "third terminal," "intermediate terminal," or "center terminal").

[0146] In this illustrated power IC 100, the bidirectional transistor is shown as a bidirectional switch 101. However, as an alternative, other suitable bidirectional transistors, such as switches 101a or 101b, may also be used. Furthermore, it should be understood that all other embodiments described herein are the same. It should also be understood that, depending on the direction of current flow through the bidirectional switch 101, the first and second terminals may be interchangeably used as drain or source terminals.

[0147] The sensing / protection / regulation interface circuit (200) connects external gate or control electrodes C1, C2 to the internal gate connection terminals G1, G2 of switch 101. This sensing / protection / regulation interface can be monolithically integrated with transistor 101. In a specific embodiment, the substrate connection terminal can be operatively connected to the third terminal T3 either internally (i.e., within the package) or externally (i.e., outside the package).

[0148] One or both of the internal gate connections G1 and G2 may include a p-type GaN region. The HEMT switch includes a substrate 4 and, depending on the material of the substrate 4, may further include one or more transition layers or nucleation layers 3. The substrate 4 may, for example, include silicon or silicon carbide. While most embodiments described herein employ a silicon substrate, it should be understood that this disclosure is equally applicable to other semiconductor and / or substrate materials.

[0149] like Figure 8 As shown, optionally, the HEMT switch may include a substrate metallization layer or a connection terminal formed on the back substrate 4.

[0150] exist Figure 8 In this embodiment, a region 1 containing an aluminum III-V semiconductor material (such as AlGaN) is formed on the GaN layer 2 to create a heterostructure at the interface of the two layers, thereby forming a two-dimensional electron gas (2DEG) at the interface. This 2DEG can help direct current along the desired current path, such as... Figure 4 The current flows along the path shown.

[0151] The sensing / protection / regulation interface 200 of the GaN power IC may contain (e.g., through monolithic integration) other devices and / or circuits, such as Miller-clamped HEMTs (pull-down transistors), voltage regulators, current sources, current-sensing HEMTs, sense load resistors, slew rate control circuits, dV / dt control circuits, drive circuits, logic circuits, short-circuit detection and protection circuits, overcurrent / overtemperature protection circuits, voltage clamping circuits, startup devices / circuits, electrostatic discharge (ESD) devices or circuits, capacitors, resistors, and diodes (e.g., Schottky diodes, or diodes formed by connecting the gate of an HEMT transistor to one of its other terminals (source or drain)). Suitable embodiments of such circuits / devices, their uses, and advantages are found, for example, in US2020 / 0168599, US2020 / 0357909, US10818786, US2021 / 0335781, and US2023 / 0131602, the contents of which are incorporated herein by reference.

[0152] In a specific implementation, the sensing / protection / regulation interface 200 is an active circuit that includes at least one actively switching element such as a transistor.

[0153] Figure 9 for Figure 8 The diagram shows an equivalent circuit of a power IC such as the power IC 100. This power IC can be represented as a single high-voltage switch with two connection terminals (T1, T2) and two control connection terminals (C1, C2). Optionally, other connection terminals may be provided, such as a DC low-voltage rail connection terminal (VDD), a short-circuit detection connection terminal, a Kelvin reference (K) connection terminal, and / or a current sensing connection terminal. The Kelvin reference terminal may be connected to a third terminal (T3) and / or a substrate connection terminal (not shown). The K connection terminal may be configured not to conduct current in the on-state (or the current in the on-state may be negligible), but instead serve as a reference voltage terminal for biasing the control connection terminals C1 and C2. For example, V G1 -V K It can be used as the gate-source potential drop of the 2DEG portion below the (p-type GaN) gate G1, V G2 -V K It can be used as the gate-source potential drop of the 2DEG portion below the (p-type GaN) gate G2, where V G1 and V G2 To provide control signals to the connection terminals G1 / G2 respectively, V K This refers to the voltage at the Kelvin reference terminal or the voltage applied to this connection. Furthermore, it should be understood that the Kelvin reference terminal can conduct current for a short period during a transient signal process.

[0154] The two external gate electrodes C1 and C2 can be driven by a single multi-output driver through two independent control signals, or they can be controlled by gate drivers that are independent of each other, wherein each gate driver provides a control signal to one of the gates.

[0155] Figure 8 and Figure 9 Each of the embodiments shown can benefit from a shared module for controlling, sensing, and protecting the two gate connections G1 and G2. For example, the two internal gate connections can share a regulation circuit, and / or any short-circuit protection circuit can include components shared by the two gate connections.

[0156] Figure 10 The diagram illustrates a power IC 700 with an exemplary sensing / protection / regulation interface. This sensing / protection / regulation interface includes: two Miller-clamped transistors (lower-down HEMTs) 202a and 202b, one for each internal gate; two logic circuits 201a and 201b driving the respective Miller-clamped transistors; and a common voltage regulator providing voltage to internal circuitry such as the logic circuitry supplying voltage to internal gates G1 and G2. Some or all of these components can be monolithically integrated with a bidirectional HEMT 101. Alternatively, some or all of the components of the sensing / protection / regulation interface can be part of a separate chip (such as a matching silicon chip or driver chip) or otherwise located external to the power IC 700.

[0157] Miller clamp transistors 202a and 202b can be "low-voltage" HEMTs, Group III nitride transistors, or any other suitable transistors. Each Miller clamp transistor 202a and 202b is operatively connected between its respective internal gate connection (G1, G2) and connection T3 of the bidirectional HEMT 101. The Miller clamp transistor can be a normally-on transistor or a normally-off transistor, or a combination of normally-on and normally-off elements in parallel. In other embodiments, one or both of the Miller clamp transistors 202a and 202b can be transistors as described in US11404565. Each Miller clamp transistor can be used as a pull-down device to ensure fast and safe turn-off, thereby improving the ability to resist transient voltage changes (dV / dt) and reducing or avoiding the need to turn off a corresponding side of the bidirectional HEMT 101 by applying a negative gate voltage. During a dV / dt event, the displacement current closed by the gate-drain capacitance can be drawn to terminal T3 by one of the Miller clamp transistors 202a or 202b. Even if terminal T3 (or, in the case where terminal T3 is directly connected to the Kelvin reference terminal, the Kelvin reference terminal) is configured to have no or almost no current flowing through it in steady-state operation, it can still conduct current during such transient events.

[0158] Logic circuits 201a and 201b (also referred to as Miller clamp drivers) can also be part of the interface circuitry. These logic circuits may include various components, such as logic inverters for operating the actively switching Miller clamp transistors 202a and 202b. The logic inverter may include resistors or resistive elements (such as load transistors or current sources) and enhancement-mode transistors. It should be understood that the above description is merely an illustrative structure, and other logic inverter designs may or may not be used outside of or on top of this structure.

[0159] In operation, each logic circuit 201a, 201b is operably connected to a corresponding external control connection terminal C1, C2, which is further used to receive a corresponding control signal from one or more gate drivers. When the control signal is high, the gate bias voltage of the active switching transistor in the corresponding Miller clamp transistor is low (and therefore its resistance is high), and vice versa.

[0160] like Figure 11 As shown, optionally, one or both of the logic circuits 201a and 201b can be connected to external control terminals C1 and C2 via corresponding gate interface circuits 209a and 209b, respectively. Each gate interface circuit 209a and 209b can be used to enable the logic circuit to respond to changes in the control signal before the corresponding Miller clamp transistors 202a and 202b are turned off, thereby avoiding or reducing the loss of gate current flowing from the Miller clamp transistors to the voltage reference connection.

[0161] Voltage regulator 203 is used to regulate different DC voltages supplied externally or internally to the startup circuit to a level suitable for devices and / or circuits operating with p-type GaN gates G1, G2. For example, an externally applied VDD voltage level of 9–20V can be used, while the maximum regulated voltage level for internal use by the power IC 700 can be 7V. More than one regulated level for internal use can be provided by suitable regulation circuitry 203, such as that described in U.S. Patent US11955478B2 and / or U.S. Patent Application US2023 / 0131602. In one embodiment, logic circuits 201a, 201b are supplied with the output voltage of the integrated regulation circuitry 203. Furthermore, the outputs of gate interface circuits 209a, 209b can be used as inputs to logic circuits 201a, 201b to limit the voltage supplied at the control connection to a level optimal for the integrated GaN HEMT contained within the logic circuitry.

[0162] Figure 12The diagram shows a power IC 900 employing another exemplary sensing / protection / regulation interface structure. This sensing / protection / regulation interface includes two auxiliary GaN HEMTs 204a and 204b, and two voltage limiting circuits 206a and 206b respectively connected to the gate terminals of the respective auxiliary GaN HEMTs 204a and 204b. Consistent with the power IC 700, this interface further includes: two Miller clamp transistors (lower-down HEMTs) 202a and 202b, one for each internal gate G1 and G2; two logic circuits 201a and 201b for driving the respective Miller clamp transistors; and a common voltage regulator 203 for providing voltage to the voltage limiting circuits, logic circuits, and other internal circuitry of the two internal gates G1 and G2. Some or all components and circuitry of this sensing / protection / regulation interface can be monolithically integrated with a bidirectional HEMT 101 to reduce parasitic effects, facilitate manufacturing, and achieve faster response times. As an alternative, part or all of this interface can be integrated into a standalone chip (such as a matching silicon chip or driver chip). The combination of auxiliary GaN HEMTs 204a, 204b and voltage limiters 206a, 206b can be referred to as an auxiliary gate interface or gate interface, and can be configured according to... Figure 11 The gate interface circuits 209a / 209b shown operate in a similar manner. It should be understood that the gate interface module may further include other circuitry or components.

[0163] Each auxiliary GaN HEMT 204a, 204b can be a low-voltage device. The corresponding gates G1, G2 of the high-voltage bidirectional HEMT 101 are connected to the source of the integrated auxiliary GaN HEMT 204a, 204b, while the drains of the auxiliary GaN HEMT 204a, 204b are connected to the corresponding control terminals of the (GaN) power IC 900 (e.g., via external gate electrodes C1, C2). Each auxiliary GaN HEMT 204a, 204b is used to adjust the drive voltage of the corresponding control terminal to a voltage level suitable for the internal gates G1, G2 of the power HEMT 101. For example, the drive voltage can be between 0V and 20V at the control terminals, but can be maintained in the range of 0 to 7V at the gate terminals G1, G2 of the high-voltage bidirectional HEMT 101. Alternatively, a diode, resistor, or a parallel combination of both may be connected in parallel with one or both of the auxiliary GaN HEMTs to serve as a pull-down network during the turn-off process of the entire structure, thereby connecting the gate connection of the active portion of the bidirectional HEMT 101 to ground.

[0164] Integrated voltage limiters 206a / 206b can be connected to the corresponding external control terminals C1 and C2, the gate terminals of auxiliary HEMTs 204a and 204b, and the connection terminal T3 of the power IC 900, respectively. Thus, when the voltage signal at the corresponding control terminal increases linearly, the voltage drop across the corresponding auxiliary GaN HEMT becomes non-linear. By limiting the potential at the corresponding gate terminals G1 and G2 of the bidirectional HEMT 101, a smaller gate leakage current can be achieved in this high-voltage bidirectional HEMT 101. This is achieved thanks to the voltage drop generated across the integrated auxiliary gate interface module. The potential limit at the internal gate terminal can be determined as follows: the voltage limiting circuit modules 206a and 206b are designed so that the gates of the auxiliary GaN HEMTs 204a and 204b are pulled down when the gate signal at the control terminal of the power IC 900 rises above a threshold level. In this way, compared with existing GaN HEMTs, the gate voltage operating window of the power IC 900 (i.e., the voltage operating window applied to the control connection terminal) can be increased.

[0165] In one embodiment, each voltage limiting module 206a, 206b may consist of: two resistors constituting a voltage divider; and an actively switching low-voltage enhancement-mode transistor. The drain-source path of the actively switching low-voltage enhancement-mode transistor may be connected between the corresponding internal gate and T3 of the bidirectional HEMT. The voltage divider may be connected between the corresponding control connection (auxiliary GaN HEMT drain (gate)) and the connection terminal T3 of the bidirectional HEMT. The midpoint of the voltage divider may be connected to the gate connection of the low-voltage enhancement-mode transistor. The enhancement-mode transistor may turn on when the voltage at the corresponding control connection rises above a specific value (threshold) to adjust the resistance between the internal gate connection and connection terminal T3. The specific value (threshold) may be controlled by selecting the resistors in the voltage divider. This function provides overvoltage protection for the internal gate connection. Various other suitable voltage limiter implementations are described in US Patent US11257811B2.

[0166] As an alternative or additional solution, a current source or resistor can be connected between the external gate connection terminals C1 and C2 and the gate of the auxiliary HEMT 204a / 204b.

[0167] Each voltage limiter 206a, 206b can be biased by an external control signal from the respective gate connection terminals C1, C2. Alternatively, the voltage limiters 206a / 206b can be biased by a signal from the VDD regulator 203, for example, by a pull-down signal from the respective logic circuits 201a, 201b.

[0168] Since the auxiliary GaN HEMTs 204a and 204b can be low-voltage devices, their source and drain terminals can be interchanged when they are symmetrically formed (or formed in a similar manner). Low-voltage devices are those with a rated breakdown voltage generally below 20V and a limited current capacity (e.g., less than 100mA). However, it should be understood that the auxiliary gate interface modules 204a and 204b can also be high-power or high-voltage devices.

[0169] Figure 13 The image shows another example of a power IC 1000. The power IC 1000 is similar to... Figure 12 The power IC 900 in this embodiment differs in that it further includes a startup circuit 205. The startup circuit 205 can be used to reduce or avoid the need for an external VDD voltage to operate the interface circuit module. In this embodiment, the voltage rail required by the interface circuit module can be internally generated by the startup circuit 205 through one or more (or combinations thereof) of either a control connection (e.g., through external gate connections C1, C2) or through connections such as T1 or T2. The startup circuit 205 may include one or more of a voltage regulator, a voltage limiter, a capacitor, a depletion-type transistor, a transfer transistor, and / or a diode. Depending on the voltage rail generated by the startup circuit, one or more diodes among 2051, 2052, 2053, and 2054 may be used. For example, if the voltage rail is generated through connection T1, diode 2051 may be used. For simplicity and clarity, Figure 13 The voltage limiting modules corresponding to the voltage limiters 206a and 206b of the power IC 900 are not shown in the diagram; however, it should be understood that the corresponding voltage limiting circuits can be selectively configured.

[0170] All the power ICs described above can have various operating modes, depending on the potentials of the first and second terminals (T1, T2) and the first and second gate terminals (G1, G2) of the high-voltage bidirectional HEMT 101.

[0171] Figure 14 The diagram illustrates the bidirectional transistor output characteristics in the first operating mode when both internal gate connections G1 and G2 are in the ON (high) state. In this case, a 2DEG is formed below both gates, and the current flow direction depends on the relative potentials of the first and second terminals T1 and T2. For example, if the voltage V1 of the first terminal is higher than the voltage V2 of the second terminal, the current flows from the first terminal T1 to the second terminal T2; conversely, the current flows from the first terminal T1 to the second terminal T2.

[0172] Figure 15The diagram shows the output characteristics of a bidirectional HEMT in the first operating mode, where both internal gate connections G1 and G2 are in the off (low) state. This mode corresponds to the case where both internal gates have the same potential as connection T3 or are grounded by their respective Miller clamp transistors. In this case, no current is conducted in either part of the bidirectional HEMT except for possible (minor) leakage current. When the voltage at either the first or second terminal T1, T2 is higher than the device's breakdown voltage (V... BR When this occurs, the bidirectional HEMT can enter a breakdown mode that conducts a large amount of current. For example, for a device with a rated voltage of 650V, the breakdown voltage range can be 800V to 1.2kV.

[0173] Figure 16 The diagram illustrates the third operating mode of a bidirectional HEMT, where the voltage at the first terminal T1 is higher than the voltage at the second terminal T2, with the difference exceeding the threshold voltage. For example, if the threshold voltage of the transistor is 1.5V and the voltage V2 at the second terminal is xV, then the voltage V1 at the first terminal is higher than x+1.5V. In this case, if the bias drive voltage at the first gate terminal G1 is higher than the connection terminal T3 (e.g., 7V), a 2DEG is formed below G2 in the first part of the bidirectional HEMT, ensuring conduction. Simultaneously, if the second gate terminal G2 is connected to the connection terminal T3, or pulled down by a Miller-clamped transistor, the second part of the bidirectional HEMT operates as a diode because the potential of T1 is higher than T2. ​​Thus, for example... Figure 16 As shown, current flows from T1 to T2 within the device. When V2 > V1, the device operates similarly to the above, but G2 is in the on state and G1 is in the off state. The output characteristics in this mode are as follows. Figure 17 As shown.

[0174] However, when the voltage V1 at the first terminal is higher than the voltage V2 at the second terminal, the first gate G1 is in the off state and the second gate G2 is in the on state, thus preventing the bidirectional HEMT from conducting current. In this case, since G1 is in the off state, the first part of the HEMT is turned off, and G2 blocks the current from T1.

[0175] It should be understood that this power IC can also be used to operate under static or dynamic conditions in other modes besides those described above.

[0176] Figure 18 For another power IC (such as Figure 8The diagram shows the equivalent circuit of the power IC 100. For many topologies using bidirectional switches, such as three-level neutral-point clamped (NPC) topologies for inverters or solid-state circuit breakers (SSCBs), short-circuit protection and / or desaturation detection may be mandatory design requirements for certain applications. As mentioned above, the sensing / protection / regulation interface 200 of the GaN power IC can include (e.g., through monolithic integration) sensing and protection circuits, such as a current sensing HEMT, a load resistance sensing circuit, short-circuit detection and protection circuitry, and overcurrent / overtemperature (hot spot) detection and protection circuitry.

[0177] As an additional or alternative, the switch may include a fault-connected terminal (FLT) for implementing the DESAT function of an external driver. In automotive applications, the gate driver may be configured with a DESAT pin to provide desaturation protection. When the voltage at the DESAT pin exceeds a threshold voltage, the driver can initiate a safety shutdown procedure to protect the power semiconductor switch. The FLT connection of the bidirectional switch can be connected to the DESAT input of the gate driver.

[0178] Bidirectional switches can be operated by a single multi-output gate driver. However, existing DESAT circuits can only operate when current flows in one direction and cannot operate when current flows in the opposite direction. Therefore, existing bidirectional switches require two DESAT circuits, one for each current direction, thus requiring two sets of drivers with DESAT functionality. However, the device of this disclosure, with its sensing / protection / regulation interface, can internally detect the saturation state of any part of the bidirectional HEMT and logically combine fault signals independent of the current direction or specific part of the device, thereby enabling a single DESAT circuit to be used simultaneously for both current directions. However, it should be understood that gate drivers can also be provided for each device gate G1, G2 as needed, and in such embodiments, each gate driver or each set of gate drivers can have its own corresponding DESAT circuit.

[0179] The sensing / protection / regulation interface 200 of the GaN power IC disclosed herein may include a short-circuit detection and protection mechanism or circuitry, such as that described in U.S. Patent Application No. 18 / 394141. In such embodiments, the drain-source voltages of the two terminals T1 and T2 may be sensed, and the combination of these two signals may be processed to generate a short-circuit detection signal (SCD), which may be output from the faulty terminal.

[0180] In one embodiment, the short-circuit detection circuit within the sensing / protection / regulation interface 200 may include: a voltage detection circuit for detecting the voltage between the first and second terminals T1 and T2 relative to the connection terminal T3 and comparing it with a reference voltage; the voltage detection circuit is also used to output a high-voltage detection signal when the voltage between either the first or second terminal and the connection terminal T3 is higher than the reference voltage; and a blanking time circuit for outputting a blanking time signal after the blanking time period ends. The short-circuit detection circuit can be used to send a short-circuit detection signal based on the high-voltage detection signal and the blanking time signal (e.g., a combination of the high-voltage detection signal and the blanking time signal). For example, the short-circuit detection circuit may further include a logic combination circuit for: receiving the high-voltage detection signal and the blanking time signal; and outputting a short-circuit detection signal based on the combination of the high-voltage detection signal and the blanking time signal. The short-circuit detection signal may be output from the FLT connection terminal. In one exemplary embodiment, the short-circuit detection signal may be received internally by a Miller clamp transistor within the sensing / protection / regulation interface 200 to turn on the Miller clamp transistor and pull down the gate voltage at the internal gate connection. Alternatively, the short-circuit detection signal may be received by a gate interface circuit within the sensing / protection / regulation interface 200. This gate interface circuit can be used, upon receiving the short-circuit detection signal, to cause a voltage limiter to limit the voltage between the corresponding gate connection and connection T3, for example, to a lower gate voltage than during normal operation. For example, the gate interface circuit can cause the voltage limiter to reduce the voltage between the corresponding gate connection and connection T3.

[0181] As an alternative, a hotspot-based short-circuit detection method, as described in U.S. Patent Application No. 18 / 394078, can be used to generate a short-circuit detection signal (SCD) to be output from the faulty connection. The sensing / protection / regulation interface 200 may include hotspot detection circuitry and protection circuitry. The hotspot detection circuitry includes a temperature sensor (or temperature sensing device) for sensing the local temperature of the bidirectional HEMT. Upon detecting a rise in the local temperature of the bidirectional HEMT, the hotspot detection circuitry sends a hotspot detection signal to the FLT pin and further to the protection circuitry. Upon receiving the hotspot detection signal, the protection circuitry reduces the current between connection T3 and connections T1, T2, and / or the protection circuitry may indirectly act on and / or shut down the bidirectional HEMT through one or more other components, circuits, or devices within the sensing / protection / regulation interface 200.

[0182] Thus, as Figure 19As shown, a single FLT pin can be directly connected to the DESAT pin on an external gate driver and report short-circuit / overcurrent / overtemperature events. In some embodiments, the FLT can be actively grounded when the switch is operating normally. Conversely, in the event of a fault, the FLT pin can be floated (e.g., via an external pull-up resistor and a current source from the DESAT pin) or actively pulled high to trigger a DESAT fault on the gate driver. The driver can then shut down the bidirectional HEMT or control the gate voltage at the control connection to drive the switch according to its specific condition.

[0183] Such implementations of semiconductor devices are particularly well-suited for applications requiring such fault detection and / or DESAT functionality, such as bidirectional switches used in automobiles (e.g., electric vehicles (EVs)).

[0184] As an alternative, the semiconductor device may have more than one FLT connection. For example, two FLT connections may be provided to independently report short-circuit / overcurrent / overtemperature events of either part of the bidirectional HEMT, and subsequently control the corresponding gate voltage to perform the corresponding drive operation on the switch.

[0185] Alternatively, fault reporting can be achieved via the FLT connection even when the gate driver used to drive the switch does not have a DESAT pin. The FLT output can be connected to the general-purpose input / output interface of a controller (or signal processor or digital signal processor (DSP)) that operates the gate driver. When a fault event is reported to the controller via the FLT output, the controller can instruct the gate driver to control the drive voltage at the bidirectional switch control connection. Optionally, the fault report can be sent to the controller via a digital isolator or any other interface circuitry required by the controller to isolate the fault signal from normal operation of the gate driver.

[0186] As an additional or alternative, the sensing / protection / regulation interface 200 may include a feedback circuit. This feedback circuit may include at least one output operatively connected to a driver feedback input. The feedback circuit can be used to provide a feedback signal to the driver feedback input, the feedback signal corresponding to the state of the semiconductor switch. For example, the feedback signal may correspond to current, voltage, and / or temperature within the semiconductor switch sensed by the sensing circuit within the sensing / protection / regulation interface. The driver can be used to adjust the drive voltage level, the frequency of the drive voltage level, the slew rate, and / or the timing of the drive voltage level based on the feedback signal.

[0187] Figure 20The following is another example of a power IC 1300. In the power IC 1300, the bidirectional HEMT 102 employs a second structure. In this second structure, the bidirectional switch does not require a central (shared) third terminal between the two internal gates G1, G2. Instead, each of the first and second terminals T1, T2 can be used as a reference voltage for its respective internal gate.

[0188] In this embodiment, the semiconductor device 1300 (also referred to as a (GaN) power IC) includes a high-voltage lateral bidirectional transistor 102 (such as a III-V group HEMT, also referred to as a "power HEMT" or "bidirectional HEMT"). The high-voltage lateral bidirectional transistor 102 includes: two main electrodes T1 and T2 (also referred to as "first terminals and second terminals"); and two external gate electrodes C1 and C2 (also referred to as "control connection terminals"). The current can be directed according to... Figure 4 The current 300 flows in a similar manner between the device's connection terminals T1 and T2. Therefore, it should be understood that each connection terminal T1 and T2 can serve as either a source or a drain terminal, depending on the direction of current flow through the bidirectional switch 102.

[0189] In addition, two sensing / protection / regulation interfaces (200a, 200b) are provided, one for each of the connection terminals T1 and T2. These two interface circuits are respectively connected to the external gate electrode, the internal gates G1 and G2, and between the first and second electrodes / connection terminals T1 and T2. The sensing / protection / regulation interfaces can be at least partially integrated with transistor 102 monolithically.

[0190] Each interface 200a, 200b may include any one of the interfaces 200 described in the above embodiments, and is referred to herein as logic / protection / regulation modules 207a, 207b, respectively.

[0191] Although substrate 4 is shown in the figure as having a back metallization layer, it should be understood that substrate 4 may have no metallization layer on the back and may not be connected to the substrate connection terminal. Substrate 4 may include, or be made of, any suitable dielectric, insulating, or semi-insulating material. Substrate materials may include, for example, but are not limited to, silicon, sapphire, diamond, quartz, gallium nitride, silicon carbide, or semi-insulating silicon carbide.

[0192] Optionally, such as Figure 21As shown, the power IC 1300 may include high-voltage low-power transistors 208a and 208b, which are operatively connected between the substrate connection and corresponding connection terminals T1 and T2, respectively, to achieve selective connection between the substrate connection and the corresponding connection terminals T1 and T2 of the power device when operating as a source. This makes it easier to adjust the substrate potential to the source potential (such as ground potential), or a threshold voltage higher than ground potential, or a low voltage (compared to the drain voltage when the corresponding side of the power device is in the on state). Furthermore, transistors 208a and 208b can help selectively disconnect (or operatively disconnect) the substrate potential from the corresponding source when the corresponding power device is in the off state, thereby reducing leakage current through the substrate connection in the off state.

[0193] Transistors 208a and 208b, connected to terminals T1 and T2 respectively, can be driven by their respective gate signals or by other drive signals. One or both of transistors 208a and 208b can be monolithically integrated with the bidirectional HEMT 102. In a specific embodiment, each finger structure of each transistor 208a and 208b can form a low-power device. Effective isolation of the substrate from ground further reduces leakage current between the drain and the substrate, thereby improving the breakdown voltage.

[0194] As an alternative, transistors 208a / 208b can be connected to 2DEG or any other layer within the bidirectional HEMT 102 stack to facilitate top-side processing.

[0195] Those skilled in the art will understand that directional terms such as "top," "back," and "upper" in the foregoing and appended claims refer to conceptual illustrations and the accompanying drawings. The use of such terms is for convenience only and is not intended to be restrictive. Therefore, these terms should be understood in conjunction with the positions of the components shown in the accompanying diagrams.

[0196] While this disclosure has been described above in conjunction with preferred embodiments, it should be understood that these embodiments are illustrative only, and the claims are not limited to such embodiments. For example, the circuits or modules described in conjunction with specific interface circuits may also be incorporated into other interface circuit embodiments. Those skilled in the art should be able to make modifications and substitutions based on this disclosure, but such modifications and substitutions should all be considered to fall within the scope of the appended claims. Each technical feature disclosed or described in this specification may be incorporated into this disclosure either alone or in combination with any other technical feature disclosed or described herein in any suitable manner.

[0197] For those skilled in the art, there are many other effective alternatives. It should be understood that this disclosure is not limited to the above-described embodiments, but covers all modifications that fall within the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first control terminal for receiving a first control signal; The second control terminal is used to receive the second control signal; A bidirectional power transistor, comprising a first gate terminal, a second gate terminal, a first terminal, a second terminal, and a third terminal, wherein: The first gate terminal and the second gate terminal are located between the first terminal and the second terminal. During use, the first terminal and the second terminal are used as the source terminal or the drain terminal of the bidirectional power transistor. The third terminal is located between the first gate terminal and the second gate terminal, and is operatively connected to the interface circuit and used to provide a reference voltage for the first gate terminal and the second gate terminal; and The interface circuit, wherein the interface circuit is monolithically integrated with the bidirectional power transistor and operably connected to the first control terminal, the second control terminal, the first gate terminal, and the second gate terminal, the interface circuit is an actively switchable circuit including one or more transistors, and the interface circuit is used for: Adjusting the first voltage at the first gate terminal of the bidirectional power transistor; and Adjust the second voltage at the second gate terminal of the bidirectional power transistor.

2. The semiconductor device as claimed in claim 1, characterized in that, The metallized area of ​​each of the first and second terminals is at least five times the metallized area of ​​the third terminal.

3. The semiconductor device as described in claim 1, characterized in that, The third terminal is operatively connected to a Kelvin reference terminal, and the first and second control terminals are biased relative to the Kelvin reference terminal.

4. The semiconductor device as claimed in claim 1, characterized in that, The third terminal includes a Schottky contact that contacts the two-dimensional electron gas below the third terminal.

5. The semiconductor device as claimed in claim 1, characterized in that, The third terminal includes an ohmic contact that contacts the two-dimensional electron gas below the third terminal.

6. The semiconductor device as claimed in claim 1, characterized in that, The third terminal is formed by a metal layer located above the p-type GaN layer.

7. The semiconductor device as claimed in claim 1, characterized in that, The bidirectional power transistor includes a substrate and a substrate metallization layer, the substrate metallization layer being operatively connected to the third terminal.

8. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device is configured such that the steady-state current flowing through the third terminal is zero or approximately zero, while the transient or displacement current flowing through the third terminal, which is proportional to the rate of change of the voltage of the first or second terminal with respect to time, is zero or greater than zero.

9. The semiconductor device as claimed in claim 1, characterized in that, The interface circuit includes: A first Miller-clamp transistor is operatively connected between the first gate terminal and the third terminal; and The second Miller clamp transistor is operatively connected between the second gate terminal and the third terminal.

10. The semiconductor device as claimed in claim 1, characterized in that, The first terminal and the second terminal are separated from each other in a first dimension; and: At least one of the following conditions must be met: (i) The third terminal includes a plurality of third terminal regions, which are separated from each other along a second dimension perpendicular to the first dimension; (ii) The third terminal extends along a third dimension perpendicular to the first dimension and the second dimension, such that the maximum dimension of the third terminal is the third dimension.

11. The semiconductor device as claimed in claim 1, characterized in that, The interface circuit includes: A first auxiliary gate interface circuit, the first auxiliary gate interface circuit being configured to adjust the voltage applied to the first control terminal such that the voltage applied to the first control terminal is operably matched with the first gate terminal; and A second auxiliary gate interface circuit is used to adjust the voltage applied to the second control terminal so that the voltage applied to the second control terminal is operably matched with the second gate terminal.

12. A semiconductor device, characterized in that, include: A first control terminal for receiving a first control signal; The second control terminal is used to receive the second control signal; A bidirectional power transistor includes a first gate terminal, a second gate terminal, a first terminal, and a second terminal. The first gate terminal and the second gate terminal are located between the first terminal and the second terminal. During use, the first terminal and the second terminal are used as the source or drain terminals of the bidirectional power transistor. as well as An interface circuit, monolithically integrated with the bidirectional power transistor and operably connected to the first control terminal, the second control terminal, the first gate terminal, and the second gate terminal, wherein the interface circuit is an actively switchable circuit including one or more transistors, and the interface circuit includes: A first interface circuit is used to adjust the first voltage at the first gate terminal of the bidirectional power transistor; as well as The second interface circuit is used to adjust the second voltage at the second gate terminal of the bidirectional power transistor.

13. The semiconductor device as claimed in claim 12, characterized in that: The first terminal is used to provide a reference voltage to the first gate terminal; The second terminal is used to provide a reference voltage to the second gate terminal.

14. The semiconductor device as claimed in claim 12, characterized in that: The first interface circuit includes a first Miller clamp transistor operably connected between the first gate terminal and the first terminal. The second interface circuit includes a second Miller clamp transistor operatively connected between the second gate terminal and the second terminal.

15. The semiconductor device as claimed in claim 12, characterized in that, The bidirectional power transistor includes a substrate and a substrate metallization layer, the substrate metallization layer being operatively connected to at least one of the first terminal and the second terminal.

16. The semiconductor device as claimed in claim 15, characterized in that, include: A first substrate transistor is operatively connected between the substrate metallization layer and the first terminal; The second substrate transistor is operatively connected between the substrate metallization layer and the second terminal; The first substrate transistor and the second substrate transistor are respectively used to selectively connect the substrate metallization layer to the first terminal and the second terminal.

17. The semiconductor device as claimed in claim 12, characterized in that: The first interface circuit includes a first auxiliary gate interface circuit, which can be used to adjust the voltage applied to the first control terminal so that the voltage applied to the first control terminal is operably matched with the first gate terminal. The second interface circuit includes a second auxiliary gate interface circuit, which can be used to adjust the voltage applied to the second control terminal so that the voltage applied to the second control terminal is operably matched with the second gate terminal.

18. The semiconductor device according to any one of claims 1 to 17, characterized in that, The interface circuit is used to receive an external voltage rail (VDD) to provide DC voltage to the components and / or circuits constituting the interface circuit.

19. The semiconductor device as claimed in claim 18, characterized in that, It includes an adjustment circuit for adjusting the voltage provided by the voltage rail to a DC voltage suitable for driving the circuitry within the interface circuitry.

20. The semiconductor device according to any one of claims 1 to 17, characterized in that, The interface circuit includes a startup circuit for generating a voltage rail (VDD) to provide DC voltage to the components and / or circuits constituting the interface circuit.

21. The semiconductor device as claimed in claim 20, characterized in that, It includes an adjustment circuit for adjusting the voltage provided by the voltage rail to a DC voltage suitable for driving the circuitry within the interface circuitry.

22. The semiconductor device as claimed in claim 1 or 13, characterized in that, The bidirectional power transistor includes a substrate, the substrate comprising one or more of the following: silicon; Silicon carbide; sapphire; Diamond; quartz; Gallium nitride; and / or Semi-insulating silicon carbide.

23. The semiconductor device according to any one of claims 1 to 17, characterized in that, The interface circuit includes one or more of the following: Logic circuits; Inverter; Current source; Capacitor; Two-dimensional charge carrier gas or metal resistor; Voltage limiter; Voltage regulator; Level converter; Short circuit detection and protection circuit; Clamping circuit; Static discharge circuit; Current sensing transistor; Overcurrent detection circuit; and / or Over-temperature detection circuit.

24. The semiconductor device according to any one of claims 1 to 17, characterized in that, Includes additional terminals for reporting a fault signal when the interface circuit detects one or more of (i) a short-circuit event, (ii) an overcurrent event, and / or (iii) an overtemperature event.

25. The semiconductor device according to any one of claims 1 to 17, characterized in that, The bidirectional power transistor is a bidirectional III-V group high electron mobility transistor.

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