Noise shaping SAR ADC and electronic system

Abstract

The invention provides a noise shaping SAR ADC and an electronic system, the noise shaping SAR ADC adopts a comparator architecture in which a pre-comparator is cascaded with a dynamic latch, and a residual error sampling processing circuit is arranged at the rear stage of the pre-comparator, so that the pre-comparator is used as a residual error amplifier, a special residual error amplifier is omitted, a relatively large residual error sampling capacitor is not needed, and the noise shaping SAR ADC is simple in structure and low in cost. And the area is saved. Furthermore, the residual error sampling processing circuit is provided with an adjustable capacitor, so that gain change of the pre-comparator is compensated by adjusting the adjustable capacitor, and nearly ideal high-order noise shaping is realized. Besides, the residual error sampling processing circuit is provided with N (N + 1) / 2 residual error sampling capacitors, residual error sampling and residual error summation operations of the residual error sampling capacitors are controlled through a simple time sequence, N-order noise shaping can be achieved, and the method is simple and efficient. Due to the adoption of the electronic system, the performance of the electronic system is improved.

Description

Technical Field

[0001] This invention relates to the field of ADC (Analog to Digital Converter) technology, and particularly to a noise-shaping SAR ADC and electronic system. Background Technology

[0002] Analog-to-digital converters (ADCs) are common circuit modules in the field of analog integrated circuits, and their function is to convert data from analog quantities to digital quantities. Among them, the Successive Approximation Register (SAR) ADC is a common structure for medium to high resolution applications with sampling rates below 5Msps (millions of samples per second). Its resolution is generally 8 bits to 16 bits. Its main advantages are simple structure, low power consumption, small size, high precision, moderate resolution and speed, and short sampling delay. It is widely used in microcontroller units (MCUs) and systems on a chip (SOCs).

[0003] Noise-shaping SAR ADCs, as a hybrid architecture of traditional SAR ADCs and Σ(Sigma)-Δ(Delta) ADCs, combine the advantages of traditional SAR ADCs (which are simple in structure, low in power consumption, and low in resolution) and Σ-Δ ADCs (which use oversampling and noise shaping in their modulators, resulting in high resolution and high power consumption). They achieve high accuracy with relatively low power consumption and have attracted much attention in recent years.

[0004] Currently, there are two main structures for noise-shaping SAR ADCs: one is the error-feedback NS-SAR structure, and the other is the cascade integrators-feedforward structure. Regardless of the structure, the implementation of high-order noise-shaping SAR ADCs is quite complex, generally involving large residual sampling capacitors (or even multiple capacitors), active integrators or dynamic amplifiers, complex timing, and multi-input comparators, resulting in problems such as complex circuitry and large footprint.

[0005] Therefore, it is necessary to propose a new noise-shaping SAR ADC and electronic system that can achieve relatively smaller area and more efficient noise shaping. Summary of the Invention

[0006] The purpose of this invention is to provide a noise-shaping SAR ADC and electronic system that can save relatively less area and achieve efficient noise shaping.

[0007] To achieve the above objectives, the present invention provides a noise-shaping SAR ADC, which includes a digital-to-analog converter, a residual sampling processing circuit, a comparator, and a control logic circuit. The comparator includes a pre-comparator and a dynamic latch.

[0008] The input terminal of the pre-comparator is coupled to the output terminal of the digital-to-analog converter, and the output terminal of the pre-comparator is coupled to the input terminal of the dynamic latch. The residual sampling processing circuit is used to couple to the output terminal of the pre-comparator in a corresponding cycle to sample the residual of the output of the pre-comparator, and to connect to the output terminal of the digital-to-analog converter in another corresponding cycle to sum the sampled residual with the output of the digital-to-analog converter.

[0009] The pre-comparator is used to compare the residual summation result with the corresponding sampled common-mode signal, and amplify and output the comparison result.

[0010] The output of the dynamic latch is coupled to the control logic circuit and is used to latch the comparison result output by the pre-comparator.

[0011] The output of the control logic circuit is coupled to the digital-to-analog converter, which is also coupled to the input signal. The control logic circuit is used to control the digital-to-analog converter to sample the input signal according to the output of the dynamic latch.

[0012] Optionally, the residual sampling processing circuit has N(N+1) / 2 switched capacitor branches, where N≥1 and is an integer. Each switched capacitor branch is used to perform residual sampling in one cycle and to sum the obtained residual with the output of the digital-to-analog converter in another cycle to obtain a residual summation result. At least one of the one cycle and the other cycle of any two switched capacitor branches is different.

[0013] Optionally, the N(N+1) / 2 switched capacitor branches are the first to the N(N+1) / 2 switched capacitor branches. The first switched capacitor branch samples the residual in the nth period and connects to the output of the digital-to-analog converter in the (n+1)th period. When N≥2, the second switched capacitor branch samples the residual in the nth period and connects to the output of the digital-to-analog converter in the (n+2)th period. The third switched capacitor branch samples the residual in the (n+1)th period and connects to the output of the digital-to-analog converter in the (n+3)th period.

[0014] Optionally, when N≥3, the fourth switched capacitor branch samples the residual in the nth cycle and connects to the output of the digital-to-analog converter in the (n+3)th cycle, the fifth switched capacitor branch samples the residual in the (n+1)th cycle and connects to the output of the digital-to-analog converter in the (n+4)th cycle, and the sixth switched capacitor branch samples the residual in the (n+2)th cycle and connects to the output of the digital-to-analog converter in the (n+5)th cycle.

[0015] Optionally, in the 1st to N(N+1) / 2th switched capacitor branches, at least one of the switched capacitor branches has a residual sampling capacitor with a capacitance value of C. RES And at least the residual sampling capacitor of the first switched capacitor branch has a capacitance value of N*C. RES .

[0016] Optionally, when N=1, the capacitance value of the residual sampling capacitor in the first switched capacitor branch is C. RES ;

[0017] When N=2, the capacitance value of the residual sampling capacitor in the second switched capacitor branch and the third switched capacitor branch is C. RES The capacitance value of the residual sampling capacitor in the first switched capacitor branch is 2*C. RES ;

[0018] When N=3, the capacitance value of the residual sampling capacitors in the first to third switched capacitor branches is 3*C. RES The residual sampling capacitors in the fourth and sixth switched capacitor branches both have a capacitance value of C. RES .

[0019] Optionally, the pre-comparator outputs a pair of differential signals. Each switched capacitor branch includes a residual sampling capacitor and a first to a fifth switch. The first terminal of the first switch is coupled to one of the pair of differential signals, and the second terminal of the second switch is coupled to the other of the pair of differential signals. The second terminal of the first switch, the first terminal of the fifth switch, and the second terminal of the third switch are all coupled to the first plate of the residual sampling capacitor. The first terminal of the second switch, the first terminal of the fourth switch, and the second terminal of the fifth switch are all coupled to the second plate of the residual sampling capacitor. The first terminal of the third switch is coupled to a first signal, and the second terminal of the fourth switch is coupled to a second signal. The control terminals of the first and second switches are all coupled to the corresponding residual sampling clocks. The control terminals of the third and fourth switches are all coupled to the corresponding residual summation clocks. The control terminal of the fifth switch is coupled to a reset clock. One of the first and second signals is the output of the digital-to-analog converter, and the other is the sampled common-mode signal.

[0020] Optionally, the residual sampling processing circuit further includes an adjustable capacitor, one end of which is coupled to the output terminal of the digital-to-analog converter and the other end is grounded. The adjustable capacitor is used to compensate for the influence of the gain change of the pre-comparator on the noise shaping effect.

[0021] Optionally, the digital-to-analog converter is a capacitive digital-to-analog converter and includes a binary capacitor array; and / or, the noise-shaping SAR ADC further includes a sampling switch, one end of which is coupled to the input terminal of the digital-to-analog converter, and the other end is coupled to the sampling common-mode signal or the input signal, the control terminal of the sampling switch is coupled to the input sampling clock of the noise-shaping SAR ADC, and the dynamic latch is coupled to the comparison clock of the noise-shaping SAR ADC.

[0022] Optionally, the pre-comparator includes first to fourth PMOS transistors and first to second NMOS transistors. The sources of the first to fourth PMOS transistors are coupled to each other, and the sources of the first to second NMOS transistors are coupled to each other. The gate and drain of the first PMOS transistor, the drain of the second PMOS transistor, the drain of the first NMOS transistor, and the gate of the third PMOS transistor are coupled to each other to form the first output terminal of the pre-comparator. The drain of the third PMOS transistor, the gate and drain of the fourth PMOS transistor, the drain of the second NMOS transistor, and the gate of the second PMOS transistor are coupled to each other to form the second output terminal of the pre-comparator. The gate of the first NMOS transistor is the first input terminal of the pre-comparator, and the gate of the second NMOS transistor is the second input terminal of the pre-comparator.

[0023] Based on the same inventive concept, the present invention also provides an electronic system comprising the noise-shaping SAR ADC as described in the present invention.

[0024] Compared with the prior art, the technical solution of the present invention has at least one of the following technical effects:

[0025] 1. A comparator architecture with a pre-comparator cascaded with a dynamic latch is adopted, and the residual sampling processing circuit is placed after the pre-comparator. Thus, the pre-comparator is used as a residual amplifier, eliminating the need for a dedicated residual amplifier and requiring no large residual sampling capacitor, which helps to save area.

[0026] 2. The gain of the pre-comparator changes little with PVT and can be compensated for by adjusting the adjustable capacitor Ct in the residual sampling processing circuit, thus achieving near-ideal high-order noise shaping.

[0027] 3. The residual sampling processing circuit has N(N+1) / 2 residual sampling capacitors. By simply controlling the residual sampling and residual summation operations of these residual sampling capacitors, Nth-order noise shaping can be achieved. Attached Figure Description

[0028] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0029] Figure 1 This is a schematic diagram of an existing first-order noise-shaping SAR ADC that employs an error feedback structure.

[0030] Figure 2 yes Figure 1 The clock timing diagram of the first-order noise-shaping SAR ADC is shown.

[0031] Figure 3 This is a schematic diagram of the architecture of a first-order noise-shaping SAR ADC that uses a residual amplifier.

[0032] Figure 4 This is a schematic diagram of the architecture of an N-order noise-shaping SAR ADC according to an embodiment of the present invention.

[0033] Figure 5A and Figure 5B These are schematic diagrams illustrating two example structures of a digital-to-analog converter in an Nth-order noise-shaping SAR ADC according to an embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram of an example structure of the i-th capacitor branch in an N-order noise-shaping SAR ADC according to an embodiment of the present invention, where 1≤i≤N and i is an integer.

[0035] Figure 7 This is a schematic diagram of an example structure of a pre-comparator in an N-order noise-shaping SAR ADC according to an embodiment of the present invention.

[0036] Figure 8 This is a schematic diagram of the architecture of an N-order noise-shaping SAR ADC according to another embodiment of the present invention.

[0037] Figure 9 This is a schematic diagram of the architecture of a first-order noise-shaping SAR ADC according to an embodiment of the present invention.

[0038] Figure 10 yes Figure 9 The clock timing diagram of the first-order noise-shaping SAR ADC is shown.

[0039] Figure 11 This is a schematic diagram of the architecture of a second-order noise-shaping SAR ADC according to an embodiment of the present invention.

[0040] Figure 12 yes Figure 11 The clock timing diagram of the second-order noise-shaping SAR ADC is shown.

[0041] Figure 13 This is a schematic diagram of the architecture of a third-order noise-shaping SAR ADC according to an embodiment of the present invention.

[0042] Figure 14 yes Figure 13 The clock timing diagram of the third-order noise-shaping SAR ADC is shown. Detailed Implementation

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, the provision of these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0044] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0045] A simple architecture of a first-order noise-shaping SAR ADC 10 employing an error feedback structure is as follows: Figure 1 As shown, it includes a capacitive digital-to-analog converter (which provides a capacitance value C). DAC 11. Residual sampling capacitors (or even multiple capacitors) C RESThe system includes a comparator (CMP) 12 and a control logic circuit (SAR-LOGIC) 13. Here, clks is the sampling clock of the first-order noise-shaping SAR ADC, clkc is the comparison clock of the first-order noise-shaping SAR ADC, and clk_sum is the residual summation clock of the first-order noise-shaping SAR ADC. A capacitive digital-to-analog converter 11 is used to sample the input signal vin under the control of the control logic circuit 13. The residual sampling capacitor C... RES The residual is used to sample and store the voltage, and is superimposed on the output of the capacitive digital-to-analog converter 11 to generate the voltage vsump. The comparator 12 is used to compare vsump with the sampled common-mode signal vicm. The sampled common-mode signal vicm is used as the input common-mode voltage of the comparator 12 during sampling. It is, for example, the voltage output of the comparator 12 after the power supply voltage of the comparator 12 is divided by the corresponding resistor series and then passed through the internal buffer.

[0046] Please combine Figure 2 The operation of this first-order noise-shaping SAR ADC 10 includes:

[0047] After comparator 12 completes the comparison, the residual sampling capacitor C... RES Sampling residuals, and during the comparison process, C RES The capacitor-type digital-to-analog converter 11 is continuously connected, and the connection with the capacitor-type digital-to-analog converter 11 is disconnected only after the comparison is completed, thus completing the sampling of the residual.

[0048] After the residual sampling is completed, the capacitive digital-to-analog converter 11 samples the input signal vin;

[0049] Input signal V in After sampling is completed, the residual sampling capacitor C RES Connect the capacitor-type digital-to-analog converter 11, and then the comparator 12 starts to compare vsump with the sampled common-mode signal vicm;

[0050] After comparator 12 completes the comparison, C RES The residual is sampled again, and this process is repeated.

[0051] The noise transfer function (NTF) of this first-order noise-shaping SAR ADC 10 is as follows:

[0052] NTF = 1 - H(z), H(z) = z -1 C RES / (C DAC +C RES ).

[0053] Where H(z) is the discrete-time loop transfer function. Clearly, only C... RES / (C DAC +C RES Ideal first-order noise shaping can only be achieved when C = 1, even if C is required to be 1. RES / (C DAC +C RES )≈1, and C also needs to be required. RES >> CDAC Larger C RES Not only is the area large, but the attenuation of VIN is also severe, which places higher demands on the design of comparator 12. Therefore, it is necessary to explore a noise-shaping SAR ADC architecture that is more area-efficient and can achieve efficient noise shaping.

[0054] Please refer to Figure 3 One way is to Figure 1 Add a capacitor C to the base sampler. RES Coupled residual amplifier 14, assuming the gain of this residual amplifier 14 is A, then the NTF becomes:

[0055] NTF = 1 - Az -1 C RES / (C DAC +C RES ).

[0056] To achieve AC RES / (C DAC +C RES )≈1, requiring C to be present. RES =C DAC / (A-1), it can be seen that if NTF is required to be approximately equal to 1-z under PVT, then... -1 For this to be valid, the gain A of the residual amplifier 14 must be stable under PVT. This places high demands on the realization of the gain A of the residual amplifier 14. Currently, dynamic amplifiers (i.e., dynamic amplifiers) are often used. Figure 1 The comparator 12 in the scheme, that is, the residual amplifier 14 and the dynamic amplifier form the comparator in the scheme, and the adjustment method is combined to achieve this, while the adjustment of the dynamic amplifier is relatively complicated.

[0057] Based on this, please refer to Figure 4 An embodiment of the present invention provides a noise-shaping SAR ADC, which includes a digital-to-analog converter 21, a residual sampling processing circuit 24, a comparator 22 and a control logic circuit 23, wherein the comparator includes a pre-comparator 22a and a dynamic latch 22b.

[0058] The digital-to-analog converter 21, the pre-comparator 22a, and the dynamic latch 22b are cascaded in sequence, that is, the input terminal of the pre-comparator 22a is coupled to the output terminal of the digital-to-analog converter 21, and the output terminal of the pre-comparator 22a is coupled to the input terminal of the dynamic latch 21b.

[0059] The residual sampling processing circuit 24 is used to couple to the output of the pre-comparator 22a in the corresponding cycle to sample the residual of the output of the pre-comparator 22a, and to connect to the output of the digital-to-analog converter 21 in the corresponding other cycle to sum the sampled residual with the output of the digital-to-analog converter 21 (i.e., residual summation).

[0060] The pre-comparator 22a compares the residual summation result provided by the residual sampling processing circuit 24 with the corresponding sampled common-mode signal vicm, and amplifies and outputs the comparison result. The sampled common-mode signal vicm serves as the input common-mode voltage of the pre-comparator 22a during sampling. It can come from an internal buffer, for example, the voltage output from the buffer after the power supply voltage of comparator 12 is divided by a series of resistors.

[0061] The output of the dynamic latch 22b (also known as a "dynamic amplifier") is coupled to the control logic circuit 23 and is used to latch the comparison result output by the pre-comparator 22a.

[0062] The output of the control logic circuit 23 is coupled to the digital-to-analog converter 21, which is also coupled to the input signal vin. The control logic circuit 23 is used to control the digital-to-analog converter 23 to sample the input signal vin according to the output of the dynamic latch 22b.

[0063] Therefore, the noise-shaping SAR ADC provided by this invention is essentially based on the traditional noise-shaping SAR ADC architecture, replacing the comparator with a pre-comparator 22a cascaded with a dynamic latch 22b, and placing the residual sampling processing circuit (i.e., the circuit with a residual sampling capacitor) 24 after the pre-comparator 22a. This circuit is coupled to the output of the pre-comparator 22a in the corresponding cycle to perform residual sampling on the output of the pre-comparator 22a, and connected to the output of the digital-to-analog converter 21 in another corresponding cycle to sum the sampled residual with the output of the digital-to-analog converter 21. Thus, the pre-comparator 22a is used as a residual amplifier, eliminating the need for a dedicated residual amplifier and the large residual sampling capacitor, which saves area and achieves a more area-saving and efficient noise-shaping SAR ADC.

[0064] It should be understood that the digital-to-analog converter 21, the residual sampling processing circuit 24, the pre-comparator 22a, the dynamic latch 22b, and the control logic circuit 23 can adopt any suitable circuit design, and the present invention does not impose any specific limitations on them.

[0065] For example, digital-to-analog converter 21 is a capacitive digital-to-analog converter that includes a binary capacitor array.

[0066] In one example, please refer to Figure 5A The digital-to-analog converter 21 includes a b-bit binary capacitor array (i.e., C0, 2*C0, ..., 2*C0). b-1 The noise-shaping SAR ADC includes a sampling switch (unlabeled). The upper plate of each capacitor is coupled to the output of the digital-to-analog converter 21, and the lower plate is coupled to the input signal vin, reference signal vrp, reference signal vrn, and reference common-mode signal vcm via corresponding switches (unlabeled). In this example, vrp and vrn can be a pair of differential reference signals. The noise-shaping SAR ADC also includes a sampling switch (unlabeled). One end of the sampling switch is coupled to the upper plate of each capacitor and the output of the digital-to-analog converter 21, and the other end is coupled to the sampling common-mode signal vicm. The control terminal is coupled to the sampling clock clks. When the sampling clock clks (e.g., high level) controls the sampling switch to close and conduct, the sampling phase of the noise-shaping SAR ADC begins. The digital-to-analog converter 21 samples the input signal vin. After the sampling phase ends, the sampling clock clks (e.g., low level) controls the sampling switch to open, entering the comparison phase of the noise-shaping SAR ADC.

[0067] In this context, the reference common-mode signal Vcm is the intermediate voltage between the differential reference signals Vrp and Vrn, i.e., Vcm = (Vrp + Vrn) / 2. Assuming Vrp is 1V and Vrn is 0V, the reference common-mode signal Vcm is 0.5V. Vicm and Vcm can have the same value or different values, depending on the design.

[0068] In another example, please refer to Figure 5B The digital-to-analog converter 21 includes a b-bit binary capacitor array (i.e., C0, 2*C0, ..., 2*C0). b-1 *C0), and the upper plate of each capacitor is coupled to the output of the digital-to-analog converter 21, and the lower plate is coupled to the reference signals vrn and vrp respectively through corresponding switches (unlabeled). In this example, vrn and vrp can be a pair of differential reference signals. The noise-shaping SAR ADC also includes a sampling switch (unlabeled). One end of the sampling switch is coupled to the upper plate of each capacitor and the output of the digital-to-analog converter 21, and the other end is coupled to the input signal vin. The control terminal is coupled to the sampling clock clks. When the sampling clock clks (e.g., high level) controls the sampling switch to close and conduct, the sampling stage of the noise-shaping SAR ADC is entered. The digital-to-analog converter 21 samples the input signal vin. After the sampling stage is completed, the sampling clock clks (e.g., low level) controls the sampling switch to open and enters the comparison stage of the noise-shaping SAR ADC.

[0069] For example, please refer to Figure 4The residual sampling processing circuit 24 has a first switched capacitor branch, a second switched capacitor branch, ..., an N(N+1) / 2 switched capacitor branches, for a total of N(N+1) / 2 switched capacitor branches, where N ≥ 1 and is an integer. When N ≥ 2, these switched capacitor branches are connected in parallel. Each switched capacitor branch is used to perform residual sampling in one cycle and sum the obtained residual with the output of the digital-to-analog converter 21 in another cycle to obtain the residual summation result vsump. At least one of the one cycle and the other cycle of any two switched capacitor branches is different, and each of the first to N(N+1) / 2 switched capacitor branches includes a residual sampling capacitor. The capacitance value of the residual sampling capacitor of at least one switched capacitor branch is C. RES And at least the residual sampling capacitor of the first switched capacitor branch has a capacitance value of N*C. RES The first switched capacitor branch samples the residual in the nth period (i.e., the current period) and connects to the output of the digital-to-analog converter 21 in the (n+1)th period. When N≥2, the second switched capacitor branch samples the residual in the nth period and connects to the output of the digital-to-analog converter in the (n+2)th period, and the third switched capacitor branch samples the residual in the (n+1)th period and connects to the output of the digital-to-analog converter in the (n+3)th period.

[0070] The circuit architecture of each switched capacitor branch can be the same or different.

[0071] For example, please refer to Figure 6 The pre-comparator 22a outputs a pair of differential signals outp and outn, and the circuit architecture of each switched capacitor branch is the same. Taking the i-th switched capacitor branch (1≤i≤N(N+1) / 2, and i is an integer) as an example, the i-th switched capacitor branch includes the residual sampling capacitor C. RESi The first to fifth switches Q1i to Q5i are connected as follows: the first terminal of the first switch Q1i is coupled to one of a pair of differential signals outp and outn (e.g., outp); the second terminal of the second switch Q2i is coupled to the other of a pair of differential signals outp and outn (e.g., outn); and the second terminal of the first switch Q1i, the first terminal of the fifth switch Q5i, and the second terminal of the third switch Q3i are all coupled to the residual sampling capacitor C. RESi The first plate (e.g., the upper plate), the first terminal of the second switch Q2i, the first terminal of the fourth switch Q4i, and the second terminal of the fifth switch Q5i are all coupled to the residual sampling capacitor C. RESiThe second plate of the circuit has the first terminal of the third switch Q3i coupled to the first signal V1i, the second terminal of the fourth switch Q4i coupled to the second signal V2i, the control terminals of the first switch Q1i and the second switch Q2i both coupled to the i-th residual sampling clock clksi, the control terminals of the third switch Q3i and the fourth switch Q4i both coupled to the i-th residual summation clock sumi, and the control terminal of the fifth switch Q5i coupled to the reset clock rst. One of the first signal V1i and the second signal V2i is the output of the digital-to-analog converter 21, and the other is the sampled common-mode signal vicm.

[0072] As an example, please refer to Figure 7 The pre-comparator 22a includes first to fourth PMOS transistors MP1 to MP4 and first to second NMOS transistors MN1 to MN2. The sources of the first to fourth PMOS transistors MP1 to MP4 are coupled to each other and can be further coupled to a power supply voltage (not shown). The sources of the first to second NMOS transistors MN1 to MN2 are coupled to each other. The gate and drain of the first PMOS transistor MP1, the drain of the second PMOS transistor MP2, the drain of the first NMOS transistor NM1, and the gate of the third PMOS transistor MP3 are coupled to each other to form the first output terminal outp of the pre-comparator 22a. The drain of the third PMOS transistor MP3, the gate and drain of the fourth PMOS transistor MP4, the drain of the second NMOS transistor NM2, and the gate of the second PMOS transistor MP2 are coupled to each other to form the second output terminal outn of the pre-comparator 22a. The gate of the first NMOS transistor NM1 is the first input terminal inp of the pre-comparator 22a, and the gate of the second NMOS transistor NM2 is the second input terminal inn of the pre-comparator 22a. The pre-comparator 22a also includes a tail current source I0, with the source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 coupled to one end of the tail current source I0, and the other end of the tail current source I0 grounded.

[0073] Assume that the transconductance of MP1 and MP4 is gmp1, the transconductance of MP2 and MP3 is gmp2, and the transconductance of MN1 and MN2 is gmn. MP1 and MP4 are the same size (the aspect ratio of MP1 equals that of MP4), MP2 and MP3 are the same size (the aspect ratio of MP2 equals that of MP3), and the aspect ratio of MP1 is K times that of MP2. Then the gain A of this precomparator 22a is:

[0074]

[0075] It can be seen that its gain A depends on μ n μ p The width-to-length ratio of K, MN1, and MN2 and the aspect ratio of MP2 and MP3

[0076] Thus, the gain A of this pre-comparator 22a varies less with the process angle PVT (process, voltage, temperature) than the gain of a residual comparator with a load of a current mirror or resistor, and it is also easy to obtain a gain of approximately 10 times. With this gain of the pre-comparator 22a, both a suitable amplification factor and considerable bandwidth can be ensured, while the size of each residual sampling capacitor in the residual sampling processing circuit 24 can be significantly reduced.

[0077] Please refer to Figure 8 In another embodiment of the present invention, the residual sampling processing circuit 24 further includes an adjustable capacitor Ct. One end of the adjustable capacitor Ct is coupled to the output terminal of the digital-to-analog converter 21, and the other end is grounded. The adjustable capacitor Ct is used to compensate for the influence of the gain A change of the pre-comparator 22a on the noise shaping effect, so as to achieve a near-ideal noise shaping effect.

[0078] The following is combined with Figures 9 to 13 The specific examples shown further illustrate the technical solution of the present invention in detail.

[0079] Example 1

[0080] Please refer to Figure 9 This example provides a first-order noise-shaping SAR ADC, which includes a digital-to-analog converter 21, a residual sampling processing circuit 24, a comparator 22, and a control logic circuit 23. The comparator includes a pre-comparator 22a and a dynamic latch 22b. The pre-comparator 22a outputs a pair of differential signals outp and outn. The digital-to-analog converter 21 includes a b-bit binary capacitor array to provide a capacitor CDAC.

[0081] Among them, the residual sampling processing circuit 24 is a first-order residual sampling processing circuit, i.e., N=1, which has a first switched capacitor branch and an adjustable capacitor Ct. The first switched capacitor branch includes the residual sampling capacitor Ct. RES1 The first to fifth switches Q11 to Q51 are connected as follows: the first terminal of the first switch Q11 is coupled to outp; the second terminal of the second switch Q21 is coupled to outn; and the second terminals of the first switch Q11, the fifth switch Q51, and the third switch Q31 are all coupled to the residual sampling capacitor C. RES1 The first plate (e.g., the upper plate), the first terminal of the second switch Q21, the first terminal of the fourth switch Q41, and the second terminal of the fifth switch Q51 are all coupled to the residual sampling capacitor C. RES1The second electrode plate, the first terminal of the third switch Q31 is coupled to vsump (i.e., the first signal V11 = vsump) and one end of the adjustable capacitor Ct, the other end of the adjustable capacitor Ct is grounded, the second terminal of the fourth switch Q41 is coupled to the sampling common-mode signal vicm (i.e., the second signal V21 = vicm), the control terminals of the first switch Q11 and the second switch Q21 are both coupled to the first residual sampling clock clks1, the control terminals of the third switch Q31 and the fourth switch Q41 are both coupled to the first residual summation clock sum1, and the control terminal of the fifth switch Q51 is coupled to the reset clock rst. The first switch Q11 and the second switch Q21 are residual sampling switches, the third switch Q31 and the fourth switch Q41 are residual summation switches, and the fifth switch Q51 is a reset switch to reset the residual sampling capacitor Ct. RES1 .

[0082] `clks` is the sampling clock that controls the sampling switch of the first-order noise-shaping SAR ADC, active high. `clkc` is the compare clock of the first-order noise-shaping SAR ADC, provided to the dynamic latch 22b. `clks1` is the residual sampling clock, and `sum1` is the residual summation clock. `rst` is the reset clock. These clocks, `clks`, `clkc`, `clks1`, and `sum1`, can be generated by digital circuits, etc. Each time the chip powers on or wakes the first-order noise-shaping SAR ADC from sleep mode, a reset clock `rst` is generated to clear the cache. RES1 The charge on the C is used to prevent the first-order noise-shaping SAR ADC from storing the charge during the initial quantization. RES1 The unknown charge on the surface affects the quantization results of the first-order noise-shaping SAR ADC.

[0083] The timing sequence of the entire circuit of this first-order noise-shaping SAR ADC is as follows: Figure 10 As shown, it includes:

[0084] First, the reset clock rst jumps high, Q51 closes and conducts, and the residual sampling capacitor C... RES1 The charge on it was cleared.

[0085] Next, the reset clock rst goes low and clks goes high, and the first-order noise-shaping SAR ADC enters the sampling phase, starting to sample the input signal vin. After sampling is complete, the residual summation clock sum1 goes high, and C... RES1 It is connected to vsump (i.e., connected to the binary capacitor array of digital-to-analog converter 21).

[0086] Subsequently, clks goes low, and the first-order noise-shaping SAR ADC enters the comparison phase. The comparison clock clkc pulses arrive one by one, and the first-order noise-shaping SAR ADC begins bit-by-bit comparison. After the comparison is complete, sum1 goes low, and C... RES1Disconnect the binary capacitor array CDAC from the digital-to-analog converter 21.

[0087] Subsequently, clks1 jumps high, sampling the outputs outp and outn of the preamp. Assuming the gain of the preamp 22a is A times, then outp-outn = -A*residue, where residual is the residual, defined as the voltage value of vsump-vicm after all bits are compared. Therefore, sampling outp-outn of the preamp 22a output can be considered as sampling the residual.

[0088] After residual sampling is completed, the first-order noise-shaping SAR ADC starts sampling again. When the first-order noise-shaping SAR ADC finishes sampling, sum1 jumps, C RES1 The stored residual voltage -A*residue is added to vsump for comparison. After the comparison, the residual voltage is sampled again, and so on, in a continuous cycle. The entire process can be summarized as: ADC sampling → residual summation (CRES connected to CDAC) → ADC comparison and quantization → residual sampling → ADC sampling...

[0089] To ensure that each stage proceeds in strict order, a certain interval can be inserted (generally the minimum value of the system clock cycle is sufficient), such as from the falling edge of rst to the rising edge of clks, from the falling edge of clks to the rising edge of sum1, from the falling edge of sum1 to the rising edge of clks1, etc. The interval between these edges can be the minimum value of the system clock cycle or several times it.

[0090] From the above description, it can be seen that the core of the circuit operation is: the residual sampling processing circuit 24 samples the residual voltage of the current period (i.e., the nth period), and adds it to vsump before the comparison begins in the next period (i.e., the n+1th period), and then compares and quantizes it.

[0091] To achieve ideal first-order noise shaping, the following is required:

[0092]

[0093] The above is red, C RES It is C RES1 The capacitance value, Cpar, is all the parasitic capacitances on the vsump, C DAC It is a capacitor provided by the digital-to-analog converter 21.

[0094] Because the gain A of the pre-comparator 22a varies slightly at the process angle PVT, an adjustable capacitor Ct is introduced to compensate for the effect of the gain A variation of the pre-comparator 22a on the noise shaping effect.

[0095] Example 2

[0096] For a second-order noise-shaping SAR ADC (i.e., N=2) with top-plate sampling (defined as the plate where each residual sampling capacitor is connected to the non-inverting input of the comparator), the following must be true:

[0097]

[0098] Therefore, in practice we only need to set 2V res (n-1)-V res (n-2) and input signal V in (n) can be summed on vsump.

[0099] If it is a second-order noise-shaping SAR ADC with base plate sampling, then only -2V needs to be changed. res (n-1)+V res (n-2) can be summed with the voltage of the top plate.

[0100] Based on this, please refer to Figure 11 This example provides a second-order noise-shaping SAR ADC, which includes a digital-to-analog converter 21, a residual sampling processing circuit 24, a comparator 22, and a control logic circuit 23. The comparator includes a pre-comparator 22a and a dynamic latch 22b. The pre-comparator 22a outputs a pair of differential signals outp and outn. The digital-to-analog converter 21 includes a b-bit binary capacitor array, providing a capacitor CDAC. The residual sampling processing circuit 24 is a second-order residual sampling processing circuit, i.e., N=2, which can realize second-order noise shaping.

[0101] The residual sampling processing circuit 24 includes a first switched capacitor branch 241, a second switched capacitor branch 242, a third switched capacitor branch 243, and an adjustable capacitor Ct.

[0102] The first switched capacitor branch 241 includes the residual sampling capacitor C. RES1 The first to fifth switches Q11 to Q51 are connected as follows: the first terminal of the first switch Q11 is coupled to outp; the second terminal of the second switch Q21 is coupled to outn; and the second terminals of the first switch Q11, the fifth switch Q51, and the third switch Q31 are all coupled to the residual sampling capacitor C. RES1 The first plate (e.g., the upper plate), the first terminal of the second switch Q21, the first terminal of the fourth switch Q41, and the second terminal of the fifth switch Q51 are all coupled to the residual sampling capacitor C. RES1The second electrode plate, the first terminal of the third switch Q31 is coupled to vsump (i.e., the first signal V11 = vsump) and one end of the adjustable capacitor Ct, the other end of the adjustable capacitor Ct is grounded, the second terminal of the fourth switch Q41 is coupled to the sampling common-mode signal vicm (i.e., the second signal V21 = vicm), the control terminals of the first switch Q11 and the second switch Q21 are both coupled to the first residual sampling clock clks1, the control terminals of the third switch Q31 and the fourth switch Q41 are both coupled to the first residual summation clock sum1, and the control terminal of the fifth switch Q51 is coupled to the reset clock rst. The first switch Q11 and the second switch Q21 are residual sampling switches, the third switch Q31 and the fourth switch Q41 are residual summation switches, and the fifth switch Q51 is a reset switch to reset the residual sampling capacitor Ct. RES1 .

[0103] The second switched capacitor branch 242 includes the residual sampling capacitor C. RES2 The first to fifth switches Q12 to Q52 are connected as follows: the first terminal of the first switch Q12 is coupled to outp; the second terminal of the second switch Q22 is coupled to outn; and the second terminals of the first switch Q12, the fifth switch Q52, and the third switch Q32 are all coupled to the residual sampling capacitor C. RES2 The first plate (e.g., the upper plate), the first terminal of the second switch Q22, the first terminal of the fourth switch Q42, and the second terminal of the fifth switch Q52 are all coupled to the residual sampling capacitor C. RES2 The second electrode plate of the circuit is connected to the first terminal of the third switch Q32, which is coupled to the common-mode sampling signal vicm (i.e., the first signal V12 = vicm). The second terminal of the fourth switch Q42 is coupled to vsump (i.e., the second signal V22 = vsump). The control terminals of the first switch Q12 and the second switch Q22 are both coupled to the second residual sampling clock clks2. The control terminals of the third switch Q32 and the fourth switch Q42 are both coupled to the second residual summation clock sum2. The control terminal of the fifth switch Q52 is coupled to the reset clock rst. The first switch Q12 and the second switch Q22 are residual sampling switches, the third switch Q32 and the fourth switch Q42 are residual summation switches, and the fifth switch Q52 is a reset switch to reset the residual sampling capacitor C. RES2 .

[0104] The third switched capacitor branch 243 includes the residual sampling capacitor C. RES3 The first to fifth switches Q13 to Q53 are connected as follows: the first terminal of the first switch Q13 is coupled to outp; the second terminal of the second switch Q23 is coupled to outn; and the second terminals of the first switch Q13, the fifth switch Q53, and the third switch Q33 are all coupled to the residual sampling capacitor C. RES3The first plate (e.g., the upper plate), the first terminal of the second switch Q23, the first terminal of the fourth switch Q43, and the second terminal of the fifth switch Q53 are all coupled to the residual sampling capacitor C. RES3 The second electrode plate of the circuit is connected to the first terminal of the third switch Q33, which is coupled to the common-mode sampling signal vicm (i.e., the first signal V13 = vicm). The second terminal of the fourth switch Q43 is coupled to vsump (i.e., the second signal V23 = vsump). The control terminals of the first switch Q13 and the second switch Q23 are both coupled to the third residual sampling clock clks3. The control terminals of the third switch Q33 and the fourth switch Q43 are both coupled to the third residual summation clock sum3. The control terminal of the fifth switch Q53 is coupled to the reset clock rst. The first switch Q13 and the second switch Q23 are residual sampling switches, the third switch Q33 and the fourth switch Q43 are residual summation switches, and the fifth switch Q53 is a reset switch to reset the residual sampling capacitor C. RES3 .

[0105] `clks` is the sampling clock that controls the sampling switch of the second-order noise-shaping SAR ADC, active high. `clkc` is the comparison clock of the first-order noise-shaping SAR ADC, provided to the dynamic latch 22b. `clks1`, `clks2`, and `clks3` are all residual sampling clocks, and `sum1`, `sum2`, and `sum3` are all residual summation clocks. `rst` is the reset clock. These clocks, `clks`, `clkc`, `clks1`, `clks2`, `clks3`, `sum1`, `sum2`, and `sum3`, can be generated by digital circuits, etc. Each time the chip powers on or wakes up from sleep mode, a reset clock `rst` is generated to clear `C`. RES1 C RES2 C RES3 The charge on the C is used to prevent the second-order noise-shaping SAR ADC from storing the charge during the initial quantization. RES1 The unknown charge on the surface affects the quantization results of the second-order noise-shaping SAR ADC.

[0106] The entire circuit of this second-order noise-shaping SAR ADC is more... Figure 9 The first-order noise-shaping SARADC shown has two additional residual sampling capacitors C. RES2 C RES3 And the corresponding residual sampling switches and residual summing switches Q12~Q52, Q13~Q53, clks2 controls C RES2 Sampling of the residuals, clks3 controls C RES3 Sampling is performed on the residuals, and sum2 controls C. RES2 Should the capacitor array C of the digital-to-analog converter 21 be connected? DAC SUM3 controls C RES3 Should the capacitor array C of the digital-to-analog converter 21 be connected?DAC .

[0107] The timing sequence of this second-order noise-shaping SAR ADC is as follows: Figure 12 As shown in the time series, C RES1 The residual is always sampled in the current period (the nth period) and connected to the capacitor array C of the digital-to-analog converter 21 in the next period (the n+1th period). DAC (That is, access vsump to sum vsump with the residual); C RES2 The residual is sampled in the nth cycle, and the capacitor array C of the digital-to-analog converter 21 is connected in the (n+2)th cycle. DAC C RES3 The residual is sampled in the (n+1)th cycle and connected to the capacitor array C of the digital-to-analog converter 21 in the (n+3)th cycle. DAC .

[0108] To achieve ideal second-order noise shaping, the following is required:

[0109]

[0110] Achieving the above equation in a design is quite easy; for example, designing C... RES3 =C RES2 =C RES C RES1 =2*C RES .

[0111] Example 3

[0112] For a third-order noise-shaping SAR ADC (i.e., N=3) sampled from a base plate, it is only necessary to adjust -V res (n-3)+3V res (n-2)-3V res The sum of (n-1) and the voltage of the top plate is sufficient.

[0113] Based on this, please refer to Figure 13 This example provides a third-order noise-shaping SAR ADC, which includes a digital-to-analog converter 21, a residual sampling processing circuit 24, a comparator 22, and a control logic circuit 23. The comparator includes a pre-comparator 22a and a dynamic latch 22b. The pre-comparator 22a outputs a pair of differential signals outp and outn. The digital-to-analog converter 21 includes a b-bit binary capacitor array, providing a capacitor CDAC. The residual sampling processing circuit 24 is a third-order residual sampling processing circuit, i.e., N=3, which can realize third-order noise shaping.

[0114] The residual sampling processing circuit 24 includes a first switched capacitor branch 241, a second switched capacitor branch 242, a third switched capacitor branch 243, a fourth switched capacitor branch 244, a fifth switched capacitor branch 245, a sixth switched capacitor branch 246, and an adjustable capacitor Ct.

[0115] The first switched capacitor branch 241 includes the residual sampling capacitor C. RES1 The first to fifth switches Q11 to Q51 are connected as follows: the first terminal of the first switch Q11 is coupled to outp; the second terminal of the second switch Q21 is coupled to outn; and the second terminals of the first switch Q11, the fifth switch Q51, and the third switch Q31 are all coupled to the residual sampling capacitor C. RES1 The first plate (e.g., the upper plate), the first terminal of the second switch Q21, the first terminal of the fourth switch Q41, and the second terminal of the fifth switch Q51 are all coupled to the residual sampling capacitor C. RES1 The second electrode plate, the first terminal of the third switch Q31 is coupled to vsump (i.e., the first signal V11 = vsump) and one end of the adjustable capacitor Ct, the other end of the adjustable capacitor Ct is grounded, the second terminal of the fourth switch Q41 is coupled to the sampling common-mode signal vicm (i.e., the second signal V21 = vicm), the control terminals of the first switch Q11 and the second switch Q21 are both coupled to the first residual sampling clock clks1, the control terminals of the third switch Q31 and the fourth switch Q41 are both coupled to the first residual summation clock sum1, and the control terminal of the fifth switch Q51 is coupled to the reset clock rst. The first switch Q11 and the second switch Q21 are residual sampling switches, the third switch Q31 and the fourth switch Q41 are residual summation switches, and the fifth switch Q51 is a reset switch to reset the residual sampling capacitor Ct. RES1 .

[0116] The second switched capacitor branch 242 includes the residual sampling capacitor C. RES2 The first to fifth switches Q12 to Q52 are connected as follows: the first terminal of the first switch Q12 is coupled to outp; the second terminal of the second switch Q22 is coupled to outn; and the second terminals of the first switch Q12, the fifth switch Q52, and the third switch Q32 are all coupled to the residual sampling capacitor C. RES2 The first plate (e.g., the upper plate), the first terminal of the second switch Q22, the first terminal of the fourth switch Q42, and the second terminal of the fifth switch Q52 are all coupled to the residual sampling capacitor C. RES2The second electrode plate of the circuit is connected to the first terminal of the third switch Q32, which is coupled to the common-mode sampling signal vicm (i.e., the first signal V12 = vicm). The second terminal of the fourth switch Q42 is coupled to vsump (i.e., the second signal V22 = vsump). The control terminals of the first switch Q12 and the second switch Q22 are both coupled to the second residual sampling clock clks2. The control terminals of the third switch Q32 and the fourth switch Q42 are both coupled to the second residual summation clock sum2. The control terminal of the fifth switch Q52 is coupled to the reset clock rst. The first switch Q12 and the second switch Q22 are residual sampling switches, the third switch Q32 and the fourth switch Q42 are residual summation switches, and the fifth switch Q52 is a reset switch to reset the residual sampling capacitor C. RES2 .

[0117] The third switched capacitor branch 243 includes the residual sampling capacitor C. RES3 The first to fifth switches Q13 to Q53 are connected as follows: the first terminal of the first switch Q13 is coupled to outp; the second terminal of the second switch Q23 is coupled to outn; and the second terminals of the first switch Q13, the fifth switch Q53, and the third switch Q33 are all coupled to the residual sampling capacitor C. RES3 The first plate (e.g., the upper plate), the first terminal of the second switch Q23, the first terminal of the fourth switch Q43, and the second terminal of the fifth switch Q53 are all coupled to the residual sampling capacitor C. RES3 The second electrode plate of the circuit is connected to the first terminal of the third switch Q33, which is coupled to the common-mode sampling signal vicm (i.e., the first signal V13 = vicm). The second terminal of the fourth switch Q43 is coupled to vsump (i.e., the second signal V23 = vsump). The control terminals of the first switch Q13 and the second switch Q23 are both coupled to the third residual sampling clock clks3. The control terminals of the third switch Q33 and the fourth switch Q43 are both coupled to the third residual summation clock sum3. The control terminal of the fifth switch Q53 is coupled to the reset clock rst. The first switch Q13 and the second switch Q23 are residual sampling switches, the third switch Q33 and the fourth switch Q43 are residual summation switches, and the fifth switch Q53 is a reset switch to reset the residual sampling capacitor C. RES3 .

[0118] The fourth switched capacitor branch 244 includes the residual sampling capacitor C. RES4 The first to fifth switches Q14 to Q54 are connected as follows: the first terminal of the first switch Q14 is coupled to outp; the second terminal of the second switch Q24 is coupled to outn; and the second terminals of the first switch Q14, the fifth switch Q54, and the third switch Q34 are all coupled to the residual sampling capacitor C. RES4 The first plate (e.g., the upper plate), the first terminal of the second switch Q24, the first terminal of the fourth switch Q44, and the second terminal of the fifth switch Q54 are all coupled to the residual sampling capacitor C. RES4The second electrode plate, the first terminal of the third switch Q34 is coupled to vsump (i.e., the first signal V14 = vsump), the second terminal of the fourth switch Q44 is coupled to the sampling common-mode signal vicm (i.e., the second signal V24 = vicm), the control terminals of the first switch Q14 and the second switch Q24 are both coupled to the fourth residual sampling clock clks4, the control terminals of the third switch Q34 and the fourth switch Q44 are both coupled to the fourth residual summation clock sum4, and the control terminal of the fifth switch Q54 is coupled to the reset clock rst. The first switch Q14 and the second switch Q24 are residual sampling switches, the third switch Q34 and the fourth switch Q44 are residual summation switches, and the fifth switch Q54 is a reset switch to reset the residual sampling capacitor C. RES4 .

[0119] The fifth switched capacitor branch 245 includes the residual sampling capacitor C. RES5 The first to fifth switches Q15-Q55 are connected as follows: the first terminal of the first switch Q15 is coupled to outp; the second terminal of the second switch Q25 is coupled to outn; and the second terminals of the first switch Q15, the fifth switch Q55, and the third switch Q35 are all coupled to the residual sampling capacitor C. RES5 The first plate (e.g., the upper plate), the first terminal of the second switch Q25, the first terminal of the fourth switch Q45, and the second terminal of the fifth switch Q55 are all coupled to the residual sampling capacitor C. RES5 The second electrode plate, the first terminal of the third switch Q35 is coupled to vsump (i.e., the first signal V15 = vsump), the second terminal of the fourth switch Q45 is coupled to the sampling common-mode signal vicm (i.e., the second signal V25 = vicm), the control terminals of the first switch Q15 and the second switch Q25 are both coupled to the fifth residual sampling clock clks5, the control terminals of the third switch Q35 and the fourth switch Q45 are both coupled to the fifth residual summation clock sum5, and the control terminal of the fifth switch Q55 is coupled to the reset clock rst. The first switch Q15 and the second switch Q25 are residual sampling switches, the third switch Q35 and the fourth switch Q45 are residual summation switches, and the fifth switch Q55 is a reset switch to reset the residual sampling capacitor C. RES5 .

[0120] The 6th switched capacitor branch 246 includes the residual sampling capacitor C. RES6 The first to fifth switches Q16-Q56 are connected as follows: the first terminal of the first switch Q16 is coupled to outp; the second terminal of the second switch Q26 is coupled to outn; and the second terminals of the first switch Q16, the fifth switch Q56, and the third switch Q36 are all coupled to the residual sampling capacitor C. RES6 The first plate (e.g., the upper plate), the first terminal of the second switch Q26, the first terminal of the fourth switch Q46, and the second terminal of the fifth switch Q56 are all coupled to the residual sampling capacitor C. RES6The second electrode plate, the first terminal of the third switch Q36 is coupled to vsump (i.e., the first signal V16 = vsump), the second terminal of the fourth switch Q46 is coupled to the sampling common-mode signal vicm (i.e., the second signal V26 = vicm), the control terminals of the first switch Q16 and the second switch Q26 are both coupled to the 6th residual sampling clock clks6, the control terminals of the third switch Q36 and the fourth switch Q46 are both coupled to the 6th residual summation clock sum6, and the control terminal of the fifth switch Q56 is coupled to the reset clock rst. The first switch Q16 and the second switch Q26 are residual sampling switches, the third switch Q36 and the fourth switch Q46 are residual summation switches, and the fifth switch Q56 is a reset switch to reset the residual sampling capacitor C. RES6 .

[0121] `clks` is the sampling clock that controls the sampling switch of the second-order noise-shaping SAR ADC, active high. `clkc` is the comparison clock of the first-order noise-shaping SAR ADC, provided to the dynamic latch 22b. `clks1` to `clks6` are residual sampling clocks, and `sum1` to `sum6` are residual summation clocks. `rst` is the reset clock. These clocks (`clks`, `clkc`, `clks1` to `clks6`, `sum1` to `sum6`) can be generated by digital circuits, etc. Each time the chip powers on or wakes up from sleep mode, a reset clock `rst` is generated to clear `C`. RES1 C RES2 C RES3 C RES4 C RES4 C RES4 The charge on the C is used to prevent the third-order noise-shaping SAR ADC from storing the charge during the initial quantization. RES1 The unknown charge on the surface affects the quantization results of the third-order noise-shaping SAR ADC.

[0122] Figure 14 This is the operating timing sequence of the third-order noise-shaping SAR ADC, where C RES1 The residual is sampled in the current period (i.e., the nth period) and connected to the capacitor array C of the digital-to-analog converter 21 in the next period (i.e., the n+1th period). DAC (That is, access vsump to sum vsump and the residual), C RES2 The residual is sampled in the nth cycle, and the capacitor array C of the digital-to-analog converter 21 is connected in the (n+2)th cycle. DAC C RES3 The residual is sampled in the (n+1)th cycle and connected to the capacitor array C of the digital-to-analog converter 21 in the (n+3)th cycle. DAC C RES4 The residual is sampled in the nth cycle, and the capacitor array C of the digital-to-analog converter 21 is connected in the (n+3)th cycle.DAC C RES5 The residual is sampled in the (n+1)th cycle and connected to the capacitor array C of the digital-to-analog converter 21 in the (n+4)th cycle. DAC C RES6 The residual is sampled in the (n+2)th cycle, and the capacitor array C of the digital-to-analog converter 21 is connected in the (n+5)th cycle. DAC .

[0123] To achieve ideal third-order noise shaping, the following is required:

[0124]

[0125] Achieving the above equation in a design is quite easy; for example, designing C... RES4 =C RES5 =C RE6 =C RES C RES1 =C RES2 =C RES3 =3*C RES .

[0126] It should be understood that, as can be seen from the analysis of Examples 1 to 3 above, achieving first-order noise shaping requires one residual sampling capacitor C. RES1 To achieve second-order noise shaping, three residual sampling capacitors C are required. RES1 ~C RES3 Achieving third-order noise shaping requires six residual sampling capacitors C. RES1 ~C RES6 To achieve Nth-order noise shaping, 1+2+3+...+N=N(N+1) / 2 residual sampling capacitors are needed, while ensuring C RES1 The residual is sampled in the current period (i.e., the nth period) and connected to the capacitor array C of the digital-to-analog converter 21 in the next period (i.e., the n+1th period). DAC C RES2 The residual is sampled in the nth cycle, and the capacitor array C of the digital-to-analog converter 21 is connected in the (n+2)th cycle. DAC C RES3 The residual is sampled in the (n+1)th cycle and connected to the capacitor array C of the digital-to-analog converter 21 in the (n+3)th cycle. DAC C RES4 The residual is sampled in the nth cycle, and the capacitor array C of the digital-to-analog converter 21 is connected in the (n+3)th cycle. DAC C RES5 The residual is sampled in the (n+1)th cycle and connected to the capacitor array C of the digital-to-analog converter 21 in the (n+4)th cycle. DAC C RES6 The residual is sampled in the (n+2)th cycle, and the capacitor array C of the digital-to-analog converter 21 is connected in the (n+5)th cycle.DAC ...and so on, Nth-order noise shaping can be achieved.

[0127] Furthermore, it should be understood that the above three examples are all single-ended input SAR ADCs. The same approach can be used for differential input SAR ADCs to achieve first-order, second-order, third-order and even higher-order noise shaping, which will not be repeated in this article.

[0128] In summary, the noise-shaping SAR ADC provided by this invention utilizes a pre-comparator as a residual amplifier, eliminating the need for a dedicated residual amplifier. Furthermore, the gain of the pre-comparator varies minimally with the PVT and its gain variation can be compensated for by adjusting the adjustable capacitor Ct, achieving near-ideal high-order noise shaping. Moreover, N-order noise shaping can be achieved using N(N+1) / 2 residual sampling capacitors and simple timing. The noise-shaping SAR ADC provided by this invention has a smaller area and higher operating efficiency.

[0129] Based on the same inventive concept, please refer to Figures 3 to 14 An embodiment of the present invention also provides an electronic system comprising the noise-shaping SAR ADC described in any embodiment of the present invention.

[0130] Furthermore, the electronic system of this embodiment can exist in any suitable product form such as a chip, dedicated circuit, functional module, or device. It may also further include a clock generation circuit (not shown, but may be a digital circuit) for generating the various clocks required to generate the noise-shaping SAR ADC of the present invention.

[0131] The electronic system in this embodiment has higher performance and smaller area due to the use of the noise-shaping SAR ADC of the present invention.

[0132] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A noise-shaping SAR ADC, characterized in that, It includes a digital-to-analog converter, a residual sampling processing circuit, a comparator, and a control logic circuit, wherein the comparator includes a pre-comparator and a dynamic latch; wherein, The input terminal of the pre-comparator is coupled to the output terminal of the digital-to-analog converter, and the output terminal of the pre-comparator is coupled to the input terminal of the dynamic latch. The residual sampling processing circuit is used to couple to the output terminal of the pre-comparator in a corresponding cycle to sample the residual of the output of the pre-comparator, and to connect to the output terminal of the digital-to-analog converter in another corresponding cycle to sum the sampled residual with the output of the digital-to-analog converter. The pre-comparator is used to compare the residual summation result with the corresponding sampled common-mode signal, and amplify and output the comparison result. The output of the dynamic latch is coupled to the control logic circuit and is used to latch the comparison result output by the pre-comparator. The output of the control logic circuit is coupled to the digital-to-analog converter, which is also coupled to the input signal. The control logic circuit is used to control the digital-to-analog converter to sample the input signal according to the output of the dynamic latch.

2. The noise-shaping SAR ADC as described in claim 1, characterized in that, The residual sampling processing circuit has N(N+1) / 2 switched capacitor branches, where N≥1 and is an integer. Each switched capacitor branch is used to perform residual sampling in one cycle and sum the obtained residual with the output of the digital-to-analog converter in another cycle to obtain the residual summation result. At least one of the one cycle and the other cycle of any two switched capacitor branches is different.

3. The noise-shaping SAR ADC as described in claim 2, characterized in that, The N(N+1) / 2 switched capacitor branches are the first to the N(N+1) / 2 switched capacitor branches. The first switched capacitor branch samples the residual in the nth period and connects to the output of the digital-to-analog converter in the (n+1)th period. When N≥2, the second switched capacitor branch samples the residual in the nth period and connects to the output of the digital-to-analog converter in the (n+2)th period. The third switched capacitor branch samples the residual in the (n+1)th period and connects to the output of the digital-to-analog converter in the (n+3)th period.

4. The noise-shaping SAR ADC as described in claim 3, characterized in that, When N≥3, the fourth switched capacitor branch samples the residual in the nth cycle and connects to the output of the digital-to-analog converter in the (n+3)th cycle; the fifth switched capacitor branch samples the residual in the (n+1)th cycle and connects to the output of the digital-to-analog converter in the (n+4)th cycle; and the sixth switched capacitor branch samples the residual in the (n+2)th cycle and connects to the output of the digital-to-analog converter in the (n+5)th cycle.

5. The noise-shaping SAR ADC as described in claim 4, characterized in that, Each of the 1st to N(N+1) / 2th switched capacitor branches includes a residual sampling capacitor, and the capacitance value of the residual sampling capacitor in at least one switched capacitor branch is C. RES And at least the residual sampling capacitor of the first switched capacitor branch has a capacitance value of N*C. RES .

6. The noise-shaping SAR ADC as described in claim 5, characterized in that, When N=1, the capacitance value of the residual sampling capacitor in the first switched capacitor branch is C. RES ; When N=2, the capacitance value of the residual sampling capacitor in the second switched capacitor branch and the third switched capacitor branch is C. RES The capacitance value of the residual sampling capacitor in the first switched capacitor branch is 2*C. RES ; When N=3, the capacitance value of the residual sampling capacitors in the first to third switched capacitor branches is 3*C. RES The residual sampling capacitors in the fourth and sixth switched capacitor branches both have a capacitance value of C. RES .

7. The noise-shaping SAR ADC as described in any one of claims 1-6, characterized in that, The pre-comparator outputs a pair of differential signals. Each switched capacitor branch includes a residual sampling capacitor and a first to a fifth switch. The first terminal of the first switch is coupled to one of the pair of differential signals, and the second terminal of the second switch is coupled to the other of the pair of differential signals. The second terminal of the first switch, the first terminal of the fifth switch, and the second terminal of the third switch are all coupled to the first plate of the residual sampling capacitor. The first terminal of the second switch, the first terminal of the fourth switch, and the second terminal of the fifth switch are all coupled to the second plate of the residual sampling capacitor. The first terminal of the third switch is coupled to a first signal, and the second terminal of the fourth switch is coupled to a second signal. The control terminals of the first and second switches are all coupled to the corresponding residual sampling clocks. The control terminals of the third and fourth switches are all coupled to the corresponding residual summation clocks. The control terminal of the fifth switch is coupled to a reset clock. One of the first and second signals is the output of the digital-to-analog converter, and the other is the sampled common-mode signal.

8. The noise-shaping SAR ADC as described in any one of claims 1-6, characterized in that, The residual sampling processing circuit also includes an adjustable capacitor, one end of which is coupled to the output terminal of the digital-to-analog converter and the other end is grounded. The adjustable capacitor is used to compensate for the influence of the gain change of the pre-comparator on the noise shaping effect.

9. The noise-shaping SAR ADC as described in claim 1, characterized in that, The digital-to-analog converter is a capacitive digital-to-analog converter and includes a binary capacitor array; And / or, the noise-shaping SAR ADC further includes a sampling switch, one end of which is coupled to the input terminal of the digital-to-analog converter, and the other end is coupled to the sampling common-mode signal or the input signal. The control terminal of the sampling switch is coupled to the input sampling clock of the noise-shaping SAR ADC, and the dynamic latch is coupled to the comparison clock of the noise-shaping SAR ADC.

10. The noise-shaping SAR ADC as described in claim 1, characterized in that, The pre-comparator includes first to fourth PMOS transistors and first to second NMOS transistors. The sources of the first to fourth PMOS transistors are coupled to each other, and the sources of the first to second NMOS transistors are coupled to each other. The gate and drain of the first PMOS transistor, the drain of the second PMOS transistor, the drain of the first NMOS transistor, and the gate of the third PMOS transistor are coupled to each other to form the first output terminal of the pre-comparator. The drain of the third PMOS transistor, the gate and drain of the fourth PMOS transistor, the drain of the second NMOS transistor, and the gate of the second PMOS transistor are coupled to each other to form the second output terminal of the pre-comparator. The gate of the first NMOS transistor is the first input terminal of the pre-comparator, and the gate of the second NMOS transistor is the second input terminal of the pre-comparator.

11. An electronic system, characterized in that, Includes a noise-shaping SARADC as described in any one of claims 1-10.

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