Comparator for eliminating dynamic imbalance generated by input common-mode fluctuation and control method
By introducing a preamplifier operating in the subthreshold region and a cross-coupled pair latch design into the comparator, the problem of comparator dynamic offset is solved, achieving high-precision and low-power comparator performance.
Patent Information
- Application Number
- CN202511778690.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-03-03
AI Technical Summary
In the prior art, the dynamic offset of the comparator is affected by the input common-mode voltage fluctuation, which leads to the degradation of the analog-to-digital converter performance. In particular, in successive approximation analog-to-digital converters, dynamic offset is difficult to eliminate effectively.
The design employs a first-stage preamplifier and a second-stage latch. The input transistor of the preamplifier operates in the subthreshold region. Combined with two pairs of cross-coupled latches, high-precision comparison is achieved by controlling the opening and closing of the switches, while reducing power consumption.
It eliminates dynamic offset under input common-mode voltage fluctuations, improves comparator accuracy and speed, reduces power consumption, and is suitable for low-power applications.
Smart Images
Figure CN121603007A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuits, and particularly relates to a comparator and control method for eliminating dynamic offset caused by input common-mode fluctuations. Background Technology
[0002] An analog-to-digital converter (ADC) is a bridge that converts analog signals into digital signals, and a comparator is an important component of an ADC. The function of a comparator is to compare analog input signals to obtain a digital output. The accuracy and speed of the comparator are important factors affecting the overall performance of the ADC.
[0003] Among the many factors affecting comparator accuracy, comparator offset is a significant one. Generally, comparator offset is divided into static offset and dynamic offset. Static offset manifests as a fixed error in the final output of the analog-to-digital converter, only reducing the dynamic range of the input signal and having a minimal impact on the number of effective bits.
[0004] Static offset is mainly caused by threshold mismatch, size mismatch, and mobility mismatch of devices. Generally, increasing device size and optimizing layout can effectively reduce static offset voltage. Dynamic offset, however, changes with the input signal, introducing harmonics into the final output of the analog-to-digital converter (ADC), worsening the ADC's effective bit depth and total harmonic distortion (THD). Besides being related to threshold mismatch, size mismatch, and mobility mismatch, dynamic offset is also affected by comparator input common-mode voltage fluctuations and output node parasitic capacitance mismatch.
[0005] Ensuring a constant common-mode input voltage of the comparator can effectively eliminate dynamic offset. However, in practical analog-to-digital converter (ADC) design, to achieve other advantages, the constant input common-mode voltage is often not guaranteed. For example, successive approximation ADCs use switching strategies with non-constant common-mode voltage to reduce power consumption. Therefore, eliminating comparator dynamic offset under fluctuating input common-mode voltage conditions becomes a pressing issue. Summary of the Invention
[0006] To overcome the shortcomings of the prior art, the present invention provides a comparator and control method for eliminating dynamic offset caused by input common-mode ripple. The overall circuit of the comparator includes a first-stage preamplifier and a second-stage latch. By setting the input transistor of the preamplifier to operate in the subthreshold region, the dynamic offset caused by input common-mode ripple is eliminated, and a high-precision comparison process is achieved. The latch uses a design of two pairs of cross-coupled pairs, which improves the speed of the third stage of comparison while reducing power consumption.
[0007] To achieve the above objectives, one or more embodiments of the present invention provide the following technical solutions: The first aspect of the present invention provides a comparator that eliminates dynamic misalignment caused by input common-mode fluctuations.
[0008] A comparator for eliminating dynamic offset caused by input common-mode ripple includes a first-stage preamplifier, the first-stage preamplifier including NMOS transistors MN1 and MN2, PMOS transistors MP1 and MP2, and capacitors C2a and C2b. The drains of MP1 and MN1 are connected to the upper and lower plates of capacitor C2a, respectively, and the gates of MP1 and MN1 are connected to the non-inverting input terminal VIP; the source of MP2 is connected to the source of MP1, the source of MN2 is connected to the source of MN1, the drains of MP2 and MN2 are connected to the upper and lower plates of capacitor C2b, respectively, and the gates of MP2 and MN2 are connected to the inverting input terminal VIN. It also includes switches S5, S6, S7, and S8: one end of switch S5 is connected to the upper plate of capacitor C2a, and the other end is connected to GND; one end of switch S6 is connected to GND, and the other end is connected to the drain of MP2; one end of switch S7 is connected to the drain of MN1, and the other end is connected to the power supply voltage VDD; one end of switch S8 is connected to the power supply voltage VDD, and the other end is connected to the drain of MN2.
[0009] As an alternative technical solution, the first-stage preamplifier also includes switches S2 and S4 and capacitor C1: one end of switch S2 is connected to the upper plate of capacitor C1, and the other end is connected to the source of MP1; one end of switch S4 is connected to the lower plate of capacitor C1, and the other end is connected to the source of MN1.
[0010] As an alternative technical solution, the first-stage preamplifier also includes switches S1 and S3: one end of switch S1 is connected to the power supply voltage VDD, and the other end is connected to the upper plate of capacitor C1; one end of switch S3 is connected to GND, and the other end is connected to the lower plate of capacitor C1.
[0011] As an optional technical solution, a second-stage latch is also included. The second-stage latch includes NMOS transistors MN3, MN4, MN5, MN6, MN7, and MN8, and PMOS transistors MP3, MP4, MP5, and MP6. The sources of MP3, MP4, MP5, and MP6 are connected to the power supply voltage VDD. The gate of MP3 is connected to the upper plate of capacitor C2b. The drains of MP3, MP5, and MN7 are connected as an inverting output VON. The gate of MP4 is connected to the upper plate of capacitor C2a. The drains of MP4, MP6, and MN8 are connected as a non-inverting output VOP. The gates of MP5 and MN5 are connected and connected to the non-inverting output VOP. The gates of MP6 and MN6 are connected and connected to the inverting output VON.
[0012] As an alternative technical solution, the source of MN7 is connected to the drain of MN3 and MN5, the source of MN8 is connected to the drain of MN4 and MN6, the gate of MN3 is connected to the lower plate of capacitor C2b, the source of MN3 is connected to the upper plate of capacitor C2a, the gate of MN4 is connected to the lower plate of capacitor C2a, the source of MN4 is connected to the upper plate of capacitor C2b, and the sources of MN5 and MN6 are connected to GND.
[0013] As an alternative technical solution, the gates of MN7 and MN8 are connected to the comparator clock signal CLK.
[0014] A second aspect of the present invention provides a control method for a comparator that eliminates dynamic misalignment caused by input common-mode fluctuations.
[0015] The control method for the comparator based on the first aspect for eliminating dynamic offset caused by input common-mode fluctuations includes a comparison phase in which control switches S2 and S4 are closed and switches S1, S3, S5, S6, S7, and S8 are open. The comparison phase includes a first comparison phase, a second comparison phase, and a third comparison phase: Compared to the first stage, under the influence of input voltages VIP and VIN, the voltage of the upper plate of C2a and C2b increases and the voltage of the lower plate decreases. CLK turns on MN7 and MN8, and VOP and VON decrease simultaneously. Comparing the second stage, the different rates of voltage change between the upper and lower plates of C2a and C2b result in different degrees of conduction of MN3, MN4, MP3, and MP4, which in turn lead to different rates of decrease in VOP and VON. In the third stage, the different deceleration rates of VOP and VON cause MP5 or MP6 to conduct. If VOP decelerates faster, MP5 conducts, VON is pulled high to VDD, then MN6 conducts, and VOP is pulled low to GND, completing the comparison process. If VON decelerates faster, MP6 conducts, VOP is pulled high to VDD, then MN5 conducts, and VON is pulled low to GND, completing the comparison process.
[0016] As an alternative technical solution, a reset phase is also included: During the reset phase, control switches S1, S3, S5, S6, S7, and S8 are closed, while switches S2 and S4 are open. The voltage difference across capacitors C1, C2a, and C2b is charged to VDD, and the output node voltages VOP and VON are reset to VDD.
[0017] As an alternative technical solution, during the comparison of the first stage and the comparison of the second stage, the voltage of the upper plate of C1 gradually decreases and the voltage of the lower plate gradually increases, while the voltage of the upper plate of C2a and C2b gradually increases and the voltage of the lower plate gradually decreases; the input tubes MP1, MN1, MP2, and MN2 of the first-stage preamplifier gradually move from the saturation region into the subthreshold region.
[0018] As an alternative technical solution, when the comparator is operating in the reset phase, CLK is low and CLKB is high.
[0019] The above one or more technical solutions have the following beneficial effects: This invention provides a high-precision comparator that eliminates dynamic offset caused by input common-mode ripple. The proposed comparator circuit includes a first-stage preamplifier and a second-stage latch. By setting the input transistor of the preamplifier to operate in the subthreshold region, the dynamic offset caused by input common-mode ripple is eliminated, achieving a high-precision comparison process. Furthermore, the latch uses a design with two pairs of cross-coupled pairs, improving the speed of the third-stage comparison while reducing power consumption.
[0020] This invention eliminates comparator dynamic offset when the comparator input common-mode voltage fluctuates. The specific analysis is as follows: During comparator phase one and comparator phase two, the voltage across the upper plate of C1 gradually decreases, while the voltage across the lower plate gradually increases. Similarly, the voltages across the upper plates of C2a and C2b gradually increase, while the voltages across the lower plates gradually decrease. The input transistors MP1, MN1, MP2, and MN2 of the first-stage preamplifier gradually move from the saturation region into the subthreshold region. Based on the characteristics of the subthreshold current of MOSFETs, the comparator offset voltage is independent of the comparator input common-mode voltage, thus eliminating the dynamic offset voltage caused by comparator input common-mode voltage fluctuations and improving the comparator's accuracy.
[0021] This invention incorporates two pairs of cross-coupling pairs in the second-stage latch to improve the speed of the third comparison stage and reduce power consumption. Specifically, during the third comparison stage, if VON decreases rapidly, MP6 conducts, pulling VOP high to VDD, and MN5 conducts, pulling VON low to GND; if VOP decreases rapidly, MP5 conducts, pulling VON high to VDD, and MN6 conducts, pulling VOP low to GND. This constitutes one pair of cross-coupling pairs. Simultaneously, during the process of VOP being pulled low to GND, the voltage on the upper plate of C2b is slightly lowered, increasing the conduction degree of MP3 and accelerating the speed at which VON is pulled high to VDD; during the process of VON being pulled low to GND, the voltage on the upper plate of C2a is slightly lowered, increasing the conduction degree of MP4 and accelerating the speed at which VOP is pulled high to VDD. This constitutes the second pair of cross-coupling pairs. The combined effect of these two pairs of cross-coupling pairs reduces the time required for the third comparison stage, thus improving the comparator's speed. Furthermore, MN4 and MN6 work together to pull VOP low, and MN3 and MN5 work together to pull VON low. The current flowing from VDD to GND will not pass through MN3 and MN4, reducing the current flowing from VDD to GND in the third stage of the comparison, thereby reducing the power consumption of the comparator.
[0022] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0023] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.
[0024] Figure 1 This is a schematic diagram of the overall circuit structure of the comparator of the present invention.
[0025] Figure 2 This is a circuit diagram of the first-stage preamplifier of the comparator of the present invention.
[0026] Figure 3 This is a circuit diagram of the second-stage latch of the comparator in this invention.
[0027] Figure 4 The diagram shows the simulation results of the comparator of this invention. Detailed Implementation
[0028] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.
[0029] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations of the present invention.
[0030] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.
[0031] Example 1 This embodiment discloses a high-precision comparator that eliminates dynamic offset caused by input common-mode ripple. The overall comparator circuit proposed in this invention includes a first-stage preamplifier and a second-stage latch. The comparator's operation is divided into two stages: comparison and reset. The comparison stage is further divided into a first comparison stage, a second comparison stage, and a third comparison stage. By setting the input transistor of the preamplifier to operate in the subthreshold region, the dynamic offset caused by the comparator's input common-mode ripple is eliminated, achieving a high-precision comparison process. In addition, the latch uses a design with two pairs of cross-coupled pairs, which improves the speed of the third comparison stage while reducing power consumption. The comparator proposed in this invention uses a fully dynamic operating mode, consumes no quiescent current, and is suitable for low-power applications.
[0032] See Figure 1 As shown, this invention proposes a high-precision comparator to eliminate dynamic offset caused by input common-mode ripple, employing a cascaded design of a first-stage preamplifier and a second-stage latch. The overall circuit consists of NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, and MN8; PMOS transistors MP1, MP2, MP3, MP4, MP5, and MP6; switches S1, S2, S3, S4, S5, S6, S7, and S8; and capacitors C1, C2a, and C2b. The comparator clocks CLK and CLKB are opposite signals.
[0033] See Figure 2 The connection method for the first-stage preamplifier is as follows: The left end of switch S1 is connected to the power supply voltage VDD, and the right end is connected to the upper plate of capacitor C1. The left end of switch S2 is connected to the upper plate of capacitor C1, and the right end is connected to the source of MP1. The left end of switch S3 is connected to GND, and the right end is connected to the lower plate of capacitor C1. The left end of switch S4 is connected to the lower plate of capacitor C1, and the right end is connected to the source of MN1. The left end of switch S5 is connected to the upper plate of capacitor C2a, and the right end is connected to GND. The left end of switch S6 is connected to GND, and the right end is connected to the drain of MP2. The left end of switch S7 is connected to the drain of MN1, and the right end is connected to the power supply voltage VDD. The left end of switch S8 is connected to the power supply voltage VDD, and the right end is connected to the drain of MN2.
[0034] The drains of MP1 and MN1 are connected to the upper and lower plates of capacitor C2a, respectively, and the gates of MP1 and MN1 are connected to the non-inverting input terminal VIP. The source of MP2 is connected to the source of MP1, and the source of MN2 is connected to the source of MN1. The drains of MP2 and MN2 are connected to the upper and lower plates of capacitor C2b, respectively, and the gates of MP2 and MN2 are connected to the inverting input terminal VIN.
[0035] See Figure 3 The connection method for the second-stage latch is as follows: The sources of MP3, MP4, MP5, and MP6 are connected to the power supply voltage VDD. The gate of MP3 is connected to the upper plate of capacitor C2b. The drains of MP3, MP5, and MN7 are connected as the inverting output VON. The gate of MP4 is connected to the upper plate of capacitor C2a. The drains of MP4, MP6, and MN8 are connected as the non-inverting output VOP. The gates of MP5 and MN5 are connected to the non-inverting output VOP. The gates of MP6 and MN6 are connected to the inverting output VON. The gates of MN7 and MN8 are connected to the comparator clock signal CLK. The source of MN7 is connected to the drains of MN3 and MN5. The source of MN8 is connected to the drains of MN4 and MN6. The gate of MN3 is connected to the lower plate of capacitor C2b. The source of MN3 is connected to the upper plate of capacitor C2a. The gate of MN4 is connected to the lower plate of capacitor C2a. The source of MN4 is connected to the upper plate of capacitor C2b. The sources of MN5 and MN6 are connected to GND.
[0036] The comparator clocks CLK and CLKB are inverted signals. CLKB is obtained by inverting CLK; that is, when CLK is high, CLKB is low, and when CLK is low, CLKB is high. When CLK is high, switches S2 and S4 are closed; when CLK is low, switches S2 and S4 are open. When CLKB is high, switches S1, S3, S5, S6, S7, and S8 are closed; when CLKB is low, switches S1, S3, S5, S6, S7, and S8 are open.
[0037] When the comparator is operating in the comparison phase, CLK is high and CLKB is low.
[0038] The overall circuit operation during the comparison phase is as follows: Switches S2 and S4 are closed, while switches S1, S3, S5, S6, S7, and S8 are open.
[0039] Compared to the first stage, under the influence of input voltages VIP and VIN, the voltage of the upper plate of C2a and C2b increases, while the voltage of the lower plate decreases. CLK turns on MN7 and MN8, and VOP and VON decrease simultaneously.
[0040] Comparing the second stage, the different rates of voltage change between the upper and lower plates of C2a and C2b result in different conduction levels of MN3, MN4, MP3, and MP4, which in turn lead to different rates of decrease in VOP and VON.
[0041] In the third stage, the different deceleration rates of VOP and VON cause MP5 or MP6 to conduct. If VOP decelerates faster, MP5 conducts, VON is pulled high to VDD, then MN6 conducts, and VOP is pulled low to GND, completing the comparison process. If VON decelerates faster, MP6 conducts, VOP is pulled high to VDD, then MN5 conducts, and VON is pulled low to GND, completing the comparison process.
[0042] Since the offset of the second-stage latch is attenuated by the gain of the first-stage preamplifier, the offset of the two-stage comparator is mainly determined by the offset of the first-stage preamplifier. During comparison phase one and comparison phase two, the voltage of the upper plate of C1 gradually decreases, and the voltage of the lower plate gradually increases; the voltage of the upper plate of C2a and C2b gradually increases, and the voltage of the lower plate gradually decreases. The input transistors MP1, MN1, MP2, and MN2 of the first-stage preamplifier gradually move from the saturation region into the subthreshold region.
[0043] Based on the characteristics of the subthreshold current of the MOSFET, the offset voltage of the comparator is independent of the input common-mode voltage of the comparator, thereby eliminating the dynamic offset voltage caused by the fluctuation of the input common-mode voltage of the comparator and improving the accuracy of the comparator.
[0044] More specifically, based on the characteristics of the subthreshold current of the MOSFET, the offset voltage of the first-stage preamplifier when the input transistor operates in the subthreshold region is as shown in formula (1): (1) in, It is the equivalent threshold mismatch voltage of the input transistor of the first-stage preamplifier. It is the parasitic capacitance mismatch ratio of the output node of the first-stage preamplifier. n These are parameters related to the MOSFET manufacturing process. V T It is thermal voltage.
[0045] It can be observed that the comparator's offset voltage is independent of the comparator's input common-mode voltage, which eliminates the dynamic offset voltage caused by fluctuations in the comparator's input common-mode voltage and improves the comparator's accuracy.
[0046] During the third comparison phase, if VON decreases rapidly, MP6 conducts, pulling VOP high to VDD, and MN5 conducts, pulling VON low to GND. If VOP decreases rapidly, MP5 conducts, pulling VON high to VDD, and MN6 conducts, pulling VOP low to GND. This is one cross-coupled pair. Simultaneously, as VOP is pulled low to GND, the voltage on the upper plate of C2b is slightly lowered, increasing the conduction level of MP3 and accelerating the speed at which VON is pulled high to VDD. Similarly, as VON is pulled low to GND, the voltage on the upper plate of C2a is slightly lowered, increasing the conduction level of MP4 and accelerating the speed at which VOP is pulled high to VDD. This is the second cross-coupled pair. The combined effect of these two cross-coupled pairs reduces the time required for the third comparison phase, increasing the comparator's speed. Furthermore, MN4 and MN6 work together to pull VOP low, and MN3 and MN5 work together to pull VON low. The current flowing from VDD to GND will not pass through MN3 and MN4, reducing the current flowing from VDD to GND in the third stage of the comparison, thereby reducing the power consumption of the comparator.
[0047] See the comparator simulation results. Figure 4 The simulation conditions were set to VIP = 600.01mV and VIN = 599.99mV. Consistent with expectations, VON decreased faster than VOP. Therefore, during comparison phase three, MP6 conducts, pulling VOP high to VDD, and MN5 conducts, pulling VON low to GND. Simultaneously, as VON is pulled low to GND, the voltage UP_P on the upper plate of C2a is slightly lowered, increasing the conduction level of MP4. MP4 and MP6 work together to accelerate the process of VOP rising to VDD, and also increase the conduction level of MN5, accelerating the rate at which VON is pulled low to GND. Finally, VOP equals VDD, and VON equals GND, completing the comparator comparison.
[0048] When the comparator is operating in the reset phase, CLK is low and CLKB is high. The overall circuit operation during the reset phase is as follows: switches S1, S3, S5, S6, S7, and S8 are closed, and switches S2 and S4 are open. The voltage difference across capacitors C1, C2a, and C2b is charged to VDD. The output node voltages VOP and VON are reset to VDD.
[0049] Example 2 This embodiment provides a control method for a comparator to eliminate dynamic misalignment caused by input common-mode fluctuations.
[0050] The control method for the comparator based on Embodiment 1 for eliminating dynamic offset caused by input common-mode fluctuations includes a comparison phase in which control switches S2 and S4 are closed and switches S1, S3, S5, S6, S7, and S8 are open. The comparison phase includes a first comparison phase, a second comparison phase, and a third comparison phase: Compared to the first stage, under the influence of input voltages VIP and VIN, the voltage of the upper plate of C2a and C2b increases and the voltage of the lower plate decreases. CLK turns on MN7 and MN8, and VOP and VON decrease simultaneously. Comparing the second stage, the different rates of voltage change between the upper and lower plates of C2a and C2b result in different degrees of conduction of MN3, MN4, MP3, and MP4, which in turn lead to different rates of decrease in VOP and VON. In the third stage, the different deceleration rates of VOP and VON cause MP5 or MP6 to conduct. If VOP decelerates faster, MP5 conducts, VON is pulled high to VDD, then MN6 conducts, and VOP is pulled low to GND, completing the comparison process. If VON decelerates faster, MP6 conducts, VOP is pulled high to VDD, then MN5 conducts, and VON is pulled low to GND, completing the comparison process.
[0051] Furthermore, it also includes a reset phase: During the reset phase, control switches S1, S3, S5, S6, S7, and S8 are closed, while switches S2 and S4 are open. The voltage difference across capacitors C1, C2a, and C2b is charged to VDD, and the output node voltages VOP and VON are reset to VDD.
[0052] Furthermore, during the comparison of the first and second stages, the voltage of the upper plate of C1 gradually decreases and the voltage of the lower plate gradually increases, while the voltage of the upper plate of C2a and C2b gradually increases and the voltage of the lower plate gradually decreases; the input transistors MP1, MN1, MP2, and MN2 of the first-stage preamplifier gradually move from the saturation region into the subthreshold region.
[0053] Furthermore, when the comparator is operating in the reset phase, CLK is low and CLKB is high.
[0054] Those skilled in the art will understand that the modules or steps of the present invention described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computer device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. The present invention is not limited to any particular combination of hardware and software.
[0055] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.
Claims
1. A comparator for eliminating dynamic offset caused by input common-mode ripple, characterized in that, The first stage preamplifier includes NMOS transistors MN1 and MN2, PMOS transistors MP1 and MP2, and capacitors C2a and C2b. The drains of MP1 and MN1 are connected to the upper and lower plates of capacitor C2a, respectively, and the gates of MP1 and MN1 are connected to the non-inverting input terminal VIP; the source of MP2 is connected to the source of MP1, the source of MN2 is connected to the source of MN1, the drains of MP2 and MN2 are connected to the upper and lower plates of capacitor C2b, respectively, and the gates of MP2 and MN2 are connected to the inverting input terminal VIN. It also includes switches S5, S6, S7, and S8: one end of switch S5 is connected to the upper plate of capacitor C2a, and the other end is connected to GND; one end of switch S6 is connected to GND, and the other end is connected to the drain of MP2; one end of switch S7 is connected to the drain of MN1, and the other end is connected to the power supply voltage VDD; one end of switch S8 is connected to the power supply voltage VDD, and the other end is connected to the drain of MN2.
2. The comparator for eliminating dynamic offset caused by input common-mode ripple as described in claim 1, characterized in that, The first-stage preamplifier also includes switches S2 and S4 and capacitor C1: one end of switch S2 is connected to the upper plate of capacitor C1 and the other end is connected to the source of MP1; one end of switch S4 is connected to the lower plate of capacitor C1 and the other end is connected to the source of MN1.
3. The comparator for eliminating dynamic offset caused by input common-mode ripple as described in claim 1, characterized in that, The first-stage preamplifier also includes switches S1 and S3: one end of switch S1 is connected to the power supply voltage VDD, and the other end is connected to the upper plate of capacitor C1; one end of switch S3 is connected to GND, and the other end is connected to the lower plate of capacitor C1.
4. The comparator for eliminating dynamic offset caused by input common-mode ripple as described in claim 1, characterized in that, It also includes a second-stage latch, which includes NMOS transistors MN3, MN4, MN5, MN6, MN7, and MN8, and PMOS transistors MP3, MP4, MP5, and MP6. The sources of MP3, MP4, MP5, and MP6 are connected to the power supply voltage VDD. The gate of MP3 is connected to the upper plate of capacitor C2b. The drains of MP3, MP5, and MN7 are connected as an inverting output VON. The gate of MP4 is connected to the upper plate of capacitor C2a. The drains of MP4, MP6, and MN8 are connected as a non-inverting output VOP. The gates of MP5 and MN5 are connected and connected to the non-inverting output VOP. The gates of MP6 and MN6 are connected and connected to the inverting output VON.
5. The comparator for eliminating dynamic offset caused by input common-mode ripple as described in claim 4, characterized in that, The source of MN7 is connected to the drain of MN3 and MN5, the source of MN8 is connected to the drain of MN4 and MN6, the gate of MN3 is connected to the lower plate of capacitor C2b, the source of MN3 is connected to the upper plate of capacitor C2a, the gate of MN4 is connected to the lower plate of capacitor C2a, the source of MN4 is connected to the upper plate of capacitor C2b, and the sources of MN5 and MN6 are connected to GND.
6. The comparator for eliminating dynamic offset caused by input common-mode ripple as described in claim 5, characterized in that, The gates of MN7 and MN8 are connected to the comparator clock signal CLK.
7. A control method for a comparator based on any one of claims 1-6 for eliminating dynamic offset caused by input common-mode ripple, characterized in that, This includes a comparison phase, during which control switches S2 and S4 are closed, and switches S1, S3, S5, S6, S7, and S8 are open. The comparison phase includes a first comparison phase, a second comparison phase, and a third comparison phase: Compared to the first stage, under the influence of input voltages VIP and VIN, the voltage of the upper plate of C2a and C2b increases and the voltage of the lower plate decreases. CLK turns on MN7 and MN8, and VOP and VON decrease simultaneously. Comparing the second stage, the different rates of voltage change between the upper and lower plates of C2a and C2b result in different degrees of conduction of MN3, MN4, MP3, and MP4, which in turn lead to different rates of decrease in VOP and VON. In the third stage, the different deceleration rates of VOP and VON cause MP5 or MP6 to conduct. If VOP decelerates faster, MP5 conducts, VON is pulled high to VDD, then MN6 conducts, and VOP is pulled low to GND, completing the comparison process. If VON decelerates faster, MP6 conducts, VOP is pulled high to VDD, then MN5 conducts, and VON is pulled low to GND, completing the comparison process.
8. The control method for a comparator to eliminate dynamic offset caused by input common-mode ripple as described in claim 7, characterized in that, It also includes a reset phase: During the reset phase, control switches S1, S3, S5, S6, S7, and S8 are closed, while switches S2 and S4 are open. The voltage difference across capacitors C1, C2a, and C2b is charged to VDD, and the output node voltages VOP and VON are reset to VDD.
9. The control method for a comparator to eliminate dynamic offset caused by input common-mode ripple as described in claim 7, characterized in that, During the comparison of the first and second stages, the voltage of the upper plate of C1 gradually decreases and the voltage of the lower plate gradually increases; the voltage of the upper plate of C2a and C2b gradually increases and the voltage of the lower plate gradually decreases; the input tubes MP1, MN1, MP2, and MN2 of the first-stage preamplifier gradually move from the saturation region into the subthreshold region.
10. The control method for a comparator to eliminate dynamic offset caused by input common-mode ripple as described in claim 8, characterized in that, When the comparator is in the reset phase, CLK is low and CLKB is high.