Full-band equalization adjustment method and circuit adapted to attenuation characteristics of different medium channels

Abstract

According to the full-band equalization adjustment method and circuit adapting to different medium channel attenuation characteristics provided by the embodiment of the invention, the tangent slope of the ascending section of the equalization frequency response curve can be freely adjusted on the premise that the power consumption and the area are not obviously increased, so that the channel loss of different media and characteristics is met. According to the invention, the equalization capability adjustment of the signal at the Nyquist frequency can be realized, and the equalization compensation capability of the medium-high frequency band can be flexibly adjusted according to different application scenes and different transmission line transmission parameter characteristics on the premise that the equalization capability at the DC gain and the Nyquist frequency is not changed. The problem that a current continuous time linear equalizer (CTLE) is generally neglected is solved, and the eye pattern quality and the signal integrity are optimized.

Description

Technical Field

[0001] This application relates to the field of signal transmission technology, specifically to a full-band equalization adjustment method and circuit that adapts to the attenuation characteristics of different media channels. Background Technology

[0002] As wired communication speeds increase, the demands on channel bandwidth also rise. To compensate for the attenuation of high-frequency transmission caused by the low-pass characteristics of the channel, the equalization module located at the analog front-end of the receiver becomes increasingly important. Continuous-time linear equalizers (CTLEs) are a commonly used equalization technique in high-speed signal transmission, primarily used to compensate for signal distortion caused by the channel. In high-frequency signal transmission, the actual transmission channel is not ideal; the higher the frequency, the greater the attenuation. CTLEs, with their high-pass transmission characteristics, complement the low-pass characteristics of the channel, achieving frequency compensation and ultimately producing a relatively flat frequency response. However, for signal transmission quality, CTLEs can only compensate for signal at the Nyquist frequency (f...). N The signal loss at f is far from sufficient. In practical testing and applications, it has been found that signal integrity is not only affected by the length of the transmission distance, but also by the signal loss at f. N The loss at the point of origin is determined by factors that are more easily overlooked, even at the same transmission distance, f N Even with the same signal loss at the same point, the signal will still exhibit different transmission characteristics due to the varying speeds of different media, even at speeds less than f. N Different degrees of attenuation and loss occur in the mid-to-high frequency band.

[0003] With the increasing prevalence of high-speed products, the drawbacks of current equalization techniques have become widely apparent: in current CTLE applications for high-speed interfaces, the equalization characteristics and channel attenuation characteristics are not perfectly matched across the entire frequency band. During eye diagram testing, the following situation typically occurs: when exactly f... N When the compensation capability is too high or too low in the mid-to-high frequency band, it leads to increased clock jitter in the signal eye diagram and deterioration in quality.

[0004] Existing CTLE structures typically achieve the required performance using a first-order architecture. However, if the channel distance is very long and attenuation is significant, multi-stage cascading methods are used to increase equalization capability. First-order CTLE structures generally employ parallel negative feedback resistors and capacitors at the sources of the input differential pair, adjusting the equalization capability by varying the values ​​of the resistors and capacitors. A first-order CTLE contains two poles and one zero, and its frequency response curve rises from 0.1 times the frequency of the zero point with a slope of +20 dB / dec to f. N , make f NThe equalization capability at the point meets the channel attenuation requirements; a second-order CTLE is usually constructed by cascading first-order CTLEs, consisting of four poles and two zeros. Therefore, the frequency response curve will rise with a slope of +40dB / dec from 0.1 times the frequency of the second zero, which allows f to... N The equalization capability is higher, which can meet the requirements of greater channel attenuation.

[0005] Existing equilibrium compensation techniques only focus on precise compensation f N The loss on the frequency band is ignored, and the matching between the equalization compensation and loss at other frequency points within the band under this condition is neglected. Furthermore, due to the limitations of the equalization technology of the circuit itself, existing technology can only actively adjust f. N The equalization capability at one frequency point can only passively follow f at other frequencies. N The equilibrium capacity adjustment at a certain point rises or falls according to the inherent slope, and cannot be achieved at f. N Actively adjusting a single point while maintaining the equalization capability means that the quality of the eye diagram cannot be fully controlled. Even if a multi-stage CTLE structure is used to change the rising slope of its equalization frequency response curve, the adjustment range is very limited, and it consumes a lot of power and area, greatly increasing the cost. Summary of the Invention

[0006] To address or mitigate the problems in the prior art, this application provides a full-band equalization adjustment circuit that adapts to the attenuation characteristics of different media channels, including: a high-speed amplifier, an equalization peak gain adjustment module, an equalization frequency response curve rising slope adjustment module, a peak level control module, a slope level control module, and a digital linkage control module.

[0007] The input terminal of the high-speed amplifier is connected to the output terminal of the channel attenuation model to transmit the input signal, and the input terminal of the channel attenuation model is a differential signal;

[0008] The high-speed amplifier is also connected to an equalization peak gain adjustment module and an equalization frequency response curve rise slope adjustment module, respectively. The equalization peak gain adjustment module is connected to a peak level control module. The equalization peak gain adjustment module is used to adjust f. N The equalization level is adjusted so that the high-speed amplifier has multiple equalization levels, and the level is switched by the peak level control module to meet the channel loss of different lengths.

[0009] The equalization frequency response curve rising slope adjustment module is connected to the slope level control module, and both the peak level control module and the slope level control module are controlled by a digital linkage control module; the equalization frequency response curve rising slope adjustment module is used to adjust the peak level below f. NThe preset frequency band equalization compensation level allows the continuous-time linear equalizer to have multiple selectable equalization curve rise slopes, and the slope level control module switches between levels to meet the requirements of f. N Channel attenuation with the same loss but different media and characteristics;

[0010] The digital linkage control module is responsible for linking the adjustment of the peak level control module and the slope level control module to maintain a single variable and eliminate the mutual influence between peak gain and the rising slope of the equalization curve during the adjustment process.

[0011] As a preferred embodiment of this application, it also includes an input pin, an output pin, and a gear adjustment pin;

[0012] The output of the channel attenuation model is connected to the input of the high-speed amplifier via an input pin.

[0013] The high-speed amplifier outputs a differential signal through its output pin.

[0014] The digital linkage control module is connected to the gear adjustment pin and is used to input control signals to the digital linkage control module.

[0015] In a preferred embodiment of this application, the high-speed amplifier includes a first branch and a second branch;

[0016] The first branch includes a first resistor, a first NMOS transistor, and a first current source; the second branch includes a second resistor, a second NMOS transistor, and a second current source.

[0017] The common terminal between the first resistor and the second resistor is connected to the power supply; the common terminal between the first resistor and the drain of the first NMOS transistor is connected to the output pin; the common terminal between the second resistor and the drain of the second NMOS transistor is connected to the output pin; and the gates of both the first NMOS transistor and the second NMOS transistor are connected to the input pin.

[0018] The source of the first NMOS transistor is connected to one end of the first current source, and the source of the second NMOS transistor is connected to one end of the second current source; the other ends of both the first and second current sources are connected to ground.

[0019] In a preferred embodiment of this application, the equalization peak gain adjustment module includes: a first capacitor and a third resistor;

[0020] The common terminal between the source of the first NMOS transistor and the first current source is connected to the common terminal between the source of the second NMOS transistor and the second current source through a first capacitor and a third resistor.

[0021] The first capacitor and the third resistor are connected in parallel. The first capacitor is connected to the output terminal of the peak level control module, and the capacitance value of the first capacitor is controlled by the output terminal of the peak level control module.

[0022] As a preferred embodiment of this application, the equalization frequency response curve rising slope adjustment module includes a third branch and a fourth branch;

[0023] The third branch includes a third NMOS transistor and a third current source; the fourth branch includes a fourth NMOS transistor and a fourth current source;

[0024] The drain of the third NMOS transistor and the gate of the fourth NMOS transistor are both connected to the common terminal between the second resistor and the drain of the second NMOS transistor.

[0025] The gate of the third NMOS transistor and the drain of the fourth NMOS transistor are both connected to the common terminal between the first resistor and the drain of the first NMOS transistor.

[0026] The source of the third NMOS transistor is connected to one end of the third current source, and the source of the fourth NMOS transistor is connected to one end of the fourth current source.

[0027] The other ends of the third and fourth current sources are connected to the ground terminal;

[0028] The common terminal between the source of the third NMOS transistor and the third current source is connected to the common terminal between the source of the fourth NMOS transistor and the fourth current source through the second capacitor.

[0029] The second capacitor is connected to the output terminal of the slope level control module, and the capacitance value of the second capacitor is controlled by the output terminal of the slope level control module.

[0030] Secondly, embodiments of this application provide an equalization adjustment method, implemented through the circuit described in the first aspect, the method comprising:

[0031] The differential signal output from the channel attenuation model is transmitted through the high-speed amplifier.

[0032] Adjust f using the equalization peak gain adjustment module N The equalization level is adjusted so that the high-speed amplifier has multiple equalization levels, and the level is switched by the peak level control module to meet the channel loss of different lengths.

[0033] The slope adjustment module of the equalization frequency response curve is used to adjust the slope below f. NThe preset frequency band equalization compensation level allows the continuous-time linear equalizer to have multiple selectable equalization curve rise slopes, and the slope level control module switches between levels to meet the requirements of f. N Channel attenuation with the same loss but different media and characteristics;

[0034] The digital linkage control module is responsible for linking the adjustment of the peak level control module and the slope level control module to maintain a single variable and eliminate the mutual influence between peak gain and the rising slope of the equalization curve during the adjustment process.

[0035] Compared with existing technologies, this application provides a full-band equalization adjustment circuit and method that adapts to the attenuation characteristics of different media channels. Without significantly increasing power consumption and area, the slope of the tangent in the rising segment of the equalization frequency response curve can be freely adjusted to meet the channel loss requirements of different media and characteristics. This application can achieve signal f N The equalization capability can be adjusted at the point, and it can also be adjusted in terms of DC gain and f. N While maintaining the equalization capability, the equalization compensation capability in the mid-to-high frequency bands can be flexibly adjusted according to different application scenarios and transmission line transmission parameter characteristics, making up for the problem that is generally ignored in CTLE and optimizing eye diagram quality and signal integrity. Attached Figure Description

[0036] Non-limiting and non-exhaustive embodiments of the invention are described by way of example with reference to the following figures, wherein:

[0037] Figure 1 A full-band equalization adjustment circuit diagram adapted to the attenuation characteristics of different media channels is provided in the embodiments of this application;

[0038] Figure 2 The frequency response curve of the channel attenuation model provided in the embodiments of this application;

[0039] Figure 3 The full-band equalized adjustable CTLE frequency response curve provided in the embodiments of this application;

[0040] Figure 4 The frequency response curve of the output terminal after channel attenuation is compensated by CTLE is provided in the embodiments of this application;

[0041] Figure 5 Eye diagram changes during a specific adjustment process provided in the embodiments of this application;

[0042] Figure 6 The circuit diagram of the full-band equalization adjustable CTLE analog section provided in the embodiments of this application;

[0043] Figure 7The diagram shows the compensation results of CTLE for channel attenuation at different frequency response curve rising slope levels provided in the embodiments of this application. Detailed Implementation

[0044] To make the above and other features and advantages of the present invention clearer, the invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explanation to those skilled in the art and are exemplary only, not restrictive.

[0045] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0046] A problem currently overlooked in continuous-time linear equalization techniques: even at the same transmission distance, f N Even with the same signal loss at the same point, the signal will still exhibit different transmission characteristics due to the varying speeds of different media, even at speeds less than f. N Different degrees of attenuation loss occur in the mid-to-high frequency bands. That is, in the current CTLE used for high-speed interfaces, the equalization characteristics and channel attenuation characteristics are not perfectly matched across the entire frequency band. During eye diagram testing, the following situation typically occurs: when exactly f... N When the compensation capability is too high or too low in the mid-to-high frequency band, it leads to increased clock jitter in the signal eye diagram and deterioration in quality. To address this issue, the following technical solution is proposed.

[0047] Firstly, such as Figure 1 As shown, this application provides a full-band equalization adjustment circuit that adapts to the attenuation characteristics of different media channels, including: a high-speed amplifier, an equalization peak gain adjustment module, an equalization frequency response curve rising slope adjustment module, a peak level control module, a slope level control module, and a digital linkage control module.

[0048] The input terminal of the high-speed amplifier is connected to the output terminal of the channel attenuation model to transmit the input signal, and the input terminal of the channel attenuation model is a differential signal;

[0049] The high-speed amplifier is also connected to an equalization peak gain adjustment module and an equalization frequency response curve rise slope adjustment module, respectively. The equalization peak gain adjustment module is connected to a peak level control module. The equalization peak gain adjustment module is used to adjust f. NThe equalization level is adjusted so that the high-speed amplifier has multiple equalization levels, and the level is switched by the peak level control module to meet the channel loss of different lengths.

[0050] The equalization frequency response curve rising slope adjustment module is connected to the slope level control module, and both the peak level control module and the slope level control module are controlled by a digital linkage control module; the equalization frequency response curve rising slope adjustment module is used to adjust f N The preset frequency band equalization compensation level below the specified value allows for multiple selectable equalization curve rise slopes in continuous-time linear equalization. The slope level control module switches between these levels to satisfy f. N Channel attenuation with the same loss but different media and characteristics;

[0051] The digital linkage control module is responsible for coordinating the adjustment of the peak level control module and the slope level control module. It addresses the problem in specific circuit implementations where changes in the rising slope of the equalization frequency response curve cause changes in the equalization peak gain, leading to mutual interference between peak gain and equalization curve slope adjustments. It maintains a single variable, ensuring that adjusting the rising slope of the equalization frequency response curve (f...)... N The equalizer size remains unchanged, and the rising slope of the equalizer frequency response curve remains consistent when adjusting the peak gain.

[0052] As a preferred embodiment of this application, it further includes an input pin, an output pin, and a gear adjustment pin; the channel attenuation model output is connected to the high-speed amplifier input via the input pin; the high-speed amplifier output outputs a differential signal via the output pin; the digital linkage control module is connected to the gear adjustment pin and is used to input control signals to the digital linkage control module.

[0053] It should be noted that the equalization adjustment circuit provided in this application includes a high-speed amplifier, an equalization peak gain adjustment module, a peak control module, an equalization frequency response curve rise slope adjustment module, a slope control module, and a digital linkage control module. The high-speed amplifier is used for signal transmission; the equalization peak gain adjustment module is responsible for adjusting f... N The equalization level at the input allows the high-speed amplifier to have multiple equalization levels, which are switched via a peak control module to meet the channel loss requirements of different lengths; the equalization frequency response curve rise slope adjustment module is responsible for adjusting f N The following mid-to-high frequency band equalization compensation levels allow for multiple selectable equalization curve ramp slopes in continuous-time linear equalization. These ramp slopes are switched via a slope control module to meet the requirements of f. NChannel attenuation with the same loss but different media and characteristics; the digital linkage control module is responsible for linking the adjustment of the two level control modules (peak control and slope control) to solve the problem that in specific circuit implementation, the change in the equalization peak gain caused by the change in the level of the equalization frequency response curve's rising slope causes the peak gain and equalization curve slope adjustment to interfere with each other, thus maintaining a single variable and ensuring that when adjusting the rising slope of the equalization frequency response curve, f N The equalizer size remains unchanged, and the rising slope of the equalizer frequency response curve remains consistent when adjusting the peak gain.

[0054] The equalization process using the equalization adjustment method and circuit of this application is as follows (indicated by...). Figure 2 (Taking the channel attenuation model of curve ① as an example):

[0055] 1. Set the full-band adjustable equalizer CTLE of this application to the default setting. The corresponding equalizer frequency response curve at this setting is as follows: Figure 3 As shown by the solid line in the middle. It will pass through Figure 2 The high-speed differential signal (signal rate coverage range from tens of MHz to several GHz) of the mid-channel attenuation model ① is sent to the full-band equalizer adjustable CTLE for signal equalization, and the eye diagram of the output signal is observed at the output of the CTLE using an oscilloscope.

[0056] 2. Observe the eye pattern. If the eye pattern quality is poor in the current gear, such as... Figure 5 As shown in (b), the oscilloscope can clearly observe that: f N The high-frequency signal amplification at that point is insufficient (underbalanced), and is below f. N The mid-to-high frequency band signals are excessively amplified (over-equalized), indicating that after the loss from the channel attenuation model and the CTLE compensation of this invention, the signal frequency response curves at the output port are as follows: Figure 4 As shown in curve ①, a "bump" is generated in the mid-to-high frequency band, that is, the equalization of the signal across the entire frequency band does not match the current channel attenuation, resulting in the eye diagram showing a double line;

[0057] 3. Adjust the peak gain adjustment pin (peak sel) in the full-band equalizer adjustable CTLE of this application to increase the peak gain adjustment level, making f N The equalization capability is improved until the high-frequency signal in the oscilloscope eye diagram is precisely compensated, such as... Figure 5 As shown in (c), f at this time N The signal at that location has been adjusted, but the mid-to-high frequency band signal is still over-balanced;

[0058] 4. Adjust the slope sel pin in the adjustable CTLE (full-band equalizer) of this invention to increase the slope adjustment level of the frequency response curve. This increases the slope of the frequency response curve, thereby reducing the equalization capability in the mid-to-high frequency bands until it is completely complementary to the channel attenuation frequency response curve within the band of interest. The signal frequency response curve at the output port is as follows: Figure 4 As shown in curve ②. Observe the oscilloscope eye diagram again, as shown... Figure 5 As shown in (d), at this point, all signals across the frequency band are adjusted to be perfectly balanced, and the eye diagram quality reaches its optimal level.

[0059] 5. Save the gear configuration information under this channel attenuation model. If this channel attenuation model is used by default in actual application, there is no need to repeatedly adjust the gear configuration to achieve the best quality signal transmission.

[0060] 6. Similarly, if the signal is in the default setting of the full-band equalizer adjustable CTLE, after passing through... Figure 2 The channel attenuation model shown in curve ③ can achieve optimal eye diagram quality simply by adjusting the slope sel pin to the opposite setting direction while keeping the other steps the same.

[0061] like Figure 6 As shown, the high-speed amplifier includes a first branch and a second branch;

[0062] The first branch includes a first resistor RD1, a first NMOS transistor M1, and a first current source I1; the second branch includes a second resistor RD2, a second NMOS transistor M2, and a second current source I2.

[0063] The common terminal between the first resistor RD1 and the second resistor RD2 is connected to the power supply; the common terminal between the first resistor RD1 and the drain of the first NMOS transistor M1 is connected to the output pin; the common terminal between the second resistor RD2 and the drain of the second NMOS transistor M2 is connected to the output pin; and the gates of the first NMOS transistor M1 and the second NMOS transistor M2 are both connected to the input pin.

[0064] The source of the first NMOS transistor M1 is connected to one end of the first current source I1, and the source of the second NMOS transistor M2 is connected to one end of the second current source I2; the other ends of the first current source I1 and the second current source I2 are both connected to the ground terminal.

[0065] The equalization peak gain adjustment module includes: a first capacitor Cdeg and a third resistor Rdeg;

[0066] The common terminal between the source of the first NMOS transistor M1 and the first current source I1 is connected to the common terminal between the source of the second NMOS transistor M2 and the second current source I2 through the first capacitor Cdeg and the third resistor Rdeg.

[0067] The first capacitor Cdeg and the third resistor Rdeg are connected in parallel. The first capacitor Cdeg is connected to the output terminal of the peak level control module, and the capacitance value of the first capacitor Cdeg is controlled by the output terminal of the peak level control module.

[0068] The equalization frequency response curve rising slope adjustment module includes a third branch and a fourth branch;

[0069] The third branch includes a third NMOS transistor M3 and a third current source I3; the fourth branch includes a fourth NMOS transistor M4 and a fourth current source I4.

[0070] The drain of the third NMOS transistor M3 and the gate of the fourth NMOS transistor M4 are both connected to the common terminal between the second resistor RD2 and the drain of the second NMOS transistor M2.

[0071] The gate of the third NMOS transistor M3 and the drain of the fourth NMOS transistor M4 are both connected to the common terminal between the first resistor RD1 and the drain of the first NMOS transistor M1.

[0072] The source of the third NMOS transistor M3 is connected to one end of the third current source I3, and the source of the fourth NMOS transistor M4 is connected to one end of the fourth current source I4.

[0073] The other end of the third current source I3 and the fourth current source I4 is connected to the ground terminal;

[0074] The common terminal between the source of the third NMOS transistor M3 and the third current source I3 is connected to the common terminal between the source of the fourth NMOS transistor M4 and the fourth current source I4 through the second capacitor CNC.

[0075] The second capacitor CNC is connected to the output terminal of the slope gear control module, and the capacitance value of the second capacitor CNC is controlled by the output terminal of the slope gear control module.

[0076] The specific implementation architecture of the analog circuit section in the full-band equalizer adjustable CTLE is as follows: Figure 6As shown, the high-speed amplifier adopts a basic differential common-source amplifier structure, the equalization peak gain adjustment module adopts source negative feedback technology, and the equalization magnitude at fN is adjusted by adjusting the position of the first source negative feedback capacitor Cdeg; the equalization frequency response curve rising slope adjustment module adopts the method of parallel cross-coupled negative resistor at the CTLE output terminal, and the rising slope of the equalization frequency response curve is adjusted by adjusting the position of the second capacitor CNC.

[0077] It should be noted that the adjustment principle is as follows: If the frequency response curve of the full-band equalizer adjustable CTLE at the current setting is as follows... Figure 7 As shown in curve ①, its frequency response curve after compensation for channel attenuation corresponds to... Figure 7 In curve ③, if there is overcompensation in the mid-to-high frequency range, the value of the second capacitor CNC is increased. At this point, the equalization frequency response curve can achieve a higher gain at fN. To ensure the equalization capability remains unchanged, the increased equalization capability needs to be reduced back to its initial value. This requires decreasing the first capacitor Cdeg in the equalization peak gain adjustment module. At this time, while the equalization remains constant, the rising zero point of the CTLE frequency response curve shifts to a higher frequency due to the reduction of the first capacitor Cdeg. Figure 7 As shown in curve ②, this increases the rising slope of the equalization frequency response curve in the mid-to-high frequency band, significantly reducing the equalization capability in the mid-to-high frequency band, and making the frequency response curve after compensation channel attenuation correspond to... Figure 7 Curve ④ eliminates the "bump" generated in the preset frequency band; conversely, if the frequency response curve after full-band equalization adjustable CTLE compensation is undercompensated in the mid-to-high frequency band under the current condition, the value of the second capacitor CNC is reduced, and the equalization frequency response curve at f N The gain at a certain point decreases. To ensure that the equalization capability remains unchanged, the reduced equalization capability needs to be restored to its initial value. This requires adding the first capacitor Cdeg in the equalization peak gain adjustment module, which shifts the zero point of the equalization frequency response curve to a lower frequency. This reduces the rising slope in the mid-to-high frequency band, significantly improving the equalization capability of the full-band adjustable equalizer CTLE in the mid-to-high frequency band.

[0078] In the full-band equalizer adjustable CTLE digital circuit section, the peak control module and the slope control module employ digital decoding. Based on the number of equalizer peak gain adjustment and equalizer frequency response curve rising slope levels, corresponding binary decoders are compiled, enabling the input signal level adjustment pin (peak sel) to... <n:0>and slope sel <n:0>When increasing or decreasing sequentially, the equalization peak gain adjustment level and the equalization frequency response curve rising slope level can be increased or decreased sequentially; the digital linkage control module adopts digital logic control, and the logic relationship is as follows: because increasing (decreasing) the equalization frequency response curve rising slope, f N The equalization capability at the point will increase (decrease) as it increases. In order to adjust the upward slope of the curve by one step, it is necessary to increase (decrease) the slope adjustment level by one step while decreasing (increasing) the peak gain adjustment level by one step to ensure that the peak gain is consistent with that before the slope adjustment.

[0079] Secondly, embodiments of this application provide an equalization adjustment method, implemented using the circuit described in any one of the first aspects, the method comprising:

[0080] The differential signal output from the channel attenuation model is transmitted through the high-speed amplifier.

[0081] Adjust f using the equalization peak gain adjustment module N The equalization level is adjusted so that the high-speed amplifier has multiple equalization levels, and the level is switched by the peak level control module to meet the channel loss of different lengths.

[0082] The slope adjustment module of the equalization frequency response curve is used to adjust the slope below f. N The preset frequency band equalization compensation level allows the continuous-time linear equalizer to have multiple selectable equalization curve rise slopes, and the slope level control module switches between levels to meet the requirements of f. N Channel attenuation with the same loss but different media and characteristics;

[0083] The digital linkage control module is responsible for linking the adjustment of the peak level control module and the slope level control module to maintain a single variable and eliminate the mutual influence between peak gain and the rising slope of the equalization curve during the adjustment process.

[0084] This application solves the problem that CTLE's equalization capability cannot be simultaneously satisfied at various rates within the overall transmission bandwidth, in addition to being able to adjust f N In addition to its ability to maintain balance, it can also ensure that f N Under the premise of constant equalization, the rising slope of the frequency response curve can be flexibly adjusted according to the attenuation characteristics of different channels, that is, the equalization capability of the mid-to-high frequency band, so as to achieve a perfect match with the attenuation characteristics of the channel, so that the overall frequency response curve of the output end has similar gain in the frequency band of interest, thereby maximizing the optimization of eye diagram quality without consuming a lot of power consumption and area.

[0085] For a specific channel attenuation characteristic, before adjusting the mid-to-high frequency equalization capability of CTLE, the overall frequency response curve at the output end will produce a "bump" in the mid-to-high frequency band, so that the overall frequency response curve after compensation is not a flat curve in the frequency band of interest, that is, the gain difference at each frequency point is large, causing the mid-to-high frequency band signal to be overcompensated, affecting the compensation effect of CTLE and the quality of eye diagram, resulting in the eye diagram showing double lines or double "eyelids" and increased clock jitter.

[0086] This application may be submitted in f N While maintaining the equalization capability unchanged, the equalization capability of the mid-to-high frequency band of the CTLE frequency response curve, i.e., the slope of the curve's ascent, is flexibly adjusted. After adjusting the level through the digital linkage control module, the gain of the overall frequency response curve in the frequency band of interest can be made to be more uniform, giving full play to the compensation performance of CTLE and obtaining the optimal eye diagram under the current equalization capability. Its clock jitter, eyelid thickness, and other indicators are significantly better than before optimization.

[0087] The technical features of the above implementation schemes can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above implementation schemes are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] Although the invention has been described in conjunction with embodiments, those skilled in the art will understand that the above description and drawings are exemplary and not restrictive, and the invention is not limited to the disclosed embodiments. Various modifications and variations are possible without departing from the spirit of the invention.

Claims

1. A full-band equalization adjustment circuit adaptable to the attenuation characteristics of different media channels, characterized in that, include: High-speed amplifier, equalization peak gain adjustment module, equalization frequency response curve rising slope adjustment module, peak level control module, slope level control module and digital linkage control module; The input terminal of the high-speed amplifier is connected to the output terminal of the channel attenuation model to transmit the input signal, and the input terminal of the channel attenuation model is a differential signal; The high-speed amplifier is also connected to an equalization peak gain adjustment module and an equalization frequency response curve rising slope adjustment module. The equalization peak gain adjustment module is connected to a peak level control module. The equalization peak gain adjustment module is used to adjust the equalization level at the Nyquist frequency so that the high-speed amplifier has multiple equalization levels. The peak level control module switches between the levels to meet the channel loss of different lengths. The equalization frequency response curve rising slope adjustment module is connected to the slope level control module. Both the peak level control module and the slope level control module are controlled by the digital linkage control module. The equalization frequency response curve rising slope adjustment module is used to adjust the equalization compensation degree of the preset frequency band below the Nyquist frequency, so that the continuous time linear equalizer has multiple selectable equalization curve rising slopes. The slope level control module switches the level to meet the channel attenuation of the same loss but different medium and characteristics at the Nyquist frequency. The digital linkage control module is responsible for linking the adjustment of the peak level control module and the slope level control module to maintain a single variable and eliminate the mutual influence between peak gain and the rising slope of the equalization curve during the adjustment process.

2. The full-band equalization adjustment circuit adapting to the attenuation characteristics of different media channels as described in claim 1, characterized in that, It also includes input pins, output pins, and gear adjustment pins; The output of the channel attenuation model is connected to the input of the high-speed amplifier via an input pin. The high-speed amplifier outputs a differential signal through its output pin. The digital linkage control module is connected to the gear adjustment pin and is used to input control signals to the digital linkage control module.

3. The full-band equalization adjustment circuit adapting to the attenuation characteristics of different media channels as described in claim 1, characterized in that, The high-speed amplifier includes a first branch and a second branch; The first branch includes a first resistor, a first NMOS transistor, and a first current source; the second branch includes a second resistor, a second NMOS transistor, and a second current source. The common terminal between the first resistor and the second resistor is connected to the power supply; the common terminal between the first resistor and the drain of the first NMOS transistor is connected to the output pin; the common terminal between the second resistor and the drain of the second NMOS transistor is connected to the output pin; and the gates of both the first NMOS transistor and the second NMOS transistor are connected to the input pin. The source of the first NMOS transistor is connected to one end of the first current source, and the source of the second NMOS transistor is connected to one end of the second current source; the other ends of both the first and second current sources are connected to ground.

4. The full-band equalization adjustment circuit adapting to the attenuation characteristics of different media channels as described in claim 2, characterized in that, The equalization peak gain adjustment module includes: a first capacitor and a third resistor; The common terminal between the source of the first NMOS transistor and the first current source is connected to the common terminal between the source of the second NMOS transistor and the second current source through a first capacitor and a third resistor. The first capacitor and the third resistor are connected in parallel. The first capacitor is connected to the output terminal of the peak level control module, and the capacitance value of the first capacitor is controlled by the output terminal of the peak level control module.

5. The equalization adjustment circuit as described in claim 2, characterized in that, The equalization frequency response curve rising slope adjustment module includes a third branch and a fourth branch; The third branch includes a third NMOS transistor and a third current source; the fourth branch includes a fourth NMOS transistor and a fourth current source; The drain of the third NMOS transistor and the gate of the fourth NMOS transistor are both connected to the common terminal between the second resistor and the drain of the second NMOS transistor. The gate of the third NMOS transistor and the drain of the fourth NMOS transistor are both connected to the common terminal between the first resistor and the drain of the first NMOS transistor. The source of the third NMOS transistor is connected to one end of the third current source, and the source of the fourth NMOS transistor is connected to one end of the fourth current source. The other ends of the third and fourth current sources are connected to the ground terminal; The common terminal between the source of the third NMOS transistor and the third current source is connected to the common terminal between the source of the fourth NMOS transistor and the fourth current source through the second capacitor. The second capacitor is connected to the output terminal of the slope level control module, and the capacitance value of the second capacitor is controlled by the slope level control module.

6. A method for equalization adjustment, characterized in that, The method, implemented using the circuit as described in any one of claims 1 to 5, comprises: The differential signal output from the channel attenuation model is transmitted through the high-speed amplifier. The equalization level at the Nyquist frequency is adjusted by the equalization peak gain adjustment module, so that the high-speed amplifier has multiple equalization levels, and the level is switched by the peak level control module to meet the channel loss of different lengths. The equalization compensation level of the preset frequency band below the Nyquist frequency is adjusted by the equalization frequency response curve rising slope adjustment module, so that the continuous time linear equalizer has multiple selectable equalization curve rising slopes, and the slope level control module is used to switch the level to meet the channel attenuation of the same loss but different medium and characteristics at the Nyquist frequency. The digital linkage control module is responsible for linking the adjustment of the peak level control module and the slope level control module to maintain a single variable and eliminate the mutual influence between peak gain and the rising slope of the equalization curve during the adjustment process.

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