Network card management system, method and electronic device

Abstract

The application discloses a network card management system and method and electronic equipment, and relates to the technical field of network card management. The system comprises a mainboard, a network card and a preset cable. The mainboard is provided with a mainboard power supply circuit, a logic controller and a connector. The connector comprises a power supply pin connected to the mainboard power supply circuit and at least one bandwidth identification pin. The inside of the mainboard side plug of the preset cable is provided with a target circuit connection structure, and the power supply pin and the bandwidth identification pin are directly electrically connected when the cable is connected. The logic controller automatically determines the network card bandwidth allocation mode by collecting the level signal of the bandwidth identification pin and generates a configuration signal to control the network card work. The technical problem that the network card bandwidth configuration in the related art depends on software setting is solved. The automatic identification and configuration of the network card bandwidth are realized through the hardware connection topology, and the system deployment efficiency and reliability are significantly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of network card management, and in particular to a network card management system and method and electronic device. BACKGROUND

[0002] As a key network component in high-performance server systems, the PCIe (Peripheral Component Interconnect Express) link bandwidth configuration of the Open Compute Project (OCP) network card directly determines the data throughput capacity of the network interface. Currently, the setting of the OCP network card bandwidth allocation mode generally relies on manual selection and setting in the software configuration interface in the system basic input / output system (BIOS) or the remote management controller (BMC). The administrator needs to manually specify the PCIe link width (such as x16, x8, or x4 mode) at which the network card should work in the firmware setting menu according to the actual deployed cable type and bandwidth requirements.

[0003] In the related art, the firmware configuration and physical hardware connection of the server system are considered as two independent links. The physical cable is only responsible for establishing electrical connection and signal transmission, and the effectiveness of the bandwidth mode completely depends on the subsequent software configuration. This soft and hard decoupling design leads to problems such as link training failure or performance not meeting expectations due to configuration and physical connection mismatch (for example, configured as x16 mode but actually connected with a cable that only supports x8 bandwidth) in actual operation and maintenance. At the same time, every time the hardware connection is changed or the application scenario is switched, it is necessary to re-enter the management interface for manual configuration, and the operation process is cumbersome, the deployment efficiency is low, and it is seriously dependent on the professional judgment of the administrator, which easily introduces the risk of human error.

[0004] Therefore, there is a lack of a mechanism that can automatically and accurately identify and configure the bandwidth mode of the network card according to the physical connection, to meet the urgent needs of data centers for automatic deployment and efficient operation and maintenance of servers. SUMMARY

[0005] The present application provides a network card management system, method and electronic device to at least solve the technical problem of network card bandwidth configuration relying on software settings in the related art.

[0006] The present application provides a network card management system, which includes a mainboard, a network card and a preset cable, and the mainboard is provided with a mainboard power supply circuit, a logic controller and a connector:

[0007] The connector comprises a power pin connected to the power supply circuit of the mainboard and at least one bandwidth identification pin; the preset cable comprises a mainboard-side plug, and the mainboard-side plug is internally provided with a target circuit connection structure, which is used to directly electrically connect the power pin and the bandwidth identification pin on the connector when the mainboard-side plug is docked with the connector; the logic controller is in communication connection with the bandwidth identification pin, and is used to acquire the level signal on the bandwidth identification pin; the network card is in communication connection with the logic controller, and is used to receive the bandwidth configuration signal from the logic controller; in response to the logic controller acquiring the level signal on the bandwidth identification pin, the logic controller determines the bandwidth allocation mode of the network card, and generates a corresponding bandwidth configuration signal, and transmits the bandwidth configuration signal to the network card, so that the network card operates according to the bandwidth allocation mode.

[0008] The application further provides a network card management method applied to a network card management system, and the method comprises the following steps:

[0009] In response to the logic controller acquiring the level signal on the bandwidth identification pin, the logic controller compares the level signal on the bandwidth identification pin with a pre-stored mode mapping table to determine the bandwidth allocation mode corresponding to the network card; in response to determining the bandwidth allocation mode corresponding to the network card, the logic controller generates a bandwidth configuration signal carrying the bandwidth allocation mode, and sends the bandwidth configuration signal to the network card; the network card receives and analyzes the bandwidth configuration signal to acquire the bandwidth allocation mode, and operates according to the bandwidth allocation mode.

[0010] The application further provides an electronic device, which comprises a memory for storing a computer program and a processor for executing the computer program to realize the steps of the network card management method in the embodiments.

[0011] In response to the logic controller acquiring the level signal on the bandwidth identification pin, the logic controller compares the level signal on the bandwidth identification pin with a pre-stored mode mapping table to determine the bandwidth allocation mode corresponding to the network card; in response to determining the bandwidth allocation mode corresponding to the network card, the logic controller generates a bandwidth configuration signal carrying the bandwidth allocation mode, and sends the bandwidth configuration signal to the network card; the network card receives and analyzes the bandwidth configuration signal to acquire the bandwidth allocation mode, and operates according to the bandwidth allocation mode.

[0012] The network interface card (NIC) management system provided in this application includes a motherboard, a NIC, and a pre-installed cable. The motherboard has a motherboard power circuit, a logic controller, and a connector. The connector includes a power pin connected to the motherboard power circuit and at least one bandwidth identification pin. The pre-installed cable includes a motherboard-side connector with a target circuit connection structure inside. This target circuit connection structure is used to directly electrically connect the power pin and the bandwidth identification pin on the connector when the motherboard-side connector is mated with the connector. The logic controller is communicatively connected to the bandwidth identification pin to acquire the voltage level signal on the bandwidth identification pin. The NIC is communicatively connected to the logic controller to receive a bandwidth configuration signal from the logic controller. The system responds to the logic controller acquiring the voltage level signal on the bandwidth identification pin. The logic controller determines the network card's bandwidth allocation mode and generates a corresponding bandwidth configuration signal, which is then transmitted to the network card to enable it to operate according to the bandwidth allocation mode. By directly and electrically connecting the power pin and the bandwidth identification pin on the connector, the level signal from the power pin is guided to the bandwidth identification pin, thus configuring different physical connection relationships with different level signals. This achieves a hardware-level, non-software-changeable bandwidth configuration encoding, enabling automatic identification and switching of the network card's bandwidth mode. This effectively solves the technical problems of cumbersome operation, low efficiency, and error-proneness in traditional software configuration methods, achieving a hardware-level plug-and-play effect and significantly improving the automation and reliability of system deployment. Attached Figure Description

[0013] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the network card management system provided in an embodiment of this application;

[0015] Figure 2 This is a schematic diagram of the network card management system provided in another embodiment of this application;

[0016] Figure 3 This is a schematic diagram of the network card management system provided in another embodiment of this application;

[0017] Figure 4 This is a schematic diagram of the target circuit connection structure provided in an embodiment of this application;

[0018] Figure 5 A flowchart illustrating a network interface card (NIC) management method provided in an embodiment of this application;

[0019] Figure 6 A flowchart illustrating a network interface card (NIC) management method provided in another embodiment of this application;

[0020] Figure 7 A flowchart illustrating a network interface card (NIC) management method according to another embodiment of this application;

[0021] Figure 8 This is an internal structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0023] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0024] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] With the development of OCP NICs (OCP network interface cards), single-host OCP and multi-host OCP have been successively introduced. Multi-host OCP NICs support at least two CPUs and can connect up to four independent host devices. The advantages of multi-host NICs include cost savings and cabling reduction—using a single 200G NIC with multi-host functionality is cheaper than configuring a separate 100G NIC for each node, and the reduced number of cards also simplifies cabling. Furthermore, it avoids network traffic routing between processors, thereby improving data transmission efficiency.

[0026] In related technologies, the identification of multi-host OCP network cards is achieved through the BIF ID[2:0] signal (bandwidth configuration signal). This signal needs to be sent by the host to inform the OCP network card whether it is in single-host or multi-host bandwidth allocation mode. Common design implementations typically rely on different cables, i.e., setting the single-host or multi-host mode through the definition of a pin on the cable. The CPLD (Logic Controller) reads the ID status on the cable and feeds it back to the OCP network card, causing it to operate in the corresponding mode. However, in practical applications, a project often requires configuring two or more OCP cables. This not only increases the complexity of the design but also fails to meet the design requirements of product consistency and universality.

[0027] In response to the above technical problems, such as Figure 1 As shown, an embodiment of this application provides a network card management system. The system specifically includes: a motherboard, a network card, and a preset cable. The motherboard is equipped with a motherboard power circuit, a logic controller, and connectors.

[0028] The motherboard is a server motherboard or a high-performance computing platform motherboard, which integrates core components such as a central processing unit, memory slots, and a PCIe root access complex. Connectors and logic controllers, as inherent components of this motherboard, are electrically connected through wiring on the motherboard PCB.

[0029] The network interface card (NIC) is a network interface card compliant with the Open Compute Project (OCP) specifications, and can be either a small or large OCP 3.0 card. This NIC connects to a pre-installed cable via a PCIe interface on its gold fingers and has the ability to receive and parse BIF ID signals to configure its internal PCIe link width.

[0030] The logic controller can be a complex programmable logic device, a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC) with programmable capabilities. In one embodiment, the logic controller can be a low-cost CPLD with internal bandwidth identification logic and BIF ID signal generation logic, communicating with the bandwidth identifier pin and network interface card (NIC) through its general purpose input / output pins.

[0031] The motherboard power supply circuit can be a power conversion and distribution network on the motherboard that provides stable operating voltage to various components, such as a voltage regulation module, DC-DC conversion circuit, etc. The motherboard power supply circuit is connected to the power pins on the connector. In addition to powering the various components on the motherboard, the motherboard power supply circuit also acts as a signal source. In this application, the power supply is used to create a hard-coded bandwidth identifier pin level signal inside the cable and send this signal back to the logic controller of the motherboard for detection.

[0032] The connector can be an MCIO connector, an SFF-TA-1002 connector, or other high-speed cable connectors conforming to industry standards. For example...Figure 1 As shown, in a basic embodiment, the connector includes a power pin and a bandwidth identification pin. In more complex embodiments, the connector may further include a first bandwidth identification pin and a second bandwidth identification pin to support more encoding states.

[0033] The connector includes a power pin and at least one bandwidth identification pin. Figure 1 The connector shown includes a power pin and a bandwidth identification pin.

[0034] The default cable can be either an MCIO x8 cable or an OCP high-speed cable. The default cable includes a motherboard-side connector, which contains a target circuit connection structure. This target circuit connection structure directly and electrically connects the power pins and bandwidth indicator pins on the connector when the motherboard-side connector mates with the connector. The target circuit connection structure can be a copper foil trace embedded in the PCB inside the connector, or a zero-ohm resistor soldered onto the PCB inside the connector. Setting up the default cable allows for bridging the power pins and bandwidth indicator pins on the motherboard connector externally, bypassing the connector's own pin definitions, when the connector and socket are fully mated.

[0035] The pre-installed cable functionally connects the network card to the connector on the motherboard to establish a PCIe data communication channel. Simultaneously, to achieve automatic bandwidth identification, the motherboard-side connector of the pre-installed cable has a target circuit connection structure. When the cable is connected, this structure establishes an electrical path from the power pin of the motherboard connector to the bandwidth indicator pin: the motherboard power supply acts as the signal source, current flows through the power pin, the target circuit connection structure, and finally reaches the bandwidth indicator pin, thereby generating a stable, hardware-defined encoded level signal on that pin.

[0036] Specifically, such as Figure 1 As shown, when the motherboard-side connector of the preset cable mates with the connector, its internal target circuit connection structure physically bridges the connector's power pin and bandwidth indicator pin. This allows a high level (e.g., 3.3V) on the power pin to be directly applied to the bandwidth indicator pin, fixing its potential high as a stable signal representing the bandwidth configuration mode. This hard-wired approach establishes a fixed electrical state, ensuring that the level signals subsequently acquired by the logic controller are stable and clearly coded signals, rather than fluctuating or uncertain states.

[0037] The logic controller communicates with the bandwidth identifier pin to acquire the voltage level signal on the pin. The network interface card (NIC) also communicates with the logic controller to receive bandwidth configuration signals from it. In response to the logic controller acquiring the voltage level signal on the bandwidth identifier pin, it determines the NIC's bandwidth allocation mode, generates a corresponding bandwidth configuration signal, and transmits this signal to the NIC to enable it to operate according to the bandwidth allocation mode. The logic controller can automatically identify and configure the bandwidth mode by monitoring the voltage level on the bandwidth identifier pin.

[0038] Upon system initialization or cable connection event triggering, the logic controller acquires the hard-coded level signal defined by the preset cable on the bandwidth identification pin. By recognizing and judging this signal, the logic controller determines the precise bandwidth allocation mode that the network interface card (NIC) should activate and generates the corresponding bandwidth configuration control signal, which is then sent to the NIC. The NIC ultimately responds to this instruction, completing the switching of the internal PCIe link, thus achieving plug-and-play automatic bandwidth configuration without software intervention.

[0039] This application's network card management system employs an innovative hardware coding mechanism, which automatically identifies bandwidth modes through a pre-defined target circuit connection structure within the cable. This structure, when the cable is connected to the connector, physically establishes an electrical connection between the power pin and a specific bandwidth identifier pin, forming a stable voltage level signal.

[0040] Related technologies generally employ component parameter encoding, relying on specific parameter values ​​of independent components such as encoding resistors and memory chips to transmit information. These solutions require complex signal processing circuits, including analog-to-digital converters or digital communication interfaces, to obtain configuration information by measuring resistance values ​​or reading chip storage. In contrast, this solution innovatively adopts a connection topology encoding mechanism, where configuration information is carried inherently through the physical connections between pins. This encoding method eliminates the need for independent encoding components, utilizing only the pre-defined circuit traces within the connector to achieve information encoding, realizing the technical effect of "connection is configuration."

[0041] Furthermore, the encoding schemes in related technologies include a complete encoding-transmission-decoding chain in their hardware architecture: encoding elements generate signals, transmission lines transmit signals, and control chips decode signals. This architecture inevitably introduces problems such as signal integrity, component accuracy, and communication reliability.

[0042] This application integrates encoding functionality into the physical connection process through a target circuit connection structure, forming a unique connection-identification architecture. This structure simultaneously completes information encoding while establishing the physical connection, eliminating the signal transmission and parsing stages found in traditional architectures and fundamentally avoiding the corresponding technical risks. The simple physical short-circuit structure avoids traditional risks such as analog signal attenuation and digital communication errors, eliminating the need for dedicated encoding components and related signal processing circuits, significantly reducing system complexity and manufacturing costs. Encoding is completed instantly upon connection establishment, eliminating the need for time-consuming processes such as signal sampling and data parsing. Furthermore, digital level signals have stronger anti-interference capabilities compared to analog measurements or serial communication. This innovative hardware encoding method achieves a fundamental shift in network card bandwidth configuration from software settings to hardware identification, providing server systems with a more reliable, efficient, and low-cost automated configuration solution.

[0043] Please see Figure 2 The connector of this application may include a power pin, a first bandwidth identification pin, and a second bandwidth identification pin: the first end of the first bandwidth identification pin is connected to the target circuit connection structure, and the second end of the first bandwidth identification pin is connected to the logic controller; the target circuit connection structure is used to directly electrically connect the power pin on the connector to the first bandwidth identification pin when the motherboard side plug is mated with the connector; the first end of the second bandwidth identification pin is connected to the reference ground pin, and the second end of the second bandwidth identification pin is connected to the logic controller; the logic controller determines the bandwidth allocation mode according to the combination of the level signals on the second end of the first bandwidth identification pin and the second end of the second bandwidth identification pin.

[0044] The first bandwidth identifier pin can refer to the ID0 pin defined on the MCIO connector. Its key feature is that, through the internal circuit connection structure of the cable, it is shorted to the power supply pin during connection, thus being fixed in a high-level state.

[0045] The second bandwidth identifier pin can refer to the ID1 pin defined on the MCIO connector. Its first end is connected to the reference ground during motherboard design via pull-down resistors or other means, making it low by default, or its level state is determined by the type of device being connected.

[0046] The reference ground pin can be the ground pin on the connector, providing a common zero-potential reference point for the circuit.

[0047] A level signal combination can refer to a binary code composed of the level states (high level '1' or low level '0') on the first bandwidth identifier pin (ID0) and the second bandwidth identifier pin (ID1). For example, "10", "11", "00", etc. Different combinations correspond to different bandwidth allocation modes. The bandwidth allocation mode refers to the allocation method of PCIe channels, such as x16, x8x8, x4x4x4x4, etc., and also includes the logical determination result of whether it is a single-host OCP mode or a multi-host OCP mode.

[0048] This application configures the connector with additional power pins (e.g., 3.3V), a first bandwidth identifier pin, a second bandwidth identifier pin, and a reference ground pin (GND), in addition to the conventional pins used for transmitting PCIe data signals and power supply. This provides support for identifying multiple bandwidth allocation modes. By permanently shorting the power pin and the first bandwidth identifier pin at the cable end, and simultaneously connecting the second bandwidth identifier pin to the reference ground, a stable and unique hardware-level electrical identifier is created for the network card. This unique pin connection generates two defined level signals, constituting the configured identification mechanism. The logic controller determines the mode by reading the specific level signal combination formed by these two pins. This mechanism physically ensures the accuracy and consistency of the identification signal, making it completely unaffected by software configuration or system state. This not only effectively avoids identification errors caused by software misconfiguration or driver incompatibility, significantly improving the reliability of the server system and its compatibility with various network cards, but also enables the system to accurately distinguish between single-host and multi-host bandwidth allocation modes and ensures correct network card initialization. This ensures that the BIOS receives accurate and error-free connection information, enabling it to accurately display the device silkscreen (such as CPU0_PE3_OCP0) in the management interface. This clearly distinguishes the device from ordinary PCIe Riser cards (such as those displaying 1111 or 0101), providing administrators with an intuitive and reliable system topology view and greatly improving the efficiency of device maintenance and fault diagnosis.

[0049] Furthermore, by unifying the cable interfaces for single-host and multi-host network cards, cable sharing is achieved, fundamentally solving the design cumbersomeness and complex bill of materials problems caused by the need to configure multiple cables with different pin definitions in traditional solutions. This standardized design greatly simplifies the initial design complexity of the system and reduces maintenance failures caused by cable mismatches later on. In addition, the DC level detection mechanism adopted in this application features stable signal and strong anti-interference capabilities, exhibiting higher robustness compared to identification schemes based on complex communication protocols or high-frequency signals. The level signal is directly read by the logic controller after conversion, with rapid response. All decision-making logic is completed at the hardware or firmware level, ensuring that the system can quickly and accurately complete device identification and configuration during the startup phase, laying a solid foundation for stable system operation.

[0050] The network card management system provided in this application also includes a basic input / output system, a central processing unit, a first expansion chip, and a second expansion chip: the central processing unit is communicatively connected to the basic input / output system.

[0051] The Basic Input / Output System (BIOS) is the firmware on the server motherboard, responsible for hardware initialization and configuration during the initial system startup, and displaying hardware topology information (silk screen) in the user interface.

[0052] The central processing unit (CPU) is the core computing and control unit of the system. In this system, it specifically refers to the CPU working in conjunction with the BIOS and connecting to peripheral chips through the system management bus (such as SMBus / I2C) to ultimately control the generation of display information.

[0053] The first expansion chip is a general-purpose input / output (GPIO) expander chip (such as PCA9555, CA9555, etc.), which is connected to the central processing unit via the system management bus. Its function is to acquire the bandwidth indicator pin level on a set of connectors and report the status to the CPU / BIOS.

[0054] The second expansion chip can be a GPIO expander chip with the same model and function as the first expansion chip, but it is connected to the logic controller (CPLD) via a bus. Its function is to acquire the bandwidth indicator pin level on another set of connectors and report the status to the CPLD.

[0055] Specifically, the first end of the first expansion chip is connected to the central processing unit (CPU), and the second end of the first expansion chip is connected to the bandwidth identification pin corresponding to the first connector group; the first end of the second expansion chip is connected to the logic controller, and the second end of the second expansion chip is connected to the bandwidth identification pin corresponding to the second connector group; the first expansion chip and the second expansion chip are respectively used to transmit the level signal of the bandwidth identification pin to the CPU and the logic controller; the logic controller determines the bandwidth allocation mode based on the level signal of the bandwidth identification pin obtained from the second expansion chip, and sends the bandwidth allocation mode to the CPU; the CPU verifies based on the level signal obtained from the first expansion chip, or generates corresponding display information according to the bandwidth allocation mode sent by the logic controller.

[0056] Please see Figure 3The network interface card (NIC) management system provided in this application features optimized and integrated hardware architecture, primarily comprising a basic input / output system (PIS), a central processing unit (CPU), a logic controller, and a first expansion chip and a second expansion chip connected to them respectively. The CPU communicates with the PIS, jointly responsible for system configuration and user interface display. The first terminal of the first expansion chip is connected to the CPU via a system management bus (e.g., I2C), while its second terminal is connected to all bandwidth indicator pins corresponding to the first connector group. Similarly, the first terminal of the second expansion chip is connected to the logic controller, and its second terminal is connected to all bandwidth indicator pins corresponding to the second connector group.

[0057] During operation, the first and second expansion chips act as signal acquisition devices, transmitting the bandwidth indicator pin level status of their respective connector groups to the central processing unit (CPU) and logic controller (Controller) in real time. The logic controller, as the core decision-making unit, quickly determines the current bandwidth allocation mode (e.g., single-host x16 or multi-host mode) based on the level signal combination acquired from the second expansion chip. Subsequently, the logic controller sends this determined mode information to the CPU. Upon receiving this mode information, the CPU performs dual verification and information generation: it can either perform cross-verification based on the level signals independently acquired from the first expansion chip to ensure the accuracy of the mode determination, or it can directly drive the BIOS to generate corresponding and accurate device connection display information (silk screen) based on the authoritative mode result sent by the logic controller, and present it on the management interface.

[0058] The first connector group includes a first connector and a second connector, and the second connector group includes a third connector and a fourth connector. The first connector and the second connector together constitute and are electrically connected to the same first high-speed peripheral component interconnect port of a central processing unit. The third connector and the fourth connector together constitute and are electrically connected to the same second high-speed peripheral component interconnect port of a central processing unit. The first connector, the second connector, the third connector, and the fourth connector each include a power pin connected to the motherboard power circuit and at least one bandwidth identification pin.

[0059] The first connector group refers to a set of two MCIO x8 connectors allocated to a specific PCIe port of the same CPU. For example, the PCIe x16 port of CPU0 is broken down into two x8 connectors.

[0060] The second connector group is similar to the first connector group, but refers to a set of two MCIO x8 connectors used by a PCIe port allocated to another CPU.

[0061] The first high-speed peripheral component interconnect port, also known as the first PCIe port, can be a PCIe root port provided by the central processing unit. Physically, it is usually x16 link width, but on the motherboard it is broken down into two MCIO x8 connectors (i.e., the first connector group).

[0062] The second high-speed peripheral component interconnect port, also known as the second PCIe port, can be another PCIe root port, which is also decomposed into two MCIO x8 connectors (i.e., the second connector group).

[0063] This application clearly defines the physical grouping and electrical connections of the connectors. Specifically, the first connector group includes a first connector and a second connector, which together constitute and are electrically connected to a complete first high-speed peripheral component interconnect port (e.g., a PCIe x16 port) of the same central processing unit. Similarly, the second connector group includes a third connector and a fourth connector, which together constitute and are electrically connected to a second high-speed peripheral component interconnect port of another central processing unit. Thus, each of the first, second, third, and fourth connectors includes not only power pins connected to the motherboard power circuitry to supply power to the connected device, but also at least one bandwidth identification pin. This consistent pin design enables the system to monitor and identify the status of each independent x8 link unit through an expansion chip, providing a solid foundation for accurate determination of the global mode.

[0064] The target circuit connection structure may include a first conductive path, a second conductive path, and an insulating barrier: the first conductive path is fixedly connected between a power supply pin and a first bandwidth identifier pin; one end of the second conductive path is connected to the power supply pin, and the other end is configured as a free end. In response to the insulating barrier being in a first position, the free end of the second conductive path is isolated from the second bandwidth identifier pin. The logic controller controls the network card to operate in a default bandwidth mode based on a first level combination on the first and second bandwidth identifier pins. In the default bandwidth mode, all functional ports of the network card share the total bandwidth of a single connector link. That is, in this mode, all network functional ports on the network card (such as two 100G ports) share the entire bandwidth of the single x8 PCIe link they are connected to.

[0065] In response to the removal of the insulating barrier or its position in the second location, the free end of the second conductive path makes electrical contact with the second bandwidth identification pin. The logic controller, based on a second level combination on the first and second bandwidth identification pins, controls the network interface card (NIC) to operate in a guaranteed bandwidth mode. In this mode, a designated functional port of the NIC is allocated half of the bandwidth of a single connector exclusively, while the remaining ports share the other half of the bandwidth. That is, in this mode, a designated functional port of the NIC (such as the first 100G port) is allocated exclusive, fixed x4 PCIe bandwidth, while the remaining ports share the remaining x4 bandwidth. This provides a deterministic, congestion-free bandwidth guarantee for critical services.

[0066] The first conductive path is a fixed conductive line (such as PCB copper foil or wire) that permanently connects the power pin to the first bandwidth identifier pin. This path is responsible for establishing the basic identification identifier of the network card.

[0067] The second conductive path is a switchable conductive line. One end is fixedly connected to the power supply pin, and the other end is a free end (i.e., an unfixed end). Its on / off state determines whether a high-level signal is transmitted to the second bandwidth indicator pin.

[0068] The insulating barrier can be a movable or removable component made of insulating material (such as a plastic spacer inside a jumper cap or an insulating slider in a microswitch). Its position determines whether the free end of the second conductive path can contact the second bandwidth marking pin.

[0069] The first position refers to the state in which the insulating barrier is inserted or slid into place, at which point it physically blocks the electrical connection between the second conductive path and the second bandwidth indicator pin.

[0070] The second position refers to the state in which the insulating barrier is removed or moved to another position, at which point the free end of the second conductive path can make electrical contact with the second bandwidth marking pin.

[0071] The first level combination is a level state consisting of a first bandwidth identifier pin that is fixedly pulled high and a second bandwidth identifier pin that is defaulted (usually pulled down) when the insulating barrier is in the first position (e.g., ID0=1, ID1=0).

[0072] The second level combination is a level state consisting of a first bandwidth identifier pin that is fixedly pulled high and a second bandwidth identifier pin that is also pulled high by the second conductive path when the insulating barrier is in the second position (e.g., ID0=1, ID1=1).

[0073] Please see Figure 4This application provides a configurable target circuit connection structure that enables the same physical network card to switch between different bandwidth allocation modes through simple physical operations.

[0074] The core of the target circuit connection structure lies in three paths: a fixed first conductive path, a switchable second conductive path, and an insulating barrier to control on / off switching. The first conductive path is permanently connected between the power supply pin (e.g., 3.3V) and the first bandwidth identifier pin (ID0), ensuring that the first bandwidth identifier pin is always pulled high, forming the basic identification signal of the network card. One end of the second conductive path is also connected to the power supply pin, while the other end is a free end; whether it is connected to the second bandwidth identifier pin is controlled by the position of the insulating barrier. This structure achieves mode switching through the following two states:

[0075] When the insulating barrier is in the first position, it physically isolates the free end of the second conductive path from the second bandwidth indicator pin. At this time, the first bandwidth indicator pin is high (1), while the second bandwidth indicator pin remains at its default low level (0), forming a first level combination (e.g., 1-0). After the logic controller (CPLD) reads this combination, it determines that the network card should operate in the default bandwidth mode. In this mode, the total bandwidth of a single x8 PCIe link connected to the network card will be dynamically shared by all functional ports on the network card (e.g., two 100G Ethernet ports).

[0076] When the insulating barrier is removed or moved to the second position, the free end of the second conductive path establishes electrical contact with the second bandwidth indicator pin, causing the second bandwidth indicator pin to be pulled high. At this time, both the first bandwidth indicator pin and the second bandwidth indicator pin are high, forming a second level combination (e.g., 1-1). After the logic controller reads this combination, it determines that the network card should operate in guaranteed bandwidth mode. In this mode, the system allocates a dedicated bandwidth equivalent to half the bandwidth of a single connector (i.e., PCIe x4) to a specific functional port on the network card (e.g., port 0), thereby providing a guaranteed performance for the traffic of that port; the remaining ports on the network card share the remaining x4 bandwidth.

[0077] This provides users with an extremely simple, low-cost, and reliable hardware-level bandwidth configuration solution. Without requiring complex software settings in the BIOS or operating system, network service quality (QoS) policies can be pre-configured at the hardware level simply by physically changing the position of the insulating barriers on the cable or network card. This is suitable for application scenarios with strict bandwidth determinism requirements.

[0078] Please see Figure 5 This application also provides a network interface card (NIC) management method, applied to a NIC management system, the method comprising:

[0079] Step 101: In response to the logic controller receiving the level signal on the bandwidth identifier pin, the logic controller compares the level signal on the bandwidth identifier pin with the pre-stored mode mapping table to determine the bandwidth allocation mode corresponding to the network card.

[0080] When the network card is plugged into the connector and powered on, the logic controller immediately acquires the level signals of the bandwidth identification pins (such as the first bandwidth identification pin (ID0) and the second bandwidth identification pin (ID1)) on the connector. Specifically, each MCIO x8 connector on the motherboard defines two bandwidth ID pins, ID[1:0]; two MCIO x8 connectors form a complete PCIe x16 port for the CPU; the two bandwidth allocation ID pins on the MCIO connector with OCP requirements are brought out; the corresponding ID[1:0] signals are flipped by a MOSFET and connected to the first expansion chip connected to the CPU system management bus and the second expansion chip connected to the CPLD, respectively. The logic controller compares this read real-time level signal with an internally stored mode mapping table. This mapping table defines the correspondence between different combinations of level signals and specific bandwidth allocation modes (such as single-host x8, multi-host x16, guaranteed bandwidth mode, etc.). By looking up the table, the logic controller can accurately determine the bandwidth allocation mode that the currently connected network card should use.

[0081] In one specific implementation, the comparison process includes: acquiring the real-time level states of the first bandwidth identifier pin and the second bandwidth identifier pin in parallel through the general-purpose input / output interface of the logic controller, and combining the acquired first pin level states and the second pin level states into a set of binary coded signals; matching the binary coded signals with a pre-stored mode mapping table inside the logic controller, the mode mapping table recording the correspondence between different binary codes and different bandwidth allocation modes; and determining the bandwidth allocation mode corresponding to the current binary coded signal based on the matching query result.

[0082] Specifically, the logic controller synchronously and in parallel acquires the real-time level states of the first bandwidth identifier pin and the second bandwidth identifier pin through its general purpose input / output (GPIO) interface. This parallel acquisition method ensures the temporal consistency of the two signal states. Subsequently, the controller combines the acquired first pin level state (such as a high level "1" or a low level "0") with the second pin level state to form a unique binary encoded signal (such as "10" or "11").

[0083] For example, specific matching rules are defined for identifying the bandwidth allocation pattern of Open Compute Project (OCP) network interface cards (NICs) for Complex Programmable Logic Devices (CPLDs). The following explanation uses Peripheral Component Interconnect Port 3 (PE3) of CPU0 and PE3 port of CPU1 as examples:

[0084] Central Processing Unit 1 (CPU1):

[0085] The first bandwidth identifier pin (ID0) and the second bandwidth identifier pin (ID1) of the first x8 MCIO connector (PE3A) of its PE3 port are connected to the fourth bit (P04) and the fifth bit (P05) of the general purpose input / output (GPIO) expander chip connected to the CPLD system management bus.

[0086] The first bandwidth identifier pin (ID0) and the second bandwidth identifier pin (ID1) of the second x8 MCIO connector (PE3C) of its PE3 port are connected to the sixth bit (P06) and the seventh bit (P07) pins of the port zero of the extender chip.

[0087] Central Processing Unit Zero (CPU0):

[0088] The first bandwidth identifier pin (ID0) and the second bandwidth identifier pin (ID1) of the first x8 MCIO connector (PE3A) of its PE3 port are connected to the zero bit (P00) and the first bit (P01) pin of port zero of the extender chip.

[0089] The first bandwidth identifier pin (ID0) and the second bandwidth identifier pin (ID1) of the second x8 MCIO connector (PE3C) of its PE3 port are connected to the second bit (P02) and the third bit (P03) of port zero of the extender chip.

[0090] Based on the above connection relationships, the matching rules are defined as follows:

[0091] When the logic controller reads that the pin status from the fourth bit (P04) to the zeroth bit (P00) of port zero is a binary sequence 1010, it determines that the Open Compute Project (OCP) network card is working in Single-Host x16 mode.

[0092] When the status of the first bit (P01) and the zeroth bit (P00) of port zero is read as 10, and the status of the fifth bit (P05) and the fourth bit (P04) of port zero is also 10, it is determined that the network card is working in Multi-Host x16 mode.

[0093] Next, the logic controller matches this binary encoded signal against a pre-stored pattern mapping table in its internal non-volatile memory. This mapping table, as a predefined dictionary, meticulously records the fixed correspondence between different binary codes and various bandwidth allocation modes. Finally, based on the matching query result, the logic controller directly determines the bandwidth allocation mode corresponding to the current binary encoded signal. By setting up a hardware-based lookup table-based decision-making mechanism, the decision-making speed is extremely fast and does not depend on upper-layer software, thus ensuring the accuracy of pattern recognition and the configuration efficiency during system startup.

[0094] In one embodiment, after the logic controller sends a bandwidth configuration signal to the network card, the logic controller and the basic input / output system interact according to a predefined communication protocol to collaboratively execute the power-on initialization sequence of the network card. Specifically, the logic controller is responsible for enabling different power rails of the network card sequentially according to the bandwidth allocation mode. The basic input / output system is responsible for performing link training on the network card after the logic controller has completed powering on all power rails and enabled the network card's main power supply. The logic controller is also used to drive the network card's status indicator light after receiving a training completion indication from the basic input / output system, indicating that the network card has entered normal operating status.

[0095] Specifically, after the logic controller sends a bandwidth configuration signal to the network card, the two enter a coordinated power-on sequence. As the core of hardware power timing management, the logic controller must enable different power rails of the network card sequentially according to the determined bandwidth allocation mode. For example, it must first enable the standby power, then enable the core power and main power, thereby mitigating the risk of equipment damage due to improper power-on sequence at the hardware level. Subsequently, the entire initialization process is clearly divided into two stages: hardware power management and software link configuration. After the logic controller completes the power-on of all power rails and finally enables the network card's main power, the basic input / output system intervenes and performs PCIe link training on the network card. This timing design ensures that the network card's hardware is fully power-ready before starting complex data link negotiation. Finally, the system forms a closed-loop control through status indicator linkage. After receiving the link training completion indication from the basic input / output system, the logic controller drives the network card's status indicator light to enter normal working state (e.g., lighting up green), thus directly linking the training results at the software layer with the visual indications at the hardware layer, providing users with accurate status diagnostics. By sequencing and protocolizing the interaction actions between the CPLD and BIOS during the initialization process, a reliable system-level collaboration mechanism is built, which effectively improves the success rate of hardware initialization and the overall maintainability of the system.

[0096] Please see Figure 6 The flowchart specifically illustrates the hardware operation sequence for the CPLD to identify the bandwidth allocation mode in step 101:

[0097] The system first reads the network card's (NIC) presence information via the CPLD. After confirming that the NIC is correctly inserted and in place, the CPLD sends an enable signal to activate the NIC's standby power supply. Upon successfully receiving a good standby power signal from the power management circuit, the system enters the crucial mode recognition phase. At this time, the pre-connected cable has permanently shorted the first bandwidth identifier pin (ID0) to the 3.3V power supply pin at its connector end, thus fixing ID0 at a high level. This signal is then transmitted to the corresponding input pin of the GPIO expander chip after being toggled by the MOS transistor circuit on the motherboard. The CPLD reads the status information of all bandwidth identifier pins on the expander chip via bus protocols such as I2C and matches the read binary code with the internally stored recognition rules. Upon successful matching, the CPLD determines the bandwidth allocation mode (e.g., single-host x16 or multi-host mode) that the NIC should operate in and immediately returns the corresponding mode command to the OCP NIC via the BIF [2:0] signal lines. After the network interface card (NIC) bandwidth allocation mode is successfully configured, the CPLD continues to trigger and complete the power-on sequence of the NIC's main power supply according to the VPP communication protocol, and finally drives the indicator lights on the NIC to indicate its normal working status. This process ensures fully automated hardware initialization from device detection and pattern recognition to power management and status indication.

[0098] Step 102: In response to determining the bandwidth allocation mode corresponding to the network card, the logic controller generates a bandwidth configuration signal carrying the bandwidth allocation mode and sends the bandwidth configuration signal to the network card.

[0099] Once the logic controller determines the bandwidth allocation mode, it generates a bandwidth configuration signal carrying this mode information. Specifically, the CPLD obtains the bandwidth allocation ID signal transmitted from the OCP cable end through the extender chip, identifies the currently configured network card bandwidth allocation mode by matching it with predefined ID recognition rules, and returns a BIFID[2:0] signal to the network card to notify the OCP network card of which mode it should operate in. This signal is sent to the network card through a specific communication interface (e.g., the BIF[2:0] signal line) to inform the network card how to configure its internal PCIe channels and bandwidth resources.

[0100] Step 103: The network card receives and parses the bandwidth configuration signal, obtains the bandwidth allocation mode, and operates according to the bandwidth allocation mode.

[0101] The network interface card (NIC) receives and parses the bandwidth configuration signal from the logic controller, obtaining the bandwidth allocation mode specified for it. The NIC then completes its initial configuration according to this mode and operates normally according to the bandwidth policy defined by that mode.

[0102] In one embodiment, the system further includes a verification and display process: in response to the central processing unit receiving a level signal of the bandwidth identification pin of at least one connector transmitted by the first expansion chip, the central processing unit verifies the bandwidth allocation mode based on the level signal of the bandwidth identification pin of the at least one connector transmitted by the first expansion chip; in response to the logic controller receiving a level signal of the bandwidth identification pin of at least one connector transmitted by the second expansion chip, the logic controller determines the bandwidth allocation mode based on the level signal of the bandwidth identification pin of the at least one connector transmitted by the second expansion chip, and sends the bandwidth allocation mode to the central processing unit, so that the central processing unit generates corresponding display information according to the received bandwidth allocation mode.

[0103] Specifically, the system employs a dual-channel acquisition and verification mechanism to further ensure the high reliability of bandwidth allocation mode determination. The central processing unit (CPU) continuously monitors the input from the first expansion chip. Once the CPU receives a level signal from the first expansion chip regarding the bandwidth identification pin on at least one connector, it immediately initiates a verification process. The CPU uses this set of independent level signals it receives to cross-verify the bandwidth allocation mode determined by the logic controller. This step constitutes a crucial verification step within the system. Simultaneously, as the core of the system's determination, the logic controller, upon receiving the bandwidth identification pin level signal from the second expansion chip's dedicated connector group, executes its core decision-making process based on this signal. It determines the final bandwidth allocation mode based on these signals and then sends this mode information to the CPU.

[0104] Please see Figure 7 This flowchart specifically illustrates how the BIOS ultimately obtains and presents bandwidth allocation mode information during the verification and display process described above:

[0105] After the DC power supply is powered on, the Basic Input / Output System (BIOS) reads the presence information of the Open Compute Project (OCP) network card.

[0106] Taking the peripheral component interconnect port 3 (PE3) of CPU0 and the peripheral component interconnect port 3 (PE3) of CPU1 as examples, the first bandwidth identifier pin (ID0) and the second bandwidth identifier pin (ID1) of connector A (PE3A) of peripheral component interconnect port 3 of CPU1 are connected to the fourth bit (P04) and the fifth bit (P05) pins of port 0 of the CPU system management bus extender chip; the first bandwidth identifier pin (ID0) and the second bandwidth identifier pin (ID1) of connector C (PE3C) of peripheral component interconnect port 3 of CPU1 are connected to the fourth bit (P04) and the fifth bit (P05) pins of port 0 of CPU1 system management bus extender chip. Wide identification pin (ID1), access port zero sixth bit (P06) and port zero seventh bit (P07) pins; the first bandwidth identification pin (ID0) and the second bandwidth identification pin (ID1) of the peripheral component interconnect port three connector A (PE3A) of the central processing unit zero (CPU0), access port zero zero bit (P00) and port zero first bit (P01) pins of the expansion chip; the first bandwidth identification pin (ID0) and the second bandwidth identification pin (ID1) of the peripheral component interconnect port three connector C (PE3C) of the central processing unit zero (CPU0), access port zero second bit (P02) and port zero third bit (P03) pins.

[0107] After recognizing the presence of the Open Compute Project (OCP) network card, the identification (ID) information of the CA9555 is read, which matches the identification (ID) pin status read by the Complex Programmable Logic Device (CPLD). When the read ID status from the fourth bit (P04) to the zeroth bit (P00) of port zero is binary 1010, the Basic Input / Output System (BIOS) considers it to be a Single-Host Open Compute Project (OCP) network card with High-Speed ​​Peripheral Component Interconnect x16 (PCIe x16). After power-on training is completed, the BIOS silkscreen will show CPUX_PEX_OCPX, where X represents the specific CPU number, PCIe port number, and Open Compute Project (OCP) network card number. In this example, it is CPU0_PE3_OCP0.

[0108] When the identity identifier (ID) status read from the fourth bit (P04) of port zero to the zeroth bit (P00) of port zero is binary 1001, the Basic Input / Output System (BIOS) considers the current status to be an Open Compute Project (OCP) network card if the first eight (x8) links are used, and an expansion card if the second eight (x8) links are used. The corresponding silkscreen should be displayed as CPU0_PE3_AC_OCP0 and CPU0_PE3_EG.

[0109] When the read states of the first bit (P01) and the zeroth bit (P00) of port zero are both 10, and the states of the fifth bit (P05) and the fourth bit (P04) of port zero are also 10, the Basic Input / Output System (BIOS) considers the current state to be a Multi-Host Open Compute Project (OCP) network card. The corresponding silkscreen markings are CPU0_PE3_AC_OCP0 and CPU1_PE3_AC_OCP0. In this state, the Open Compute Project (OCP) network card operates in a dual-host state, operating as both CPU0 and CPU1. After the Open Compute Project (OCP) network interface card (NIC) ID is read, the Basic Input / Output System (BIOS) and Complex Programmable Logic Device (CPLD) communicate via the Virtual Pin Pair (VPP) protocol to power on and illuminate the NIC. Once power-on and successful training are complete, the corresponding BIOS silkscreen will be displayed.

[0110] With this configuration, the Central Processing Unit (CPU) has raw data from the first expansion chip for verification, and also directly receives authoritative judgment results from the Logic Controller (CPLD). Similarly, the Basic Input / Output System (BIOS) obtains the Bandwidth Allocation Identity (ID) signal transmitted from the Open Compute Project (OCP) cable end via the CPU's system management bus. This ID is used to determine the operating mode of the High-Speed ​​Peripheral Component Interconnect (PCIe) port corresponding to the current Media Converter Input / Output (MCIO) connector and to correctly display the BIOS silkscreen information. For example, when the ID status read from the fourth bit (P04) to the zeroth bit (P00) of port zero is binary 1010, the Basic Input / Output System (BIOS) considers it to be a Single-Host Open Compute Project (OCP) network card with High-Speed ​​Peripheral Component Interconnect x16 (PCIe x16), and the silkscreen is CPUX_PEX_OCPX; when the status read from the first bit (P01) and the zeroth bit (P00) of port zero is 10, and the fifth bit (P00) of port zero is... When both P05 and the fourth bit of port zero (P04) are in the state of 10, the Basic Input / Output System (BIOS) considers the current state to be a Multi-Host Open Compute Project (OCP) network card, corresponding to the silkscreen display as CPU0_PE3_AC_OCP0 and CPU1_PE3_AC_OCP0. The CPU will ultimately use this verified and reliable bandwidth allocation pattern to drive the BIOS to generate completely corresponding and accurate display information (such as the device silkscreen), thus presenting the user with an unambiguous connection topology on the system management interface. This dual-path information processing mechanism minimizes misjudgments and incorrect displays caused by a single signal path failure, greatly improving the system's robustness.

[0111] In one embodiment, the bandwidth mode is switched by the physical state of the target circuit connection structure: in response to the first conductive path in the target circuit connection structure fixing the power pin to the first bandwidth identification pin, and its insulating barrier being in a first position to isolate the second conductive path from the second bandwidth identification pin, the logic controller controls the network card to operate in the default bandwidth mode according to a first level combination on the first bandwidth identification pin and the second bandwidth identification pin, wherein in the default bandwidth mode, all functional ports of the network card share the total bandwidth of a single connector link; in response to the insulating barrier being removed or being in a second position, making the second conductive path electrically contact the second bandwidth identification pin, the logic controller controls the network card to operate in the guaranteed bandwidth mode according to a second level combination on the first bandwidth identification pin and the second bandwidth identification pin, wherein in the guaranteed bandwidth mode, the designated functional port of the network card is allocated half of the bandwidth of a single connector exclusively, and the remaining ports share the other half of the bandwidth of the single connector.

[0112] Specifically, to distinguish the OCP card from other expansion cards, the ID0 pin is shorted on the cable corresponding to each MCIO x8 connector, keeping ID0 constantly high. This ID0 is then switched to a level of 0 by the MOSFET. When the first conductive path in the target circuit connection structure fixes the power pin to the first bandwidth identifier pin, and its insulating barrier is in the first position, physically isolating the second conductive path from the second bandwidth identifier pin, the logic controller will acquire a first level combination (e.g., "10") where the first bandwidth identifier pin is high and the second bandwidth identifier pin is low. Upon recognizing this specific combination, the logic controller will control the network card to operate in the default bandwidth mode. In this mode, the total bandwidth of a single PCIe link (e.g., an x8 link) connected to the network card is treated as a single resource pool and dynamically shared by all functional ports on the network card (e.g., two 100G ports).

[0113] Conversely, when the insulating barrier is removed or moved to the second position, causing the second conductive path to establish electrical contact with the second bandwidth identification pin, the logic controller will acquire a second level combination (e.g., "11") where both the first and second bandwidth identification pins are high. Upon recognizing this upgraded combination, the logic controller will control the network interface card (NIC) to switch to guaranteed bandwidth mode. In this mode, the system prioritizes bandwidth resources: a specific functional port of the NIC (e.g., port 0) is allocated exclusive, fixed bandwidth (equivalent to half the bandwidth of a single connector, i.e., PCIe x4), thus providing a guaranteed performance for critical services; while the remaining ports on the NIC share the remaining half of the bandwidth (another PCIe x4).

[0114] In this application, two ID pins are defined on each MCIO x8 connector, and the pin corresponding to ID0 on the OCP cable end is shorted to 3.3V, keeping it at a high level. Each ID pin is connected to the expander chip of the CPU system management bus and the CPLD I2C bus respectively after being toggled by a MOSFET. The CPLD reads the ID level value on the expander and matches it with the ID in the rules to determine the current configuration of the OCP network card and notify the OCP of the required bandwidth allocation mode. Correspondingly, the BIOS also needs to read the ID pin status on its corresponding expander chip to obtain the current working status of the OCP network card, and complete the corresponding silkscreen display after power-on training with the CPLD.

[0115] In this way, the complex bandwidth allocation pattern recognition and configuration process is hardware-based and automated. The system can quickly and accurately complete network card configuration in the early stages of startup without user intervention or operating system driver loading, greatly improving the convenience and reliability of system deployment. At the same time, through simple physical structure changes or cable shorting schemes, hardware-level switching between two different quality of service (QoS) bandwidth policies and clear differentiation between OCP network cards and other expansion cards are achieved, providing users with flexible and reliable configuration options.

[0116] Embodiments of this application also provide an electronic device, such as... Figure 8 As shown, it includes a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to perform the steps in any of the above-described network interface card management method embodiments.

[0117] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the network interface card management method embodiments described above when running.

[0118] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), mobile device, magnetic disk, or optical disk.

[0119] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0120] The network card management system, method, and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A network interface card (NIC) management system, characterized in that, The system includes a motherboard, a network card, and pre-installed cables. The motherboard is equipped with a motherboard power circuit, a logic controller, and connectors. The connector includes a power pin that connects to the motherboard power circuit and at least one bandwidth identification pin. The preset cable includes a motherboard-side plug, and the motherboard-side plug has a target circuit connection structure inside. The target circuit connection structure is used to directly electrically connect the power pin and the bandwidth identification pin on the connector when the motherboard-side plug is mated with the connector. The logic controller is communicatively connected to the bandwidth identifier pin and is used to acquire the level signal on the bandwidth identifier pin; The network interface card (NIC) is communicatively connected to the logic controller and is used to receive bandwidth configuration signals from the logic controller. In response to the logic controller receiving the level signal on the bandwidth identifier pin, the logic controller determines the bandwidth allocation mode of the network card, generates a corresponding bandwidth configuration signal, and transmits the bandwidth configuration signal to the network card so that the network card operates according to the bandwidth allocation mode.

2. The network interface card (NIC) management system according to claim 1, characterized in that, The connector includes a first bandwidth identification pin and a second bandwidth identification pin: The first end of the first bandwidth identifier pin is connected to the target circuit connection structure, and the second end of the first bandwidth identifier pin is connected to the logic controller; the target circuit connection structure is used to directly electrically connect the power pin on the connector to the first bandwidth identifier pin when the motherboard side plug is mated with the connector; The first end of the second bandwidth identifier pin is connected to the reference ground pin, and the second end of the second bandwidth identifier pin is connected to the logic controller. The logic controller determines the bandwidth allocation mode based on the combination of the level signals on the second end of the first bandwidth identifier pin and the second end of the second bandwidth identifier pin.

3. The network interface card (NIC) management system according to claim 1, characterized in that, The system also includes a basic input / output system, a central processing unit, a first expansion chip, and a second expansion chip. The central processing unit is communicatively connected to the basic input / output system; The first end of the first expansion chip is connected to the central processing unit, and the second end of the first expansion chip is connected to the bandwidth identification pin corresponding to the first connector group. The first end of the second expansion chip is connected to the logic controller, and the second end of the second expansion chip is connected to the bandwidth identifier pin corresponding to the second connector group. The first expansion chip and the second expansion chip are respectively used to transmit the level signal of the bandwidth identification pin to the central processing unit and the logic controller; The logic controller determines the bandwidth allocation mode based on the level signal of the bandwidth identifier pin obtained from the second expansion chip, and sends the bandwidth allocation mode to the central processing unit; the central processing unit verifies based on the level signal obtained from the first expansion chip, or generates corresponding display information according to the bandwidth allocation mode sent by the logic controller.

4. The network interface card management system according to claim 3, characterized in that, The first connector group includes a first connector and a second connector, and the second connector group includes a third connector and a fourth connector. The first connector and the second connector together constitute and are electrically connected to the same first high-speed peripheral component interconnect port of a central processing unit. The third connector and the fourth connector together constitute and are electrically connected to the same second high-speed peripheral component interconnect port of a central processing unit. The first connector, the second connector, the third connector, and the fourth connector each include a power pin connected to the motherboard power circuit and at least one bandwidth identification pin.

5. The network interface card (NIC) management system according to claim 2, characterized in that, The target circuit connection structure includes a first conductive path, a second conductive path, and an insulating barrier: The first conductive path is fixedly connected between the power supply pin and the first bandwidth indicator pin; The first end of the second conductive path is connected to the power supply pin, and the second end of the second conductive path is configured as a free end; In response to the insulating barrier being in the first position, the free end of the second conductive path is isolated from the second bandwidth identification pin. The logic controller controls the network card to operate in the default bandwidth mode according to the first level combination on the first bandwidth identification pin and the second bandwidth identification pin. In the default bandwidth mode, all functional ports of the network card share the total bandwidth of a single connector link. In response to the removal of the insulating barrier or its position in the second location, the free end of the second conductive path makes electrical contact with the second bandwidth identification pin; the logic controller controls the network card to operate in a guaranteed bandwidth mode based on a second level combination on the first bandwidth identification pin and the second bandwidth identification pin, wherein, in the guaranteed bandwidth mode, a designated functional port of the network card is allocated half of the bandwidth of a single connector exclusively, and the remaining ports share the other half of the bandwidth of the single connector.

6. A network interface card (NIC) management method, characterized in that, The network interface card (NIC) management method is applied to the NIC management system as described in any one of claims 1-5, and the method includes: In response to the logic controller receiving the level signal on the bandwidth identifier pin, the logic controller compares the level signal on the bandwidth identifier pin with a pre-stored mode mapping table to determine the bandwidth allocation mode corresponding to the network card. In response to determining the bandwidth allocation mode corresponding to the network interface card (NIC), the logic controller generates a bandwidth configuration signal carrying the bandwidth allocation mode and sends the bandwidth configuration signal to the NIC. The network interface card (NIC) receives and parses the bandwidth configuration signal to obtain the bandwidth allocation mode, and then operates according to the bandwidth allocation mode.

7. The network interface card (NIC) management method according to claim 6, characterized in that, The bandwidth identification pin includes a first bandwidth identification pin and a second bandwidth identification pin. In response to the logic controller receiving a level signal on the bandwidth identification pin, the logic controller compares the level signal on the bandwidth identification pin with a pre-stored mode mapping table to determine the bandwidth allocation mode corresponding to the network card, including: The logic controller uses its general-purpose input / output interface to collect the real-time level states of the first bandwidth identifier pin and the second bandwidth identifier pin in parallel, and combines the collected first pin level states and the second pin level states into a set of binary coded signals. The binary encoded signal is matched and queried with a pre-stored pattern mapping table inside the logic controller. The pattern mapping table records the correspondence between different binary codes and different bandwidth allocation modes. Based on the matching query results, determine the bandwidth allocation mode corresponding to the current binary encoded signal.

8. The network interface card (NIC) management method according to claim 6, characterized in that, The method further includes: In response to the central processing unit receiving a level signal from the bandwidth identification pin of at least one connector transmitted by the first expansion chip, the central processing unit verifies the bandwidth allocation mode based on the level signal from the bandwidth identification pin of at least one connector transmitted by the first expansion chip. In response to the logic controller receiving a level signal from the bandwidth identification pin of at least one connector transmitted by the second expansion chip, the logic controller determines a bandwidth allocation mode based on the level signal from the bandwidth identification pin of at least one connector transmitted by the second expansion chip, and sends the bandwidth allocation mode to the central processing unit, so that the central processing unit generates corresponding display information according to the received bandwidth allocation mode.

9. The network interface card (NIC) management method according to claim 6, characterized in that, The method further includes: In response to the first conductive path in the target circuit connection structure, the power supply pin is fixedly connected to the first bandwidth identification pin, and its insulating blocking part is located in the first position to isolate the second conductive path from the second bandwidth identification pin. The logic controller controls the network card to work in the default bandwidth mode according to the first level combination on the first bandwidth identification pin and the second bandwidth identification pin. In the default bandwidth mode, all functional ports of the network card share the total bandwidth of a single connector link. In response to the removal of the insulating barrier or its position in the second location, causing the second conductive path to make electrical contact with the second bandwidth identification pin, the logic controller controls the network card to operate in a guaranteed bandwidth mode based on a second level combination on the first bandwidth identification pin and the second bandwidth identification pin. In the guaranteed bandwidth mode, a designated functional port of the network card is allocated half of the bandwidth of a single connector exclusively, while the remaining ports share the other half of the bandwidth of the single connector.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the network interface card management method as described in any one of claims 6 to 9 when executing the computer program.

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