Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: a substrate body including a plurality of wiring layers including a pair of first wiring patterns spaced apart from each other and disposed at the same height as each other with respect to a thickness direction of the printed circuit board, and a plurality of via layers including a plurality of second wiring patterns spaced apart from each other and disposed at the same height as each other with respect to a thickness direction of the printed circuit board; and a first redistribution unit including one or more first redistribution layers, in which the one or more first redistribution layers include a first redistribution pattern disposed at a height different from a height of the pair of first wiring patterns with respect to the thickness direction, the first redistribution unit is embedded in the substrate main body, and wherein the first redistribution pattern connects the pair of first wiring patterns to each other.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0114348, filed on August 26, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] Recently, with the increase in the number of semiconductor chips mounted on the package substrate, the substrate area has increased. Furthermore, with the increase in the number of wirings, the number of substrate layers has also increased. For example, with the increase in the number of wirings, entanglement between wirings may increase, and to resolve entanglement, separation of wiring layers may be necessary. Therefore, the number of substrate layers may need to be increased. Additionally, it may be necessary to insert ground layers between the separated wiring layers, thus potentially further increasing the number of layers. Furthermore, multilayer package substrates can be manufactured using a double-sided lamination method relative to the core layer, and in this case, the number of layers may also be increased on opposite sides. Such an increase in the number of substrate layers may increase manufacturing time and cost, and may also lead to a decrease in yield. Summary of the Invention

[0004] One aspect of this disclosure is to provide a printed circuit board that can effectively solve wiring tangling, thereby reducing the need for additional layers.

[0005] Another aspect of this disclosure is to provide a printed circuit board that can integrate layer-separated wiring into a single layer using redistribution units including a redistribution pattern.

[0006] According to an example embodiment, a printed circuit board includes: a substrate body including a plurality of wiring layers and a plurality of via layers, wherein the plurality of wiring layers include a pair of first wiring patterns, the pair of first wiring patterns being spaced apart from each other and disposed at the same height relative to the thickness direction of the printed circuit board; and a first redistribution unit including one or more first redistribution layers, wherein the one or more first redistribution layers include a first redistribution pattern, the first redistribution pattern being disposed at a height different from the height of the pair of first wiring patterns relative to the thickness direction, wherein the first redistribution unit is embedded in the substrate body, and wherein the first redistribution pattern connects the pair of first wiring patterns to each other.

[0007] According to another example embodiment, a printed circuit board includes: a pair of first wiring patterns disposed on the same first layer and spaced apart from each other on the same first layer; a pair of second wiring patterns disposed on the same second layer and spaced apart from each other on the same second layer; a first redistribution unit including a first redistribution pattern disposed on a layer different from the pair of first wiring patterns and connecting the pair of first wiring patterns to each other; and a second redistribution unit including a second redistribution pattern disposed on a layer different from the pair of second wiring patterns and connecting the pair of second wiring patterns to each other. Attached Figure Description

[0008] The above and other aspects, features, and advantages of this disclosure will be more clearly understood through the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram illustrating an example of an electronic device system; Figure 2 This is a perspective view showing an example of an electronic device; Figure 3 This is a plan view of a printed circuit board according to an example embodiment; Figure 4 It shows along Figure 3 A cross-sectional view of the printed circuit board taken by line I-I' in the diagram; Figure 5 It shows along Figure 3 A cross-sectional view of the printed circuit board taken by line II-II' in the diagram; Figure 6 This is a cross-sectional view illustrating an example of a redistribution unit according to an exemplary embodiment; Figure 7 This is a cross-sectional view showing another example of a redistribution unit according to an example embodiment; Figure 8 This is a cross-sectional view of a printed circuit board according to another example embodiment; Figure 9 This is a cross-sectional view of a printed circuit board according to another example embodiment; Figure 10 This is a cross-sectional view of a printed circuit board according to another example embodiment; and Figure 11 This is a cross-sectional view of a printed circuit board according to another example embodiment. Detailed Implementation

[0009] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. In the drawings, some elements may be exaggerated, omitted, or simplified, and the dimensions of the elements may not necessarily reflect their actual dimensions.

[0010] Electronic devices Figure 1 This is a block diagram illustrating an example of an electronic device system.

[0011] Reference Figure 1 The electronic device 1000 may house the motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically or electrically connected to the motherboard 1010. These electronic components may be connected to other electronic components described below via various signal lines 1090.

[0012] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips.

[0013] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, GSM+, EDGE+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, LAN, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the aforementioned protocols. However, network-related component 1030 is not limited to this, and may also include components compatible with or operating according to various other wireless or wired standards or protocols. Furthermore, network-related component 1030 may be combined with the aforementioned chip-related component 1020.

[0014] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, other electronic components are not limited to these and may include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. Depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0016] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital camera, digital video camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device capable of processing data.

[0017] Figure 2 This is a perspective view showing an example of an electronic device.

[0018] Reference Figure 2 For example, the electronic device may be a smartphone 1100. A motherboard 1110 may be housed in the smartphone 1100, and various components 1120 may be physically and / or electrically connected to the motherboard 1110. Furthermore, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the motherboard 1110 or not physically and / or electrically connected to the motherboard 1110 may be housed in the smartphone 1100. A portion of component 1120 may be a chip-related component, such as a component package 1121, but its exemplary embodiments are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components (including active and / or passive components) are mounted. Alternatively, the component package 1121 may be constructed as a printed circuit board in which electronic components (including active and / or passive components) are embedded. The electronic device is not necessarily limited to the smartphone 1100 and may be other electronic devices as described above.

[0019] Printed Circuit Board Figure 3 This is a plan view of a printed circuit board according to an example embodiment.

[0020] Figure 4 It shows along Figure 3 The cross-sectional view of the printed circuit board taken by line I-I' in the figure.

[0021] Figure 5 It shows along Figure 3 The cross-sectional view of the printed circuit board taken from line II-II' in the figure.

[0022] Reference Figures 3 to 5The printed circuit board 500A according to the example may include a substrate body and a redistribution unit 200A. The substrate body includes an insulating layer 110, a wiring layer 120, and a via layer 130. The redistribution unit 200A is embedded in the substrate body and includes a dielectric layer 210 and a redistribution layer 220. The wiring layer 120 may include a pair of first wiring patterns L1-1 and L1-2 spaced apart from each other on substantially the same layer (e.g., at substantially the same height in the thickness direction). In this disclosure, the thickness direction is the thickness direction of the printed circuit board, for example, the direction along which the plurality of insulating layers 110 are stacked on top of each other. The redistribution layer 220 may include a first redistribution pattern R1 disposed in a layer different from the pair of first wiring patterns L1-1 and L1-2 (e.g., at different heights in the thickness direction). The via layer 130 may include a pair of first connection vias v1-1 and v1-2. The first redistribution pattern R1 can be connected to the pair of first wiring patterns L1-1 and L1-2 through the pair of first connection vias v1-1 and v1-2, respectively. Therefore, a pair of first wiring patterns L1-1 and L1-2 can be connected by a first redistribution pattern R1. That is, the first redistribution pattern R1 can connect a pair of first wiring patterns L1-1 and L1-2 to each other.

[0023] The printed circuit board 500A may include a redistribution unit 200A, which includes a first redistribution pattern R1 electrically connecting a pair of first wiring patterns L1-1 and L1-2 to each other. Therefore, a pair of first wiring patterns L1-1 and L1-2 that might otherwise require layer separation can be formed on substantially the same layer without layer separation. This effectively solves wiring entanglement and reduces the need for additional layers. Consequently, substrate manufacturing time and costs are reduced, and yield reductions are minimized.

[0024] The wiring layer 120 may further include a pair of second wiring patterns L2-1 and L2-2 spaced apart from each other on substantially identical layers (e.g., at substantially the same height relative to the thickness direction). The pair of first wiring patterns L1-1 and L1-2 and the pair of second wiring patterns L2-1 and L2-2 may be disposed on substantially identical layers, for example, at substantially the same height relative to the thickness direction. Furthermore, the redistribution layer 220 may also include a second redistribution pattern R2 disposed on a different layer than the pair of second wiring patterns L2-1 and L2-2 (e.g., at different heights relative to the thickness direction). The first redistribution pattern R1 and the second redistribution pattern R2 may be disposed on substantially identical layers, for example, at substantially the same height relative to the thickness direction, but embodiments are not limited thereto, and the first redistribution pattern R1 and the second redistribution pattern R2 may also be disposed at different heights. The via layer 130 may further include a pair of second connecting vias v2-1 and v2-2. The second redistribution pattern R2 can be connected to a pair of second wiring patterns L2-1 and L2-2 via a pair of second connection vias v2-1 and v2-2, respectively. Therefore, the pair of second wiring patterns L2-1 and L2-2 can be connected via the second redistribution pattern R2. In other words, the second redistribution pattern R2 can connect the pair of second wiring patterns L2-1 and L2-2 to each other.

[0025] In the printed circuit board 500A, a pair of first wiring patterns L1-1 and L1-2, and a pair of second wiring patterns L2-1 and L2-2, which may require layer separation, can be disposed on substantially the same layer, and wiring pattern entanglement can be effectively resolved by a first redistribution pattern R1 and a second redistribution pattern R2, respectively. Therefore, wiring entanglement can be effectively resolved, and the increase in the number of layers can be reduced. This reduces substrate manufacturing time and cost, and minimizes yield reduction. Furthermore, the virtual lines connecting the minimally spaced ends of the pair of first wiring patterns L1-1 and L1-2 can intersect with the virtual lines connecting the minimally spaced ends of the pair of second wiring patterns L2-1 and L2-2.

[0026] When the substrate body and redistribution unit 200A are viewed from above (e.g., along the thickness direction), the second redistribution pattern R2 can be superimposed on at least one of a pair of first wiring patterns L1-1 and L1-2. Therefore, wiring entanglement can be effectively resolved, and the increase in the number of layers can be reduced. Consequently, substrate manufacturing time and manufacturing costs can be further reduced, and yield reduction can be further minimized.

[0027] In the following description, the components of the printed circuit board 500A will be described in more detail with reference to the accompanying drawings.

[0028] Insulating layer 110 may include an insulating material. The insulating material may include thermosetting resins (such as epoxy resins) and / or thermoplastic resins (such as polyimide). Optionally, the insulating material may include a material prepared by impregnating inorganic fillers, organic fillers, and / or glass fibers (such as glass fabric, for example, glass cloth) in these resins. For example, the insulating material may be copper-clad laminate (CCL), prepreg (PPG), ABF (Ajinomoto laminate), photosensitive dielectric (PID), solder resist (SR), etc., but embodiments are not limited thereto. Insulating layer 110 may include multiple layers and may include the same insulating material or may include different insulating materials. Adjacent insulating layers 110 may have a distinct boundary, or, if desired, adjacent insulating layers 110 may be integral, making the boundary between them indistinct.

[0029] Wiring layer 120 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, wiring layer 120 may include copper (Cu), but embodiments thereof are not limited thereto. Wiring layer 120 may perform various functions depending on the design. For example, wiring layer 120 may include signal patterns, power patterns, ground patterns, etc. Each of these patterns may have various shapes such as lines, planes, pads, etc. Wiring layer 120 may include a seed layer and a plating layer. The seed layer may be formed by an electroless plating process (e.g., electroless copper plating, etc.) and, if desired, by a sputtering process. Optionally, both electroless plating and sputtering processes may be used. The plating layer may be formed by an electrolytic plating process (e.g., electrolytic copper plating, etc.). If desired, in addition to the seed layer and plating layer, wiring layer 120 may also include copper foil. Wiring layer 120 may include multiple layers. Multiple wiring layers 120 can be disposed on multiple insulating layers 110 or disposed in multiple insulating layers 110 respectively.

[0030] The via layer 130 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the via layer 130 may include copper (Cu), but embodiments thereof are not limited thereto. The via layer 130 may include a plurality of connection vias. The plurality of connection vias may perform various functions depending on the design. For example, the via layer 130 may include signal vias, power vias, grounding vias, etc. The plurality of connection vias may include filled vias (filled VIAs) in which the via holes are filled with metal, or may also include conformal vias (conformal VIAs) in which metal is disposed along the wall surface of the via holes. Furthermore, the plurality of connection vias may include through-holes (through VIAs) of various shapes. In cross-section, each of the plurality of connection vias may have a vertical shape, a tapered shape, and / or an hourglass shape. The via layer 130 may include a seed layer and a plating layer. The seed layer can be formed by an electroless plating process (e.g., electroless copper plating, etc.) or, if desired, by a sputtering process. Optionally, both electroless plating and sputtering processes can be used. The plating layer can be formed by an electrolytic plating process (e.g., electrolytic copper plating, etc.). The via layer 130 may include multiple layers. The multiple via layers 130 may be respectively disposed in multiple insulating layers 110.

[0031] The redistribution unit 200A may be a sub-substrate embedded in the substrate body. Considering manufacturing process difficulty, cost reduction, embedding process difficulty, and yield, the redistribution unit 200A may include an organic bridge substrate structure, but its embodiments are not limited thereto, and if necessary, the redistribution unit 200A may include a silicon bridge substrate structure. The redistribution unit 200A may include a dielectric layer 210 and a redistribution layer 220, the redistribution layer 220 being disposed on or within the dielectric layer 210. If necessary, a redistribution via layer may be disposed within the dielectric layer 210. The redistribution unit 200A may be attached to at least one of the plurality of insulating layers 110 via an adhesive film (such as a chip attachment film (DAF)) and may be embedded in at least another of the plurality of insulating layers 110. The redistribution unit 200A may include a single-layer structure (see...). Figure 6 :200-1) or multi-layered structure (see :200-1) Figure 7 (200-2). Further description of the components included in the redistribution unit 200A will be provided later.

[0032] Figure 6 This is a cross-sectional view illustrating an example of a redistribution unit according to an exemplary embodiment.

[0033] Reference Figure 6The redistribution unit 200-1, according to the example, can be a single-layer structure comprising a dielectric layer 210 and a redistribution layer 220 disposed on the dielectric layer 210. An adhesive film 250 may be attached to the lower surface of the dielectric layer 210. For example, when the entanglement of a pair of first wiring patterns and a pair of second wiring patterns is relatively minor, or as otherwise required, a first redistribution pattern for resolving the entanglement of a pair of first wiring patterns and a second redistribution pattern for resolving the entanglement of a pair of second wiring patterns may be spaced apart from each other at substantially the same height relative to the thickness direction. For example, the first redistribution pattern and the second redistribution pattern may be formed in a single redistribution layer 220.

[0034] The dielectric layer 210 may comprise an organic insulating material or an inorganic insulating material. The organic insulating material may comprise a thermosetting resin (such as epoxy resin) and / or a thermoplastic resin (such as polyimide). Optionally, the organic insulating material may comprise a material prepared by impregnating these resins with inorganic fillers. For example, the organic insulating material may comprise an Ajinomoto film stacked as a substrate (ABF), a photosensitive dielectric (PID), etc., but embodiments are not limited thereto. The inorganic insulating material may comprise silicon (Si), etc., and may comprise, for example, silicon dioxide or silicon nitride, but embodiments are not limited thereto.

[0035] The redistribution layer 220 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the redistribution layer 220 may include copper (Cu), but embodiments thereof are not limited thereto. The redistribution layer 220 may perform various functions depending on the design. For example, the redistribution layer 220 may include signal patterns, power patterns, ground patterns, etc. Each of these patterns may have various shapes such as lines, planes, pads, etc. The redistribution layer 220 may include a seed layer and a plating layer. The seed layer may be formed by an electroless plating process, or, if desired, by a sputtering process, or both electroless plating and sputtering processes may be used. The plating layer may be formed by an electrolytic plating process, but embodiments thereof are not limited thereto, and the plating layer may be formed by an electroless plating process and / or a sputtering process.

[0036] The adhesive film 250 may include various insulating materials with adhesive properties. For example, the adhesive film 250 may include epoxy resin, polyimide, silicone resin, etc., but embodiments thereof are not limited thereto. Metal particles such as copper (Cu) or silver (Ag) may be added to the adhesive film 250, but embodiments thereof are not limited thereto. A chip attachment film (DAF) may be used as the adhesive film 250, but embodiments thereof are not limited thereto.

[0037] Figure 7 This is a cross-sectional view showing another example of a redistribution unit according to an example embodiment.

[0038] Reference Figure 7 According to another example, the redistribution unit 200-2 may have a multilayer structure, including multiple dielectric layers 210, multiple redistribution layers 220, and multiple redistribution via layers 230. The multiple redistribution layers 220 are respectively disposed on or within the multiple dielectric layers 210, and the multiple redistribution via layers 230 are respectively disposed within the multiple dielectric layers 210 and connect the multiple redistribution layers 220 to each other. For example, the multiple redistribution via layers 230 can connect adjacent redistribution layers among the multiple redistribution layers 220 to each other. An adhesive film 250 may be attached to the lower surface of the lowest dielectric layer 210 among the multiple dielectric layers 210. For example, when the entanglement of a pair of first wiring patterns and a pair of second wiring patterns is relatively severe, or as otherwise required, a first redistribution pattern for resolving the entanglement of a pair of first wiring patterns and a second redistribution pattern for resolving the entanglement of a pair of second wiring patterns may be disposed at different heights relative to the thickness direction. For example, the first redistribution pattern and the second redistribution pattern can be formed in redistribution layers 220 in different layers.

[0039] Each of the plurality of dielectric layers 210 may include an organic insulating material or an inorganic insulating material. Organic insulating materials may include thermosetting resins (such as epoxy resins) and / or thermoplastic resins (such as polyimide). Optionally, the organic insulating material may include a material prepared by impregnating these resins with inorganic fillers. For example, organic insulating materials may include Ajinomoto deposited film (ABF), photosensitive dielectric (PID), etc., as a stacking material for a substrate, but embodiments are not limited thereto. Inorganic insulating materials may include silicon (Si), etc., and may include, for example, silicon dioxide or silicon nitride, but embodiments are not limited thereto. Each of the plurality of dielectric layers 210 may include the same insulating material, but embodiments are not limited thereto. Adjacent dielectric layers 210 may have distinct boundaries, but embodiments are not limited thereto, and adjacent dielectric layers 210 may be integrated with each other such that the boundaries between them are indistinct.

[0040] Each of the plurality of redistribution layers 220 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, each of the plurality of redistribution layers 220 may include copper (Cu), but embodiments thereof are not limited thereto. Each of the plurality of redistribution layers 220 may perform various functions according to design. For example, each of the plurality of redistribution layers 220 may include signal patterns, power patterns, ground patterns, etc. Each of these patterns may have various shapes such as lines, planes, and pads. Each of the plurality of redistribution layers 220 may include a seed layer and a plating layer. The seed layer may be formed by an electroless plating process, or, if desired, by a sputtering process. Optionally, both electroless plating and sputtering processes may be used. The plating layer may be formed by an electrolytic plating process, but embodiments thereof are not limited thereto, and the plating layer may be formed by an electroless plating process and / or a sputtering process. Multiple redistribution layers 220 may have a structure in which redistribution layers including redistribution pattern R and redistribution layers including grounding pattern G are stacked alternately, and in this case, electromagnetic interference can be effectively prevented.

[0041] Among the multiple redistribution layers 220, the uppermost redistribution layer 220 may include multiple connection pads P and a ground pattern (i.e., a second ground pattern) G disposed between the multiple connection pads P. The multiple connection pads P may include a pair of first connection pads respectively connected to a pair of first wiring patterns and a pair of second connection pads respectively connected to a pair of second wiring patterns. The uppermost redistribution layer 220 may have a greater thickness than each of the other redistribution layers 220, thus facilitating connections between a pair of first connection vias and a pair of first connection pads, as well as connections between a pair of second connection vias and a pair of second connection pads.

[0042] Each of the plurality of redistributed via layers 230 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, each of the plurality of redistributed via layers 230 may include copper (Cu), but embodiments thereof are not limited thereto. Each of the plurality of redistributed via layers 230 may include one or more connection vias. The one or more connection vias may perform various functions depending on the design. For example, the one or more connection vias may include signal vias, power vias, ground vias, etc. The one or more connection vias may include filled vias (filled VIAs) in which the via is filled with metal, or may also include conformal vias (conformal VIAs) in which metal is disposed along the wall surface of the via. The one or more connection vias included in the plurality of redistributed via layers 230 may be arranged in a stacked via configuration. Each of the one or more connection vias may penetrate one dielectric layer 210, or, if desired, each of the one or more connection vias may simultaneously penetrate multiple dielectric layers 210. In the cross-section, each of one or more connecting vias may have a vertical shape, a tapered shape, and / or an hourglass shape. Each of the plurality of redistributed via layers 230 may include a seed layer and a plating layer. The seed layer may be formed by an electroless plating process, or, if desired, by a sputtering process, or both electroless plating and sputtering processes may be used. The plating layer may be formed by an electroplating process, but embodiments thereof are not limited thereto, and may be formed by an electroless plating process and / or a sputtering process.

[0043] The adhesive film 250 may include various insulating materials with adhesive properties. For example, the adhesive film 250 may include epoxy resin, polyimide, silicone resin, etc., but embodiments thereof are not limited thereto. Metal particles such as copper (Cu) or silver (Ag) may be added to the adhesive film 250, but embodiments thereof are not limited thereto. Chip attachment film (DAF) may be used as the adhesive film 250, but embodiments thereof are not limited thereto.

[0044] Figure 8 This is a cross-sectional view of a printed circuit board according to another example embodiment.

[0045] Reference Figure 8 According to another example, the printed circuit board 500B may include multiple insulating layers 110, multiple wiring layers 120, and multiple via layers 130 as a substrate body, and the redistribution unit 200B may be embedded in the substrate body. The substrate body may be at least a portion of a multilayer package substrate structure. For example, the multilayer package substrate may be a double-sided stacked structure relative to the core layer, and Figure 8 The substrate shown may represent a portion of a double-sided stacked structure. Alternatively, the multilayer package substrate may be a coreless multilayer stacked structure without a core layer, and Figure 8 The substrate body shown may represent a portion of a coreless multilayer stacked structure. However, embodiments thereof are not limited to this, and the substrate body may also be at least a portion of an intermediate substrate structure, in addition to a multilayer package substrate structure.

[0046] The printed circuit board 500B may further include a passivation layer 115, a semiconductor chip 310, and a plurality of electrical connection metals 150. The passivation layer 115 may be disposed on the uppermost insulating layer 110 among a plurality of insulating layers 110, and the passivation layer 115 has a plurality of openings exposing at least a portion of the uppermost wiring layer 120 among a plurality of wiring layers 120. The semiconductor chip 310 may be disposed on the passivation layer 115. The semiconductor chip 310 may have a plurality of bumps B1 comprising a conductive material. A plurality of electrical connection metals 150 comprising solder material may be disposed in each of the plurality of openings in the passivation layer 115, and the plurality of bumps B1 may be respectively connected to the plurality of electrical connection metals 150. Therefore, the semiconductor chip 310 may be mounted on the passivation layer 115.

[0047] Multiple wiring layers 120 may include a ground pattern (i.e., a first ground pattern) G, and the redistribution unit 200B may be attached to the ground pattern G via an adhesive film 250. The redistribution unit 200B may include a single-layer structure as described above (see...). Figure 6 :200-1) or multi-layered structure (see :200-1) Figure 7 :200-2). For example, such as Figure 8 As shown, the redistribution unit 200B may include one or more dielectric layers 210, one or more redistribution layers 220, and one or more redistribution via layers 230. The redistribution unit 200B can redistribute lines or paths that transmit specific electrical signals or power within the substrate body. For example, the redistribution unit 200B can be used to achieve connections between the semiconductor chip 310 and multiple wiring layers 120, and can also perform network redistribution (NR) in a package structure. For example, the redistribution unit 200B may not be used for die-to-die connections. Therefore, only one semiconductor chip 310 may be mounted on the passivation layer 115. However, embodiments thereof are not limited to this, and when multiple semiconductor chips are mounted, the redistribution unit 200B can provide die-to-die connections.

[0048] At least one connection via v included in the plurality of via layers 130 may connect one or more redistribution layers 220 and at least one of the plurality of wiring layers 120. At least one other connection via V included in the plurality of via layers 130 may penetrate at least a portion of each of the redistribution unit 200B and the adhesive film 250. The at least one other connection via V may be a connection via for signal connection between the plurality of wiring layers 120, but embodiments thereof are not limited thereto.

[0049] Other descriptions and Figures 3 to 7 The descriptions are essentially the same, therefore, no duplicate descriptions will be provided.

[0050] Figure 9 This is a cross-sectional view of a printed circuit board according to another example embodiment.

[0051] Reference Figure 9 In a printed circuit board 500C according to another example, the number of multiple insulating layers 110, multiple wiring layers 120, and multiple via layers 130 included in the substrate body may be greater than the number of multiple insulating layers 110, multiple wiring layers 120, and multiple via layers 130 included in the printed circuit board 500B according to another example described above, and multiple redistribution units 200C-1 and 200C-2 may be embedded in the substrate body. Each of the multiple redistribution units 200C-1 and 200C-2 may include a single-layer structure as described above (see...). Figure 6 :200-1) or multi-layered structure (see :200-1) Figure 7 :200-2). For example, such as Figure 9 As shown, the plurality of redistribution units 200C-1 and 200C-2 may include a first redistribution unit 200C-1 and a second redistribution unit 200C-2. The first redistribution unit 200C-1 includes one or more first dielectric layers 211, one or more first redistribution layers 221, and one or more first redistribution via layers 231. The second redistribution unit 200C-2 includes one or more second dielectric layers 212, one or more second redistribution layers 222, and one or more second redistribution via layers 232. The first redistribution unit 200C-1 and the second redistribution unit 200C-2 may be attached to the substrate body and embedded in the substrate body through a first adhesive film 251 and a second adhesive film 252, respectively.

[0052] The first redistribution unit 200C-1 and the second redistribution unit 200C-2 may be embedded in the substrate body at different heights relative to the thickness direction. A plurality of wiring layers 120 may include a pair of third wiring patterns spaced apart from each other at substantially the same height relative to the thickness direction and a pair of fourth wiring patterns spaced apart from each other at the same height relative to the thickness direction. The pair of third wiring patterns and the pair of fourth wiring patterns may be disposed at different heights relative to the thickness direction. A plurality of via layers 130 may include a pair of third connection vias v1 and a pair of fourth connection vias v2. One or more first redistribution layers 221 may include a third redistribution pattern connected to a pair of third connection vias v1 included in the plurality of via layers 130 and electrically connecting the pair of third wiring patterns to each other. One or more second redistribution layers 222 may include a fourth redistribution pattern connected to a pair of fourth connection vias v2 included in the plurality of via layers 130 and electrically connecting the pair of fourth wiring patterns to each other. The third redistribution pattern and the pair of third wiring patterns may be disposed at different heights relative to the thickness direction. Furthermore, a pair of third wiring patterns may be positioned at a height different from that of a pair of first wiring patterns relative to the thickness direction. As another example, a pair of third wiring patterns may also be positioned at a height substantially the same as that of a pair of first wiring patterns relative to the thickness direction. A fourth redistribution pattern and a pair of fourth wiring patterns may be positioned at different heights relative to the thickness direction.

[0053] The first redistribution unit 200C-1 and the second redistribution unit 200C-2 can be bridge units for redistributing lines or paths that transmit specific electrical signals or power in the substrate body. For example, the first redistribution unit 200C-1 and the second redistribution unit 200C-2 can be used to achieve connections between the semiconductor chip 310 and multiple wiring layers 120, and can also perform network redistribution (NR) in the package structure. For example, the first redistribution unit 200C-1 and the second redistribution unit 200C-2 may not be used for die-to-die connections. Therefore, only one semiconductor chip 310 can be mounted on the passivation layer 115. However, embodiments thereof are not limited to this, and when multiple semiconductor chips are mounted, the first redistribution unit 200C-1 and / or the second redistribution unit 200C-2 can also be used as bridge units for die-to-die connections.

[0054] Multiple wiring layers 120 may include a ground pattern G, and at least one connection via V (ground connection via) included in multiple via layers 130 may penetrate the second redistribution unit 200C-2 and the second adhesive film 252 and may be connected to the ground pattern G. If desired, at least one connection via V may also penetrate the ground pattern included in one or more second redistribution layers 222. Such a connection via V may be a connection via for grounding connections between multiple wiring layers 120 and / or for grounding connections between multiple wiring layers 120 and one or more second redistribution layers 222, but embodiments thereof are not limited thereto.

[0055] Other descriptions may be related to Figures 3 to 8 The descriptions are essentially the same, therefore, no duplicate descriptions will be provided.

[0056] Figure 10 This is a cross-sectional view of a printed circuit board according to another example embodiment.

[0057] Reference Figure 10 According to another example, the printed circuit board 500D may include multiple insulating layers 111 and 112, multiple wiring layers 121 and 122, and multiple via layers 131 and 132 as a substrate body, and multiple redistribution units 200D-1 and 200D-2 may be embedded in the substrate body. The substrate body may be at least a portion of a multilayer package substrate structure. For example, the multilayer package substrate may be a double-sided stacked structure relative to the core layer, and Figure 10 The substrate body shown may represent a portion of a double-sided stacked structure. However, embodiments thereof are not limited to this, and in addition to multilayer package substrate structures, the substrate body may also be at least a portion of an intermediate substrate structure.

[0058] The plurality of insulating layers 111 and 112 may include a plurality of first insulating layers 111 and a plurality of second insulating layers 112, and the thickness of each of the plurality of first insulating layers 111 may be smaller than the thickness of each of the plurality of second insulating layers 112. The plurality of wiring layers 121 and 122 may include a plurality of first wiring layers 121 and a plurality of second wiring layers 122, and the average pitch of each of the plurality of first wiring layers 121 may be smaller than the average pitch of each of the plurality of second wiring layers 122. The plurality of via layers 131 and 132 may include a plurality of first via layers 131 and a plurality of second via layers 132, and the average diameter of each of the plurality of first via layers 131 may be smaller than the average diameter of each of the plurality of second via layers 132. For example, the substrate body may have a 2.nD (an interconnect package structure between 2D and 3D, such as 2.1D, 2.3D, and 2.5D) level package substrate structure. Furthermore, the descriptions of multiple insulating layers 110, multiple wiring layers 120, and multiple via layers 130 can also be applied to multiple insulating layers 111 and 112, multiple wiring layers 121 and 122, and multiple via layers 131 and 132, respectively.

[0059] Each of the plurality of semiconductor chips 320 and 330 may be mounted on the uppermost first insulating layer 111 of the plurality of first insulating layers 111. The plurality of semiconductor chips 320 and 330 may be chips of the same type or different types; for example, each of the plurality of semiconductor chips 320 and 330 may be an application-specific integrated circuit (ASIC), a high-bandwidth memory (HBM), etc., but embodiments thereof are not limited thereto. The plurality of semiconductor chips 320 may be connected to at least a portion of the uppermost first wiring layer 121 of the plurality of first wiring layers 121 via a plurality of bumps B2 and a plurality of electrical connection metals 152, and the plurality of semiconductor chips 330 may be connected to at least another portion of the uppermost first wiring layer 121 of the plurality of first wiring layers 121 via a plurality of bumps B3 and a plurality of electrical connection metals 153. Each of the plurality of bumps B2 and B3 may include a conductive material, and each of the plurality of electrical connection metals 152 and 153 may include solder material, but embodiments thereof are not limited thereto.

[0060] Each of the multiple redistribution units 200D-1 and 200D-2 may include a single-layer structure as described above (see Figure 6 :200-1) or multi-layered structure (see :200-1) Figure 7(e.g., 200-2). For example, multiple redistribution units 200D-1 and 200D-2 may include a third redistribution unit 200D-1 and a fourth redistribution unit 200D-2. The third redistribution unit 200D-1 includes one or more third dielectric layers 213, one or more third redistribution layers 223, and one or more third redistribution via layers 233. The fourth redistribution unit 200D-2 includes one or more fourth dielectric layers 214, one or more fourth redistribution layers 224, and one or more fourth redistribution via layers 234. The third redistribution unit 200D-1 and the fourth redistribution unit 200D-2 may be attached to and embedded in the substrate body via a third adhesive film 253 and a fourth adhesive film 254, respectively.

[0061] The third redistribution unit 200D-1 and the fourth redistribution unit 200D-2 may be embedded in the substrate body at substantially the same height relative to the thickness direction. A plurality of second wiring layers 122 may include a pair of fifth wiring patterns spaced apart from each other at substantially the same height relative to the thickness direction and a pair of sixth wiring patterns spaced apart from each other at the same height relative to the thickness direction. The pair of fifth wiring patterns and the pair of sixth wiring patterns may be disposed at substantially the same height relative to the thickness direction. One or more third redistribution layers 223 may include a fifth redistribution pattern connected to a pair of fifth connection vias v3 included in a plurality of second via layers 132 and electrically connecting the pair of fifth wiring patterns to each other. One or more fourth redistribution layers 224 may include a sixth redistribution pattern connected to a pair of sixth connection vias v4 included in a plurality of second via layers 132 and electrically connecting the pair of sixth wiring patterns to each other. The fifth redistribution pattern and the pair of fifth wiring patterns may be disposed at different heights in the thickness direction. The sixth redistribution pattern and the pair of sixth wiring patterns may be disposed at different heights in the thickness direction.

[0062] Redistribution and / or die-to-die connections can be performed via the third redistribution unit 200D-1 and the fourth redistribution unit 200D-2. For example, the third redistribution unit 200D-1 can redistribute lines or paths that transmit specific electrical signals or powers within the substrate body. For example, the third redistribution unit 200D-1 can realize connections between the first semiconductor chip 320 and multiple wiring layers 121 and 122, and can also perform network redistribution (NR) in the package structure. Furthermore, the fourth redistribution unit 200D-2 can provide lines or paths for transmitting specific electrical signals or powers between multiple semiconductor chips 320 and 330. For example, the fourth redistribution unit 200D-2 can perform die-to-die (DtD) connections.

[0063] Other descriptions may be related to Figures 3 to 9 The descriptions are essentially the same, therefore, no duplicate descriptions will be provided.

[0064] Figure 11 This is a cross-sectional view of a printed circuit board according to another example embodiment.

[0065] Reference Figure 11 In a printed circuit board 500E according to another example, unlike the printed circuit board 500D according to another example described above, a single redistribution unit 200E may be embedded in the substrate body instead of multiple redistribution units 200D-1 and 200D-2. The redistribution unit 200E may comprise a single-layer structure as described above (see...). Figure 6 :200-1) or multi-layered structure (see :200-1) Figure 7 :200-2). For example, such as Figure 11 As shown, the redistribution unit 200E may include a fifth redistribution unit 200E, which includes one or more fifth dielectric layers 215, one or more fifth redistribution layers 225, and one or more fifth redistribution via layers 235. The fifth redistribution unit 200E can be attached to and embedded in the substrate body via a fifth adhesive film 255. The one or more fifth redistribution layers 225 may include at least one redistribution pattern that resolves entanglement of at least one pair of wiring patterns included in the plurality of wiring layers 121 and 122. The at least one redistribution pattern can be connected to at least one pair of wiring patterns included in the plurality of wiring layers 121 and 122 via at least one pair of connection vias v5 included in the plurality of via layers 131 and 132, respectively.

[0066] Both redistribution and die-to-die connections can be performed via the fifth redistribution unit 200E. For example, the fifth redistribution unit 200E can redistribute lines or paths that transmit specific electrical signals or power within the substrate body. For instance, the fifth redistribution unit 200E can enable connections between the first semiconductor chip 320 and multiple wiring layers 121 and 122, and can also perform network redistribution (NR) within the package structure. Furthermore, the fifth redistribution unit 200E can provide lines or paths for transmitting specific electrical signals or power between multiple semiconductor chips 320 and 330. For example, die-to-die (DtD) connections can be performed via the fifth redistribution unit 200E.

[0067] Other descriptions may be related to Figures 3 to 10 The descriptions are essentially the same, therefore, no duplicate descriptions will be provided.

[0068] According to the foregoing example embodiments, a printed circuit board can be provided that can effectively solve wiring tangles and thus reduce the increase in the number of layers.

[0069] Parameters such as thickness, width, length, pitch, and depth can be measured using a scanning electron microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cross-section can be vertical or horizontal, and the values ​​of the above parameters can be measured based on the desired cross-section. When the measured values ​​of the above parameters are not constant, the values ​​of the above parameters can be determined as the average of the values ​​measured at five arbitrary points. The width of the upper and / or lower ends of the via can be measured in a cross-section of the substrate taken along the central axis of the via in the thickness direction. In a cross-section of the substrate taken along the central axis of the via in the thickness direction, the depth of the via can be measured as the distance from the upper end to the lower end of the via.

[0070] In this disclosure, the term "cover" can include not only complete coverage but also partial coverage, and can also include direct coverage and indirect coverage. Furthermore, the term "fill" can include not only complete filling but also substantial filling; for example, the term "fill" can include the presence of gaps or voids. Furthermore, the expression "around" can include not only complete surrounding but also surrounding a portion, or substantial surrounding. Furthermore, the term "exposed" can include not only complete exposure but also partial exposure, and the term "exposed" can indicate that an element is exposed from a corresponding element into which it is embedded. For example, an opening that exposes a pad can indicate that the pad is exposed from a solder resist layer, and a surface treatment layer can be disposed on the exposed pad.

[0071] In this disclosure, "basic" can be a concept that includes process errors, positional deviations, and measurement errors occurring in the manufacturing process. For example, the concept of "basically the same line width, distance, thickness, and height" can include not only cases where the elements are exactly the same in a numerical sense, but also cases where the elements have approximate values. Furthermore, the concept of "having a basically predetermined shape" can include not only cases where the shape is almost identical to the predetermined shape, but also cases where the shape is similar to the predetermined shape.

[0072] In this disclosure, "the same insulating material" can refer not only to completely identical insulating materials, but also to insulating materials of the same type. Therefore, the composition of the insulating materials can be substantially the same, but the specific composition ratios of the insulating materials can be slightly different.

[0073] For ease of description, the terms "lower side," "lower part," "lower surface," etc., may be used to refer to a side, portion, or surface in which the cross-section in the reference drawings is formed in the downward direction; the terms "upper side," "upper part," "upper surface," etc., may be used to refer to a side, portion, or surface in which the cross-section in the reference drawings is formed in the upward direction; and the terms "side portion," "side surface," etc., may be used to refer to a portion or surface formed in a direction perpendicular to the upper and lower surfaces. However, for ease of description, the terms may be defined as above, and the scope of the claims is not particularly limited to the terms described above.

[0074] In the example embodiments, the term "connection" can refer not only to a "direct connection" but also to an "indirect connection" via components such as an adhesive layer. Furthermore, the term "electrical connection" can include both cases where elements are "physically connected" and cases where elements are "not physically connected." Additionally, the terms "first," "second," etc., can be used to distinguish one element from another and do not limit the order and / or importance associated with the elements. In some cases, without departing from the scope of the claims, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0075] In this disclosure, the term "example embodiment" may not refer to the same example embodiment and may be provided to describe and highlight the distinct features of each example embodiment. The example embodiments suggested above may be implemented without excluding the possibility of combining features with those of other example embodiments. For example, unless otherwise indicated, even if a feature described in one example embodiment is not described in other example embodiments, the description may be understood to be relevant to other example embodiments.

[0076] Unless they have a distinctly different meaning in the context, a statement used in the singular form contains a statement used in the plural form.

[0077] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: The substrate body includes multiple wiring layers and multiple via layers, wherein the multiple wiring layers include a pair of first wiring patterns, the pair of first wiring patterns being spaced apart from each other and disposed at the same height relative to the thickness direction of the printed circuit board; and The first redistribution unit includes one or more first redistribution layers, wherein the one or more first redistribution layers include a first redistribution pattern, the first redistribution pattern being disposed at a height different from the height of the pair of first wiring patterns relative to the thickness direction. The first redistribution unit is embedded in the substrate body, and The first redistribution pattern connects the pair of first wiring patterns to each other.

2. The printed circuit board according to claim 1, in, The plurality of via layers includes a pair of first connection vias that connect the first redistribution pattern to each of the pair of first wiring patterns.

3. The printed circuit board according to claim 1, in, The plurality of wiring layers further includes a pair of second wiring patterns, the pair of second wiring patterns being spaced apart from each other and disposed at the same height relative to the thickness direction. The one or more first redistribution layers further include a second redistribution pattern, the second redistribution pattern being disposed at a height different from the height of the pair of second wiring patterns relative to the thickness direction. The second redistribution pattern connects the pair of second wiring patterns to each other.

4. The printed circuit board according to claim 3, wherein, The plurality of via layers includes a pair of second connection vias that connect the second redistribution pattern to each of the pair of second wiring patterns.

5. The printed circuit board according to claim 3, in, The pair of first wiring patterns and the pair of second wiring patterns are positioned at the same height relative to the thickness direction, and When the substrate body and the first redistribution unit are viewed along the thickness direction, the second redistribution pattern is superimposed on at least one of the pair of first wiring patterns.

6. The printed circuit board according to claim 3, in, The virtual lines connecting the two ends of the pair of first wiring patterns, spaced apart by a minimum distance, intersect with the virtual lines connecting the two ends of the pair of second wiring patterns, also spaced apart by a minimum distance.

7. The printed circuit board according to claim 3, wherein, The first redistribution pattern and the second redistribution pattern are spaced apart from each other and are positioned at the same height relative to the thickness direction.

8. The printed circuit board according to claim 3, wherein, The first redistribution pattern and the second redistribution pattern are positioned at different heights relative to the thickness direction.

9. The printed circuit board according to claim 1, further comprising: The second redistribution unit includes one or more second redistribution layers. The plurality of wiring layers further includes a pair of third wiring patterns, the pair of third wiring patterns being spaced apart from each other and disposed at the same height relative to the thickness direction. Wherein, the one or more second redistribution layers include a third redistribution pattern, the third redistribution pattern being disposed at a height different from the height of the pair of third wiring patterns relative to the thickness direction, and The third redistribution pattern connects the pair of third wiring patterns to each other.

10. The printed circuit board according to claim 9, wherein, The plurality of via layers includes a pair of third connection vias that connect the third redistribution pattern to each of the pair of third wiring patterns.

11. The printed circuit board according to claim 9, in, The pair of third wiring patterns are positioned at a height different from that of the pair of first wiring patterns relative to the thickness direction, and The second redistribution unit is embedded in the substrate body and is positioned at a height different from that of the first redistribution unit relative to the thickness direction.

12. The printed circuit board according to claim 9, in, The pair of third wiring patterns are positioned at the same height as the pair of first wiring patterns relative to the thickness direction, and The second redistribution unit is embedded in the substrate body and is positioned at the same height as the first redistribution unit relative to the thickness direction.

13. The printed circuit board according to claim 1, in, The plurality of wiring layers include a first ground pattern, and The first redistribution unit is attached to the first grounding pattern via an adhesive film.

14. The printed circuit board according to claim 13, wherein, The plurality of via layers includes a ground connection via that penetrates the first redistribution unit and the adhesive film and is connected to the first grounding pattern.

15. The printed circuit board according to claim 13, in, The one or more first redistribution layers are constructed as a plurality of first redistribution layers, and The first redistribution unit includes a plurality of first redistribution via layers that connect adjacent first redistribution layers among the plurality of first redistribution layers.

16. The printed circuit board according to claim 15, wherein, The plurality of first redistribution layers include a structure in which a first redistribution layer including a redistribution pattern is alternately stacked with another first redistribution layer including a second grounding pattern.

17. The printed circuit board according to claim 15, in, Among the plurality of first redistribution layers, the first redistribution layer disposed on the uppermost side in the thickness direction includes a pair of first connection pads connected to each of the pair of first wiring patterns, and Among the plurality of first redistribution layers, the thickness of the first redistribution layer disposed on the uppermost side in the thickness direction is greater than the thickness of each of the other first redistribution layers.

18. A printed circuit board, comprising: A pair of first wiring patterns are disposed on the same first layer and spaced apart from each other on the same first layer; A pair of second wiring patterns are disposed on the same second layer and spaced apart from each other on the same second layer; A first redistribution unit includes a first redistribution pattern, the first redistribution pattern being disposed in a layer different from the pair of first wiring patterns and connecting the pair of first wiring patterns to each other. The second redistribution unit includes a second redistribution pattern, which is disposed in a different layer than the pair of second wiring patterns and connects the pair of second wiring patterns to each other.

19. The printed circuit board according to claim 18, in, The printed circuit board has a multilayer wiring substrate structure, which includes multiple insulating layers, multiple wiring layers, and multiple via layers. The plurality of wiring layers include the pair of first wiring patterns and the pair of second wiring patterns, and The first redistribution unit and the second redistribution unit are embedded in the plurality of insulating layers at the same height relative to the thickness direction of the printed circuit board, or in the plurality of insulating layers at different heights relative to the thickness direction.

20. The printed circuit board according to claim 18, in, The first layer and the second layer are positioned at the same height or at different heights relative to the thickness direction of the printed circuit board.

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