Preparation method of embedded word line
By forming a nitrogen-containing mask layer within the word line trench and etching back the metal layer to form a stepped metal layer, combined with a semiconductor layer and a capping layer, the problem of the sloping structure at the end of the word line is solved, the GIDL problem of the memory device is improved, and the performance and reliability of the device are enhanced.
Patent Information
- Application Number
- CN202411183636.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2026-03-03
AI Technical Summary
In existing buried word line technology, the word line ends have a sloping structure, which leads to gate-induced drain leakage (GIDL) at the end of the memory cell in the memory array word line, affecting the performance of the memory device.
A nitrogen-containing mask layer is formed in the word line trench. The metal layer is then etched back using a fluorine-containing gas to form a stepped metal layer. A semiconductor layer and a capping layer are then filled on top of this layer to form an ideal vertical structure. This reduces the load effect during the etching process of the contact holes of the word line contact plug and solves the problems of word line contact plugs and open circuits in word lines.
It effectively improves the gate-induced drain leakage (GIDL) problem at the end of the word line of the memory array, thereby enhancing the performance and reliability of the memory device.
Smart Images
Figure CN121604398A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method for fabricating embedded word lines. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a type of volatile memory. A DRAM device typically includes a memory array region composed of memory cells and a peripheral region composed of logic control circuitry. A typical memory cell includes a switching structure (such as a transistor) and a storage structure (such as a capacitor). The logic control circuitry in the peripheral region addresses each memory cell in the memory array region via multiple word lines and bit lines that pass through the memory array region, and activates the switching structure to electrically connect with the storage structure to perform data read, write, or access. In advanced semiconductor manufacturing, by employing an architecture with embedded word lines, the chip size of DRAM devices can be significantly reduced. This architecture allows the active regions of the memory cells to be arranged with dense spacing, achieving higher cell density.
[0003] As semiconductor devices, including logic controllers and memory devices, are shrunk to smaller sizes, the technical hurdles facing patterning processes are becoming increasingly significant. For example, in existing buried word line processes, the word line ends have a sloping structure, which further leads to gate-induced drain leakage (GIDL) at the end of the memory cell in the memory array word line. Summary of the Invention
[0004] According to embodiments of this disclosure, a method for fabricating embedded word lines is provided, comprising: providing a substrate; forming word line trenches in the substrate; forming a gate dielectric layer within the word line trenches; filling the word line trenches with a metal layer located on the surface of the gate dielectric layer; forming a nitrogen-containing mask layer within the word line trenches, the nitrogen-containing mask layer covering the end region of the metal layer; using the nitrogen-containing mask layer as a mask, etching back the metal layer with a fluorine-containing gas to form a metal layer with a stepped shape; filling the word line trenches with a semiconductor layer located on a portion of the metal layer with a stepped shape; using the nitrogen-containing mask layer as a mask, etching back the semiconductor layer; and forming a capping layer in the remaining word line trenches.
[0005] In some embodiments, the fluorine-containing gas is carbon fluoride.
[0006] In some embodiments, the thickness of the nitrogen-containing mask layer is 5nm-25nm.
[0007] In some embodiments, the nitrogen-containing mask layer is silicon nitride, the metal layer is metal nitride, and the semiconductor layer is doped polysilicon.
[0008] In some embodiments, the stepped metal layer includes a first upper surface, a second upper surface, and a side surface connecting the first upper surface and the second upper surface, the first upper surface and the second upper surface being parallel, and the side surface being substantially perpendicular to the first upper surface and the second upper surface.
[0009] In some embodiments, the step of forming a nitrogen-containing mask layer in a word line trench includes: forming a nitrogen-containing mask layer material covering a metal layer, and forming a photoresist layer covering the nitrogen-containing mask layer material in an end region; using the photoresist layer as a mask, etching the nitrogen-containing mask layer material with a hydrogen and fluorine-containing gas to form a nitrogen-containing mask layer, the nitrogen-containing mask layer covering the end region of the metal layer.
[0010] In some embodiments, the hydrogen and fluorine-containing gas is composed of carbon, hydrogen, and fluorine.
[0011] In some embodiments, the step of forming a capping layer within a word line trench includes: retaining a nitrogen-containing mask layer, depositing a capping layer material on a semiconductor layer and a nitrogen-containing mask layer; patterning the capping layer material, removing the capping layer material outside the word line trench, and forming the remaining capping layer material and the nitrogen-containing mask layer within the word line trench as a capping layer, wherein the capping layer conformally covers the surface of the semiconductor layer and the surface of a metal layer having a stepped shape.
[0012] In some embodiments, the substrate includes an array region and a peripheral region, and a contact region located between the array region and the peripheral region, with the end region located within the contact region.
[0013] In some embodiments, the method further includes forming a through-cover layer that directly contacts a word line contact plug having a stepped metal layer.
[0014] This disclosure provides a method for fabricating embedded word lines. By forming a nitrogen-containing mask layer in the end region of the metal layer in the embedded word line, and etching back the metal layer with a fluorine-containing gas to form a metal layer with a stepped shape, followed by the formation of a semiconductor layer and a capping layer, an ideal vertical structure can be formed at the end of the word line. This effectively reduces the load effect during the etching process of the contact hole of the word line contact plug, solves the problems of word line contact plugs and open circuits in word lines, and further improves the gate-induced drain leakage (GIDL) problem of memory cells at the end of the word line in the memory array. Attached Figure Description
[0015] Figure 1 This is a plan view of a semiconductor device according to an exemplary embodiment;
[0016] Figure 2 It is along Figure 1 A sectional view taken by line A-A' in the middle;
[0017] Figure 3This is a schematic diagram illustrating the process of fabricating embedded character lines according to an exemplary embodiment.
[0018] Figures 4 to 18 This is a cross-sectional view illustrating various stages in the fabrication process of an embedded character line according to an exemplary embodiment.
[0019] Figures 19 to 22 This is a cross-sectional view illustrating the fabrication process of an embedded word line according to yet another exemplary embodiment.
[0020] Figure 23 This is a schematic diagram of the structure of an electronic device according to an exemplary embodiment. Detailed Implementation
[0021] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0022] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0023] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0024] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0025] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0026] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0027] Figure 1 This is a plan view of a semiconductor device according to an exemplary embodiment. Figure 2 It is along Figure 1 The sectional view taken by line A-A' in the middle.
[0028] Please refer to Figure 1 and Figure 2 This disclosure provides a semiconductor device including a substrate 100, buried word lines 200, bit lines 300, word line contact plugs 400 and 500, and logic control circuitry 600. The semiconductor device is, for example, a 6F... 2 The architecture of a dynamic random access memory (DRAM) device, where "F" represents the feature size corresponding to the cell.
[0029] The substrate 100 includes a memory array region 100A, an edge region 100B, and a peripheral region 100C. Multiple memory cells (each consisting of one transistor and one capacitor, 1T1C) are disposed within the array region 100A, and buried word lines 200 and bit lines 300 are coupled to the memory cells, respectively. Within the array region 100A, the substrate 100 is isolated from each other by shallow trench isolation structures 101 (STI) to define multiple first active regions 110 arranged in an array. The transistors of the memory cells in the array region 100A are formed on the first active regions 110.
[0030] The peripheral region 100C is located around the array region 100A. The logic control circuit 600 is disposed in the peripheral region 100C to address the memory cells within the array region 100A and perform data read and write operations. In the peripheral region 100C, the substrate 100 is isolated from each other by shallow trench isolation structures 101 (STI) to define a plurality of second active regions 120. The transistors of the logic control circuit 600 in the peripheral region 100C are formed on the second active regions 120.
[0031] Edge region 100B is located between array region 100A and peripheral region 100C. Word line contact plugs 400 and bit line contact plugs 500 are located in edge region 100B, leading out the buried word line 200 and bit line 300 of array region 100A, respectively. In edge region 100B, substrate 100 is not defined as an active region, but is only filled by shallow trench isolation structure 101 (STI), which isolates the active regions 110 and 120 of array region 100A and peripheral region 100C.
[0032] The substrate 100 is made of semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The shallow trench isolation structure 101 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride to electrically isolate the active regions 110 and 120.
[0033] Please continue to refer to this. Figure 1 and Figure 2 The buried word line 200 is located within the substrate 100 and extends in a direction parallel to the surface of the substrate 100. Each buried word line 200 passes through a plurality of first active regions 110 and STI 101 along this direction and is connected to the gate of the memory cell transistor.
[0034] In this embodiment, the buried word line 200 includes a gate dielectric layer 210, a metal layer 220, a semiconductor layer 230, and a capping layer 240. The buried word line 200 extends from an array region 100A to a contact region 100B, with its end region located within the contact region 100B. The buried word line 200 has an ideal vertical structure in its end region; for example, the metal layer 220 extends from the array region 100A to the contact region 100B and has an upward protrusion in the contact region 100B, forming a stepped metal layer 220. Please refer to... Figure 2The enlarged portion within the central circle, the stepped metal layer 220, includes a first upper surface 221, a second upper surface 222, and a side surface 223 located between the first upper surface 221 and the second upper surface 222. The first upper surface 221 and the second upper surface 222 are respectively the lower-order and higher-order surfaces of the stepped metal layer 220, and they are parallel to each other. The first upper surface 221 extends from the array region 100A to the contact region 100B, and the second upper surface 222 extends within the contact region 100B. The side surface 223 extends within the contact region 100B and connects the first upper surface 221 and the second upper surface 222. The side surface 223 and the first upper surface 221 / second upper surface 222 are in a generally perpendicular relationship; for example, the angle between the side surface 223 and the first upper surface can vary in the range of 60-120°, and further, in the range of 80-110°.
[0035] The semiconductor layer 230 in the embedded word line 200 also extends from the array region 100A to the contact region 100B. The semiconductor layer 230 is located on a partially stepped metal layer 220. Exemplarily, the semiconductor layer 230 is located on the first upper surface 221 and side surface 223 of the stepped metal layer 220, but not on the second upper surface 222. The capping layer 240 conformally covers the surface of the semiconductor layer 230 and the surface of the stepped metal layer 220. The metal layer 220 has a stepped shape at its end. The semiconductor layer 230 is located on the partially stepped metal layer 220 and exposes the metal layer at the end. This allows the buried word line 200 to have an ideal vertical structure at the end region, ensuring that the end of the metal layer 220 has a thicker conductive portion. The subsequent word line contact plug 400 can penetrate the cover layer 240 and directly contact the metal layer 220, effectively reducing the load effect during the contact hole etching process of the word line contact plug 400. This solves the problems of word line contact plugs and word lines being open-circuited, and further improves the gate-induced drain leakage (GIDL) problem of memory cells at the end of the word line in the memory array.
[0036] The gate dielectric layer 210 in the embedded word line 200 can be selected from silicon oxide, silicon nitride, silicon oxynitride, and high-k dielectric films with a higher dielectric constant than silicon oxide, such as any one or any combination of hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO3), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (Al2O3), tantalum oxide (Ta2O3), and lead scandium tantalum oxide (PbScTaO). Metal layer 220 is selected from high work function metals or metal nitrides, such as tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), and tantalum aluminum nitride (TaAlN). Semiconductor layer 230 is selected from low work function polycrystalline silicon layers, such as n-type or p-type doped polycrystalline silicon. The combination of semiconductor layer 230 and metal layer 220 can form a double work function gate, effectively improving the GIDL problem of the device. Capping layer 240 is at least one of silicon oxide, silicon nitride, and silicon oxynitride, protecting the device surface.
[0037] Please continue to refer to this. Figure 1 and Figure 2 Bit line 300 extends in a direction parallel to the surface of substrate 100, located above and perpendicular to embedded word line 200. Bit line 300 can be electrically connected to the first source region 110 via a contact plug (BLC) (not shown). Bit line 300 includes a bit line conductive layer, a bit line capping layer, and a sidewall layer covering the bit line conductive layer and bit line capping layer on the BLC. Bit line 300 extends from array region 100A to contact region 100B, with the end region of bit line 300 located within contact region 100B. Bit line contact plug 500 is located in contact region 100B and connects to bit line 300 in contact region 100B, leading out the signal of bit line 300.
[0038] The bit line conductive layer in bit line 300 can be selected from at least one of doped polysilicon, metal, metal nitride, or metal carbide, such as tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), aluminum tantalum carbonitride (TaAlCN), and silicon tantalum carbonitride (TaSiCN). For example, the bit line conductive layer can be a single layer or a stack of the above materials. The bit line capping layer is, for example, silicon nitride or silicon oxynitride. The sidewall layer is, for example, a non-ON stack of silicon nitride, silicon oxide, and silicon nitride. The bit line 300 and the buried word line 200 / substrate 100 can be isolated from each other by an insulating layer 205.
[0039] Please continue to refer to this. Figure 1 and Figure 2 The semiconductor device may also include a capacitor located in the array region 100A and above the bit line 300 and the buried word line 200. The capacitor is connected to the first active region 110 via a storage node plug (NC) 700. The capacitor may be a cylinder or a pillar capacitor.
[0040] Please continue to refer to this. Figure 1 and Figure 2 The word line contact plug 400 and the bit line contact plug 500 are located in contact areas 100B, and may be located in different contact areas 100B. The word line contact plug 400 is located at the end of the embedded word line 200 in the extending direction, and multiple word line contact plugs 400 are arranged at intervals. The word line contact plugs 400 of adjacent embedded word lines 200 may be arranged alternately on both sides of the embedded word line 200. The bit line contact plug 500 is located at the end of the bit line 300 in the extending direction, and the bit line contact plugs 500 of adjacent bit lines 300 may also be arranged alternately on both sides of the bit line 300.
[0041] Please continue to refer to this. Figure 1 and Figure 2 The logic control circuit 600 is located in the peripheral region 100C and includes, for example, multiple transistors. These transistors include a second active region 120, a gate structure 610 located above and directly in contact with the second active region 120, and source / drain regions 120a and drain / source regions 120b located in the second active region 120 and on opposite sides of the gate structure 610. These transistors can be of different types, forming corresponding devices such as sense amplifiers and word line drivers, to control the reading of memory cells within the array region 100A.
[0042] Figure 3This is a flowchart illustrating a method for preparing an embedded word line according to an exemplary embodiment. Figures 4 to 18 This is a schematic cross-sectional view illustrating the various stages of fabricating an embedded word line according to an exemplary embodiment. Please continue to refer to... Figure 1-18 The method for fabricating the embedded word line 200 provided in this disclosure will be described in detail. It should be understood that... Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs.
[0043] Please refer to Figure 3 , Figures 1 to 2 ,as well as Figure 4 Step S10 is performed to provide a substrate 100. In some embodiments, the substrate 100 includes a storage array region 100A, an edge region 100B, and a peripheral region 100C. The substrate 100 is defined by ST1 101, which isolates it from each other, to form a plurality of first active regions 110 and a plurality of second active regions 120. The plurality of first active regions 110 are located in the array region 100A and are defined and isolated from each other by ST1 101. The plurality of second active regions 120 are located in the peripheral region 100C and are defined and isolated from each other by ST1 101. The edge region 100B does not include active region structures and only includes ST1 101. Exemplarily, the substrate 100 can be patterned to form active regions 110 and 120 and to fill ST1 101, which is higher than the surface of the substrate 100 and covers the substrate 100 to protect the substrate 100.
[0044] Please refer to Figure 3 ,as well as Figure 5 Step S20 is executed to form a word line trench 200a in the substrate 100. To form the word line trench 200a, the first active region 110 and ST1 101 can be etched in the array region 100A of the substrate 100, and a portion of ST1 101 can be etched in the contact region 100B. The etching depth of the word line trench 200a can be 150nm-300nm, for example, 150nm, 180nm, 220nm, 260nm, etc. Therefore, the height of the buried word line 200 formed within the word line trench 200a is also between 150nm and 300nm, ensuring device performance. Word line trench 200a extends from array region 100A to contact region 100B. Both ends of word line trench 200a are located within contact region 100B. Word line trench 200a is located in array region 100A and partially within contact region 100B. The portion located in contact region 100B forms the end region of the word line. Word line trench 200a exposes multiple first active regions 110, which protrude in a saddle shape from STI 101.
[0045] Please continue to refer to this. Figure 3 ,as well as Figure 5 Step S30 is executed to form a gate dielectric layer 210 within the word line trench 200a. The gate dielectric layer 210 can be formed on the surface of the exposed word line trench 200a using in-situ vapor deposition (ISSG) and / or atomic layer deposition (ALD). The gate dielectric layer 210 extends within the word line trench 200a, and its thickness should not be too thick, for example, within the range of 3-10 nm, to ensure the electrical performance of the memory cell transistor.
[0046] Please continue to refer to this. Figure 3 ,as well as Figures 6 to 7 In step S40, a metal layer 220b is filled into the word line trench 200a. The metal layer 220b is located on the surface of the gate dielectric layer 210. Please refer to... Figure 6 A metal layer material 220a can be deposited within the word line trench 200a, filling the trench 200a and extending beyond it, for example, extending into the remaining contact area 100B and the peripheral area 100C. Please refer to [further details to be added]. Figure 7 The metal layer material 220a is etched back to form a metal layer 220b, the upper surface of which is lower than the upper surface of the contact region 100B / peripheral region 100C. This back-etching process not only removes the metal layer material 220a outside the word line trench 200a, but also continues to etch downwards, providing formation space for the deposition of the semiconductor layer 230 and the capping layer 240 within the word line trench 200a.
[0047] Please continue to refer to this. Figure 3 ,as well as Figures 8 to 1 0. Execute step S50 to form a nitrogen-containing mask layer 201b within the word line trench 200a, the nitrogen-containing mask layer 201b covering the end region of the metal layer 220b. Please refer to... Figure 8 A nitrogen-containing mask layer material 201a is formed on the surface of the metal layer 220b within the word line trench 200a. The nitrogen-containing mask layer material 201a covers the surface of the metal layer 220b and extends to cover the remaining contact area 100B and the peripheral area 100C. Subsequently, the surface of the nitrogen-containing mask layer material 201a is planarized using a chemical mechanical polishing (CMP) process, and the planarized nitrogen-containing mask layer material 201a covers the entire surface of the substrate 100. Please refer to [further details to be provided]. Figure 9 A photoresist layer 202 is formed on the nitrogen-containing mask layer material 201a, and the photoresist layer 202 covers the nitrogen-containing mask layer material at the end region of the metal layer 220b. Exemplarily, the photolithographic pattern can cover the peripheral region 100C and part of the contact region 100B, i.e., part of the end region, while exposing the main part of the word line. Please refer to [further details]. Figure 10aand Figure 10b , Figure 10a A cross-sectional view of the formation of the nitrogen-containing mask layer is shown. Figure 10b The diagram shows a planar view of the formation of a nitrogen-containing mask layer. Using photoresist layer 202 as a mask, the nitrogen-containing mask layer material 201a is etched with a hydrogen and fluorine-containing gas to form a nitrogen-containing mask layer 201b. Figure 10b As shown, the nitrogen-containing mask layer 201b is located within a portion of the word line trench 200a and extends beyond the word line trench 200a. It extends in a direction parallel to the substrate 100, covering the end regions of multiple spaced metal layers 220b and the STI 101 regions between adjacent metal layers 220b. Furthermore, it can also cover the STI 101 of the remaining contact region 100B and the peripheral region 100C. The thickness of the nitrogen-containing mask layer 201b on the metal layer 220b is relatively thicker, while the thickness of the STI 101 between adjacent metal layers 220b is relatively thinner. The thickness of the remaining contact area 100B and the peripheral area 100C can be the same as that of the STI 101 between adjacent metal layers 220b. This ensures that the blocked portion of the metal layer 220b is protected when the exposed metal layer 220b is etched back, and also facilitates the removal of the nitrogen-containing mask layer material 201a on the peripheral area 100C in subsequent processes.
[0048] The nitrogen-containing mask layer material 201a and the nitrogen-containing mask layer 201b formed after photolithographic pattern transfer are both silicon nitride. The hydrogen and fluorine-containing gas is composed of carbon, hydrogen, and fluorine, such as CH3F, CH2F2, and CHF3. Based on the high etch selectivity between the layer materials, CH3F can be selected. Using silicon nitride hard mask material, CH3F is selected as the etch gas for the silicon nitride hard mask to transfer the pattern of the photoresist layer 202. CH3F has a high SiN / SiO2 etch selectivity, reducing damage to the gate dielectric layer 210 of the memory array. At the same time, silicon nitride has a stronger ability to block lateral etching than the photoresist layer, avoiding the slope problem caused by directly using the photoresist layer 202 as a mask to etch back down to the metal layer 220b. In addition, during the pattern transfer process of the photoresist layer, in addition to using CH3F as the etching gas, oxygen (O2) can also be used, with a ratio of (2-5):1. Using etching gases within the above range can ensure complete removal of the silicon nitride mask in the memory array area while avoiding damage to the gate dielectric.
[0049] The thickness of the nitrogen-containing mask layer 201b is between 5-25 nm, such as 5 nm, 10 nm, 15 nm, 20 nm, and 25 nm. It is important to note that the thickness of the nitrogen-containing mask layer 201b here refers to the thickness of the nitrogen-containing mask layer 201b covering the metal layer 220b. With a fixed depth of the word line trench 200a, the nitrogen-containing mask layer 201b at this location acts as a barrier mask for the etch-back metal layer 220b. If the thickness is too high, the overall nitrogen-containing mask layer becomes too thick, which is detrimental to the formation of the stepped metal layer 220 and makes it difficult to completely remove the nitrogen-containing mask layer located outside the end region, such as the peripheral region 100C. If the thickness is too low, the barrier effect of the nitrogen-containing mask layer is poor, which is also detrimental to the formation of the stepped metal layer 220 and can easily cause damage to the array region gate dielectric layer 210.
[0050] Please continue to refer to this. Figure 3 ,as well as Figures 11 to 12 In step S60, using a nitrogen-containing mask layer 201b as a mask, a metal layer 220 with a stepped shape is formed by etching back the metal layer 220b with a fluorine-containing gas. Multiple nitrogen-containing mask layers 201 are formed after etching and are located in the end regions of the word line trench 200a. In this embodiment, each metal layer 220 has a stepped shape at both ends. In one embedded word line 200, a corresponding word line contact plug 400 is connected to the metal layer 220 of the embedded word line 200 from one end. In an adjacent embedded word line 200, a corresponding word line contact plug 400 is connected to the metal layer 220 of the embedded word line 200 from the other end. That is, the word line contact plugs 400 of adjacent embedded word lines 200 can be arranged alternately on both sides of the embedded word line 200.
[0051] In this embodiment of the present disclosure, a nitrogen-containing mask layer 201b, such as silicon nitride, is used as a mask, and STI 101 is used as an etch stop layer. Fluorine-containing gas is used to etch back the metal layer 220b until STI 101 is exposed. The nitrogen-containing mask layer 201b and the metal layer 220b have a high etch selectivity ratio. The nitrogen-containing mask layer 201b has an ideal ability to block lateral etch, protecting the unexposed metal layer 220b below. A generally vertical stepped structure is formed in the metal layer 220b, thereby forming an ideal vertical structure at the end of the word line. The stepped metal layer 220 includes a first upper surface 221, a second upper surface 222, and a side surface 223 located between the first upper surface 221 and the second upper surface 222. The first upper surface 221 and the second upper surface 222 are the lower-order and higher-order surfaces of the stepped metal layer 220, respectively, and are parallel to each other. The etched nitrogen-containing mask layer 203 covers the second upper surface 222, exposing the first upper surface 221 and the side surface 223. The first upper surface 221 extends from the array region 100A to the contact region 100B, and the second upper surface 222 extends within the contact region 100B. The side surface 223 extends within the contact region 100B and connects the first upper surface 221 and the second upper surface 222. The side surface 223 is approximately perpendicular to the first upper surface 221 and the second upper surface 222. For example, the included angle between the side surface 223 and the first upper surface 221 can vary in the range of 60-120°, and further, it can be in the range of 80-110°.
[0052] Please continue to refer to this. Figure 12 and Figure 18 For example, the stepped structure is completely vertical, that is, the side surface 223 and the first upper surface 221 and the second upper surface 222 are completely perpendicular, avoiding the sloped structure at the end of the word line that would cause gate-induced drain leakage (GIDL) at the end of the memory cell in the memory array WL. In this embodiment, a nitrogen-containing mask layer 201, such as silicon nitride, is used as a hard mask material to fabricate the buried word line, forming an ideal vertical structure at the end of the word line. The metal layer protrudes vertically upward in the end region, and the metal layer has two parts of thickness, with a thicker metal layer in the end region, closer to the top of the word line trench 200a. When the contact hole of the word line contact plug 400 is subsequently formed, the problem of open circuit between the contact hole and the word line can be improved, the load effect during the contact hole etching process can be reduced, and the device performance can be improved. Of course, it is not limited to this; a roughly vertical structure can also be understood as a non-perfectly vertical case. For examples, please refer to Figure 18 and Figure 22This illustrates other morphologies of the stepped metal layer 220. It is worth noting, of course, that through the fabrication method of this embodiment, the included angle between the side surface 223 and the first upper surface 221 and the second upper surface 222 can be in the range of 80-110°, with a maximum range of 60-120°, without deviating from this range.
[0053] Please continue to refer to this. Figure 11 The metal layer is selected from metals or metal nitrides with high work function, such as tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), and tantalum aluminum nitride (TaAlN). As mentioned above, based on the angle of the nitrogen-containing mask layers 201b and 201 being silicon nitride composed of only nitrogen and silicon, the metal layer can be, for example, titanium nitride (TiN). The etching between titanium nitride and silicon nitride is selected with a high selectivity. Further, by controlling the etching selectivity ratio of titanium nitride to silicon nitride, for example, controlling the etching selectivity ratio to be greater than or equal to 5:1, and further greater than or equal to 10:1. For example, a fluorine-containing gas, such as carbon tetrafluoride (CF4), can ensure that the etching selectivity ratio between titanium nitride and silicon nitride is greater than or equal to 5:1, and further greater than or equal to 10:1, thereby protecting the titanium nitride in the end region from lateral etching and the formation of a slope. Furthermore, using silicon nitride as a mask, the CF4 etching gas can achieve a high etching selectivity between silicon nitride and the array region gate dielectric layer 210, such as silicon dioxide, preventing damage to the memory array gate dielectric layer 210. In addition, during the etching back of the metal layer 220b using the nitrogen-containing mask layer 201b as a mask, oxygen (O2) can be used in addition to the CF4 etching gas, with a ratio of (1-3):1. Using etching gases within this range ensures that the etching back depth of titanium nitride meets the requirements while the silicon nitride in the peripheral area is cleanly etched. It is worth noting that excessive O2 should be avoided to prevent oxidation of the titanium nitride surface, which could lead to excessively high contact resistance.
[0054] Please continue to refer to this. Figure 3 , Figures 13 to 14 In step S70, a semiconductor layer 230b is filled into the word line trench 200a. The semiconductor layer 230b is located on a portion of the stepped metal layer 220. Please refer to [reference needed]. Figure 13 Semiconductor layer material 230a is filled into the word line trench 200a. Semiconductor layer material 230a can cover the entire surface of the substrate 100, that is, the surface of the layer material covering the array region 100A, the contact region 100B, and the peripheral region 100C. Please refer to [the relevant documentation / reference] for further details. Figure 14Using the etched nitrogen-containing mask layer 201 on the second upper surface 222 of the metal layer 220 as a polishing stop layer, the semiconductor layer material 230a is planarized by chemical mechanical polishing (CMP) to form a semiconductor layer 230b. The semiconductor layer 230b is located on the stepped portion of the metal layer 220 exposed by the nitrogen-containing mask layer 201, for example, covering the first upper surface 221 and side surfaces 223 of the stepped metal layer 220, and is flush with the surface of the etched nitrogen-containing mask layer 201 on the second upper surface 222 of the metal layer 220. The semiconductor layer 230b can be n-type or p-type doped polysilicon, forming a dual-function conductive layer with the metal layer 220, such as titanium nitride, with both low and high work functions, thus improving the GIDL problem of the device.
[0055] Please continue to refer to this. Figure 3 , Figure 14 and Figure 15 In step S80, using the nitrogen-containing mask layer 201 (the remaining material after the nitrogen-containing mask layer 201b has been etched) as a mask, the semiconductor layer 230b is etched back. The nitrogen-containing mask layer 201 and the semiconductor layer 230b are flush. The etching selectivity between the semiconductor layer 230b (e.g., doped polysilicon) and the nitrogen-containing mask layer 201 (e.g., silicon nitride) is high. Using silicon nitride as a mask, fluorine- and sulfur-containing gases are used to etch back the semiconductor layer 230b downwards to thin it. The etched semiconductor layer 230 is thinner than the minimum thickness of the stepped metal layer 220, in order to adjust the work function of the device while reducing its resistance. The etched semiconductor layer 230 is located on the lower surface of the stepped metal layer 220, that is, on the first upper surface 221 of the stepped metal layer 220. In this embodiment of the disclosure, by directly forming a thinner semiconductor layer 230 on a partially stepped metal layer 220, instead of first forming a metal layer 220 covering the entire stepped metal layer 220 and then etching the semiconductor layer 230 to expose the metal layer at the end region again (i.e., the second upper surface 222 of the metal layer), not only can the process be saved, but damage to the word line conductive layer can also be avoided.
[0056] Please continue to refer to this. Figure 3 , Figures 16 to 18 Step S90 is performed to form a cover layer 240 within the remaining word line groove 200a. For an example, please refer to [reference needed]. Figure 16Following the aforementioned etch-back process, from a process-saving perspective, the nitrogen-containing mask layer 201 can be retained without removing it, and a capping layer material 203 can be deposited directly on the etched semiconductor layer 230 and the nitrogen-containing mask layer 201. For example, it can be at least one selected from silicon oxide, silicon nitride, and silicon oxynitride. The capping layer material 203 covers the entire substrate 100, that is, it covers the array region 100A, the contact region 100B, and the peripheral region 100C, and has a stepped shape. Please refer to [further details to be added]. Figure 17 First, an oxide layer 204, such as silicon oxide, is deposited over the entire surface to reduce peeling that may occur in subsequent processes. Then, a capping material 203 is used as a polishing stop layer, and the entire device surface is planarized using a chemical mechanical polishing (CMP) process. Afterwards, please refer to... Figure 18 Using oxide layer 204 as a mask layer, capping layer material 203 is etched downwards to remove capping layer material outside word line trench 200a, and the remaining oxide layer 204 is removed. The capping layer material 203 within word line trench 200a and the nitrogen-containing mask layer 201 form capping layer 240. Subsequently, excess STI 101 material on the substrate 100 of the peripheral region 100C and part of the contact region 100B can be further removed to reduce the height difference between the array region 100A and the contact region 100B / peripheral region 100C. Figure 18 As shown, the capping layer 240 fills the remaining space of the word line trench 200a, partially covering the surface of the semiconductor layer 230 and partially covering the surface of the metal layer 220. The capping layer 240 is located in the array region 100A and a portion of the contact region 100B, and is flush with the upper surface of the remaining contact region 100B and the peripheral region 100C. For other embodiments, please refer to... Figure 16 and Figure 18 Alternatively, after depositing capping material 203 directly on the etched semiconductor layer 230 and the nitrogen-containing mask layer 201, the capping material 203 can be planarized using a chemical mechanical masking (CMP) process. Then, the capping material 203 is etched again to remove the capping material 203 outside the word line trench 200a. The remaining capping material 203 within the word line trench 200a and the nitrogen-containing mask layer 201 form the capping layer 240. Finally, excess STI 101 material on the substrate 100 in the peripheral region 100C and part of the contact region 100B is removed.
[0057] It is worth noting that, Figures 16 to 18 This is an exemplary embodiment of the present disclosure. In other embodiments, the nitrogen-containing mask layer 201 may be removed first, and a cover layer material 203 may be formed directly on the surface of the semiconductor layer 230 and the metal layer 220. The patterned cover layer material 203 serves as a cover layer 240, in which case the cover layer 240 does not include the nitrogen-containing mask layer 201.
[0058] The method for fabricating embedded character lines also includes forming a character line contact plug 400 that penetrates the cover layer 240 and directly contacts the stepped metal layer 220. Please return to the reference. Figure 1 and Figure 2 The capping layer 240 fills the remaining word line trenches 200a, flush with the upper surface of the contact region 100B / peripheral region 100C. Insulating layers 205 and 206, selected from at least one of silicon oxide, silicon nitride, or silicon oxynitride, can be formed across the entire surface. These insulating layers 205 and 206 can be a single layer or a stacked layer. Then, bit lines 300 and capacitor contact plugs 700 are formed in the insulating layer 206 in the array region 100A. Contact holes exposing the second upper surface 222 of the stepped metal layer 220 are formed in the insulating layers 205 and 206 in the contact region 100B, for example, above the end region of the embedded word line 200. Word line contact plugs 400 are then formed within the contact holes.
[0059] Figures 19 to 22 Cross-sectional views of various stages in another embodiment of the fabrication of embedded character lines are shown. In this embodiment, the side surface 223 of the stepped metal layer 220 and the first upper surface 221 / second upper surface 222 are not perfectly perpendicular; instead, the side surface 223 intersects the first upper surface 221 / second upper surface 222 at a slight inclination. The fabrication process of the embedded character lines in this embodiment is similar to... Figures 1 to 18 The fabrication process for embedded character lines described is basically the same.
[0060] Please refer to Figures 19 to 22 After forming a nitrogen-containing mask layer 201b at the end region of the metal layer 220b, the thickness of the nitrogen-containing mask layer 201b and the flow rate of the fluorine-containing etching gas are controlled. Using the nitrogen-containing mask layer 203 as a mask layer, the exposed metal layer 220b is etched back downwards until the STI 101 on the exposed contact region 100B / peripheral region 100C is exposed. The metal layer 220b is partially side-cut, so that the side surface 223 of the stepped metal layer 220 is slightly inclined and intersects the first upper surface 221 / second upper surface 222. The included angle between the side surface 223 and the first upper surface 221 / second upper surface 222 is, for example, in the range of 80-110°. Then, please refer to... Figure 20 A nitrogen-containing mask layer 201 covers the second upper surface 222 of a stepped metal layer 220. A semiconductor layer 230b is formed on the exposed portion of the stepped metal layer 220 by the nitrogen-containing mask layer 201. The semiconductor layer 230b fills word line trenches 200a and is located on the first upper surface and side surfaces of the stepped metal layer 220, flush with the nitrogen-containing mask layer 201. (The following is a further explanation.) Figure 21The semiconductor layer 230b is then etched again using a nitrogen-containing mask layer 201 to thin the semiconductor layer and form the etched semiconductor layer 230. The etched semiconductor layer 230 is located on a partially stepped metal layer 220. Because the metal layer 220 below the nitrogen-containing mask layer 201 undergoes partial side cutout, a portion of the semiconductor layer 230 is still located in the end region, below the nitrogen-containing mask layer 201, covering the side surface 223 of the stepped metal layer 220, and the upper surface of this portion of the semiconductor layer 230 is flush with the second upper surface 222 of the stepped metal layer 220. Please refer to [further details to be added]. Figure 22 A capping layer 240 is formed. The capping layer 240 fills the remaining space of the word line trench 200a, with a portion covering the surface of the semiconductor layer 230 and another portion covering the surface of the metal layer 220. The capping layer 240 is located in the array region 100A and part of the contact region 100B, and is flush with the upper surface of the remaining contact region 100B and the peripheral region 100C.
[0061] This disclosure provides a method for fabricating embedded word lines. By forming a nitrogen-containing mask layer in the end region of the metal layer in the embedded word line, and etching back the metal layer with a fluorine-containing gas to form a metal layer with a stepped shape, followed by the formation of a semiconductor layer and a capping layer, an ideal vertical structure can be formed at the end of the word line. This effectively reduces the load effect during the etching process of the contact hole of the word line contact plug, solves the problems of word line contact plugs and open circuits in word lines, and further improves the gate-induced drain leakage (GIDL) problem of memory cells at the end of the word line in the memory array.
[0062] Please refer to Figure 23 This disclosure also provides an electronic device 1 with storage function. The electronic device includes a processor 2 and a storage device 3 electrically connected to the processor. The storage device 3 includes the aforementioned... Figures 1 to 22 The semiconductor device 4 described herein. Electronic devices can be terminal devices, such as personal computers, mobile phones, tablets, consumer electronics (e.g., smart home appliances, autonomous vehicles, smart wearable products such as smartwatches and smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, and can also be servers, data centers, etc. The storage function in electronic device 1 can be implemented through these storage devices 3.
[0063] In some embodiments, the processor 2 and memory 3 can be two separate chips forming an independent memory. In other embodiments, the memory 3 and processor 2 can also be integrated into the same chip to form an embedded memory. This electronic device 1 is similar to the one described above. Figures 1 to 22 The semiconductor device 4 described is able to solve the same technical problem and achieve the same expected results.
[0064] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for preparing embedded character lines, characterized in that, include: Provide substrate; Word line trenches are formed in the substrate; A grid dielectric layer is formed within the word line groove; A metal layer is filled in the word line groove, and the metal layer is located on the surface of the gate dielectric layer; A nitrogen-containing mask layer is formed within the word line groove, and the nitrogen-containing mask layer covers the end region of the metal layer; Using the nitrogen-containing mask layer as a mask, the metal layer is etched back with fluorine-containing gas to form a metal layer with a stepped shape; A semiconductor layer is filled in the word line trench, the semiconductor layer being located on a portion of the stepped metal layer; Using the nitrogen-containing mask layer as a mask, the semiconductor layer is etched back; A cover layer is formed within the remaining word line grooves.
2. The preparation method according to claim 1, characterized in that, The fluorine-containing gas is carbon fluoride.
3. The preparation method according to claim 1, characterized in that, The thickness of the nitrogen-containing mask layer is 5nm-25nm.
4. The preparation method according to claim 1, characterized in that, The nitrogen-containing mask layer is silicon nitride, the metal layer is metal nitride, and the semiconductor layer is doped polycrystalline silicon.
5. The preparation method according to claim 1, characterized in that, The stepped metal layer includes a first upper surface, a second upper surface, and a side surface connecting the first upper surface and the second upper surface. The first upper surface and the second upper surface are parallel, and the side surface is substantially perpendicular to the first upper surface and the second upper surface.
6. The preparation method according to claim 1, characterized in that, The step of forming a nitrogen-containing mask layer within the word line trench includes: A nitrogen-containing mask layer material is formed to cover the metal layer, and a photoresist layer covering the nitrogen-containing mask layer material is formed in the end region; Using the photoresist layer as a mask, the nitrogen-containing mask layer material is etched with a hydrogen and fluorine-containing gas to form the nitrogen-containing mask layer, which covers the end region of the metal layer.
7. The preparation method according to claim 6, characterized in that, The hydrogen and fluorine-containing gas is composed of carbon, hydrogen, and fluorine.
8. The preparation method according to claim 1, characterized in that, The step of forming a cover layer within the letter groove includes: The nitrogen-containing mask layer is retained, and a capping layer material is deposited on the semiconductor layer and the nitrogen-containing mask layer; The cover layer material is patterned, and the cover layer material other than the word line trench is removed. The remaining cover layer material in the word line trench and the nitrogen-containing mask layer are formed into the cover layer, which conformally covers the surface of the semiconductor layer and the surface of the metal layer with a stepped shape.
9. The preparation method according to any one of claims 1-8, characterized in that, The substrate includes an array region and a peripheral region, and a contact region located between the array region and the peripheral region, with the end region located within the contact region.
10. The preparation method according to claim 1, characterized in that, The method further includes forming a word line contact plug that penetrates the cover layer and directly contacts the metal layer having a stepped shape.