Electrical structure and preparation method thereof
By using an ultra-diluted hydrofluoric acid cleaning agent to form electrical contacts with improved profiles, the electrical contact profile problem was solved, thereby improving the electrical characteristics and yield of the semiconductor structure.
Patent Information
- Application Number
- CN202510233415.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-14
- Filing Date
- 2025-02-28
- Publication Date
- 2026-03-03
AI Technical Summary
In semiconductor structures, the profile of electrical contacts affects contact resistance and the speed of electronic current transmission, leading to a decrease in electrical characteristics, quality, and yield.
By using an ultra-diluted hydrofluoric acid (HF) cleaning agent, an electrical contact with an improved profile is formed, ensuring that the width difference between the first and second portions of the electrical contact is less than 10%, and isolation and conductive features are formed on the substrate to improve the connection quality of the contact.
It improves the quality of electrical contacts, reduces seams or cracks, increases the connection reliability and contact area of electrical contacts with conductive characteristics, and reduces contact resistance.
Smart Images
Figure CN121604402A_ABST
Abstract
Description
Technical Field
[0001] This application claims priority to U.S. Patent Application No. 18 / 804,383 (i.e., priority date "August 14, 2024"), the contents of which are incorporated herein by reference in their entirety.
[0002] This disclosure relates to an electrical structure and a method for its fabrication, and more particularly to an electrical structure including electrical contacts and a method for its fabrication. Background Technology
[0003] Semiconductor structures are used in a wide range of electronic applications, and their dimensions are constantly shrinking to meet current application requirements. However, this shrinkage process introduces various problems that affect the final electrical characteristics, quality, cost, and yield. Typical memory elements (such as dynamic random access memory (DRAM) elements) include electrical contacts for the electrical interconnection of different components. The profile of these electrical contacts is a critical issue because it affects contact resistance and the speed of electron current transport.
[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention
[0005] One aspect of this disclosure provides an electrical structure comprising: a substrate; a first insulating layer disposed on a first surface of the substrate; a second insulating layer disposed on the first insulating layer; an electrical contact extending through the first insulating layer and the second insulating layer to be electrically connected to the first surface of the substrate, wherein the electrical contact includes a first portion and a second portion, the first portion being disposed in the first insulating layer and the second portion being disposed in the second insulating layer, the first portion having a first width and the second portion having a second width, and a difference between the first width and the second width being less than 10% of the first width; at least one isolation feature extending into the substrate and disposed below the first surface of the substrate; and at least one conductive feature extending through the second insulating layer and the first insulating layer and extending into the substrate.
[0006] Another aspect of this disclosure provides an electrical structure comprising: a substrate; a first insulating layer disposed on a first surface of the substrate and defining a first through-hole extending through the first insulating layer, wherein the first through-hole has a first width; a second insulating layer disposed on the first insulating layer and defining a second through-hole extending through the second insulating layer, wherein the second through-hole has a second width, and a difference between the first width and the second width is less than one-tenth of the first width; an electrical contact disposed in the first through-hole and the second through-hole and electrically connected to the first surface of the substrate; at least one isolation feature extending into the substrate and disposed below the first surface of the substrate; and at least one conductive feature extending through the second insulating layer and the first insulating layer and extending into the substrate.
[0007] Another aspect of this disclosure provides a method for fabricating an electrical structure. The method includes providing a laminated structure comprising a substrate, a first insulating layer and a second insulating layer stacked on top of each other, wherein at least one insulating feature is formed in the substrate and below a first surface of the substrate; forming a first pore structure extending through the first insulating layer and the second insulating layer, wherein the first pore structure exposes a portion of the substrate; and forming at least one third pore structure extending through the second insulating layer and the first insulating layer and extending into the substrate; and cleaning an exposed portion of the substrate with a cleaning agent to enlarge the first pore structure into a second pore structure, wherein the cleaning agent comprises water and hydrofluoric acid (HF), and the weight ratio of water to HF is between 500:1 and 2500:1. The method further includes forming an electrical contact in the second pore structure.
[0008] By using ultra-diluted hydrofluoric acid (HF), electrical contacts with improved profiles can be formed.
[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description
[0010] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the detailed description and considering the diagrams, where similar reference numbers refer to similar elements in the whole diagram.
[0011] Figure 1This is a cross-sectional view illustrating the electrical structure of some embodiments of the present disclosure.
[0012] Figure 2 This is a stage of a method for preparing an electrical structure that exemplifies some embodiments of the present disclosure.
[0013] Figure 3 This is a stage of a method for preparing an electrical structure that exemplifies some embodiments of the present disclosure.
[0014] Figure 4 This is a stage of a method for preparing an electrical structure that exemplifies some embodiments of the present disclosure.
[0015] Figure 5 This is a stage of a method for preparing an electrical structure that exemplifies some embodiments of the present disclosure.
[0016] Figure 6 This is a stage of a method for preparing an electrical structure that exemplifies some embodiments of the present disclosure.
[0017] Figure 7 This is a stage of a method for preparing an electrical structure that exemplifies some embodiments of the present disclosure.
[0018] Figure 8 This is a stage of a method for preparing an electrical structure that exemplifies some embodiments of the present disclosure.
[0019] Figure 9 This is a stage of a method for preparing an electrical structure that exemplifies some embodiments of the present disclosure.
[0020] Figure 10 This is a flowchart illustrating a method for preparing an electrical structure according to some embodiments of this disclosure.
[0021] The reference numerals in the attached figures are explained as follows:
[0022] 1: Electrical Structure
[0023] 2: Base
[0024] 3: First metal-oxide-semiconductor transistor
[0025] 3a: Second metal-oxide-semiconductor transistor
[0026] 4: First insulating layer
[0027] 5: Second insulation layer
[0028] 6: Electrical contacts
[0029] 7: Base
[0030] 13: Hole structure / Second hole structure
[0031] 13': First hole structure
[0032] 21: First Surface
[0033] 22: Drain electrode
[0034] 23: Source electrode
[0035] 24: Source electrode
[0036] 25: concave part
[0037] 26: Low-resistivity layer
[0038] 28: Exposed parts
[0039] 31: Gate oxide layer
[0040] 31a: Gate oxide layer
[0041] 32: First gate conductor layer
[0042] 32a: First gate conductor layer
[0043] 33: Second gate conductor layer
[0044] 33a: Second gate conductor layer
[0045] 34: Upper level
[0046] 34a: Upper layer
[0047] 35: Gap element
[0048] 35a: Spacer
[0049] 36: First floor
[0050] 36a: First layer
[0051] 37: Second layer
[0052] 37a: Second layer
[0053] 38: Third floor
[0054] 38a: Third layer
[0055] 41: First Surface
[0056] 43: First through hole
[0057] 43': Fourth through hole
[0058] 50: Electrical conductivity characteristics
[0059] 50a: Conductivity characteristics
[0060] 51: First Surface
[0061] 53: Second through hole
[0062] 53': Fifth through hole
[0063] 60: Central material
[0064] 61: Part One
[0065] 62: Part Two
[0066] 63: Part Three
[0067] 65: Peripheral layer
[0068] 72: Layered structure
[0069] 80: Cleaning agent
[0070] 82: Cobalt
[0071] 108: Second contact hole
[0072] 130: Isolation Features
[0073] 130a: Isolation Feature
[0074] 380: Connector Layer
[0075] 400: Third hole structure
[0076] 400a: Third hole structure
[0077] 405: First contact hole
[0078] 510: Lower part
[0079] 510a: lower part
[0080] 512: Peripheral surface
[0081] 520: Upper part
[0082] 520a: upper part
[0083] 522: Peripheral Surface
[0084] 653: Central Hole
[0085] 900: Preparation method
[0086] CD1: First Key Dimension
[0087] CD2: Second Key Size
[0088] S901: Steps
[0089] S902: Steps
[0090] S903: Steps
[0091] S904: Steps
[0092] W1: First width
[0093] W2: Second width
[0094] W3: Third Width
[0095] W4: Fourth Width
[0096] W5: Fifth Width
[0097] W6: Sixth Width
[0098] W7: Seventh Width Detailed Implementation
[0099] Embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as commonly done by one of ordinary skill in the art related to the content of this disclosure. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same reference numerals.
[0100] It should be understood that although the terms first, second, third, etc., can be used to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part without departing from the teachings of the present invention.
[0101] The terminology used herein is for describing specific embodiments only and is not intended to limit the scope of the invention. As used herein, the singular forms “a,” “an,” and “the” also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms “comprising” and “including,” when used in this specification, indicate the presence of the stated feature, integer, step, operation, element, or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
[0102] Figure 1This is a cross-sectional view illustrating an electrical structure 1 according to some embodiments of the present disclosure. In some embodiments, the electrical structure 1 may be a semiconductor structure or semiconductor element including circuitry, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell). In some embodiments, the electrical structure 1 may be an interconnect structure.
[0103] Furthermore, electrical structure 1 may be or include part of an integrated circuit (IC) wafer, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bijunction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.
[0104] The electrical structure 1 may include a substrate 2 (e.g., a semiconductor substrate), a first metal-oxide-semiconductor (MOS) transistor 3, a second MOS transistor 3a, a first insulating layer 4, a second insulating layer 5, and an electrical contact 6.
[0105] In some embodiments, substrate 2 may have a first surface 21 (e.g., a top surface). Substrate 2 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials. In some other embodiments, substrate 2 may include a semiconductor-insulator substrate, such as a silicon-insulator (SOI) substrate, a silicon-germanium-insulator (SGOI) substrate, or a germanium-insulator (GOI) substrate.
[0106] Depending on the fabrication stage of the IC, the substrate 2 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form features of the IC (e.g., doped regions, isolation features, gate features, source or drain electrode features, interconnect features, other features, or combinations thereof).
[0107] like Figure 1As shown, the substrate 2 may include a drain electrode 22, a source electrode 23, and a source electrode 24. The substrate 2 may define a recess 25 recessed from a first surface 21 (e.g., the top surface) of the substrate 2. The recess 25 may be disposed in the drain electrode 22. The recess 25 has a third width W3. The third width W3 may be the maximum width of the recess 25. Furthermore, the substrate 2 may include a low-resistivity layer 26 disposed on the bottom wall of the recess 25. The low-resistivity layer 26 may include cobalt (Co), for example, cobalt disilicide (CoSi2).
[0108] The first MOS transistor 3 and the second MOS transistor 3a can each be part of a word line. The first MOS transistor 3 and the second MOS transistor 3a can be disposed on the first surface 21 of the substrate 2. The first MOS transistor 3 can correspond to a drain electrode 22 and a source electrode 23. The first MOS transistor 3 may include a gate oxide layer 31, a first gate conductor layer 32, a second gate conductor layer 33, an upper layer 34, and a spacer 35. The gate oxide layer 31 can be disposed on the first surface 21 of the substrate 2 and may include an oxide material for electrical insulation. The first gate conductor layer 32 can be disposed on the gate oxide layer 31 and may include a polysilicon material. The second gate conductor layer 33 can be disposed on the first gate conductor layer 32 and may include tungsten silicide (WSi). x Material. The first gate conductor layer 32 and the second gate conductor layer 33 may together form a gate electrode. The upper layer 34 may be disposed on the second gate conductor layer 33 and may include a nitride material. In some embodiments, the gate electrode may include the upper layer 34.
[0109] The spacer 35 may surround the gate electrode (including, for example, the first gate conductor layer 32 and the second gate conductor layer 33) or may be disposed around the gate electrode. In some embodiments, the spacer 35 may include a first layer 36, a second layer 37, and a third layer 38. The first layer 36 may cover the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, and the upper layer 34, and may include a nitride material. The second layer 37 may be disposed on the side of the first layer 36 and a portion of the first surface 21 of the substrate 2. The second layer 37 may taper upwards and may include an oxide material. The third layer 38 may cover the first layer 36 and the second layer 37. For example, the third layer 38 may cover the top surface of the first layer 36 and the top surface of the second layer 37. Thus, the second layer 37 may be sandwiched between the first layer 36 and the third layer 38. The bottom end of the third layer 38 may be disposed on the first surface 21 of the substrate 2.
[0110] Similarly, the second MOS transistor 3a can correspond to the drain electrode 22 and the source electrode 24. The second MOS transistor 3a may include a gate oxide layer 31a, a first gate conductor layer 32a, a second gate conductor layer 33a, an upper layer 34a, and a spacer 35a. The gate oxide layer 31a, the first gate conductor layer 32a, the second gate conductor layer 33a, the upper layer 34a, and the spacer 35a of the second MOS transistor 3a may be the same as the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, the upper layer 34, and the spacer 35a of the first MOS transistor 3, respectively.
[0111] A gate oxide layer 31a may be disposed on a first surface 21 of the substrate 2 and may include an oxide material for electrical insulation. A first gate conductor layer 32a may be disposed on the gate oxide layer 31a and may include a polysilicon material. A second gate conductor layer 33a may be disposed on the first gate conductor layer 32a and may include a tungsten silicide (WSix) material. The first gate conductor layer 32a and the second gate conductor layer 33a may together form a gate electrode. An upper layer 34a may be disposed on the second gate conductor layer 33a and may include a nitride material. In some embodiments, the gate electrode may include the upper layer 34a.
[0112] A spacer 35a may surround or be disposed around the gate electrode (including, for example, a first gate conductor layer 32a and a second gate conductor layer 33a). In some embodiments, the spacer 35a may include a first layer 36a, a second layer 37a, and a third layer 38a. The first layer 36a may cover the gate oxide layer 31a, the first gate conductor layer 32a, the second gate conductor layer 33a, and the upper layer 34a, and may include a nitride material. The second layer 37a may be disposed on the side of the first layer 36a and a portion of the first surface 21 of the substrate 2. The second layer 37a may be tapered upwards and may include an oxide material. The third layer 38a may cover the first layer 36a and the second layer 37a. For example, the third layer 38a may cover the top surface of the first layer 36a and the top surface of the second layer 37a. Therefore, the second layer 37a may be sandwiched between the first layer 36a and the third layer 38a. The bottom end of the third layer 38a may be disposed on the first surface 21 of the substrate 2.
[0113] A first insulating layer 4 may be disposed on a first surface 21 of a substrate 2. In some embodiments, the first insulating layer 4 may be disposed on a first surface 21 of a substrate 2 and may cover a first MOS transistor 3 and a second MOS transistor 3a. The first insulating layer 4 may include an oxide material, such as silicon dioxide (SiO2). The first surface 41 (e.g., a top surface) of the first insulating layer 4 may be coplanar with the top surface of the third layer 38 of the first MOS transistor 3 and the top surface of the third layer 38a of the second MOS transistor 3a. Therefore, the top surfaces of the third layer 38 of the first MOS transistor 3 and the third layer 38a of the second MOS transistor 3a may be exposed by the first surface 41 of the first insulating layer 4.
[0114] The first insulating layer 4 defines a first through-hole 43 extending through the first insulating layer 4. The first through-hole 43 has a first width W1. The first width W1 can be the maximum width of the first through-hole 43. The recess 25 of the substrate 2 can communicate with the first through-hole 43 of the first insulating layer 4. That is, the first through-hole 43 can also extend through the connecting layer 380 (connecting the third layer 38 and the third layer 38a), and the connecting layer 380 contacts the first surface 21 of the substrate 2. The connecting layer 380, the third layer 38, and the third layer 38a can be the same layer. The third width W3 of the recess 25 can be smaller than the first width W1 of the first through-hole 43. The width of the through-hole of the connecting layer 380 can gradually decrease from the first width W1 to the third width W3.
[0115] A second insulating layer 5 may be disposed on the first insulating layer 4. The second insulating layer 5 may cover and contact the first surface 41 of the first insulating layer 4. The material of the second insulating layer 5 may be different from the material of the first insulating layer 4. The second insulating layer 5 may include a nitride material such as silicon nitride (Si3N4 or SiN). The second insulating layer 5 may define a second through-hole 53 extending through the second insulating layer 5. The second through-hole 53 of the second insulating layer 5 may communicate with the first through-hole 43 of the first insulating layer 4 to form a hole structure 13 (or contact hole). The central axis of the first through-hole 43 may be substantially aligned with the central axis of the second through-hole 53. Therefore, the hole structure 13 may extend through the first insulating layer 4 and the second insulating layer 5, and may include the first through-hole 43 and the second through-hole 53. In some embodiments, the hole structure 13 may also extend into the substrate 2 and may include a recess 25.
[0116] The second through hole 53 has a second width W2. The second width W2 can be the maximum width of the second through hole 53. The second width W2 of the second through hole 53 can be smaller than the first width W1 of the first through hole 43. The third width W3 of the recess 25 can be smaller than the second width W2 of the second through hole 53.
[0117] In some embodiments, the difference between the first width W1 and the second width W2 is less than one-tenth of the first width W1. That is, the ratio (W1-W2) / W1 can be less than 0.1, for example, 0.09, 0.08, 0.07, or 0.06. Therefore, the offset between the sidewall of the first through hole 43 and the sidewall of the second through hole 53 can be very small. The sidewall of the first through hole 43 and the sidewall of the second through hole 53 can be approximately aligned.
[0118] Electrical contact 6 may be disposed in the hole structure 13 and may extend through the first insulating layer 4 and the second insulating layer 5 to electrically connect to the first surface 21 of the substrate 2. Furthermore, electrical contact 6 may also extend into the substrate 2. Electrical contact 6 may include a peripheral layer 65 and a central material 60. Peripheral layer 65 may be disposed on the sidewall of hole structure 13 and may define a central hole. Central material 60 may fill the central hole defined by peripheral layer 65. Peripheral layer 65 may include titanium nitride (TiN), while central material 60 may include tungsten (W).
[0119] Electrical contact 6 may include a first portion 61, a second portion 62, and a third portion 63. The first portion 61 may be disposed in a first through-hole 43 of the first insulating layer 4 and may have a first width W1. It should be understood that the first width W1 of the first portion 61 may be the maximum width of the first portion 61 and may be substantially equal to the first width W1 of the first through-hole 43 of the first insulating layer 4. The first portion 61 may include a portion of the peripheral layer 65 and a portion of the central material 60.
[0120] The second portion 62 may be disposed within the second through-hole 53 of the second insulating layer 5 and may have a second width W2. It should be understood that the second width W2 of the second portion 62 may be the maximum width of the second portion 62 and may be substantially equal to the second width W2 of the second through-hole 53 of the second insulating layer 5. The second portion 62 may include a portion of the peripheral layer 65 and a portion of the central material 60. The ratio of the difference between the first width W1 and the second width W2 to the first width W1 may be less than 10%. That is, the ratio of (W1-W2) / W1 may be less than 10%, for example, 9%, 8%, 7%, or 6%. Therefore, the offset between the sidewalls of the first portion 61 and the sidewalls of the second portion 62 can be very small. The sidewalls of the first portion 61 and the sidewalls of the second portion 62 may be approximately aligned with each other.
[0121] The third portion 63 may be disposed within the recess 25 of the substrate 2 and may have a third width W3. It should be understood that the third width W3 of the third portion 63 may be the maximum width of the third portion 63 and may be substantially equal to the third width W3 of the recess 25 of the substrate 2. The third portion 63 may include a portion of the peripheral layer 65 and a portion of the central material 60. The third width W3 may be less than the first width W1 and less than the second width W2. The low-resistance layer 26 may be substantially conformal to the third portion 63 of the electrical contact 6.
[0122] The first portion 61, the second portion 62, and the third portion 63 of the electrical contact 6 can be formed integrally and simultaneously, thus allowing the electrical contact 6 to be a monolithic structure. The electrical contact 6 can be disposed between the first MOS transistor 3 and the second MOS transistor 3a. The electrical contact 6 can be electrically connected to the electrodes of the first MOS transistor 3 and / or the electrodes of the second MOS transistor 3a. Figure 1 As shown, electrical contact 6 can be electrically connected to the common electrode (e.g., drain electrode 22) of the first MOS transistor 3 and the second MOS transistor 3a. However, in other embodiments, electrical contact 6 can be electrically connected to the first electrode of the first MOS transistor 3 and / or the second electrode of the second MOS transistor 3a. The first electrode of the first MOS transistor 3 may be different from the second electrode of the second MOS transistor 3a.
[0123] One or more isolation features may be configured in the substrate 2. In some embodiments, the one or more isolation features comprise oxides or nitrides, and may be deposited, for example, using a (plasma) chemical vapor deposition (CVD) process. Figure 1 In the illustrated embodiment, there are two isolation features 130 and 130a. Isolation features 130 and 130a are disposed on both sides of the electrical contact 6. In some embodiments, isolation feature 130 extends into the substrate 2 and is disposed below the first surface 21 of the substrate 2. Furthermore, isolation feature 130 is adjacent to the source electrode 23 and the first MOS transistor 3, and is spaced apart from the first MOS transistor 3. Similarly, isolation feature 130a extends into the substrate 2 and is disposed below the first surface 21 of the substrate 2. Furthermore, isolation feature 130a is adjacent to the source electrode 24 and the second MOS transistor 3a, and is spaced apart from the second MOS transistor 3a.
[0124] Conductive features are disposed on both sides of electrical contact 6. In some embodiments, the conductive features comprise polycrystalline silicon and are deposited, for example, using a CVD process. Figure 1In the illustrated embodiment, there are two conductive features 50 and 50a. In some embodiments, conductive feature 50 extends through the second insulating layer 5, the first insulating layer 4, and the third layer 38 of the spacer 35, and extends into the substrate 2. Furthermore, conductive feature 50 is electrically connected to the source electrode 23. Similarly, conductive feature 50a extends through the second insulating layer 5, the first insulating layer 4, and the third layer 38a of the spacer 35, and extends into the substrate 2. Furthermore, conductive feature 50a is electrically connected to the source electrode 24. In some embodiments, conductive feature 50 is disposed between electrical contact 6 and isolation feature 130, and conductive feature 50a is disposed between electrical contact 6 and isolation feature 130a.
[0125] More specifically, the conductive feature 50 includes a lower portion 510 disposed below the first surface 21 of the substrate 2 and inserted into the substrate 2, and an upper portion 520 disposed above the first surface 21 of the substrate 2 and inserted into the third layer 38 of the second insulating layer 5, the first insulating layer 4, and the spacer 35. Specifically, the lower portion 510 of the conductive feature 50 is inserted into the source electrode 23. Similarly, the conductive feature 50a includes a lower portion 510a disposed below the first surface 21 of the substrate 2 and inserted into the substrate 2, and an upper portion 520a disposed above the first surface 21 of the substrate 2 and inserted into the third layer 38a of the second insulating layer 5, the first insulating layer 4, and the spacer 35a. Specifically, the lower portion 510a of the conductive feature 50a is inserted into the source electrode 24.
[0126] The lower portion 510 of the conductive feature 50 below the first surface 21 of the substrate 2 may have a first critical dimension CD1, while the upper portion 520 of the conductive feature 50 above the first surface 21 of the substrate 2 may have a second critical dimension CD2 greater than the first critical dimension CD1. In some embodiments, the first critical dimension CD1 gradually decreases with increasing distance from the first surface 21 of the substrate 2, while the second critical dimension CD2 remains constant. In particular, the peripheral surface 512 of the lower portion 510 of the conductive feature 50 is discontinuous with the peripheral surface 522 of the upper portion 520 of the conductive feature 50. It should be understood that the lower portion 510 and the upper portion 520 (including polysilicon) of the conductive feature 50 are integrally formed. The structure of the conductive feature 50a is the same as or similar to the structure of the conductive feature 50, and repeated descriptions are omitted.
[0127] The lower portion 510 of conductive feature 50 and the lower portion 510a of conductive feature 50a extend into the substrate 2, which increases the contact area between conductive feature 50 and substrate 2, and between conductive feature 50a and substrate 2. Therefore, the contact resistance through the relevant conductive features 50 and 50a can be effectively reduced.
[0128] In some instances, a low-resistance layer 26 may be disposed between the electrical contact 6 and the drain electrode 22 of the substrate 2 to reduce the resistance of the ohmic contact between the electrical contact 6 and the substrate 2. During fabrication, the portion of the substrate 2 exposed in the via structure needs to be cleaned with a cleaning agent before the low-resistance layer 26 is formed. In a comparative example, the cleaning agent may cause a significant difference between the first width of the first via in the first insulating layer and the second width of the second via in the second insulating layer. Therefore, the via structure may have an "arc-shaped profile," resulting in weak electrical contacts within the via structure. For example, this electrical contact is prone to forming seams or cracks. Figure 1 As shown, the hole structure 13 can be formed according to one embodiment described below, and the difference between the first width W1 of the first through-hole 43 and the second width W2 of the second through-hole 53 can be reduced. Therefore, the sidewalls of the hole structure 13 can be substantially linear to facilitate the deposition process of the peripheral layer 65 and the filling process of the central material 60. The electrical contact 6 can have an improved profile. The quality of the electrical contact 6 is improved. That is, seams or cracks can be reduced. The electrical contact 6 can be seamless or crack-free.
[0129] Figures 2 to 9 The following describes a method for preparing an electrical structure 1 according to some embodiments of this disclosure. Figure 10 A flowchart illustrating a method 900 for fabricating an electrical structure 1 according to some embodiments of this disclosure is provided. (Refer to...) Figures 2 to 5 A laminated structure 72 is provided. The method for preparing the laminated structure 72 is as follows.
[0130] In some embodiments, the fabrication method 900 may include step S901, wherein a stacked structure is provided, the stacked structure including a substrate, a first insulating layer, and a second insulating layer stacked on top of each other. For example, as Figure 5 As shown, a laminated structure 72 may be provided, which may include a substrate 2, a first insulating layer 4, and a second insulating layer 5 stacked on top of each other. (Refer to...) Figure 2 A base 7 is provided. The base 7 may include a substrate 2, a first MOS transistor 3, a second MOS transistor 3a, an isolation feature 130, and an isolation feature 130a. Figure 2 The substrate 2, the first MOS transistor 3, the second MOS transistor 3a, the isolation feature 130, and the isolation feature 130a can be respectively connected to... Figure 1 The substrate 2, the first MOS transistor 3, the second MOS transistor 3a, the isolation feature 130 and the isolation feature 130a are the same or similar.
[0131] In some embodiments, the substrate 2 may have a first surface 21 (e.g., a top surface). The substrate 2 may include a drain electrode 22, a source electrode 23, and a source electrode 24. The substrate 2 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.
[0132] A first MOS transistor 3 and a second MOS transistor 3a may be formed or disposed on a first surface 21 of a substrate 2. The first MOS transistor 3 may correspond to a drain electrode 22 and a source electrode 23. The first MOS transistor 3 may include a gate oxide layer 31, a first gate conductor layer 32, a second gate conductor layer 33, an upper layer 34, and a spacer 35. The gate oxide layer 31 may be formed or disposed on the first surface 21 of the substrate 2 and may include an oxide material for electrical insulation. The first gate conductor layer 32 may be formed or disposed on the gate oxide layer 31 and may include a polysilicon material. The second gate conductor layer 33 may be formed or disposed on the first gate conductor layer 32 and may include a tungsten silicide (WSix) material. The upper layer 34 may be disposed on the second gate conductor layer 33 and may include a nitride material.
[0133] A spacer 35 may surround or be disposed around the gate electrode (including, for example, a first gate conductor layer 32 and a second gate conductor layer 33). In some embodiments, the spacer 35 may include a first layer 36, a second layer 37, and a third layer 38. The first layer 36 may cover the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, and the upper layer 34, and may include a nitride material. The second layer 37 may be disposed on the side of the first layer 36 and a portion of the first surface 21 of the substrate 2. The second layer 37 may taper upwards and may include an oxide material. The third layer 38 may cover the first layer 36 and the second layer 37. For example, the third layer 38 may cover the outer surface of the second layer 37 and the top surface of the first layer 36. Thus, the second layer 37 may be sandwiched between the first layer 36 and the third layer 38. The bottom end of the third layer 38 may be disposed on the first surface 21 of the substrate 2.
[0134] Similarly, the second MOS transistor 3a can correspond to the drain electrode 22 and the source electrode 24. The structure of the second MOS transistor 3a can be the same as or similar to the structure of the first MOS transistor 3, and can include a gate oxide layer 31a, a first gate conductor layer 32a, a second gate conductor layer 33a, an upper layer 34a, and a spacer 35a. The gate oxide layer 31a, the first gate conductor layer 32a, the second gate conductor layer 33a, the upper layer 34a, and the spacer 35a of the second MOS transistor 3a can be the same as or similar to the gate oxide layer 31, the first gate conductor layer 32, the second gate conductor layer 33, the upper layer 34, and the spacer 35a of the first MOS transistor 3.
[0135] A spacer 35a may surround or be disposed around the gate electrode (including, for example, a first gate conductor layer 32a and a second gate conductor layer 33a). In some embodiments, the spacer 35a may include a first layer 36a, a second layer 37a, and a third layer 38a. The first layer 36a may cover the gate oxide layer 31a, the first gate conductor layer 32a, the second gate conductor layer 33a, and the upper layer 34a, and may include a nitride material. The second layer 37a may be disposed on the side of the first layer 36a and a portion of the first surface 21 of the substrate 2. The second layer 37a may be tapered upwards and may include an oxide material. The third layer 38a may cover the first layer 36a and the second layer 37a. For example, the third layer 38a may cover the outer surface of the second layer 37a and the top surface of the first layer 36a. Therefore, the second layer 37a may be sandwiched between the first layer 36a and the third layer 38a. The bottom end of the third layer 38a may be disposed on the first surface 21 of the substrate 2.
[0136] The connecting layer 380 can connect the third layer 38 and the third layer 38a, and can contact the first surface 21 of the substrate 2. The connecting layer 380, the third layer 38 and the third layer 38a can be the same layer and can be formed simultaneously.
[0137] Reference Figure 2 An isolation feature 130 is formed to extend into the substrate 2 and below the third layer 38 of the spacer 35. Furthermore, the isolation feature 130 is formed adjacent to the source electrode 23 and spaced apart from the first MOS transistor 3. Similarly, an isolation feature 130a is formed to extend into the substrate 2 and below the third layer 38a of the spacer 35a. Furthermore, the isolation feature 130a is formed adjacent to the source electrode 24 and spaced apart from the second MOS transistor 3a.
[0138] Reference Figure 3The first insulating layer 4 can be formed or disposed on the first surface 21 of the substrate 2. In some embodiments, the first insulating layer 4 can be disposed on the first surface 21 of the substrate 2 and can cover the first MOS transistor 3 and the second MOS transistor 3a. The first surface 41 (e.g., the top surface) of the first insulating layer 4 can be higher than the top surface of the third layer 38 of the first MOS transistor 3 and the top surface of the third layer 38a of the second MOS transistor 3a. Therefore, the top surfaces of the third layer 38 of the first MOS transistor 3 and the third layer 38a of the second MOS transistor 3a can be covered by the first insulating layer 4.
[0139] Reference Figure 4 The first insulating layer 4 can be thinned from the first surface 41, for example, by grinding. Therefore, the upper portion of the first insulating layer 4 can be removed, and the first surface 41 of the first insulating layer 4 can be coplanar with the top surface of the third layer 38 of the first MOS transistor 3 and the top surface of the third layer 38a of the second MOS transistor 3a. Therefore, the top surfaces of the third layer 38 of the first MOS transistor 3 and the third layer 38a of the second MOS transistor 3a can be exposed by the first surface 41 of the first insulating layer 4.
[0140] Reference Figure 5 A second insulating layer 5 may be formed or disposed on the first insulating layer 4. The second insulating layer 5 may cover and contact the first surface 41 of the first insulating layer 4. Accordingly, a stacked structure 72 may be formed. The stacked structure 72 may include a substrate 2, a first insulating layer 4, and a second insulating layer 5 stacked on top of each other. In addition, the stacked structure 72 may also include a first MOS transistor 3 and a second MOS transistor 3a disposed on the substrate 2 and covered by the first insulating layer 4 and the second insulating layer 5.
[0141] In some embodiments, the fabrication method 900 may include step S902, in which a first pore structure is formed to extend through the first insulating layer and the second insulating layer to expose a portion of the substrate, and in step S902, at least one third pore structure is formed to extend through the second insulating layer and the first insulating layer and into the substrate. For example, as Figure 6 As shown, a first hole structure 13' extending through the first insulating layer 4 and the second insulating layer 5 can be formed, thus exposing the exposed portion 28 of the substrate 2, and each of two third hole structures 400 and 400a extending through the second insulating layer 5 and the first insulating layer 4 and entering the substrate 2 can be formed. (Refer to...) Figure 6The first via structure 13' can be formed, for example, by dry etching, from the first surface 51 of the second insulating layer 5 to expose the exposed portion 28 of the substrate 2. The first via structure 13' can extend through the first insulating layer 4 to form a fourth via 43' having a fourth width W4. The first via structure 13' can extend through the second insulating layer 5 to form a fifth via 53' having a fifth width W5. The fourth width W4 can be substantially equal to the fifth width W5. The first via structure 13' can be disposed between the first MOS transistor 3 and the second MOS transistor 3a. In some embodiments, the first via structure 13' can also extend through the interconnect layer 380 and into the substrate 2 to form a recess 25 recessed from the first surface 21 of the substrate 2. The recess 25 has a third width W3. The third width W3 can be the maximum width of the recess 25 and can be less than the fourth width W4.
[0142] The third hole structure 400 can be formed, for example, by dry etching, extending through the second insulating layer 5, the first insulating layer 4, and the third layer 38 of the spacer 35, and entering the substrate 2 (i.e., the source electrode 23). Similarly, the third hole structure 400a can be formed, for example, by dry etching, extending through the second insulating layer 5, the first insulating layer 4, and the third layer 38a of the spacer 35a, and entering the substrate 2 (i.e., the source electrode 24). In some embodiments, the third hole structure 400 is disposed between the first hole structure 13' and the isolation feature 130, and the third hole structure 400a is disposed between the first hole structure 13' and the isolation feature 130a. The third hole structures 400 and 400a each have a first contact hole 405 (with a substantially uniform sixth width W6) and a second contact hole 108 (with a non-uniform seventh width W7). In some instances, the seventh width W7 gradually decreases with increasing distance from the first surface 21 of the substrate 2.
[0143] In some embodiments, the preparation method 900 may include step S903, in which a cleaning agent is used to clean the exposed portion of the substrate to expand the first pore structure into a second pore structure, wherein the cleaning agent includes water and hydrofluoric acid (HF), and the weight ratio of water to HF in the cleaning agent is between 500:1 and 2500:1. For example, as Figure 7 As shown, the exposed portion 28 of the substrate 2 is cleaned using a cleaning agent 80 to enlarge the first pore structure 13' into a second pore structure 13. The cleaning agent 80 comprises water and hydrofluoric acid (HF), and the weight ratio of water to HF in the cleaning agent 80 is between 500:1 and 2500:1. (Refer to...) Figure 7The exposed portion 28 of the substrate 2 can be cleaned using a cleaning agent 80 applied to the first hole structure 13'. The cleaning agent 80 can etch the first insulating layer 4 and the second insulating layer 5 to enlarge the first hole structure 13' into a second hole structure 13. Therefore, the second hole structure 13 can be formed, for example, by wet etching. The cleaning agent 80 may include water and hydrofluoric acid (HF), and the weight ratio of water to HF may be between 500:1 and 2500:1, between 1800:1 and 2200:1, between 1000:1 and 2000:1, or between 1500:1 and 2100:1. Such a cleaning agent 80 may also be referred to as "ultra-diluted hydrofluoric acid (HF)".
[0144] Figure 7 The second hole structure 13 can be similar to Figure 1 The second hole structure 13 can extend through the first insulating layer 4 to form a first through-hole 43 (or a first enlarged through-hole) having a first width W1. The second hole structure 13 can extend through the second insulating layer 5 to form a second through-hole 53 (or a second enlarged through-hole) having a second width W2. The first width W1 can be greater than the second width W2 because the etching rate of the cleaning agent 80 on the first insulating layer 4 is greater than the etching rate on the second insulating layer 5.
[0145] In some embodiments, the difference between the first width W1 and the second width W2 is less than one-tenth of the first width W1. That is, the ratio (W1-W2) / W1 can be less than 0.1, for example, 0.09, 0.08, 0.07, or 0.06. Therefore, the offset between the sidewall of the first through hole 43 and the sidewall of the second through hole 53 can be very small. The sidewall of the first through hole 43 and the sidewall of the second through hole 53 can be approximately aligned.
[0146] Reference Figure 8 A low-resistivity layer 26 can be formed on the cleaned exposed portion 28 of the substrate 2 by, for example, sputtering and annealing. In some embodiments, the low-resistivity layer 26 is formed by sputtering cobalt (Co) 82 followed by annealing, and therefore the low-resistivity layer 26 may include cobalt disilicide (CoSi2). In this disclosure, the ultra-diluted hydrofluoric acid (HF) as described above does not affect the formation of the low-resistivity layer 26.
[0147] Secondly, residual cobalt (Co) can be removed, for example, by wet cleaning. Subsequently, as described below, electrical contacts 6 (such as...) can be formed or configured in the second hole structure 13. Figure 1 (As shown).
[0148] Reference Figure 9 A peripheral layer 65 can be formed or configured on the sidewalls of the second pore structure 13, for example, by deposition. The peripheral layer 65 may define the central pore 653. The peripheral layer 65 may include titanium nitride (TiN). Figure 7As shown, the difference between the first width W1 of the first through-hole 43 and the second width W2 of the second through-hole 53 can be reduced. Therefore, the sidewalls of the second hole structure 13 can be substantially linear to facilitate the deposition process of the peripheral layer 65.
[0149] In some embodiments, the fabrication method 900 may include step S904, in which an electrical contact is formed in the second hole structure 13, and in step S904, a conductive feature is formed in each of the third hole structures. For example, Figure 1 As shown, electrical contact 6 is formed in the second hole structure 13, and conductive features 50 and 50a are formed in the third hole structures 400 and 400a, respectively. (Refer to...) Figure 1 and Figure 9 The central material 60 may fill the central hole 653 defined by the peripheral layer 65 to form the electrical contact 6. The central material 60 may include tungsten (W). For example, conductive features 50 and 50a (including polycrystalline silicon) are formed using a CVD process in the respective first contact hole 405 and second contact hole 108 of the two third hole structures 400 and 400a. A portion of each conductive feature 50 and 50a in the substrate 2 may have a funnel shape. In some embodiments, conductive feature 50 is formed between the electrical contact 6 and the isolation feature 130, while conductive feature 50a is formed between the electrical contact 6 and the isolation feature 130a. Thus, an electrical structure 1 (or a semiconductor structure) is obtained.
[0150] like Figure 7 As shown, the difference between the first width W1 of the first via 43 and the second width W2 of the second via 53 can be reduced. Therefore, the sidewalls of the second hole structure 13 can be substantially linear to facilitate the filling process of the central material 60. This improves the quality of the electrical contact 6, i.e., reduces seams or cracks in the electrical contact 6. The electrical contact 6 can be seam-free or crack-free. Furthermore, as shown in the wafer electrical testing, the resistance between the electrical contact 6 and the substrate 2 remains very low. That is, the use of the aforementioned ultra-diluted hydrofluoric acid (HF) does not significantly affect the resistance between the electrical contact 6 and the substrate 2.
[0151] One aspect of this disclosure provides an electrical structure comprising: a substrate; a first insulating layer disposed on a first surface of the substrate; a second insulating layer disposed on the first insulating layer; an electrical contact extending through the first insulating layer and the second insulating layer to be electrically connected to the first surface of the substrate, wherein the electrical contact includes a first portion and a second portion, the first portion being disposed in the first insulating layer and the second portion being disposed in the second insulating layer, the first portion having a first width and the second portion having a second width, and a difference between the first width and the second width being less than 10% of the first width; at least one isolation feature extending into the substrate and below the first surface of the substrate; and at least one conductive feature extending through the second insulating layer and the first insulating layer and extending into the substrate.
[0152] Another aspect of this disclosure provides an electrical structure comprising: a substrate; a first insulating layer disposed on a first surface of the substrate and defining a first through-hole extending through the first insulating layer, wherein the first through-hole has a first width; a second insulating layer disposed on the first insulating layer and defining a second through-hole extending through the second insulating layer, wherein the second through-hole has a second width, and a difference between the first width and the second width is less than one-tenth of the first width; an electrical contact disposed in the first through-hole and the second through-hole and electrically connected to the first surface of the substrate; at least one isolation feature extending into the substrate and below the first surface of the substrate; and at least one conductive feature extending through the second insulating layer and the first insulating layer and extending into the substrate.
[0153] Another aspect of this disclosure provides a method for fabricating an electrical structure. The method includes providing a laminated structure comprising a substrate, a first insulating layer and a second insulating layer stacked on top of each other, wherein at least one insulating feature is formed in the substrate and below a first surface of the substrate; forming a first pore structure extending through the first insulating layer and the second insulating layer, wherein the first pore structure exposes a portion of the substrate; and forming at least one third pore structure extending through the second insulating layer and the first insulating layer and extending into the substrate; and cleaning an exposed portion of the substrate with a cleaning agent to enlarge the first pore structure into a second pore structure, wherein the cleaning agent comprises water and hydrofluoric acid (HF), and the weight ratio of water to HF in the cleaning agent is between 500:1 and 2500:1. The method further includes forming an electrical contact in the second pore structure.
[0154] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined by the claims. For example, many of the processes described above may be implemented using different methods, and other processes, or combinations thereof, may be substituted for many of the processes described above.
[0155] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.
Claims
1. An electrical structure, comprising: One base; A first insulating layer is disposed on a first surface of the substrate; A second insulating layer is disposed on the first insulating layer; An electrical contact extends through the first insulating layer and the second insulating layer to be electrically connected to the first surface of the substrate, wherein the electrical contact includes a first portion disposed in the first insulating layer and a second portion disposed in the second insulating layer, the first portion having a first width and the second portion having a second width, and a difference between the first width and the second width being less than 10% of the first width; At least one isolation feature extends into the substrate and is below the first surface of the substrate; as well as At least one conductive feature extends through the second insulating layer and the first insulating layer and into the substrate.
2. The electrical structure as claimed in claim 1, wherein the first portion and the second portion of the electrical contact are formed integrally and simultaneously.
3. The electrical structure of claim 1, wherein the substrate comprises silicon.
4. The electrical structure of claim 1 further includes a first MOS transistor and a second MOS transistor disposed on the substrate, wherein the electrical contact is configured between the first MOS transistor and the second MOS transistor.
5. The electrical structure as claimed in claim 4, wherein the electrical contact is electrically connected to an electrode of the first MOS transistor, an electrode of the second MOS transistor, or to the electrodes of both the first MOS transistor and the second MOS transistor.
6. The electrical structure of claim 1, wherein a material of the second insulating layer is different from a material of the first insulating layer.
7. The electrical structure of claim 1, wherein the electrical contact extends further into the substrate.
8. The electrical structure of claim 7, wherein the electrical contact further includes a third portion disposed in the substrate, and the third portion has a third width smaller than the first width.
9. The electrical structure of claim 8, wherein the third width is smaller than the second width.
10. The electrical structure of claim 8, wherein the first portion, the second portion, and the third portion of the electrical contact are integrally and simultaneously formed.
11. The electrical structure of claim 8, wherein the substrate includes a low-resistance layer and the low-resistance layer is substantially conformally fitted to the third portion of the electrical contact.
12. The electrical structure of claim 11, wherein the low-resistance layer comprises cobalt.
13. The electrical structure of claim 4, wherein the at least one isolation feature comprises two isolation features, and the two isolation features are disposed on both sides of the electrical contact.
14. The electrical structure of claim 13, wherein one of the two isolation features is configured adjacent to and spaced apart from the first MOS transistor, and the other of the two isolation features is configured adjacent to and spaced apart from the second MOS transistor.
15. The electrical structure of claim 14, wherein the at least one conductive feature comprises two conductive features, one of which is disposed between the electrical contact and the isolation feature and adjacent to the first MOS transistor, and the other of which is disposed between the electrical contact and the isolation feature and adjacent to the second MOS transistor.
16. The electrical structure of claim 1, wherein the at least one conductive feature includes a lower portion disposed below the first surface of the substrate and inserted into the substrate, and an upper portion disposed above the first surface of the substrate and inserted into the second insulating layer and the first insulating layer.
17. The electrical structure of claim 16, wherein the lower portion of each of the two conductive features has a first critical dimension, and the upper portion of each of the two conductive features has a second critical dimension, and the second critical dimension is larger than the first critical dimension.
18. The electrical structure of claim 17, wherein the first critical dimension gradually decreases at locations farther from the first surface of the substrate, while the second critical dimension remains constant.