Semiconductor structure comprising magnetic tunnel junction and inductor

Abstract

A semiconductor structure including a magnetic tunnel junction (MTJ) and an inductor includes a substrate, an element region and an inductor region defined on the substrate, a magnetic tunnel junction (MTJ) located in the element region, where the magnetic tunnel junction includes a first MTJ material layer, and an inductor located in the inductor region, where the inductor includes a multi-layer structure, and where the multi-layer structure includes a second MTJ material layer. Wherein the multi-layer structure comprises at least one second MTJ material layer, the first MTJ material layer and the second MTJ material layer are made of the same material, the first MTJ material layer extends along a horizontal direction from a cross-sectional view, the second MTJ material layer comprises a horizontal part and two vertical parts, and the vertical parts extend along a vertical direction.

Description

Technical Field

[0001] This invention relates to a semiconductor structure integrating a magnetoresistive random access memory (MRAM) and an inductor, and a method for fabricating the same, particularly to a semiconductor structure containing an inductor capable of storing high magnetic energy and a method for fabricating the same. Background Technology

[0002] Many modern electronic devices incorporate electronic memory. Electronic memory can be volatile or non-volatile. Non-volatile memory retains its stored data even without power, while volatile memory loses its stored data when power is lost. Magnetoresistive random access memory (MRAM) is highly anticipated as the next generation of non-volatile memory technology due to its superior characteristics compared to current electronic memory.

[0003] Currently, MRAM is not integrated with inductors for radio frequency (RF) applications. Most inductors are assembled with MRAM on a circuit board in an off-chip manner, which increases costs. However, off-chip inductors require additional space on the circuit board. Therefore, if MRAM and inductors can be integrated on a single manufacturing process and a single chip, integration can be greatly improved and costs can be reduced. Summary of the Invention

[0004] This invention provides a semiconductor structure comprising a magnetic tunnel junction (MTJ) and an inductor, comprising a substrate, on which a device region and an inductor region are defined adjacent to the device region, and a magnetic tunnel junction (MTJ) is located within the device region, wherein the magnetic tunnel junction includes a first MTJ material layer, and an inductor is located within the inductor region, wherein the inductor comprises a multilayer structure, wherein the multilayer structure includes at least one second MTJ material layer, wherein the first MTJ material layer and the second MTJ material layer are made of the same material, and wherein, from a cross-sectional view, the first MTJ material layer extends along a horizontal direction, and the second MTJ material layer includes a horizontal portion and two vertical portions, the vertical portions extending along a vertical direction.

[0005] The present invention further provides a method for fabricating a semiconductor structure comprising a magnetic tunnel junction (MTJ) and an inductor, comprising providing a substrate, wherein a device region and an inductor region are defined on the substrate adjacent to the device region, forming a magnetic tunnel junction (MTJ) within the device region, wherein the magnetic tunnel junction comprises a first MTJ material layer, and forming an inductor within the inductor region, wherein the inductor comprises a multilayer structure, wherein the multilayer structure includes at least one second MTJ material layer, wherein the first MTJ material layer and the second MTJ material layer are made of the same material, and wherein, from a cross-sectional view, the first MTJ material layer extends along a horizontal direction, and the second MTJ material layer comprises a horizontal portion and two vertical portions, the vertical portions extending along a vertical direction.

[0006] This invention provides a semiconductor structure integrating MRAM and an inductor, as well as a method for fabricating the same. The inductor is formed concurrently during the MRAM fabrication process, thus saving fabrication steps. Furthermore, the inductor is arranged vertically and penetrates multiple dielectric layers, effectively utilizing unused space within the stacked dielectric layers. In addition, the inductor is surrounded by a helical coil structure, which is formed by multiple notched metal layers and conductive vias connected in series. Therefore, when the coil structure is energized, a larger electric field is generated, increasing the magnetic energy stored in the inductor. Thus, this invention improves semiconductor quality and simplifies the fabrication process. Attached Figure Description

[0007] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0008] Figures 1 to 8 A cross-sectional view of a semiconductor structure integrating MRAM and an inductor, as described in one embodiment of the present invention.

[0009] Figure 9 This is a top view of the MTJ material layer and coil structure within the inductor region of the present invention;

[0010] Figure 10 This is a schematic diagram of the coil structure C of the present invention.

[0011] Symbol Explanation

[0012] 10: Mask layer

[0013] 12: Mask layer

[0014] 14: Mask layer

[0015] 16: Mask layer

[0016] 18: Fourth dielectric layer

[0017] 20: Conductive via

[0018] 22: Groove

[0019] 24: Bottom electrode layer

[0020] 26: MTJ material layer

[0021] 26A: MTJ material layer

[0022] 26B: MTJ material layer

[0023] 26BH: Horizontal section

[0024] 26BV: Vertical section

[0025] 28: Top electrode layer

[0026] 30: Mask layer

[0027] 32: Nitride layer

[0028] 34: Oxide layer

[0029] 36: Fifth dielectric layer

[0030] 38: Mask layer

[0031] C: Coil Structure

[0032] G: Gap

[0033] I: Inductance

[0034] IMD1: First dielectric layer

[0035] IMD2: Second dielectric layer

[0036] IMD3: Third dielectric layer

[0037] L1: Horizontal plane

[0038] M1: First metal layer

[0039] M2: Second metal layer

[0040] M3: Third metal layer

[0041] M4: Fourth Metal Layer

[0042] Mx: Ring-shaped metal layer

[0043] R1: Component Area

[0044] R2: Inductor area

[0045] S: Substrate

[0046] ST: Stepped structure

[0047] V1: Conductive via

[0048] V2: Conductive via

[0049] V3: Conductive via

[0050] V4: Conductive via

[0051] Vx: Conductive via

[0052] V X-1 Conductive via Detailed Implementation

[0053] To enable those skilled in the art to further understand the present invention, preferred embodiments of the invention are described below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings.

[0054] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0055] Although the present invention uses terms such as first, second, third, etc., to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0056] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, such as within 10%, 5%, 3%, 2%, 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate, meaning that the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0057] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0058] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0059] As described in the prior art, with the advancement of semiconductor technology, in order to reduce the space required for components and lower manufacturing costs, it is possible to integrate various different components onto the same substrate. The semiconductor structure described below includes an integrated structure of a magnetoresistive random access memory (MRAM) and an inductor, which will be described in detail in the following paragraphs.

[0060] Please refer to Figures 1 to 8 , Figures 1 to 8 A cross-sectional schematic diagram illustrating a semiconductor structure integrating MRAM and an inductor according to an embodiment of the present invention is shown. Figure 1 As shown, a substrate S is first provided, such as a silicon substrate or a material layer containing electronic components (such as transistors). Multiple layers are sequentially formed on the substrate S to... Figure 1 For example, it includes a mask layer 10, a first dielectric layer IMD1, a mask layer 12, a second dielectric layer IMD2, a mask layer 14, a third dielectric layer IMD3, a mask layer 16, and a fourth dielectric layer 18. The first dielectric layer IMD1, the second dielectric layer IMD2, the third dielectric layer IMD3, and the fourth dielectric layer 18 are made of, for example, silicon oxide, while the mask layers 10, 12, 14, and 16 are made of, for example, silicon nitride or silicon oxynitride, but the invention is not limited thereto. Furthermore, Figure 1 The number of mask layers and dielectric layers shown in the figure can also be adjusted according to actual needs. In other words, in other embodiments of the present invention, the semiconductor structure may also contain more or fewer mask layers and dielectric layers, and such variations are also within the scope of the present invention.

[0061] The mask layer 10 and the first dielectric layer IMD1 contain conductive vias V1 and a first metal layer M1; the mask layer 12 and the second dielectric layer IMD2 contain conductive vias V2 and a second metal layer M2; the mask layer 14 and the third dielectric layer IMD3 contain conductive vias V3 and a third metal layer M3; and the mask layer 16 and the fourth dielectric layer 18 contain conductive vias 20. The conductive vias V1, V2, and V3, as well as the first metal layer M1, second metal layer M2, and third metal layer M3, are made of materials with good conductivity, such as tungsten, cobalt, copper, aluminum, gold, and silver. The first metal layer M1, second metal layer M2, and third metal layer M3 are mainly used for electrically connecting components in the horizontal direction, that is, electrically connecting various electronic components in the same layer structure. The main function of the conductive vias V1, V2, V3, and V4 is to connect electronic components in the vertical direction (i.e., different layers). The technology regarding metal layers and conductive vias is existing technology in this field and will not be elaborated upon here.

[0062] also, Figure 1 The semiconductor device further includes a device region R1 and an inductor region R2, wherein preferably the device region R1 and the inductor region R2 are adjacent to each other. In subsequent steps, devices such as MRAM will be formed in the device region R1, while an inductor will be formed in the inductor region R2 for storing magnetic energy.

[0063] It is worth noting that the conductive vias V1, V2, and V3 in the inductor region R2, together with the first metal layer M1, the second metal layer M2, and the third metal layer M3, form a spiral coil structure C. The first metal layer M1, the second metal layer M2, and the third metal layer M3 are annular or frame-shaped structures with openings, and are connected to each other to form a continuous structure through the conductive vias V1, V2, and V3. The characteristics of the coil structure C will be described more clearly in subsequent paragraphs.

[0064] Then as Figure 2 As shown, a groove 22 is formed in the inductor region R2 using an etching process. In this embodiment, the groove 22 sequentially penetrates the fourth dielectric layer 18, the mask layer 16, the third dielectric layer IMD3, the mask layer 14, the second dielectric layer IMD2, the mask layer 12, and the first dielectric layer IMD1, exposing the surface of the mask layer 10.

[0065] In subsequent steps, an inductor structure will be formed within the groove 22. Since the inductor structure penetrates multiple dielectric layers along the vertical direction, it forms an inductor with a larger area within a limited space, which is beneficial for storing more magnetic energy. Details will be described in subsequent paragraphs.

[0066] like Figure 3 As shown, a bottom electrode layer 24, an MTJ material layer 26, a top electrode layer 28, and a mask layer 30 are sequentially formed in the component region R1 and the inductor region R2. The bottom electrode layer 24 and the top electrode layer 28 are made of materials such as titanium, titanium nitride, tantalum, or tantalum nitride, but are not limited to these. The bottom electrode layer 24 and the top electrode layer 28 electrically connect the magnetic tunneling junction (MTJ) subsequently formed. The MTJ material layer 26 will serve as the magnetic tunneling junction (MTJ) of the MRAM in subsequent steps. The MTJ material layer 26 may contain a multilayer structure, such as magnetic materials and insulating materials. Common magnetic materials include CoPt alloys, CoFe alloys, FePt alloys, IrMn alloys, PtMn alloys, Co / Pt or Co / Pd multilayer films, etc. Common insulating materials include MgO or Al2O3, but the invention is not limited to these. The main function of the mask layer 30 is to protect the magnetic tunnel junction (MTJ). The material of the mask layer 30 is, for example, silicon oxide, but is not limited to this.

[0067] It is worth noting that the bottom electrode layer 24, MTJ material layer 26, top electrode layer 28 and mask 30 are formed on the surface of the fourth dielectric layer 18 in the component area R1, and are also formed in the groove 22 in the inductor area R2. That is to say, the above material layers will be stacked sequentially on the side wall and bottom surface of the groove 22. From the cross-sectional view, the above material layers present a "U" shaped cross-section.

[0068] Then as Figure 4 As shown, a patterning step is performed, removing a portion of the top electrode layer 28 and mask layer 30 within the component region R1 to define a predetermined MTJ pattern within the component region R1, and removing excess top electrode layer 28 and mask layer 30. Simultaneously, in the inductor region R2, a portion of the top electrode layer 28 and mask layer 30 within the component region R1 are also removed. In this embodiment, at this time, the top surfaces of the top electrode layer 28 and mask layer 30 in the inductor region R2 are horizontally aligned with the top surface of the MTJ material layer 26 in the component region R1, as shown... Figure 4 The horizontal plane L1 is shown. However, the present invention is not limited to this. In other embodiments of the present invention, the parameters during the patterning step may be adjusted so that the top surface of the top electrode layer 28 and the top surface of the mask layer 30 in the inductor region R2 are not aligned with the top surface of the MTJ material layer 26 in the component region R1. This is also within the scope of the present invention.

[0069] like Figure 5As shown, using the aforementioned mask layer 30 as a mask, an etching step is performed to remove a portion of the MTJ material layer 26, bottom electrode layer 24, and fourth dielectric layer 18 within the component region R1. Then, a dry etching step removes the mask layer 30. At this point, the remaining bottom electrode layer 24, MTJ material layer 26, and top electrode layer 28 within the component region R1 are defined as a magnetic tunneling junction (MTJ). The MTJ electrically connects to the conductive via 20 below. After the etching step, the MTJ material layer 26 within the component region R1 and the MTJ material layer 26 within the inductor region R2 are separated. For ease of distinction, the MTJ material layer 26 within the component region R1 is defined as MTJ material layer 26A, and the MTJ material layer 26 within the inductor region R2 is defined as MTJ material layer 26B. Here, MTJ material layer 26A will be part of the magnetic tunneling junction (MTJ), while MTJ material layer 26B will be part of the subsequently formed inductor. It is understandable that MTJ material layer 26A and MTJ material layer 26B are made of the same material, so they are made of the same material. In addition, since MTJ material layer 26B has a U-shaped cross-section as seen in the cross-sectional view, MTJ material layer 26B has a horizontal portion 26BH and two vertical portions 26BV, wherein the horizontal portion 26BH and the two vertical portions 26BV together constitute MTJ material layer 26B.

[0070] Furthermore, in the aforementioned dry etching step for removing the mask layer 30, since the etching process includes a vertical ion bombardment etching, when the mask layer 30 in the device region R1 is completely removed, the mask layer 30 located on the bottom surface of the groove 22 in the inductor region R2 may also be completely removed, thereby exposing the top surface of the underlying top electrode layer 28. However, some of the mask layers 30 on the inner side of the groove 22 are not completely removed, and these mask layers 30 are retained in the groove 22. Next, a nitride layer 32 is formed in the device region R1 and the inductor region R2. The nitride layer 32 covers each magnetic tunnel junction (MTJ) and each material layer in the groove 22, for example, covering the side surface of the mask layer 30 and the top surface of the top electrode layer 28. In this embodiment, the material of the nitride layer 32 includes silicon nitride.

[0071] Additionally, during the etching process, after defining the required magnetic tunneling junction (MTJ) within the component region R1, a mask layer (not shown) can be used to cover and protect the MTJ. This mask layer is then removed before the nitride layer 32 is formed. Therefore, since the inductor region R2 is not covered by the mask layer, some material layers within the inductor region R2 will be etched more. For example, from... Figure 5 As can be seen, the top surface of the fourth dielectric layer 18 in the inductor region R2 is lower than the top surface of the fourth dielectric layer 18 in the component region R1, resulting in a stepped structure ST at the junction of the component region R1 and the inductor region R2.

[0072] like Figure 6 As shown, an oxide layer 34 is then formed to fill the gaps between each magnetic tunneling junction (MTJ) and to fill the groove 22. Since the gaps between the MTJs are relatively small, the oxide layer 34 can be formed using atomic layer deposition (ALD), but the invention is not limited to this. Excess oxide layer 34 is subsequently removed. At this point, the bottom electrode layer 24, MTJ material layer 26, top electrode layer 28, mask layer 30, nitride layer 32, and oxide layer 34 formed within the groove 22 are defined as inductor I. Inductor I includes an MTJ material layer 26B, and the MTJ material layer 26B of inductor I and the MTJ material layer 26A in the MTJs are formed simultaneously and contain the same material. Furthermore, inductor I is surrounded by a coil structure C. Additionally, when removing excess oxide layer 34, a portion of the nitride layer 32 may also be removed. In this embodiment, a portion of the nitride layer 32 within the inductor region R2 is removed, but a portion of the nitride layer 32 still covers the top surface of the bottom electrode layer 24, the MTJ material layer 26B, the top electrode layer 28, and the mask layer 30.

[0073] like Figure 7 As shown, a fifth dielectric layer 36 is then formed in the component region R1 and the inductor region R2. The fifth dielectric layer 36 contains an ultra-low dielectric constant material (ULK), such as silicon carbide (SiCOH) or organosilicon glass (OSG), but the present invention is not limited thereto.

[0074] like Figure 8 As shown, a fourth metal layer M4 is formed within the component region R1 and the inductor region R2, wherein the fourth metal layer M4 is electrically connected to the top electrode layer 28 of the magnetic tunnel junction MTJ. Furthermore, the fourth metal layer M4 and a conductive via V4 are formed within the inductor region R2, wherein the conductive via V4 is electrically connected to the underlying third metal layer M3. Subsequently, a mask layer 38 is formed to cover the above structure. At this step, the semiconductor structure comprising MRAM and an inductor described in this invention is complete.

[0075] One feature of this invention is that, during the step of forming the magnetic tunnel junction (MTJ), inductor I is simultaneously formed within the inductor region R2 adjacent to the component region R1, thus saving fabrication steps. Inductor I includes an MTJ material layer 26B, which in turn contains magnetic materials such as CoPt alloy, CoFe alloy, FePt alloy, IrMn alloy, PtMn alloy, Co / Pt, or Co / Pd multilayer films. Therefore, inductor I can be used to store magnetic energy. It is worth noting that in this embodiment, inductor I is not electrically connected to other components; that is, inductor I is in a floating state.

[0076] Another feature of this invention is that the inductor I extends through multiple dielectric layers, meaning that a portion of each material layer of the inductor I extends vertically. Therefore, within a limited space, the inductor I has a relatively high vertical height. Furthermore, the inductor I covers the sidewalls of the groove 22 (which, in cross-sectional view, has two vertical sidewalls), thus giving the inductor I a larger effective area, thereby effectively increasing the magnetic energy that the inductor I can store.

[0077] It is also worth noting that in this embodiment, the inductor I is mainly located within the first dielectric layer IMD1, the second dielectric layer IMD2, and the third dielectric layer IMD3, while the magnetic tunneling junction MTJ is located above the fourth dielectric layer 18 and at the same horizontal level as the fifth dielectric layer 36. That is, from a horizontal perspective, the horizontal position of the inductor I in this embodiment is lower than the horizontal position of the magnetic tunneling junction MTJ. In existing structures, the inductor and the magnetic tunneling junction MTJ may be formed in the same dielectric layer, leaving the dielectric layer space below the inductor unused and idle. This invention effectively utilizes the dielectric layer space within the inductor region R2, using this space to house the inductor I. This configuration effectively utilizes the idle space within the inductor region R2, avoiding space waste.

[0078] Please refer to Figure 9 , Figure 9 A top view schematic diagram illustrating the MTJ material layer within the inductor region and the coil structure C of the present invention is shown. For clarity, Figure 9 The main focus is on the MTJ material layer 26B within the inductor region and the coil structure C, while other components are omitted. For example... Figure 9 As shown in the top view, the MTJ material layer 26B is, for example, annular, while the coil structure C includes an annular metal layer Mx with a notch G, and conductive vias Vx and Vx-1 electrically connecting the two ends of the annular metal layer Mx with the notch. Here, the annular metal layer Mx is, for example, the one described above. Figures 1 to 8 The first metal layer M1, the second metal layer M2, or the third metal layer M3 are shown, and the conductive vias Vx and V... X-1 These represent conductive vias that connect to the metal layer, such as conductive via V1, conductive via V2, conductive via V3, conductive via V4, etc.

[0079] Please refer to this as well. Figure 10 , Figure 10 A schematic diagram of the coil structure C of the present invention is shown. Figures 1 to 8Taking the coil structure C shown as an example, the coil structure C includes a first metal layer M1, a second metal layer M2, and a third metal layer M3. Each metal layer includes a notch G, and conductive vias are electrically connected to both ends of the notch in each metal layer to connect the metal layer to other metal layers. For example, conductive vias V2 and V3 are connected to both ends of the notch G in the second metal layer M2, respectively, so that the second metal layer is electrically connected to the first metal layer M1 and the third metal layer. With this configuration, multiple metal layers can be connected in series to form a continuous coil structure. The coil structure is wrapped around the outside of the inductor I. When the coil structure C is energized, a larger electric field can be generated, thereby increasing the magnetic energy stored in the inductor I.

[0080] The above-mentioned Figures 1 to 10 This invention provides a semiconductor structure comprising MRAM and an inductor, and a method for fabricating the same. In other embodiments of the invention, variations can be made to the semiconductor structure described above. For example, the number of dielectric layers can be changed, resulting in a semiconductor structure containing more or fewer dielectric layers; or the shape of the magnetic tunnel junction (MTJ), inductor I, or coil structure C can be changed, for example, from a circular shape to a square shape in a top view, all of which fall within the scope of this invention.

[0081] Furthermore, in this invention, the horizontal position of inductor I is lower than the horizontal position of the magnetic tunnel junction (MTJ). This configuration, as described above, effectively utilizes the unused dielectric layer space. In other embodiments of this invention, the position of inductor I can be changed; for example, the horizontal position of inductor I can be set higher than the horizontal position of the MTJ, thus achieving the same advantage of efficient space utilization. Such variations also fall within the scope of this invention.

[0082] Based on the above description and accompanying drawings, the present invention discloses a semiconductor structure comprising a magnetic tunnel junction (MTJ) and an inductor, comprising a substrate S, wherein a device region R1 and an inductor region R2 are defined on the substrate S adjacent to the device region R1, and a magnetic tunnel junction (MTJ) is located within the device region R1, wherein the magnetic tunnel junction (MTJ) comprises a first MTJ material layer (i.e., MTJ material layer 26A in the magnetic tunnel junction (MTJ) located within the device region R1), and an inductor I is located within the inductor region R2, wherein the inductor I comprises a multilayer structure, wherein the multilayer structure includes at least one second MTJ material layer 26B, wherein the first MTJ material layer 26A and the second MTJ material layer 26B are made of the same material, and wherein, from a cross-sectional view, the first MTJ material layer 26A extends along a horizontal direction, and the second MTJ material layer 26B comprises a horizontal portion 26BH and two vertical portions 26BV, wherein the vertical portions 26BV extend along a vertical direction.

[0083] In some embodiments of the present invention, the inductor I in the inductor region R2 is located in a first dielectric layer IMD1, and the magnetic tunnel junction MTJ in the element region R1 is located in a fifth dielectric layer 26, wherein the first dielectric layer IMD1 and the fifth dielectric layer 36 are located on different horizontal planes.

[0084] In some embodiments of the present invention, the horizontal position of the first dielectric layer IMD1 is lower than the horizontal position of the fifth dielectric layer 36.

[0085] In some embodiments of the present invention, a coil structure C is located within the inductance region R2, and the coil structure C is located around and surrounds the inductor I.

[0086] In some embodiments of the present invention, the coil structure C includes a plurality of annular patterned layers (e.g., a first metal layer M1, a second metal layer M2, and a third metal layer M3) arranged in a vertical direction, and each annular patterned layer includes a notch G when viewed from a top view.

[0087] In some embodiments of the present invention, the two ends of the notch G in the annular pattern layer are defined as a first end and a second end, respectively, and the notch also includes at least one conductive via, electrically connecting the first end of one annular pattern layer to the second end of another adjacent annular pattern layer, thereby electrically connecting multiple annular pattern layers to each other and forming a spiral structure (see reference). Figure 9 and Figure 10 ).

[0088] In some embodiments of the present invention, the MTJ material layer 26B of the inductor I, viewed from a top view, presents an annular pattern or a frame pattern, and includes an oxide layer 34 located in the middle of the annular pattern or the frame pattern.

[0089] In some embodiments of the present invention, the multilayer structure of the inductor I includes a bottom electrode layer 24, a second MTJ material layer 26B, a top electrode layer 28, a mask layer 30, a nitride layer 32, and an oxide layer 34. In a cross-sectional view, the bottom electrode layer 24, the second MTJ material layer 26B, the top electrode layer 28, and the nitride layer 32 have a U-shaped profile, and the mask layer 30 has an I-shaped profile (as mentioned in the previous paragraph, due to the influence of vertical etching during the etching process, the bottom of the mask layer 30 is removed while the sidewall portion is retained).

[0090] In some embodiments of the present invention, wherein, as viewed in cross-sectional view, the nitride layer 32 covers a top surface of the bottom electrode layer 24, a top surface of the second MTJ material layer 26B, a top surface of the top electrode layer 28 and a top surface of the mask layer 30, but does not cover the top surface of the oxide layer 34.

[0091] The present invention further provides a method for fabricating a semiconductor structure including a magnetic tunnel junction (MTJ) and an inductor, comprising providing a substrate S, wherein a device region R1 and an inductor region R2 are defined on the substrate S adjacent to the device region R1, and a magnetic tunnel junction MTJ is formed within the device region R1, wherein the magnetic tunnel junction MTJ includes a first MTJ material layer 26A, and an inductor I is formed within the inductor region R2, wherein the inductor I includes a multilayer structure, wherein the multilayer structure includes at least one second MTJ material layer 26B, wherein the first MTJ material layer 26A and the second MTJ material layer 26B are made of the same material, and wherein, from a cross-sectional view, the first MTJ material layer 26A extends along a horizontal direction, and the second MTJ material layer 26B includes a horizontal portion 26BH and two vertical portions 26BV, wherein the vertical portions 26BV extend along a vertical direction.

[0092] In some embodiments of the present invention, the inductor I in the inductor region R2 is located in a first dielectric layer IMD1, and the magnetic tunnel junction MTJ in the element region R1 is located in a fifth dielectric layer 26, wherein the first dielectric layer IMD1 and the fifth dielectric layer 36 are located on different horizontal planes.

[0093] In some embodiments of the present invention, the horizontal position of the first dielectric layer IMD1 is lower than the horizontal position of the fifth dielectric layer 36.

[0094] In some embodiments of the present invention, it further includes forming a coil structure C located within the inductance region R2, the coil structure C being located around and surrounding the inductance I.

[0095] In some embodiments of the present invention, the coil structure C includes a plurality of annular patterned layers (e.g., a first metal layer M1, a second metal layer M2, and a third metal layer M3) arranged in a vertical direction, and each annular patterned layer includes a notch G when viewed from a top view.

[0096] In some embodiments of the present invention, the two ends of the notch G in the annular pattern layer are defined as a first end and a second end, respectively, and the notch also includes at least one conductive via, electrically connecting the first end of one annular pattern layer to the second end of another adjacent annular pattern layer, thereby electrically connecting multiple annular pattern layers to each other and forming a spiral structure (see reference). Figure 9 and Figure 10 ).

[0097] In some embodiments of the present invention, it further includes forming at least one conductor layer (including a first metal layer M1, a second metal layer M2, and a third metal layer M3, etc. within the element region) located below the magnetic tunnel junction MTJ within the element region R1, and the conductor layer is electrically connected to the magnetic tunnel junction MTJ, wherein the conductor layer and one of the annular pattern layers of the plurality of annular pattern layers of the coil structure C are formed simultaneously (that is, at least one of the first metal layer M1, the second metal layer M2, and the third metal layer M3 is formed simultaneously in the element region R1 and the inductor region R2).

[0098] In some embodiments of the present invention, the MTJ material layer 26B of the inductor I, viewed from a top view, presents an annular pattern or a frame pattern, and includes an oxide layer 34 located in the middle of the annular pattern or the frame pattern.

[0099] In some embodiments of the present invention, the multilayer structure of the inductor I includes a bottom electrode layer 24, a second MTJ material layer 26B, a top electrode layer 28, a mask layer 30, a nitride layer 32, and an oxide layer 34. In a cross-sectional view, the bottom electrode layer 24, the second MTJ material layer 26B, the top electrode layer 28, and the nitride layer 32 have a U-shaped profile, and the mask layer 30 has an I-shaped profile.

[0100] In some embodiments of the present invention, wherein, as viewed in cross-sectional view, the nitride layer 32 covers a top surface of the bottom electrode layer 24, a top surface of the second MTJ material layer 26B, a top surface of the top electrode layer 28 and a top surface of the mask layer 30, but does not cover the top surface of the oxide layer 34.

[0101] In some embodiments of the present invention, the first MTJ material layer 26A of the magnetic tunnel junction and the second MTJ material layer 26B of the inductor I are formed simultaneously.

[0102] In summary, this invention provides a semiconductor structure integrating MRAM and an inductor, as well as a method for fabricating the same. The inductor is formed concurrently during the MRAM fabrication process, thus saving fabrication steps. Furthermore, the inductor is arranged vertically and penetrates multiple dielectric layers, effectively utilizing unused space within the stacked dielectric layers. In addition, the inductor is surrounded by a helical coil structure, which is formed by multiple notched metal layers and conductive vias connected in series. Therefore, when the coil structure is energized, a larger electric field is generated, increasing the magnetic energy stored in the inductor. Thus, this invention improves semiconductor quality and simplifies the fabrication process.

[0103] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure comprising a magnetic tunnel junction (MTJ) and an inductor, comprising: A substrate on which a component area and an inductor area are defined, located next to the component area; The magnetic tunneling junction is located within the element region, wherein the magnetic tunneling junction includes a first magnetic tunneling junction material layer; An inductor is located within the inductor region, wherein the inductor comprises a multilayer structure, wherein the multilayer structure includes at least one second magnetic tunneling material layer, wherein the first magnetic tunneling material layer and the second magnetic tunneling material layer are made of the same material, and wherein, from a cross-sectional view, the first magnetic tunneling material layer extends along the horizontal direction, and the second magnetic tunneling material layer includes a horizontal portion and two vertical portions, wherein the vertical portions extend along the vertical direction.

2. The semiconductor structure comprising a magnetic tunnel junction and an inductor as claimed in claim 1, wherein the inductor in the inductor region is located in a first dielectric layer, and the magnetic tunnel junction in the element region is located in a fifth dielectric layer, wherein the first dielectric layer and the fifth dielectric layer are located on different horizontal planes.

3. The semiconductor structure comprising a magnetic tunnel junction and an inductor as described in claim 2, wherein the horizontal position of the first dielectric layer is lower than the horizontal position of the fifth dielectric layer.

4. The semiconductor structure comprising a magnetic tunnel junction and an inductor as claimed in claim 1, further comprising a coil structure located within the inductor region, the coil structure being located around and surrounding the inductor.

5. The semiconductor structure comprising a magnetic tunnel junction and an inductance as claimed in claim 4, wherein the coil structure comprises a plurality of annular patterned layers arranged along the vertical direction, and each annular patterned layer comprises a notch when viewed from a top view.

6. The semiconductor structure comprising a magnetic tunnel junction and an inductor as described in claim 5, wherein the two ends of the notch in the annular patterned layer are defined as the beginning end and the end end, respectively, and further comprises at least one conductive via electrically connecting the beginning end of one of the annular patterned layers and the end end of another adjacent annular patterned layer, thereby electrically connecting the plurality of annular patterned layers to each other and forming a spiral structure.

7. The semiconductor structure comprising a magnetic tunneling junction and an inductor as claimed in claim 1, wherein, viewed from a top view, the second magnetic tunneling junction material layer comprising the inductor presents an annular pattern or a frame pattern, and includes an oxide layer located in the middle of the annular pattern or the frame pattern.

8. The semiconductor structure comprising a magnetic tunneling junction and an inductor as claimed in claim 1, wherein the multilayer structure of the inductor comprises a bottom electrode layer, the second magnetic tunneling junction material layer, a top electrode layer, a mask layer, a nitride layer, and an oxide layer, wherein, from the cross-sectional view, the bottom electrode layer, the second magnetic tunneling junction material layer, the top electrode layer, and the nitride layer exhibit a U-shaped profile, and the mask layer exhibits an I-shaped profile.

9. The semiconductor structure comprising a magnetic tunneling junction and an inductor as described in claim 8, wherein, as viewed in the cross-sectional view, the nitride layer covers the top surface of the bottom electrode layer, the top surface of the second magnetic tunneling junction material layer, the top surface of the top electrode layer and the top surface of the mask layer, but does not cover the top surface of the oxide layer.

10. A method for fabricating a semiconductor structure comprising a magnetic tunnel junction (MTJ) and an inductor, comprising: A substrate is provided on which component areas and inductor areas are defined adjacent to the component areas; A magnetic tunnel junction is formed within the element region, wherein the magnetic tunnel junction includes a first magnetic tunnel junction material layer; An inductor is formed within the inductor region, wherein the inductor comprises a multilayer structure, wherein the multilayer structure includes at least one second magnetic tunneling material layer, wherein the first magnetic tunneling material layer and the second magnetic tunneling material layer are made of the same material, and wherein, from a cross-sectional view, the first magnetic tunneling material layer extends along the horizontal direction, and the second magnetic tunneling material layer includes a horizontal portion and two vertical portions, wherein the vertical portions extend along the vertical direction.

11. The method of fabricating a semiconductor structure comprising a magnetic tunnel junction and an inductor as described in claim 10, wherein the inductor in the inductor region is located in a first dielectric layer, and the magnetic tunnel junction in the element region is located in a fifth dielectric layer, wherein the first dielectric layer and the fifth dielectric layer are located on different horizontal planes.

12. The method of fabricating a semiconductor structure comprising a magnetic tunnel junction and an inductor as described in claim 11, wherein the horizontal position of the first dielectric layer is lower than the horizontal position of the fifth dielectric layer.

13. The method of fabricating a semiconductor structure comprising a magnetic tunnel junction and an inductor as described in claim 10, further comprising forming a coil structure located within the inductor region, the coil structure being located around and surrounding the inductor.

14. The method of fabricating a semiconductor structure comprising a magnetic tunnel junction and an inductance as described in claim 13, wherein the coil structure comprises a plurality of annular patterned layers arranged along the vertical direction, and each annular patterned layer comprises a notch when viewed from a top view.

15. The method of fabricating a semiconductor structure comprising a magnetic tunnel junction and an inductance as described in claim 14, wherein the two ends of the notch in the annular patterned layer are defined as a beginning end and an end end, and further comprises forming at least one conductive via, electrically connecting the beginning end of one of the annular patterned layers and the end end of another adjacent annular patterned layer, so that the plurality of annular patterned layers are electrically connected to each other and form a spiral structure.

16. The method of fabricating a semiconductor structure comprising a magnetic tunnel junction and an inductor as claimed in claim 14, further comprising forming at least one conductive layer located below the magnetic tunnel junction within the device region, and the conductive layer being electrically connected to the magnetic tunnel junction, wherein the conductive layer and one of the annular patterned layers of the plurality of annular patterned layers of the coil structure are formed simultaneously.

17. The method of fabricating a semiconductor structure comprising a magnetic tunneling junction and an inductor as described in claim 10, wherein, from a top view, the second magnetic tunneling junction material layer comprising the inductor presents an annular pattern or a frame pattern, and includes an oxide layer located in the middle of the annular pattern or the frame pattern.

18. The method for fabricating a semiconductor structure comprising a magnetic tunneling junction and an inductor as described in claim 10, wherein the multilayer structure of the inductor comprises a bottom electrode layer, the second magnetic tunneling junction material layer, a top electrode layer, a mask layer, a nitride layer, and an oxide layer, wherein, as viewed in the cross-sectional view, the bottom electrode layer, the second magnetic tunneling junction material layer, the top electrode layer, and the nitride layer exhibit a U-shaped profile, and the mask layer exhibits an I-shaped profile.

19. The method of fabricating a semiconductor structure comprising a magnetic tunneling junction and an inductor as described in claim 18, wherein, as viewed from the cross-sectional view, the nitride layer covers the top surface of the bottom electrode layer, the top surface of the second magnetic tunneling junction material layer, the top surface of the top electrode layer and the top surface of the mask layer, but does not cover the top surface of the oxide layer.

20. The method for fabricating a semiconductor structure comprising a magnetic tunneling junction and an inductor as described in claim 10, wherein the first magnetic tunneling junction material layer of the magnetic tunneling junction and the second magnetic tunneling junction material layer of the inductor are formed simultaneously.

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