Semiconductor device

Abstract

A semiconductor device includes: a substrate; a lower channel stack on the substrate; an upper channel stack on the lower channel stack; a gate electrode extending around the lower channel stack and the upper channel stack; a gate cut-out region on the substrate and including an insulating material; a semiconductor material layer between the upper channel stack and the gate cut region; and an insulating layer between the semiconductor material layer and the upper channel stack.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Integrated circuit devices can utilize stacked transistors to increase density and improve performance. In some cases, the stacked transistors can be complementary to each other (e.g., complementary metal-oxide-semiconductor (CMOS) transistors). For example, a complementary FET (CFET) layout can include multiple pairs of vertically stacked gate-all-around field-effect transistors (GAAFETs) having a P-type GAAFET at one height, an N-type GAAFET at another height (i.e., above or below), and a common gate, wherein each common gate extends between and wraps around the channel patterns of the stacked pairs of N-type and P-type GAAFETs. In this structure, the source / drain regions of the lower GAAFET are electrically isolated from the source / drain regions of the upper GAAFET by a dielectric layer. The gate, channel patterns, and isolation structures can be dimensionally similar between the upper and lower devices of the stacked transistors. Summary of the Invention

[0003] According to some embodiments, a semiconductor device includes: a substrate; a lower channel stack on the substrate; an upper channel stack on the lower channel stack; a gate electrode extending around the lower channel stack and the upper channel stack; a gate cut-out region on the substrate and including an insulating material; a semiconductor material layer between the upper channel stack and the gate cut-out region; and an insulating layer between the semiconductor material layer and the upper channel stack.

[0004] In some embodiments, the semiconductor material layer includes at least one of polycrystalline silicon, amorphous silicon, crystalline silicon, doped silicon, or germanium.

[0005] In some embodiments, the insulating layer comprises at least one of silicon dioxide or a dielectric material having a dielectric constant greater than that of silicon dioxide.

[0006] In some embodiments, the upper channel stack includes a plurality of upper channel patterns, an insulating layer including silicon dioxide and the dielectric material, portions of the silicon dioxide contacting a first surface of each of the plurality of upper channel patterns, and portions of the dielectric material contacting a second surface of each of the plurality of upper channel patterns.

[0007] In some embodiments, the width of the semiconductor material layer in a first direction parallel to the upper surface of the substrate is less than or equal to 10 nm.

[0008] In some embodiments, a semiconductor material layer is located between the lower channel stack and the gate cut-out region, and an insulating layer is located between the semiconductor material layer and the lower channel stack.

[0009] In some embodiments, the lower channel stack includes a plurality of lower channel patterns, an insulating layer including silicon dioxide and a dielectric material having a dielectric constant greater than that of silicon dioxide, portions of the silicon dioxide respectively contacting a first surface of each of the plurality of lower channel patterns, and portions of the dielectric material respectively contacting a second surface of each of the plurality of lower channel patterns.

[0010] In some embodiments, the width of each of the plurality of lower channel patterns in a first direction parallel to the upper surface of the substrate is greater than the width of each of the plurality of upper channel patterns in the first direction.

[0011] In some embodiments, the semiconductor device further includes an intermediate dielectric isolation layer between the lower channel stack and the upper channel stack.

[0012] In some embodiments, the lower channel stack and the semiconductor material layer are not stacked in a first direction parallel to the upper surface of the substrate.

[0013] In some embodiments, the width of the lower portion of the semiconductor material layer in the first direction is smaller than the width of the upper portion of the semiconductor material layer in the first direction.

[0014] In some embodiments, the insulating layer contacts the upper surface of the substrate.

[0015] According to some embodiments, a semiconductor device includes: a substrate; a lower channel stack on the substrate and including a plurality of lower channel patterns; an upper channel stack on the lower channel stack and including a plurality of upper channel patterns; a gate electrode extending around the lower channel stack and the upper channel stack; a gate cut-out region on the substrate and including an insulating material; a semiconductor material layer between the upper channel stack and the gate cut-out region and between the lower channel stack and the gate cut-out region, wherein the semiconductor material layer includes at least one of polycrystalline silicon, amorphous silicon, crystalline silicon, doped silicon, or germanium; and an insulating layer between the semiconductor material layer and the upper channel stack and between the semiconductor material layer and the lower channel stack, wherein the insulating layer includes at least one of silicon dioxide or a dielectric material having a dielectric constant greater than that of silicon dioxide.

[0016] In some embodiments, the insulating layer includes silicon dioxide and the dielectric material, with portions of the silicon dioxide contacting a first surface of each of the plurality of upper channel patterns and a first surface of each of the plurality of lower channel patterns, and portions of the dielectric material contacting a second surface of each of the plurality of upper channel patterns and a second surface of each of the plurality of lower channel patterns.

[0017] In some embodiments, the width of the semiconductor material layer in a first direction parallel to the upper surface of the substrate is less than or equal to 10 nm.

[0018] In some embodiments, the insulating layer contacts the upper surface of the substrate.

[0019] According to some embodiments, a semiconductor device includes: a substrate; a lower channel stack on the substrate and including a plurality of lower channel patterns; an upper channel stack on the lower channel stack and including a plurality of upper channel patterns; a gate electrode extending around the lower channel stack and the upper channel stack; a gate cut-out region on the substrate and including an insulating material; a semiconductor material layer between the upper channel stack and the gate cut-out region and not stacked with the lower channel stack in a first direction parallel to the upper surface of the substrate; and an insulating layer between the semiconductor material layer and the upper channel stack and between the semiconductor material layer and the lower channel stack.

[0020] In some embodiments, the semiconductor material layer includes at least one of polycrystalline silicon, amorphous silicon, crystalline silicon, doped silicon, or germanium.

[0021] In some embodiments, the insulating layer comprises at least one of silicon dioxide or a dielectric material having a dielectric constant greater than that of silicon dioxide.

[0022] In some embodiments, the insulating layer includes silicon dioxide and the dielectric material, with portions of the silicon dioxide contacting a first surface of each of the plurality of upper channel patterns, a first surface of each of the plurality of lower channel patterns, and an upper surface of the substrate, and portions of the dielectric material contacting a second surface of each of the plurality of upper channel patterns and a second surface of each of the plurality of lower channel patterns.

[0023] According to some embodiments, a method of forming a semiconductor device includes: forming a plurality of alternately stacked channel layers and sacrificial layers on a substrate; performing a first etching process on the plurality of channel layers and sacrificial layers to form a channel pattern and a sacrificial gate pattern, wherein the channel pattern includes an upper channel pattern and a lower channel pattern; disposing a barrier oxide layer on the channel pattern and the sacrificial gate pattern; disposing a pre-semiconductor material layer on the barrier oxide layer; forming a gate cut-out region on the substrate; performing a second etching process on the pre-semiconductor material layer to remove a portion of the pre-semiconductor material layer and form a semiconductor material layer between the upper channel pattern and the gate cut-out region; forming an insulating layer on the semiconductor material layer; and forming a gate electrode extending around the lower channel pattern and the upper channel pattern.

[0024] In some embodiments, a second etching process is performed to form a semiconductor material layer between the lower channel pattern and the gate cut-out region.

[0025] In some embodiments, a second etching process is performed to form a semiconductor material layer that is not superimposed on the lower channel stack in a first direction parallel to the upper surface of the substrate.

[0026] In some embodiments, the semiconductor material layer includes at least one of polycrystalline silicon, amorphous silicon, crystalline silicon, doped silicon, or germanium.

[0027] In some embodiments, the step of forming an insulating layer on a semiconductor material layer further includes: performing a third etching process to remove the sacrificial gate pattern and forming a first portion of the insulating layer on the semiconductor material layer based on the barrier oxide layer; and forming a second portion of the insulating layer on the semiconductor material layer.

[0028] In some embodiments, the insulating layer comprises at least one of silicon dioxide or a dielectric material having a dielectric constant greater than that of silicon dioxide.

[0029] Other apparatuses, devices, and / or methods according to some embodiments will become clear to those skilled in the art after reviewing the following accompanying drawings and detailed description. It is intended that all such additional embodiments, in addition to any and all combinations of the embodiments described above, be included within this specification, within the scope of this disclosure, and protected by the appended claims.

[0030] The present invention provides a semiconductor device with improved performance and a method for manufacturing the semiconductor device.

[0031] The semiconductor device with improved performance according to the present invention may include an insulating layer extending around the upper channel stack and the lower channel stack, thereby providing enhanced performance.

[0032] The semiconductor device of the present invention includes a semiconductor material layer and an insulating layer, which can be configured to suppress parasitic capacitance without degrading gate control.

[0033] By reducing parasitic capacitance, stacked transistors can operate with reduced power consumption at a given operating frequency. Attached Figure Description

[0034] Figure 1 This is a schematic plan view illustrating an example semiconductor device according to some embodiments of the present disclosure.

[0035] Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D This illustrates some embodiments according to the present disclosure. Figure 1 Schematic cross-sectional views of various structures of semiconductor devices.

[0036] Figure 4A , Figure 4B , Figure 5A and Figure 5B This is a schematic cross-sectional view illustrating various configurations of an example semiconductor device according to some embodiments of the present disclosure.

[0037] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F and Figure 6G This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0038] Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0039] Figure 8 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0040] In the embodiments described herein, the stacked transistor structure may include a first transistor and a second transistor. The first transistor may be a first type of transistor (e.g., an n-type metal-oxide-semiconductor (NMOS) transistor), and the second transistor may be a second type of transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). The first type of transistor and the second type of transistor may be complementary to each other (e.g., CMOS transistors), and in some embodiments, the stacked transistors may be or may include a stack of CMOS transistors. The first and second transistors may be stacked in any order (e.g., with the first transistor on top of the second transistor or the second transistor on top of the first transistor) to produce a stack including a top device (also referred to herein as an upper device or upper transistor relative to the lower substrate) and a bottom device (also referred to herein as a lower device or lower transistor relative to the lower substrate). The gate, channel, and source / drain regions of the upper and lower devices may also be referred to by the terms “upper” and “lower” (e.g., upper gate / lower gate, upper channel / lower channel, upper source / drain region / lower source / drain region, and upper inner spacer / lower inner spacer).

[0041] Some embodiments of this disclosure may stem from the understanding that parasitic capacitance can exist between components of a semiconductor device due to their relatively close proximity. Parasitic capacitance can suppress one or more electrical, performance, and / or operational characteristics (such as increased power consumption, suppressed signal integrity, etc.) of stacked transistors. As an example, in a FinFET (Fin Field-Effect Transistor) including a channel region extending vertically beyond the substrate (e.g., in a direction perpendicular to the upper surface of the substrate), parasitic capacitance can exist between the gate extension and the gate contact, and reducing the gate extension without affecting channel width, capacitance, power consumption, and gate controllability can be challenging.

[0042] Embodiments of this disclosure provide stacked transistor structures, such as 3D stacked field-effect transistors (3DSFETs) in a CMOS fabrication or multi-bridge channel field-effect transistors (MBCFETs) in a CMOS fabrication. TM A semiconductor device. The stacked transistor structure may include a semiconductor material layer and an insulating layer between a gate cut-out region and at least one of an upper channel stack and a lower channel stack. In some embodiments, the semiconductor material layer may be formed by selectively removing (e.g., partially removing) portions of one or more semiconductor layers (e.g., polysilicon layers) of the stacked transistor structure during a manufacturing process, and the insulating layer may be formed to selectively contact corresponding portions of the channel stack and / or the substrate. The semiconductor material layer and the insulating layer may be configured to suppress parasitic capacitances in in-bound standard cells (e.g., standard cells configured to perform one or more memory-based or logic-based operations), out-bound standard cells (e.g., standard cells extending around in-bound standard cells and configured to perform, for example, one or more input / output (I / O) interface connection operations and / or electrostatic discharge (ESD) operations), and mid-bound standard cells (e.g., standard cells between in-bound and out-bound standard cells and configured to perform, for example, one or more voltage shift operations, isolation operations, and / or clock-based operations). The semiconductor material layers and insulating layers can be configured to suppress parasitic capacitance by reducing the gate extension of the stacked transistors without reducing gate controllability (e.g., without reducing or degrading the short-channel effect (SCE)). By reducing parasitic capacitance, the stacked transistors can operate with reduced power consumption for a given operating frequency.

[0043] Reference Figure 1 , Figure 2 and Figures 3A to 3D This illustrates a semiconductor device 100 according to some embodiments of the present disclosure. Figure 2 It is along Figure 1An example cross-sectional view of the semiconductor device 100, indicated by the dashed line AA, and... Figures 3A to 3D It is along Figure 1 Example cross-sectional view of semiconductor device 100 with dashed line BB in the figure.

[0044] In some embodiments, the semiconductor device 100 may be or include off-boundary standard cells. The semiconductor device 100 may have a stacked transistor structure, including a lower transistor 102 and an upper transistor 104 vertically stacked on a substrate 106. In some embodiments, the substrate 106 may include a semiconductor material (such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor). For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 106 may be provided as a body wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0045] In some embodiments, the lower transistor 102 and the upper transistor 104 have complementary conductivity types, for example, to provide a CMOS device. Specifically, the lower transistor 102 may have a first conductivity type (e.g., n-type), while the upper transistor 104 may have a second conductivity type opposite to the first conductivity type (e.g., p-type), or vice versa. That is, the stacked transistor structure according to embodiments of the present disclosure is not limited to a specific orientation of transistors with different conductivity types. Furthermore, in some embodiments, the lower transistor 102 and the upper transistor 104 may have the same conductivity type (e.g., both the lower transistor 102 and the upper transistor 104 may be n-type, or both the lower transistor 102 and the upper transistor 104 may be p-type). Moreover, although shown with reference to the lower transistor 102 and the upper transistor 104, it will be understood that the stacked transistor structure according to embodiments of the present disclosure is not limited to a two-transistor arrangement and may include additional transistors (e.g., a third transistor, a fourth transistor, etc.) vertically stacked on the substrate 106.

[0046] The lower transistor 102 may include a lower channel stack 108 comprising a plurality of lower channel patterns 110, and the upper transistor 104 may include an upper channel stack 114 comprising a plurality of upper channel patterns 116. The lower channel patterns 110 and upper channel patterns 116 may comprise various types of semiconductor materials (such as silicon, germanium, gallium arsenide, and / or other known semiconductor materials). Figure 1 , Figure 2 and Figures 3A to 3DIn the example, multiple upper channel patterns 116 (e.g., in the Z-axis direction perpendicular to the uppermost surface 106US of the substrate 106) are vertically stacked on multiple lower channel patterns 110; however, embodiments of this disclosure may include fewer or more channel patterns than those shown. Each of the upper channel patterns 116 may have a width in the X-axis direction that is smaller than the width in the X-axis direction of each of the lower channel patterns 110. In some embodiments, the widths of the upper channel patterns 116 in the X-axis direction may be the same or different from each other, and the widths of the lower channel patterns 110 in the X-axis direction may be the same or different from each other.

[0047] The lower transistor 102 and the upper transistor 104 may include a gate electrode 118 having one or more conductive patterns extending around the lower channel stack 108 and the upper channel stack 114 and extending in an X-axis direction parallel to the uppermost surface 106US of the substrate 106. In some embodiments, the gate electrode 118 may include various types of conductive materials (such as doped polysilicon (Poly-Si), titanium nitride (TiN), tantalum nitride (TaN), molybdenum (Mo), cobalt (Co), nickel silicide (NiSi), and / or other known conductive materials).

[0048] Semiconductor device 100 may include a gate contact structure 120, which includes a gate contact portion electrically connected to a gate electrode 118 and a dielectric material electrically isolating or separating the gate contact portion and the gate electrode 118 from other portions of the semiconductor device 100. Although not shown in the figures, it should be understood that in some embodiments, the gate contact structure 120 may include one or more metal interconnect layers and / or barrier layers. While the gate contact structure 120 is shown on the upper region 118A of the gate electrode 118, in other embodiments, when the substrate 106 is an insulator, the gate contact structure 120 may be disposed on the lower surface of the substrate 106.

[0049] Semiconductor device 100 may include a gate cutout region 122 extending in the Y-axis direction (parallel to the uppermost surface 106US of substrate 106) and the Z-axis direction (e.g., perpendicularly), such that the gate cutout region 122 contacts, is on, and / or extends into the gate contact structure 120 and substrate 106. The gate cutout region 122 may include an insulating material (such as at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and / or combinations thereof).

[0050] Semiconductor device 100 may include a semiconductor material layer 124, which is located between an upper channel stack 114 and a gate cut-out region 122, and between a lower channel stack 108 and a gate cut-out region 122. The semiconductor material layer 124 may extend in the Y-axis and Z-axis directions such that it contacts the gate contact structure 120, the gate electrode 118 (e.g., the upper region 118A of the gate electrode 118), and the substrate 106 (e.g., the upper surface 106U of the substrate 106) and / or on the gate contact structure 120, the gate electrode 118 (e.g., the upper region 118A of the gate electrode 118), and the substrate 106 (e.g., the upper surface 106U of the substrate 106). The width W1 of the lower portion of the semiconductor material layer 124 in the X-axis direction may be less than or equal to 10 nm. The width W2 of the upper portion of the semiconductor material layer 124 in the X-axis direction may be less than or equal to the width W1 of the lower portion of the semiconductor material layer 124. In some embodiments, the semiconductor material layer 124 comprises at least one selected from polycrystalline silicon, amorphous silicon, monocrystalline silicon, doped silicon, germanium, boron, and phosphorus. As described in further detail below, the semiconductor material layer 124 can be formed by removing portions of one or more pre-constructed semiconductor layers of a stacked transistor structure during a manufacturing process (without removing other portions).

[0051] The semiconductor device 100 may include an insulating layer 126, which is located between and contacts the semiconductor material layer 124 and the upper channel stack 114, and between and contacts the semiconductor material layer 124 and the lower channel stack 108. The insulating layer 126 may extend around the lower channel stack 108 and the upper channel stack 114, thereby electrically isolating or de-isolating the lower channel stack 108 and the upper channel stack 114 from the gate electrode 118 and the semiconductor material layer 124. The insulating layer 126 may extend in the Y-axis and Z-axis directions such that it contacts the side surface of the gate notch region 122, the uppermost surface 106US and / or the upper surface 106U of the substrate 106, each surface of the upper channel stack 114, each surface of the lower channel stack 108, and one or more surfaces of the gate electrode 118, and / or on the side surface of the gate notch region 122, the uppermost surface 106US and / or the upper surface 106U of the substrate 106, each surface of the upper channel stack 114, each surface of the lower channel stack 108, and one or more surfaces of the gate electrode 118. Additional details regarding the fabrication of the insulating layer 126 are provided below.

[0052] In some embodiments, the insulating layer 126 may include at least one of silicon dioxide and a dielectric material having a dielectric constant greater than that of silicon dioxide (hereinafter referred to as "high-k dielectric material") (e.g., hafnium dioxide, aluminum oxide, titanium dioxide, tantalum pentoxide, zirconium dioxide, barium strontium titanate, and other dielectric materials having a dielectric constant greater than that of silicon dioxide). In some embodiments, the insulating layer 126 may include a silicon dioxide portion (also referred to herein as a "barrier oxide portion") and / or a high-k dielectric material portion, which are selectively positioned on various components of the semiconductor device 100 to maintain target gate controllable characteristics (e.g., materials are selectively formed and positioned to suppress SCE degradation).

[0053] As an example and reference Figure 3A The insulating layer 126 may include a high-k dielectric material portion 126-HK, which extends around each surface of each of the upper channel pattern 116 and the lower channel pattern 110 and along the side surfaces of the gate electrode 118 and the gate cutout region 122. The insulating layer 126 may also include a silicon dioxide portion 126-SO, which is located between and contacts the upper surface 106U of the substrate 106 and the lowermost high-k dielectric material portion 126-HK-L of the high-k dielectric material portions. The lowermost high-k dielectric material portion 126-HK-L of the high-k dielectric material portions directly contacts the uppermost surface 106US of the substrate 106.

[0054] As another example and reference Figure 3B The insulating layer 126 includes a silicon dioxide portion 126-SO, which contacts the side surface 116-1 of each of the upper channel patterns 116, the side surface 110-1 of each of the lower channel patterns 110, and the upper surface 106U of the substrate 106. The insulating layer 126 may also include a high-k dielectric material portion 126-HK, which contacts the surfaces 116-2, 116-3, and 116-4 of each of the upper channel patterns 116, the surfaces 110-2, 110-3, and 110-4 of each of the lower channel patterns 110, and the side surfaces of the gate electrode 118 and the gate cutout region 122.

[0055] As yet another example and reference Figure 3CThe insulating layer 126 includes a silicon dioxide portion 126-SO, which contacts the side surface 116-1 of each of the upper channel patterns 116, the side surface 110-1 of each of the lower channel patterns 110, the side surface 118-1 of the gate electrode, and the upper surface 106U of the substrate 106. The insulating layer 126 may also include a high-k dielectric material portion 126-HK, which contacts the surfaces 116-2, 116-3, and 116-4 of each of the upper channel patterns 116, the surfaces 110-2, 110-3, and 110-4 of each of the lower channel patterns 110, the upper region 118A of the gate electrode 118, the side surface of the gate cutout region 122, and the uppermost surface 106US of the substrate 106.

[0056] As an additional example and reference Figure 3D The insulating layer 126 includes a high-k dielectric material portion 126-HK and does not include a silicon dioxide portion 126-SO. The high-k dielectric material portion 126-HK may extend around each surface of each of the upper channel pattern 116 and the lower channel pattern 110. The high-k dielectric material portion 126-HK may also contact the gate electrode 118, the gate cutout region 122, the intermediate dielectric isolation layer 140, and the uppermost surface 106US of the substrate 106.

[0057] Reference Figure 2 The lower source / drain region 132 of the lower transistor 102 having a first conductivity type (e.g., n-type) may be disposed on the opposite side (also referred to herein as the opposite end) of the lower channel pattern 110, and the upper source / drain region 134 of the upper transistor 104 having a second conductivity type opposite to the first conductivity type (e.g., p-type) may be disposed on the opposite side or opposite end of the upper channel pattern 116. In some embodiments, the lower source / drain region 132 may comprise the same material or material composition as the lower channel pattern 110 and the substrate 106. For example, the lower channel pattern 110 and the lower source / drain region 132 may be implemented as a silicon layer. In some embodiments, the upper source / drain region 134 may comprise a different material or material composition than the lower source / drain region 132. For example, the upper channel pattern 116 and the upper source / drain region 134 may be implemented as a silicon-germanium (SiGe) layer. In some embodiments, the lower source / drain region 132 and the upper source / drain region 134 may extend between portions of the gate electrode 118 and directly contact the lower channel pattern 110 and the upper channel pattern 116. The lower channel pattern 110 and the upper channel pattern 116 may extend in the Y-axis direction and may be between two adjacent source / drain regions 132 and two adjacent source / drain regions 134.

[0058] In some embodiments, source / drain electrodes 138 and source / drain contact structures 139 may be disposed on and electrically connected to the lower source / drain region 132 and the upper source / drain region 134. The source / drain contact structures may be electrically isolated from or separated from each other and from the gate contact structure 120. In some embodiments, the semiconductor device 100 may include an intermediate dielectric isolation layer 140 comprising an insulating (e.g., oxidized) material and disposed between the lower channel pattern 110 and the upper channel pattern 116. The semiconductor device 100 may also include an insulating region 142 (e.g., a leakage protection region) in the substrate 106 and comprising an oxide-based (e.g., silicon oxide) pattern or a nitride-based (e.g., silicon nitride) pattern.

[0059] Reference Figure 4A The diagram shows a cross-sectional view of a semiconductor device 200 according to some embodiments of the present disclosure. Except that the widths of the upper channel pattern 116 and the lower channel pattern 110 in the X-axis direction may differ from each other such that they gradually decrease from the uppermost surface 106US of the substrate (106) to the upper region 118A of the gate electrode 118, the semiconductor device 200 may be... Figures 1 to 2 and Figures 3A to 3D The semiconductor device 100 shown is similar. For example, it can be gradually increased to the point that the difference in width between the uppermost upper channel pattern 116-U and the lowermost lower channel pattern 110-L in the X-axis direction is significant (e.g., Figure 4A The predetermined values ​​(such as approximately 5%, approximately 10%, approximately 20%, and other example percentage differences) indicated by the dashed lines L1 and L2 in the diagram. Although the semiconductor device 200 is shown having... Figure 3B The insulating layer 126 has a substantially similar construction to the embodiment shown, but it should be understood that the semiconductor device 200 may have a similar structure. Figure 3A , Figure 3C or Figure 3D The embodiment shown has a similar insulating layer 126.

[0060] Reference Figure 4B This diagram shows a cross-sectional view of a semiconductor device 250 according to some embodiments of the present disclosure. Except that the width of the upper channel pattern 116 in the X-axis direction can be a first width and the width of the lower channel pattern 110 in the X-axis direction can be a second width greater than the first width, the semiconductor device 250 can be... Figures 1 to 2 and Figures 3A to 3DThe semiconductor device 100 shown is similar. In addition, the center line CL of the lower channel stack 108 may be at least partially superimposed in the Z-axis direction with the side surface of the insulating layer 126, the gate electrode 118, or the side surface of the upper channel pattern 116.

[0061] Reference Figure 5A This diagram illustrates a cross-sectional view of a semiconductor device 300 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 300 may include or may be a standard cell within its boundaries. Except for the gate cutout region 322 (which is similar to the gate cutout region 122) on the upper surface 140U of the intermediate dielectric isolation layer 140 and the upper region 118A of the gate electrode 118, the semiconductor device 300 may be... Figures 1 to 2 and Figures 3A to 3D Similar to the semiconductor device 100 shown. Furthermore, a semiconductor material layer 324 (similar to semiconductor material layer 124) may extend between the upper region 118A of the gate electrode 118 and the upper surface 140U of the intermediate dielectric isolation layer 140, and is not stacked with the lower channel stack 108 in the X-axis direction. That is, the lower channel stack 108 and the gate cutout region 322 may not have a semiconductor material layer 324 between the lower channel stack 108 and the gate cutout region 322. Although the semiconductor device 300 is shown with the semiconductor material layer 324 stacked with the upper channel stack 114 and not stacked with the lower channel stack 108 in the X-axis direction, it should be understood that in some embodiments, the semiconductor material layer 324 may not be stacked with the upper channel stack 114 in the X-axis direction and may be stacked with the lower channel stack 108. Furthermore, although the semiconductor device 300 is shown with... Figure 3B The insulating layer 126 has a substantially similar structure to the embodiment shown, but it should be understood that the semiconductor device 300 may have a similar structure. Figure 3A , Figure 3C or Figure 3D The embodiment shown has a similar insulating layer 126. This is an example variant of the semiconductor device 300, and as... Figure 5B As shown, the insulating layer 126 may include silicon dioxide portions 126-SO, which respectively contact the side surface 110-1 of each of the lower channel patterns 110 and the side surface 116-1 of each of the upper channel patterns 116 (e.g., Figure 3B (as shown in the diagram) and the upper surface 106U of the substrate 106. The insulating layer 126 may also include a high-k dielectric material portion 126-HK, which respectively contacts the surfaces 116-2, 116-3, 116-4 of each of the upper channel patterns 116 (as shown in the diagram). Figure 3B As shown), the surfaces 110-2, 110-3, 110-4 of each of the lower channel patterns 110 (as shown) Figure 3B(as shown in the diagram) as well as the side surfaces of the gate electrode 118 and the gate cutout region 322.

[0062] The following reference Figures 6A to 6G Methods for forming semiconductor devices 100, 200, 250 and / or 300 are described. Figures 6A to 6G A schematic cross-sectional view depicting an intermediate process for forming semiconductor device 100 is shown. It should be understood that certain steps may be omitted in various embodiments, and the order of steps for forming semiconductor devices 100, 200, 250, and / or 300 is not limited to the examples shown and described herein.

[0063] Reference Figure 6A The method may include forming a plurality of channel layers 602 and sacrificial layers 604 alternately stacked on a substrate 106. In some embodiments, the method may further include forming an intermediate sacrificial layer 606 between a set of sacrificial layers 604 (which may correspond to a lower transistor 102 and an upper transistor 104). In some embodiments, the intermediate sacrificial layer 606 may have a greater thickness than the sacrificial layers 604. The plurality of channel layers 602 may include a semiconductor material (such as silicon (Si)), and the sacrificial layers 604, 606 may include a material (such as silicon germanium (SiGe)) having etch selectivity with respect to the material of the channel layers 602.

[0064] Reference Figure 6B The method may include forming an upper channel pattern 116, a lower channel pattern 110, an intermediate dielectric isolation layer 140, and a sacrificial gate pattern 608. For example, the channel patterns 116 and 110, the intermediate dielectric isolation layer 140, and the sacrificial gate pattern 608 may be formed by patterning a plurality of channel layers 602, an intermediate sacrificial layer 606, and a sacrificial layer 604 (e.g., performing an etching process on the plurality of channel layers 602, the intermediate sacrificial layer 606, and the sacrificial layer 604). In some embodiments, the respective lengths of the upper channel pattern 116 may be less than each of the respective lengths of the lower channel pattern 110 (e.g., semiconductor devices 100, 200, 250, or 300) and / or may be different from each other (e.g., semiconductor device 200). In some embodiments, the respective lengths of the upper sacrificial gate pattern 608 may be less than each of the respective lengths of the lower sacrificial gate pattern 608 (e.g., semiconductor devices 100, 200, 250, or 300) and / or may be different from each other (e.g., semiconductor device 200).

[0065] To form channel patterns 110, 116, intermediate dielectric isolation layer 140, and sacrificial gate pattern 608, methods may include, for example, performing wet etching processes and / or dry etching processes (such as plasma-enhanced etching), and using one or more mask patterns (not shown) to form desired profiles. The etching process may involve gases including, but not limited to, HBr, Cl2, O2, SF6, and N2. In some embodiments, the etching process includes performing a dry etching process and controlling parameters of the dry etching process (e.g., controlling mass flow rate, pressure, power, ion density, and etchant ratio) to form the desired profiles. In some embodiments, the etching process includes performing a wet etching process and controlling parameters of the wet etching process (e.g., controlling the etchant type) to form the desired width of each of the channel patterns 110, 116, intermediate dielectric isolation layer 140, and sacrificial gate pattern 608.

[0066] Continue to refer to Figure 6B The method may include depositing a barrier oxide layer 626-BO (also referred to herein as "silicon dioxide layer 626-BO") on a substrate 106 and an upper channel pattern 116 and a lower channel pattern 110 (e.g., conformally) using, for example, chemical vapor deposition (CVD) or other known deposition techniques. The method may also include depositing a pre-semiconductor layer 624 on the barrier oxide layer 626-BO (e.g., conformally) using CVD or other known deposition techniques.

[0067] Reference Figure 6C The method may include forming a gate cut-out region 122. As an example, one or more etch masks (not shown) may be formed on a portion of the pre-formed semiconductor layer 624 and / or substrate 106, such that exposed portions are etched during subsequent etch processes (e.g., dry etching and / or wet etching) forming the recess 122R. Subsequently, the recess 122R may be at least partially filled with an insulating material (e.g., at least one of SiN, SiON, SiCN, SiOCN, SiBN, SiOBN, SiOC, and / or combinations thereof) to form the gate cut-out region 122. In a variation (e.g., with...) Figure 5A In the embodiment corresponding to the semiconductor device 300, a recess 122R may be formed such that the recess 122R contacts the upper surface of the intermediate dielectric isolation layer 140 and the side surface of the lower channel pattern 110, thereby forming a gate cutout region 322.

[0068] Reference Figure 6DThe method may include forming a semiconductor material layer 124. As an example, one or more etch masks (not shown) may be disposed on corresponding portions of the upper transistor 104, the lower transistor 102, and the gate cutout region 122, such that they (e.g., in the X-axis, Y-axis, and Z-axis directions) are superimposed on the semiconductor layer region 124R. Subsequently, one or more etching processes (e.g., dry etching and / or wet etching) may be performed to remove exposed portions of the prepared semiconductor layer 624 (e.g., portions not in the semiconductor layer region 124R). Thus, the unremoved portions (e.g., portions in the semiconductor layer region 124R) may correspond to the semiconductor material layer 124.

[0069] Reference Figure 6E The method may include using a known etching process (such as a dry etching process / wet etching process) and one or more etching masks to remove portions of the sacrificial gate pattern 608 and the blocking oxide layer 626-BO that do not directly contact the semiconductor material layer 124 (e.g., with...). Figure 3C The embodiment corresponding to insulating layer 126 shown). In a variant (e.g., with Figure 3A In the embodiment corresponding to the insulating layer 126 shown, after the etching process, only the portion (e.g., portion 626-BO1) that directly contacts both the substrate 106 and the semiconductor material layer 124 of the blocking oxide layer 626-BO is retained. In another variation (e.g., with...), Figure 3B In the embodiment corresponding to the insulating layer 126 shown, after the etching process, only the portion where the blocking oxide layer 626-BO directly contacts "both the substrate 106 and the semiconductor material layer 124, both the upper channel pattern 116 and the semiconductor layer 124, and both the lower channel pattern 110 and the semiconductor layer 124" is retained. In another variation (e.g., with...) Figure 3D In the embodiment corresponding to the insulating layer 126 shown, each portion of the barrier oxide layer 626-BO is removed after the etching process is performed.

[0070] Reference Figure 6F The method may include forming an insulating layer 126 by partially replacing a portion of the removed barrier oxide layer 626-BO with a high-k dielectric material layer 626-HK. For example, Figure 6F It shows having with Figure 3C The insulating layer 126 shown in the embodiment has a substantially similar structure. As an example, the high-k dielectric material layer 626-HK portion can be deposited using atomic layer deposition (ALD).

[0071] Reference Figure 6GThe method may include forming a gate electrode 118 by depositing a conductive material (e.g., using ALD, physical vapor deposition (PVD), and / or electroplating processes) to at least partially fill the recess defined by the lower channel pattern 110 and the upper channel pattern 116 and contact the insulating layer 126. For example, Figure 6G It shows having with Figure 3B The insulating layer 126 has a substantially similar structure to the embodiment shown.

[0072] Although not shown, the method may also include forming source / drain regions 132, 134, forming a gate contact structure 120 on the upper channel stack 114, and / or forming a source / drain contact structure 139 on the source / drain region 132. The source / drain regions 132, 134 may be formed, respectively, between adjacent upper transistors 104 and adjacent lower transistors 102, by selective epitaxial growth, for example, at opposite ends of the upper channel stack 114 and opposite ends of the lower channel stack 108.

[0073] Figure 7 This is a flowchart 700 illustrating a method for forming a semiconductor device according to some embodiments. The method shown in flowchart 700 may correspond to a single or combination of the intermediate process diagrams described above (such as, Figures 6A to 6G (Intermediate process diagram). It should be understood that certain steps may be omitted in various embodiments, and the order of steps for forming a semiconductor device is not limited to the examples shown and described herein.

[0074] In step 702, the method may include forming a plurality of alternately stacked channel patterns (e.g., an upper channel pattern and a lower channel pattern) and a sacrificial gate pattern on a substrate, and forming an intermediate dielectric isolation layer (e.g., between the upper channel pattern and the lower channel pattern) between them. Figures 6A to 6B (The intermediate process shown). In step 704, the method may include depositing a barrier oxide layer (e.g., on the substrate, the upper trench pattern, and the lower trench pattern). Figure 6B The intermediate process shown), and in step 706, the method may include depositing a pre-semiconductor layer on the barrier oxide layer (e.g., the intermediate process shown), and in step 706, the method may include depositing a pre-semiconductor layer on the barrier oxide layer (e.g., Figure 6B (The intermediate process shown).

[0075] In step 708, the method may include forming a gate notch region 122 (e.g., Figure 6C The intermediate process shown), and in step 710, the method may include forming a semiconductor material layer (e.g., Figure 6D The intermediate process shown in step 712 may include removing the sacrificial gate pattern (e.g., the intermediate process shown in the figure). Figure 6E The intermediate process shown), and in step 714, the method may include forming an insulating layer (e.g., Figure 6F(The intermediate process shown). In step 716, the method may include forming a gate electrode (e.g., Figure 6G (The intermediate process shown). According to this application, the insulating layer may refer to, for example, insulating layer 126.

[0076] Figure 8 This is a flowchart 800 illustrating a method for forming a semiconductor device according to some embodiments. The method shown in flowchart 800 may correspond to a single or combination of the intermediate process diagrams described above (such as, Figures 6A to 6G (Intermediate process diagram). It should be understood that certain steps may be omitted in various embodiments, and the order of steps for forming a semiconductor device is not limited to the examples shown and described herein.

[0077] In step 802, the method may include forming a plurality of alternately stacked channel layers and sacrificial layers (e.g., ...) on a substrate. Figure 6A (The intermediate process shown). In step 804, the method may include performing a first etching process (e.g., dry etching and / or wet etching) on ​​multiple channel layers and sacrificial layers to form a channel pattern (e.g., an upper channel pattern and a lower channel pattern) and a sacrificial gate pattern (e.g., ...). Figure 6B The intermediate process shown in the figure). In step 806, the method may include (e.g., using CVD) forming a barrier oxide layer (e.g., ...) on the sacrificial gate pattern, the upper channel pattern, and the lower channel pattern. Figure 6B The intermediate process shown), and in step 808, the method may include (e.g., using CVD) forming a pre-semiconductor material layer on the barrier oxide layer (e.g., Figure 6B (The intermediate process shown). In step 810, the method may include forming a gate notch region 122 (e.g., Figure 6C The intermediate process shown in the figure). In step 812, the method may include performing a second etching process (e.g., dry etching and / or wet etching) on ​​the pre-existing semiconductor material layer to remove a portion of the pre-existing semiconductor material layer and form a semiconductor material layer between the upper channel pattern and the gate cut-out region (e.g., Figure 6D (The intermediate process shown). In some embodiments, a second etching process may be performed to form a semiconductor material layer between the lower channel pattern and the gate cut-out region. In a variant, a second etching process may be performed to form a semiconductor material layer that is not stacked with the lower channel stack in a direction parallel to the upper surface of the substrate (e.g., the X-axis direction).

[0078] In step 814, the method may include forming an insulating layer on a semiconductor material layer. As an example, forming an insulating layer on a semiconductor material layer may include performing a third etching process (e.g., dry etching and / or wet etching) to remove the sacrificial gate pattern and forming a first portion of the insulating layer on the semiconductor material layer based on a barrier oxide layer (e.g., Figure 6E (The intermediate process shown). Subsequently, forming the insulating layer may include providing a second portion of the insulating layer on the channel patterns 110 and 116, the gate cutout region 122, and the substrate 106 (e.g., Figure 6F (The intermediate process shown). In step 816, the method may include forming a gate electrode extending around the lower channel pattern and the upper channel pattern (e.g., Figure 6G (The intermediate process shown).

[0079] According to embodiments of this disclosure, a semiconductor device includes a semiconductor material layer (e.g., a polysilicon layer) intentionally modified (e.g., to accommodate stacked transistors in standard cells outside the boundary and / or standard cells inside the boundary). That is, portions of the semiconductor material layer may be intentionally retained without being stripped or removed. Therefore, a reduced gate extension can be achieved by selectively retaining portions of the semiconductor material layer, thereby suppressing parasitic capacitance while maintaining desired or targeted gate controllability. However, embodiments of this disclosure are not limited thereto.

[0080] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, all terms should be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and should not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0081] In the above description, each example embodiment has been described with reference to a region of a specific conductivity type. It will be understood that devices with opposite conductivity types can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. Therefore, it will be understood that this disclosure covers both n-channel and p-channel devices for each different device structure.

[0082] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. The terms “comprising” and / or “including” describe the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof.

[0083] It will be understood that although the terms “first,” “second,” etc., are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0084] It will be understood that when a component (such as a layer, region, or substrate) is referred to as being "on" or extending "on" another component, the component may be directly on or directly extending to the other component, or intermediate components may be present. In contrast, when a component is referred to as being "directly on" or "directly" extending "on" another component, no intermediate components are present. It will also be understood that when a component is referred to as being "connected" or "bonded" to another component, the component may be directly connected or bonded to the other component, or intermediate components may be present. In contrast, when a component is referred to as being "directly connected" or "directly bonded" to another component, no intermediate components are present.

[0085] Spatial relative terms (such as "below" or "above" or "upper" or "lower" or "top" or "bottom") may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region based on a reference point (e.g., a base), as shown in the figures. It will be understood that these terms are intended to cover different orientations of the apparatus in addition to those depicted in the figures.

[0086] Example embodiments are described herein with reference to the accompanying drawings, which may include cross-sectional views as schematic illustrations of idealized embodiments (and intermediate structures). Many different forms and embodiments are possible without departing from the teachings of this disclosure. Therefore, this disclosure should not be construed as limited to the example embodiments set forth herein. Consequently, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined herein. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Furthermore, variations in the shape of the figures can be anticipated due to, for example, manufacturing techniques and / or manufacturing tolerances.

[0087] Embodiments of this disclosure are also described with reference to manufacturing operations and flowcharts. It will be understood that the steps shown in the manufacturing operations and flowcharts do not need to be performed in the order shown.

[0088] The subject matter disclosed above is intended to be illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the scope of this disclosure. Therefore, to the fullest extent permitted by law, the scope will be determined by the widest permissible interpretation of the appended claims and their equivalents, and should not be limited or restricted by the foregoing detailed description.

Claims

1. A semiconductor device, comprising: Base; Lower channel stacked components, on the substrate; Upper channel stacked component, on the lower channel stacked component; The gate electrode extends around the lower channel stack and the upper channel stack; The gate cutout region is on the substrate and includes insulating material; A semiconductor material layer is located between the upper channel stack and the gate cutout region; as well as An insulating layer is placed between the semiconductor material layer and the upper channel stack.

2. The semiconductor device according to claim 1, wherein, The semiconductor material layer includes at least one of polycrystalline silicon, amorphous silicon, monocrystalline silicon, doped silicon, and germanium.

3. The semiconductor device according to claim 1, wherein, The insulating layer includes at least one of silicon dioxide and a dielectric material having a dielectric constant greater than that of silicon dioxide.

4. The semiconductor device according to claim 3, wherein: The upper channel stack includes multiple upper channel patterns; The insulating layer comprises silicon dioxide and the dielectric material; The silicon dioxide portions respectively contact the first surface of each of the plurality of upper channel patterns; and A portion of the dielectric material contacts the second surface of each of the plurality of upper channel patterns.

5. The semiconductor device according to claim 1, wherein, The width of the semiconductor material layer in a first direction parallel to the upper surface of the substrate is less than or equal to 10 nm.

6. The semiconductor device according to claim 1, wherein, A semiconductor material layer is located between the lower channel stack and the gate cut-out region, and an insulating layer is located between the semiconductor material layer and the lower channel stack.

7. The semiconductor device according to claim 6, wherein: The lower channel stack includes multiple lower channel patterns; The insulating layer comprises silicon dioxide and a dielectric material having a dielectric constant greater than that of silicon dioxide; The silicon dioxide portions respectively contact the first surface of each of the plurality of lower trench patterns; and A portion of the dielectric material contacts the second surface of each of the plurality of lower channel patterns.

8. The semiconductor device according to claim 7, wherein, The width of each of the plurality of lower channel patterns in a first direction parallel to the upper surface of the substrate is greater than the width of each of the plurality of upper channel patterns in the first direction.

9. The semiconductor device according to claim 1, further comprising: An intermediate dielectric isolation layer is located between the lower channel stack and the upper channel stack.

10. The semiconductor device according to claim 1, wherein, The lower channel stack and the semiconductor material layer are not stacked in a first direction parallel to the upper surface of the substrate.

11. The semiconductor device according to claim 10, wherein, The width of the lower part of the semiconductor material layer in the first direction is smaller than the width of the upper part of the semiconductor material layer in the first direction.

12. The semiconductor device according to any one of claims 1 to 11, wherein, The insulating layer contacts the upper surface of the substrate.

13. A semiconductor device, comprising: Base; A lower channel stack, on a substrate and including multiple lower channel patterns; An upper channel stack is on a lower channel stack and includes multiple upper channel patterns; The gate electrode extends around the lower channel stack and the upper channel stack; The gate cutout region is on the substrate and includes insulating material; A semiconductor material layer is located between the upper channel stack and the gate cutout region, and between the lower channel stack and the gate cutout region. as well as An insulating layer is located between the semiconductor material layer and the upper channel stack, and between the semiconductor material layer and the lower channel stack.

14. The semiconductor device according to claim 13, wherein: The insulating layer comprises silicon dioxide and a dielectric material having a dielectric constant greater than that of silicon dioxide; The silicon dioxide portions respectively contact the first surface of each of the plurality of upper channel patterns and the first surface of each of the plurality of lower channel patterns; and A portion of the dielectric material contacts the second surface of each of the plurality of upper channel patterns and the second surface of each of the plurality of lower channel patterns.

15. The semiconductor device according to claim 13, wherein, The width of the semiconductor material layer in a first direction parallel to the upper surface of the substrate is less than or equal to 10 nm.

16. The semiconductor device according to any one of claims 13 to 15, wherein, The insulating layer contacts the upper surface of the substrate.

17. A semiconductor device, comprising: Base; A lower channel stack, on a substrate and including multiple lower channel patterns; An upper channel stack is on a lower channel stack and includes multiple upper channel patterns; The gate electrode extends around the lower channel stack and the upper channel stack; The gate cutout region is on the substrate and includes insulating material; A semiconductor material layer is located between the upper channel stack and the gate cutout region, and is not stacked with the lower channel stack in a first direction parallel to the upper surface of the substrate. as well as An insulating layer is located between the semiconductor material layer and the upper channel stack, and between the semiconductor material layer and the lower channel stack.

18. The semiconductor device according to claim 17, wherein, The semiconductor material layer includes at least one of polycrystalline silicon, amorphous silicon, monocrystalline silicon, doped silicon, and germanium.

19. The semiconductor device according to claim 17, wherein, The insulating layer includes at least one of silicon dioxide and a dielectric material having a dielectric constant greater than that of silicon dioxide.

20. The semiconductor device of claim 19, wherein: The insulating layer comprises silicon dioxide and the dielectric material; The silicon dioxide portion respectively contacts the first surface of each of the plurality of upper channel patterns, the first surface of each of the plurality of lower channel patterns, and the upper surface of the substrate; as well as A portion of the dielectric material contacts the second surface of each of the plurality of upper channel patterns and the second surface of each of the plurality of lower channel patterns.

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