Semiconductor device manufacturing method and semiconductor device manufacturing apparatus

Abstract

The invention discloses a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus. A method for manufacturing a semiconductor element according to an embodiment of the present invention comprises: a step for providing a semiconductor structure including one or more channel layers having an interface layer formed on a surface thereof; an interface layer surface activation step of activating the interface layer surface by performing hydrogen plasma treatment on the semiconductor structure; and a dipole doping step: combining a dipole on the surface of the activated interface layer to form atoms. According to the invention, after hydrogen plasma processing is carried out on the surface of the interface layer and activation is carried out, dipoles are doped to form atoms, so that the effect that a dipole interface can be formed on the gate insulation layer through a simple process is achieved.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices and an apparatus for manufacturing semiconductor devices. Background Technology

[0002] Techniques for adjusting the threshold voltage (Vt) of transistors while using dielectric materials with high dielectric constants (High K) and metal gate electrodes in the gate stack of semiconductor devices are becoming increasingly important. Methods for adjusting the threshold voltage of transistors include adding a work function adjustment layer to the gate stack, or forming dipoles by doping the gate insulating layer with materials such as lanthanum (La) or aluminum (Al).

[0003] Existing techniques for forming dipoles typically involve forming a dipole forming layer on a gate insulating layer followed by high-temperature heat treatment. The gate insulating layer, formed on top of the channel layer, typically comprises a stack of an interface layer composed of a silicon oxide film and a high-dielectric layer such as a hafnium oxide film (HfO2). The dipole forming layer can be a lanthanum (La) or aluminum (Al) layer or a layer containing lanthanum (La) or aluminum (Al). If high-temperature heat treatment is performed after the dipole forming layer is formed, lanthanum (La) or aluminum (Al) atoms from the dipole forming layer diffuse into the gate insulating layer, forming dipoles within the gate insulating layer through activation by high-temperature energy. Typically, dipoles form at the interface between the interface layer constituting the gate insulating layer and the high-dielectric layer; therefore, a dipole interface is formed due to the dipole formation.

[0004] On the other hand, in such a method, a capping layer is formed above the dipole forming layer and then subjected to high-temperature heat treatment to prevent structural deformation at high temperatures and to promote the diffusion of lanthanum (La) or aluminum (Al) atoms into the gate insulating layer. As the capping layer, titanium nitride (TiN) film and / or amorphous silicon film are used. The capping layer is a layer that is not needed in the gate stack and is therefore removed by an etching process after the high-temperature heat treatment for dipole interface formation.

[0005] The existing dipole interface formation technology requires capping layer formation and removal processes, which not only makes the process complex, but also increases the thermal budget of semiconductor devices due to the need for high-temperature thermal treatment.

[0006] In particular, existing dipole interface formation techniques are more difficult to apply to three-dimensional transistor structures (such as GAA-FETs, C-FETs, and forksheet structures). For example, in the case of a vertically stacked C-FET structure with a GAA structure, the spacing between the channel layers is very small, making it difficult to form and remove capping layers in the spaces between the channel layers. These difficulties are likely to be even more pronounced when the channel layers are in nanosheet form rather than nanowires.

[0007] To form a dipole interface, an implantation method is used to directly dope lanthanum (La) or aluminum (Al) into the gate insulating layer. However, this method cannot achieve integral doping of the gate insulating layer that surrounds the channel layer. Therefore, this method is not suitable for three-dimensional transistor structures such as C-FETs.

[0008] (Patent Document 1) US2022 / 0085015 A1 (May 17, 2022)

[0009] (Patent Document 2) US2022 / 0238680 A1 (July 28, 2022) Summary of the Invention

[0010] The present invention aims to solve the problems of the prior art described above, and aims to provide a method and apparatus for manufacturing semiconductor devices that can form a dipole interface in the gate insulating layer through a simpler process.

[0011] In addition, the present invention has another objective of providing a method and apparatus for manufacturing semiconductor devices that can effectively form dipole interfaces in the gate insulating layer of a three-dimensional transistor structure.

[0012] In addition, the present invention has another objective of providing a method and apparatus for manufacturing semiconductor devices in which a dipole interface can be formed in the gate insulating layer without damage to the interface layer.

[0013] The semiconductor device manufacturing method according to an embodiment of the present invention is characterized by comprising: a step of providing a semiconductor structure, the semiconductor structure including one or more channel layers on the surface having an interface layer formed thereon; an interface layer surface activation step of activating the interface layer surface by subjecting the semiconductor structure to hydrogen plasma treatment; and a dipole doping step of binding dipole-forming atoms on the activated interface layer surface.

[0014] In an embodiment of the present invention, the semiconductor structure may include: a substrate; and a plurality of channel layers arranged in a vertical direction (z-direction) above the substrate.

[0015] In embodiments of the present invention, the plurality of channel layers may be provided in the form of nanosheets extending in the horizontal direction (x direction).

[0016] In an embodiment of the present invention, the plurality of channel layers may be interconnected by sources and drains respectively disposed at both ends in the horizontal direction (x direction).

[0017] In an embodiment of the present invention, the interface layer may be a silicon oxide film.

[0018] In an embodiment of the present invention, a dangling key may be formed on the surface of the interface layer through the interface layer surface activation step.

[0019] In an embodiment of the present invention, the interface layer surface activation step may be a step of treating the interface layer surface with hydrogen plasma using hydrogen free radicals.

[0020] In an embodiment of the present invention, the dipole doping step may include: a dipole formation precursor adsorption step, in which a dipole formation precursor containing dipole forming atoms is adsorbed onto the surface of the interface layer; and a byproduct removal step, in which the ligands of the dipole formation precursor are removed.

[0021] In embodiments of the present invention, the dipole-forming atom may be lanthanum (La) or aluminum (Al).

[0022] In an embodiment of the present invention, the byproduct removal step may be a plasma treatment step using a gas containing oxygen (O).

[0023] In embodiments of the present invention, the dipole formation precursor adsorption step and the byproduct removal step may be performed simultaneously, or the byproduct removal step may be performed for a certain period of time after the dipole formation precursor adsorption step is completed.

[0024] In embodiments of the present invention, the interface layer surface activation step and the dipole doping step may be repeated more than twice.

[0025] A semiconductor device manufacturing method according to an embodiment of the present invention is characterized by comprising: a semiconductor structure providing step, providing a semiconductor structure having a plurality of channel layers spaced apart from each other in a vertical direction formed above a substrate; an interface layer forming step, depositing a silicon oxide film on the surface of the plurality of channel layers to form an interface layer; an interface layer surface activation step, subjecting the semiconductor structure to hydrogen plasma treatment to form dangling bonds on the surface of the interface layer; a dipole doping step, combining dipole-forming atoms with dangling bonds on the surface of the interface layer by plasma treatment simultaneously with supplying a dipole-forming precursor containing dipole-forming atoms and an oxygen gas; a gate dielectric layer deposition step, depositing a gate dielectric layer on the surface of the interface layer to which the dipole atoms are combined; and a gate metal layer deposition step.

[0026] In an embodiment of the present invention, the semiconductor structure providing step may include: a stacking step, in which a channel layer serving as a semiconductor layer and a sacrificial layer capable of selectively etching the channel layer are alternately stacked on the substrate; a nanosheet patterning step, in which the alternately stacked channel layer and the sacrificial layer are patterned with a predetermined width; and an etching step, in which the sacrificial layer is selectively etched in the nanosheet pattern.

[0027] In an embodiment of the present invention, the interface layer may be a silicon oxide film and the gate dielectric layer may be a hafnium oxide film (HfO2).

[0028] A semiconductor device manufacturing apparatus according to an embodiment of the present invention is characterized by comprising: a cavity providing a processing space inside; a base disposed within the cavity to support a wafer; a plasma source for generating plasma in the processing space; a gas inlet for supplying hydrogen gas, a dipole-forming precursor containing dipole-forming atoms, oxygen gas, and an inert gas to the cavity; an exhaust port for discharging gas and byproducts from the cavity; an ion barrier disposed above the base to divide the processing space into an upper processing space and a lower processing space, and including a through-hole connecting the upper processing space and the lower processing space; and a controller means for controlling: placing a wafer with a semiconductor structure formed thereon onto the base, the semiconductor structure including one or more channel layers on the surface of which an interface layer is deposited; generating hydrogen plasma while supplying hydrogen gas and an inert gas to the processing space through the gas inlet to form dangling bonds on the surface of the interface layer; and generating plasma while supplying the dipole-forming precursor and oxygen gas to the processing space through the gas inlet to combine dipole-forming atoms on the surface of the interface layer.

[0029] In an embodiment of the invention, the ion blocker may be connected to ground via a switch, and the controller controls the switch to connect the ion blocker to ground at least during the period when hydrogen plasma is generated in the processing space.

[0030] In an embodiment of the present invention, the gas inlet may include a first gas inlet for supplying gas to the upper processing space and a second gas inlet for supplying gas to the lower processing space. Hydrogen gas, oxygen gas, and inert gas are supplied to the upper processing space through the first gas inlet, and a dipole forming precursor is supplied to the lower processing space through the second gas inlet.

[0031] Through embodiments of the present invention, dipole-forming atoms are activated by hydrogen plasma treatment of the interface layer surface, thereby achieving the effect of forming a dipole interface in the gate insulating layer through a simple process.

[0032] In addition, the present invention does not require capping layer deposition and removal processes, thus effectively forming a dipole interface in the gate insulating layer of a three-dimensional transistor structure with very small spacing between channel layers.

[0033] In addition, the present invention uses hydrogen free radicals to treat the surface of the interface layer with hydrogen plasma, which has the effect of forming a dipole interface in the gate insulating layer without damaging the interface layer. Attached Figure Description

[0034] Figure 1 This is a flowchart of a semiconductor device manufacturing method according to an embodiment of the present invention.

[0035] Figure 2 This is a flowchart of a dipole doping method according to an embodiment of the present invention.

[0036] Figures 3A to 3G This is a diagram illustrating the steps of a semiconductor device manufacturing method according to an embodiment of the present invention.

[0037] Figure 4 These are XPS measurements of the interface layer surface after hydrogen plasma treatment.

[0038] Figures 5A to 5D This is a diagram illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0039] Figure 6 This is a simplified diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

[0040] (Explanation of reference numerals in the attached diagram)

[0041] 100: Semiconductor Structures

[0042] 102: Substrate

[0043] 108: Sacrificial Layer

[0044] 110: Channel layer

[0045] 200: Gate insulating layer

[0046] 210: Interface Layer

[0047] 220: Gate dielectric layer

[0048] 230: Gate metal layer

[0049] 500: Cavity

[0050] 510: Base

[0051] 520: Plasma Source

[0052] 530: Gas Inlet

[0053] 540: Exhaust port

[0054] 550: Ion Blocker Detailed Implementation

[0055] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this invention pertains can readily implement it. The present invention can be implemented in various different ways and is not limited to the embodiments described herein.

[0056] To clearly illustrate the invention, irrelevant parts have been omitted, and the same or similar components are marked with the same reference numerals throughout the specification.

[0057] Furthermore, in multiple embodiments, the same reference numerals are used to describe only representative embodiments of the constituent elements having the same structure, while in other embodiments only structures different from the representative embodiments are described.

[0058] In the specification as a whole, when a part is described as being "connected (or combined)" with other parts, it includes not only the case of "direct connection (or combination)" but also the case of "indirect connection (or combination)" where other components are placed in between. Furthermore, when a part is described as "including" a constituent element, unless otherwise stated otherwise, it means that other constituent elements may be included, rather than excluding them.

[0059] Unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the same meaning as commonly understood by one of ordinary knowledge in the art to which this invention pertains. Terms such as those defined in commonly used dictionaries shall be interpreted as having the same meaning as in the relevant technical context, and shall not be ideally or excessively interpreted as having a formal meaning unless expressly defined in this application.

[0060] Figure 1 This is a flowchart of a semiconductor device manufacturing method according to an embodiment of the present invention. Figure 2 This is a flowchart of a dipole doping method according to an embodiment of the present invention. Figures 3A to 3G This is a diagram illustrating the steps of a semiconductor device manufacturing method according to an embodiment of the present invention. The following refers to... Figures 1 to 3G The method for semiconductor devices according to embodiments of the present invention will be described. Figures 1 to 3G This is a diagram intended to aid in understanding a semiconductor element method according to an embodiment of the present invention; therefore, only the main steps are shown briefly, and it should be understood that there may be additional steps and structures not described.

[0061] like Figure 1 The flowchart shows that the semiconductor device manufacturing method (S100) according to an embodiment of the present invention may include a semiconductor structure providing step (S110) of providing a semiconductor structure including one or more channel layers, an interface layer forming step (S120) of forming an interface layer on the surface of the channel layer, an interface layer surface activation step (S130) of activating the interface layer surface by hydrogen plasma treatment of the semiconductor structure, a dipole doping step (S140) of bonding dipole forming atoms to the activated interface layer surface, a gate dielectric layer deposition step (S150) of forming a gate dielectric layer on the interface layer surface bonded with dipole forming atoms, and a gate metal layer deposition step (S160).

[0062] The semiconductor structure provided in the semiconductor structure providing step (S110) is a semiconductor structure including one or more channel layers.

[0063] like Figure 3A As exemplarily shown, the semiconductor structure 100 provided in the semiconductor structure providing step (S110) includes a substrate 102 and one or more channel layers 110 formed above the substrate 102.

[0064] Substrate 102 may be a single-crystal silicon (Si) substrate, but is not limited thereto. Substrate 102 may be silicon-germanium (SiGe), silicon carbide (SiC), carbon-doped silicon (Si:C), silicon carbide-germanium (SiGeC), carbon-doped silicon-germanium (SiGe:C), III-V or II-VI compound semiconductors, SOI (Silicon-on-Insulator), silicon-germanium-on-insulator, glass, sapphire, organic semiconductor substrates, or substrates containing these materials. Furthermore, substrate 102 may include doped or undoped regions, and may include patterned or unpatterned regions. Figure 3A As shown, substrate 102 may include isolation regions, such as STI (Shallow Trench Isolation) regions.

[0065] The channel layer 110 can be a semiconductor layer. The channel layer 110 can be a silicon layer or a silicon-germanium (SiGe) layer. The channel layer 110 can be a single crystal layer. The channel layer 110 can serve as a charge movement path between the source and drain in three-dimensional transistor structures such as GAA, C-FET, and Forksheet.

[0066] The channel layer 110 can be formed in Figure 3A The nanosheet shape extends long in the x-direction. That is, the channel layer 110 can be formed into a sheet shape with a rectangular cross-section.

[0067] exist Figure 3A The illustration shows three channel layers 110 arranged in the z-direction formed above substrate 102, but this is exemplary and the number of channel layers 110 is not limited to a specific value or range in this invention.

[0068] exist Figure 3A The diagram shows multiple channel layers 110 arranged only in the z direction, but may include other multiple channel layers 110 arranged spaced apart in the x and / or y directions.

[0069] Multiple channel layers 110 can be passed through in Figure 3A A separate structure (not shown) supports the substrate 102. For example, the source and drain of the multiple channel layers 110 can be disposed at both ends of the channel layer 110 in the x-direction to connect the multiple channel layers 110 to each other. That is, the multiple channel layers 110 can be in the form of a bridge, with the source and drain connected at both ends respectively and supported by the source and drain.

[0070] The interface layer formation step (S120) is a step of forming an interface layer 210, which together with the gate dielectric layer 220 described later, constitutes the gate insulating layer 200, on the surface of the channel layer 110. The interface layer 210 may be a silicon oxide layer, and may be formed in several... Up to dozens Thickness. The interface layer 210 can be formed with a uniform thickness over the entire area of ​​the channel layer 110 by atomic layer deposition, but is not limited to this.

[0071] like Figure 3B As shown, an interface layer 210 of uniform thickness can be formed on the surface of each of the plurality of channel layers 110 through the interface layer forming step (S120). When the channel layer 110 is a nanosheet shape extending in the x direction, the interface layer 210 can be formed to completely surround the top (+z direction), bottom (-z direction), left side (-y direction), and right side (+y direction) of each nanosheet.

[0072] The interface layer surface activation step (S130) is a step of activating the surface of the interface layer 210 by performing hydrogen plasma treatment on the semiconductor structure on which the interface layer 210 is formed on the surface of the channel layer 110. Figure 3C Activation on this surface means forming dangling bonds on the surface.

[0073] For hydrogen plasma treatment, hydrogen gas and an inert gas can be supplied to generate plasma. The hydrogen plasma reacts with interface layer 210, forming dangling bonds on the surface of interface layer 210. When interface layer 210 is a silicon oxide layer, oxygen on the surface of the silicon oxide layer can be at least partially removed by the hydrogen plasma. Oxygen on the surface of interface layer 210 can react with hydrogen from the hydrogen plasma and be removed in the form of water (H2O) molecules. Therefore, the surface of interface layer 210 can become an oxygen-deficient silicon oxide film (SiO2). x (x<2), forming multiple dangling bonds on the surface of interface layer 210.

[0074] Hydrogen plasma treatment can be performed at pressures of 10 mTorr to 1 Torr and temperatures of 300°C to 700°C.

[0075] Figure 4 These are XPS measurements of the interface layer surface before and after hydrogen plasma treatment. For example, in... Figure 4 The study confirmed that most of the sample was SiO2 before hydrogen plasma treatment, and SiO2 with a binding energy of 103.0 eV was detected after hydrogen plasma treatment. x That is, SiO is formed by removing oxygen from the surface of the interface layer through hydrogen plasma treatment. xThis means that dangling bonds are formed at the sites where oxygen has been removed. Dangling bonds are readily bonded, so as a result, the interface layer surface becomes activated after hydrogen plasma treatment.

[0076] The interface layer surface activation step (S130) removes hydrogen ions from the hydrogen plasma, primarily utilizing hydrogen radicals. For this purpose, any suitable component can be used, such as an ion blocker to block ions or a remote plasma source to supply only radicals. By activating the interface layer surface using only hydrogen radicals, interface layer damage from ions or the generation of fixed charge can be suppressed, thus forming a dipole interface in the gate insulating layer.

[0077] Refer again Figure 1 The process involves performing a dipole doping step (S140) to bind dipole-forming atoms to the activated interface layer 210 surface. The dipole-forming atoms can be lanthanum (La) or aluminum (Al), and the atom can be selected to obtain the desired threshold voltage (Vt). The dipole-forming atoms can be bound to dangling bonds on the interface layer 210 surface generated in the interface layer surface activation step (S130) via the dipole doping step (S140).

[0078] Reference Figure 2 as well as Figure 3D The dipole doping step (S140) may include a dipole formation precursor adsorption step (S141) and a byproduct removal step (S142).

[0079] The dipole-forming precursor adsorption step (S141) is a step of adsorbing a dipole-forming precursor, which is a precursor containing dipole-forming atoms, onto the surface of the interface layer 210. Specifically, dipole-forming atoms contained in the dipole-forming precursor, such as lanthanum (La) or aluminum (Al), are adsorbed onto dangling bonds formed on the surface of the interface layer 210.

[0080] The dipole-forming precursor can be a compound containing ligands bonded to dipole-forming atoms, such as lanthanum (La) or aluminum (Al). It is not particularly limited, but the dipole-forming precursor can be AlH3(NEtMe2), AlH3(MeNC4H4), AlMe2(OiPr), AlMe3, La(CpEt)3, La(CpiPr)3, etc.

[0081] The byproduct removal step (S142) is a step to remove ligands from the dipole-forming precursor, which can be performed by plasma treatment with a gas capable of removing ligands. The gas capable of removing ligands can be a gas containing oxygen (O). For example, it can be oxygen (O2), ozone (O3), carbon dioxide (CO2), nitrous oxide (N2O), with oxygen (O2) being preferred. The ligands from the dipole-forming precursor can be removed by oxygen plasma treatment, specifically removing dangling bonds formed by dipole-forming atoms such as lanthanum (La) and aluminum (Al) bonded to the surface of interface layer 210.

[0082] According to an embodiment of the present invention, the surface of the interface layer 210 is activated by hydrogen plasma treatment, so that even without a separate high-temperature heat treatment process, dipole-forming atoms can bond to the surface of the interface layer to form a dipole interface. Furthermore, dipole doping is performed directly on the surface of the interface layer before depositing the gate dielectric layer, thus eliminating the need for high-temperature heat treatment for diffusion, as well as the need for capping layer formation and removal processes required for high-temperature heat treatment.

[0083] exist Figure 2 The diagram illustrates the sequential adsorption step (S141) for dipole formation and the byproduct removal step (S142), but these two steps can be performed simultaneously. That is, the dipole doping step (S140) can be performed by simultaneously supplying the dipole formation precursor and oxygen plasma. The ligands in the dipole formation precursor can be removed by the oxygen plasma, leaving only the dipole-forming atoms bound to the dangling bonds on the surface of the interface layer 210.

[0084] When the dipole formation precursor adsorption step (S141) and the byproduct removal step (S142) are performed simultaneously, the byproduct removal step (S142) can also continue for a certain period of time after the dipole formation precursor adsorption step (S141) ends. That is, dipole doping can be performed by simultaneously supplying the dipole formation precursor and oxygen plasma, and then the supply of the dipole formation precursor can be interrupted while the oxygen plasma treatment continues for a certain period of time. In this way, ligands on the surface of the interface layer 210 or inside the processing space can be completely removed.

[0085] The interface layer surface activation step (S130) and the dipole doping step (S140) can be repeated more than twice. That is, a unit cycle including the interface layer surface activation step (S130) and the dipole doping step (S140) can be repeated multiple times. Alternatively, in this method, after the dangling bonds formed on the surface of interface layer 210 by hydrogen plasma treatment are consumed in the dipole doping step, repeated hydrogen plasma treatment is performed to generate new dangling bonds on the surface of interface layer 210, providing new sites for dipole-forming atomic bonding.

[0086] After the dipole doping step (S140), the gate dielectric layer deposition step (S150) can be performed. Figure 3E As shown, the gate dielectric layer 220 can be deposited to cover the entire area surrounding the interface layer 210. The gate dielectric layer 220 can form a gate insulating layer 200 together with the interface layer 210. Dipole doping is performed on the surface of the interface layer 210, so the gate insulating layer 200 can include a dipole interface.

[0087] The gate dielectric layer 220 can be formed as a high-dielectric layer containing a high-dielectric material. The gate dielectric layer 220 may include, for example, a hafnium oxide film (HfO2), a zirconium oxide film (ZrO2), a yttrium oxide film (Y2O3), an aluminum oxide film (Al2O3), or HfZrO or HfLaO. x Ternary oxide films such as HfTiO are used. Preferably, the gate dielectric layer 220 can be a hafnium oxide film (HfO2).

[0088] The gate dielectric layer 220 can be deposited by atomic layer deposition (ALD) to surround the entire area of ​​the interface layer 210 with a uniform thickness.

[0089] After the gate dielectric layer 220 is deposited, the gate metal layer deposition step (S160) can be performed. For example... Figure 3F as well as Figure 3G As shown, the gate metal layer 230 can be formed as a pillar structure extending in the y-direction entirely around the plurality of channel layers 110. The gate metal layer 230 can function as a gate electrode for applying a gate voltage for transistor turn-on and turn-off.

[0090] The gate metal layer 230 may comprise a titanium nitride film (TiN), a tantalum nitride film (TaN), tantalum carbide (TaC), cobalt (Co), ruthenium (Ru), aluminum (Al), or a combination thereof. The gate metal layer 230 may be a single layer or may be formed as multiple layers.

[0091] Figures 5A to 5D It is used to explain the manufacturing process. Figure 3A A diagram illustrating an exemplary method for constructing a semiconductor structure. Figures 5A to 5D This diagram is intended to help understand the method of forming the channel layer 110, and therefore only the main steps are shown briefly. It should be understood that there may be additional steps and structures that are not described.

[0092] like Figure 5A A sacrificial layer 108 and a channel layer 110 are alternately deposited on a substrate 102. The sacrificial layer 108 is formed of a material that can selectively etch the channel layer 110. The etch selectivity ratio of the sacrificial layer 108 to the channel layer 110 can be 10:1 or higher.

[0093] When the channel layer 110 is a silicon layer, the sacrificial layer 108 can be a silicon-germanium (SiGe) layer. When the channel layer 110 is a silicon-germanium (SiGe) layer, the sacrificial layer 108 can be a germanium (Ge) layer. Alternatively, the channel layer 110 and the sacrificial layer 108 can be silicon-germanium layers with different germanium (Ge) concentrations. For example, the channel layer 110 can be a SiGe layer with a germanium content of x relative to silicon. x The sacrificial layer 108 can be a SiGe with a germanium content of y relative to silicon. y layer.

[0094] like Figure 5B The sacrificial layer 108 and the channel layer 110 are patterned into nanosheets with a predetermined width in the y-direction. For patterning, any suitable mask material and anisotropic etching method can be used.

[0095] After patterning, such as Figure 5C An isolation region, such as an STI region, can be formed in a predetermined area of ​​the substrate 102.

[0096] like Figure 5D The sacrificial layer 108 can be selectively removed. This can be achieved through the selective removal of the sacrificial layer 108. Figure 3A The semiconductor structure. The sacrificial layer 108 can be removed by any suitable etching method that can selectively etch the channel layer 110. For etching the sacrificial layer 108, atomic layer etching (ALE) can be used.

[0097] Figure 6 This is a simplified diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention. Figure 6 The semiconductor manufacturing apparatus is suitable for performing the semiconductor device manufacturing method according to embodiments of the present invention. Figure 1 The apparatus for steps S130 and S140 in the process.

[0098] Reference Figure 6 As described above, a semiconductor manufacturing apparatus 1000 according to an embodiment of the present invention may include a cavity 500, a base 510 disposed within the cavity and supporting a wafer W, a plasma source 520 for plasma generation, a gas inlet 530 for supplying gas into the cavity, an exhaust port 540 for discharging gas and byproducts from the cavity, an ion blocker 550 disposed above the base 510, and a controller 600.

[0099] The cavity 500 provides a processing space S for performing semiconductor device manufacturing methods and can be made of a metal such as aluminum (Al). The processing space S can include the upper processing space S based on the ion barrier 550. A and the lower processing space S B.

[0100] The base 510 is in the processing space S, specifically, the lower processing space S B Inner support wafer W. Wafer W can be formed with... Figure 3B The semiconductor structure is supplied to the lower processing space S in a state of semiconductor structure. B That is, performing, for example, outside the semiconductor manufacturing apparatus 1000. Figures 5A to 5D Semiconductor structure formation process and Figure 3B The wafer W formed by the interface layer 210 process can be supplied to the next processing space S. B It is placed on the base 510. A heater (not shown) for heating the wafer W can be built into the base 510.

[0101] Plasma source 520 is used in processing space S, specifically, on processing space S A The structure that generates the plasma can use any plasma source. The plasma source 520 can be any of the following: microwave source, ICP (Inductively Coupled Plasma) source, CCP (Capacitively Coupled Plasma) source, or remote plasma source.

[0102] The gas inlet 530 may include a first gas inlet 532 for supplying inert gases such as hydrogen (H2), oxygen (O2), and argon (Ar), and a second gas inlet 534 for supplying precursors for dipole formation. It may be provided as an upper processing space S above the ion barrier 550, with the first gas inlet 532 supplying gas to the processing space. A The gas supply, the second gas inlet 534, leads to the lower processing space S below the ion blocker 550. B Supply gas.

[0103] An exhaust port 540 can be located at the lower part of the cavity 500 to discharge the gas and byproducts inside the cavity 500. For this purpose, the exhaust port 540 can be connected to a vacuum pump (not shown). A baffle plate 542 for adjusting the exhaust conductivity can be disposed between the processing space S and the exhaust port 540. The baffle plate 542 can be disposed between the side wall of the cavity 500 and the base 510.

[0104] The ion blocker 550 can divide the processing space S inside the cavity 500 into an upper processing space S. A and the lower processing space S B It is provided in the form of a plate including multiple through holes 552. Upper processing space S A and the lower processing space S BMultiple through-holes 552 can be connected. The ion blocker 550 can be connected to ground via a switch (not shown). Alternatively, if the ion blocker 550 is connected to ground, then in the upper processing space S... A Ions from the plasma generated in the process are blocked by ion blocker 550, and only electrically neutral free radicals pass through through-hole 552 into the lower processing space S in which the wafer W is disposed. B Supply. When ion blocking is not required, the ion blocker 550 can be switched off and grounded.

[0105] The controller 600 controls the operation of the semiconductor manufacturing apparatus 1000 to enable the execution of a semiconductor device manufacturing method according to an embodiment of the present invention. The controller 600 may include a CPU, a memory, and circuitry. The CPU may be any type of general-purpose processor, and the memory may be any type of local or remote digital storage device, including RAM, ROM, floppy disk, hard disk, etc. The memory may store process recipes for executing the semiconductor device manufacturing method according to an embodiment of the present invention.

[0106] If the wafer W is placed on the base 510, the controller 600 can control the plasma source 520 to process hydrogen (H2) gas and inert gas upward into the processing space S through the first gas inlet 532. A Hydrogen plasma is generated simultaneously with the supply. The surface of interface layer 210 can be activated by the hydrogen plasma. At this time, controller 600 can control the ion blocker 550 to be connected to ground via a switch, thereby blocking the plasma ions and supplying only hydrogen radicals to wafer W through via 552. By activating the interface layer surface through hydrogen radicals, a dipole interface can be formed in the gate insulating layer without damaging the interface layer.

[0107] After the interface layer surface activation step, the controller 600 can be controlled to process the upward space S through the first gas inlet 532. A Oxygen (O2) gas is supplied and processed downwards into space S through the second gas inlet 534. B While supplying the precursor for dipole formation, the dipole doping step is performed. The controller 600 can control the plasma source 520 to operate in the upper processing space S. A Oxygen plasma is generated internally. While ligands and byproducts of dipole formation precursors are removed by the oxygen plasma, dipole-forming atoms are bonded to the surface of interface layer 210. At this time, controller 600 can selectively switch ion blocker 550 to or from ground, controlling either the process to primarily perform byproduct removal via oxygen radicals or to also involve oxygen ions in the byproduct removal process.

[0108] The controller 600 can be configured to continue the oxygen supply through the first gas inlet 532 for a certain period of time after the supply of the dipole forming precursor through the second gas inlet 534 is interrupted.

[0109] Furthermore, the controller 600 can control the semiconductor device manufacturing apparatus 1000 to repeat the interface layer surface activation step and the dipole doping step more than twice. Therefore, a single cycle including the interface layer surface activation step and the dipole doping step can be repeated multiple times.

[0110] In the semiconductor device manufacturing apparatus 1000 according to an embodiment of the present invention, the ion barrier 550 may be omitted. That is, if a device that utilizes only hydrogen radicals for interface layer activation is not required, the ion barrier 550 may not be included in the semiconductor device manufacturing apparatus 1000. In this case, the processing space S is not divided into an upper processing space S. A and the lower processing space S B .

[0111] exist Figure 6 The diagram shows a gas inlet 530 disposed on the side wall of the cavity 500, but the invention is not limited thereto. The gas inlet 530 may also be configured to supply gas from the upper wall of the cavity 500 to the processing space S.

[0112] This embodiment and the accompanying drawings are merely illustrative of a portion of the technical concept included in this invention. It is obvious that variations and specific embodiments that can be readily derived by those skilled in the art within the scope of the technical concept included in the specification and drawings of this invention are all included within the scope of the claims of this invention.

[0113] Therefore, the concept of the present invention is not limited to the illustrated embodiments, and not only the appended claims, but also equivalent or equivalent variations thereof fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: The step of providing a semiconductor structure, said semiconductor structure comprising one or more channel layers having an interface layer formed on its surface; The interface layer surface activation step involves activating the interface layer surface by subjecting the semiconductor structure to hydrogen plasma treatment; and The dipole doping step involves binding dipoles to form atoms on the activated interface layer surface.

2. The semiconductor device manufacturing method according to claim 1, wherein, The semiconductor structure includes: Substrate; and Multiple channel layers are arranged vertically above the substrate.

3. The semiconductor device manufacturing method according to claim 2, wherein, The plurality of channel layers are provided in the form of nanosheets extending in the horizontal direction.

4. The semiconductor device manufacturing method according to claim 2, wherein, The multiple channel layers are interconnected by source and drain electrodes respectively located at both ends in the horizontal direction.

5. The semiconductor device manufacturing method according to claim 1, wherein, The interface layer is a silicon oxide film.

6. The semiconductor device manufacturing method according to claim 5, wherein, Through the interface layer surface activation step, dangling bonds are formed on the interface layer surface.

7. The semiconductor device manufacturing method according to claim 6, wherein, The interface layer surface activation step is a step of treating the interface layer surface with hydrogen plasma using hydrogen free radicals.

8. The semiconductor device manufacturing method according to claim 1, wherein, The dipole doping step includes: The dipole-forming precursor adsorption step involves adsorbing a dipole-forming precursor containing dipole-forming atoms onto the surface of the interface layer; and The byproduct removal step removes the ligands of the dipole-forming precursor.

9. The semiconductor device manufacturing method according to claim 8, wherein, The dipole-forming atom is lanthanum or aluminum.

10. The semiconductor device manufacturing method according to claim 8, wherein, The byproduct removal step is a plasma treatment step.

11. The semiconductor device manufacturing method according to claim 10, wherein, The byproduct removal step is a plasma treatment step using an oxygen-containing gas.

12. The semiconductor device manufacturing method according to claim 8, wherein, The dipole formation precursor adsorption step and the byproduct removal step are performed simultaneously.

13. The semiconductor device manufacturing method according to claim 12, wherein, After the dipole formation precursor adsorption step is completed, the byproduct removal step is also performed for a certain period of time.

14. The semiconductor device manufacturing method according to claim 1, wherein, The interface layer surface activation step and the dipole doping step are repeated more than twice.

15. A method for manufacturing a semiconductor device, comprising: A semiconductor structure providing step, providing a semiconductor structure having a plurality of channel layers spaced apart from each other in a vertical direction formed above a substrate; In the interface layer formation step, a silicon oxide film is deposited on the surface of the plurality of channel layers to form an interface layer; The interface layer surface activation step involves treating the semiconductor structure with hydrogen plasma to form dangling bonds on the interface layer surface. The dipole doping step involves plasma treatment while supplying a dipole-forming precursor containing dipole-forming atoms and an oxygen gas, thereby binding dipole-forming atoms to dangling bonds on the surface of the interface layer. The gate dielectric layer deposition step involves depositing a gate dielectric layer on the surface of the interface layer in which the dipole atoms are bonded; and Gate metal layer deposition step.

16. The semiconductor device manufacturing method according to claim 15, wherein, The steps for providing the semiconductor structure include: The lamination step involves alternately laminating a channel layer, which serves as a semiconductor layer, and a sacrificial layer capable of selectively etching the channel layer on the substrate. The nanosheet patterning step involves patterning the alternately stacked channel layers and sacrificial layers with a predetermined width; and The etching step involves selectively etching the sacrificial layer within the nanosheet pattern.

17. The semiconductor device manufacturing method according to claim 15, wherein, The interface layer is a silicon oxide film, and the gate dielectric layer is a hafnium oxide film.

18. A semiconductor device manufacturing apparatus, comprising: The cavity provides processing space inside; A base, disposed within the cavity, supports the wafer; A plasma source for generating plasma in the processing space; A gas inlet is provided for supplying hydrogen gas, a dipole-forming precursor containing dipole-forming atoms, oxygen gas, and an inert gas into the cavity. An exhaust port is used to discharge the gas and byproducts inside the cavity. An ion barrier, disposed above the base to divide the processing space into an upper processing space and a lower processing space, includes a through-hole connecting the upper processing space and the lower processing space; and Controller The controller controls: A wafer having a semiconductor structure formed thereon is placed on the substrate, the semiconductor structure comprising one or more channel layers having an interface layer deposited on its surface; Hydrogen plasma is generated while hydrogen gas and inert gas are supplied to the processing space through the gas inlet, thus forming dangling bonds on the surface of the interface layer. Plasma is generated while dipole-forming precursors and oxygen gas are supplied to the processing space through the gas inlet, thereby binding dipole-forming atoms on the surface of the interface layer.

19. The semiconductor device manufacturing apparatus according to claim 18, wherein, The ion blocker is connected to ground via a switch. The controller controls the switch so that the ion blocker is connected to ground at least during the period when hydrogen plasma is generated in the processing space.

20. The semiconductor device manufacturing apparatus according to claim 18, wherein, The gas inlet includes a first gas inlet for supplying gas to the upper processing space and a second gas inlet for supplying gas to the lower processing space. Hydrogen, oxygen, and inert gases are supplied to the upper processing space through the first gas inlet. The dipole-forming precursor is supplied to the lower processing space through the second gas inlet.

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