Manufacturing method of metal gate
By performing ozone oxidation on the TSN layer and combining it with room temperature wet etching, the contact resistance and electromigration problems caused by the TaN layer were solved, resulting in higher device reliability and protection of the TSN layer, thus avoiding gate leakage.
Patent Information
- Application Number
- CN202511767507.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-03-03
AI Technical Summary
In the prior art, TaN as the etch stop layer of the work function layer causes increased contact resistance and electromigration problems in nanoscale gate structures, while directly omitting TaN leads to high TSN layer loss and gate leakage, affecting device reliability.
After the TSN layer is formed, ozone oxidation is performed, combined with room temperature wet etching. The TSN layer is used as the etching stop layer of the P-type work function metal layer, and the TaN layer is removed. By adjusting the etching selectivity, the etching stops on the TSN layer, thus forming the gate structures of NMOS and PMOS.
It effectively eliminates high contact resistance and electromigration problems, improves device reliability, reduces TSN layer loss, and avoids gate leakage.
Smart Images
Figure CN121604490A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for manufacturing a metal gate (MG). Background Technology
[0002] In advanced manufacturing processes (MG) loops, TaN is typically used as an etch stop layer for work function removal. This is achieved by depositing a TaN layer of appropriate thickness and TiN as a p-type work function layer using die lithography and etching (ETCH). The areas requiring TiN removal are then opened using lithography and etch solution SC2 or H2O2 to remove the TiN from the opened areas and leave it on top of the TaN.
[0003] However, as semiconductor devices evolve towards more advanced processes, TaN has certain limitations as a work function regulating material. TaN has a high resistivity, which can easily lead to increased contact resistance and electromigration problems in nanoscale gate structures, affecting device reliability.
[0004] However, if the TaN at the bottom of the P-type work function layer is omitted, the wet etching process will not stop on the surface of the silicon-doped TiN (Ti-Si-N, TSN) layer at the bottom, resulting in high TSN loss and gate leakage. This will be further explained below:
[0005] like Figures 1A to 1C The diagram shown is a schematic representation of the device structure in each step of the existing first method for manufacturing a metal gate; the existing first method for manufacturing a metal gate includes the following steps:
[0006] like Figure 1A As shown, a high dielectric constant layer (HK) 101, a TSN layer 102, and a TaN layer 103 are sequentially formed on the top surface of a semiconductor substrate (not shown).
[0007] Figure 1A In this context, the high dielectric constant layer (HK) 101, the TSN layer 102, and the TaN layer 103 are also represented by HK, TSN, and TaN, respectively.
[0008] An interface layer is also formed between the high dielectric constant layer 101 and the top surface of the semiconductor substrate. Figure 1A In this context, the structure below the high dielectric constant layer 101 is omitted.
[0009] The TSN layer 102 and the TaN layer 103 together serve as the bottom barrier layer (BBM).
[0010] A P-type work function metal layer 104 is formed on the top surface of the TaN layer 103. The material of the P-type work function metal layer 104 is TiN. Figure 1A In this context, the P-type work function metal layer 104 is also represented by TiN.
[0011] like Figure 1B As shown, the area of the P-type work function metal layer 104 that needs to be removed is opened, and then wet etching is performed to remove the P-type work function metal layer 104 and stop on the TaN layer 103. Figure 1B Only the region of the P-type work function metal layer 104 that needs to be removed is shown; this region is typically the NMOS formation region.
[0012] like Figure 1C As shown, an N-type work function metal layer 104 is formed, and the material of the N-type work function metal layer 104 includes TiAl. Figure 1C In this context, the N-type work function metal layer 104 is also represented by TiAl.
[0013] Then a top barrier layer 105 and a metal conductive material layer 106 are formed.
[0014] The material of the top barrier layer 105 includes TiN. Figure 1C In this context, the top barrier layer 105 is also represented by TBM TiN.
[0015] The material of the metallic conductive material layer 106 includes W. Figure 1C In this context, the metallic conductive material layer 106 is also represented by W.
[0016] Depend on Figure 1C As shown, the gate structure includes the TaN layer 103. As the process node continues to shrink, the TaN layer 103 increases the contact resistance of the gate structure and causes electromigration problems.
[0017] like Figures 2A to 2C The diagram shown is a schematic diagram of the device structure in each step of the existing second metal gate manufacturing method; the difference between the existing first metal gate manufacturing method and the existing second metal gate manufacturing method is that the TaN layer 103 is omitted in the existing second metal gate manufacturing method.
[0018] like Figure 2A As shown, after the TSN layer 102 is formed, the P-type work function metal layer 104 is formed directly.
[0019] Figure 2B In the corresponding wet etching process, since the bottom barrier layer no longer includes the TaN layer 103, the TSN layer 102 will be subject to greater loss, thus reducing the thickness of the TSN layer 102.
[0020] Figure 2C In this process, the steps following wet etching are the same as those in the existing first type of metal gate manufacturing method.
[0021] Depend on Figure 2C As shown, due to the high loss of TSN layer 102, gate leakage is prone to occur. Summary of the Invention
[0022] The technical problem to be solved by the present invention is to provide a method for manufacturing a metal gate that does not require the use of TaN as an etching stop layer for the P-type work function metal layer. The TaN layer can be removed in the bottom barrier layer at the bottom of the P-type work function metal layer, thereby eliminating the problems of high contact resistance and electromigration caused by the TaN layer, and thus improving the reliability of the device.
[0023] To solve the above-mentioned technical problems, the manufacturing method of the metal grid provided by the present invention includes the following steps:
[0024] A gate dielectric layer and a TSN layer are sequentially formed on the top surface of a semiconductor substrate.
[0025] The top surface of the TSN layer is oxidized using ozone.
[0026] A P-type work function metal layer is formed on the top surface of the TSN layer.
[0027] The first region is opened and wet etching is performed at room temperature to remove the P-type work function metal layer in the first region. The wet etching solution is SC2 or H2O2. The etching rate of the TSN is reduced by utilizing the characteristics of room temperature and the oxidation treatment of the top surface of the TSN, thereby increasing the etching selectivity of the P-type work function metal layer to the TSN layer. The etching selectivity satisfies the requirement of the TSN layer as an etching stop layer, so that the wet etching stops on the TSN layer.
[0028] An N-type work function metal layer is formed, which covers the top surface of the TSN in the first region and the top surface of the P-type work function metal layer outside the first region.
[0029] A layer of conductive metallic material is formed.
[0030] A further improvement is that the material of the P-type work function metal layer includes TiN.
[0031] A further improvement is that the first region is the formation region of NMOS, and the area outside the first region is the formation region of PMOS.
[0032] A further improvement is that the material of the N-type work function metal layer includes TiAl.
[0033] A further improvement is that the minimum deposition thickness of the TSN layer is [value missing]. above.
[0034] A further improvement is that, after the wet etching, the thickness of the TSN is... above.
[0035] A further improvement is that, prior to forming the metallic conductive material layer, the following steps are also included:
[0036] Forming a top barrier layer (TBM).
[0037] A further improvement is that the material of the top barrier layer includes TiN.
[0038] A further improvement is that the material of the metallic conductive material layer includes Al or W.
[0039] A further improvement is that a gate trench is formed on the semiconductor substrate.
[0040] The gate structure of the PMOS includes a superposition structure of the gate dielectric layer, the TSN layer, the P-type work function metal layer, the N-type work function metal layer and the metal conductive material layer formed in the gate trench of the formation region of the PMOS.
[0041] The gate structure of the NMOS includes a superimposed structure of the gate dielectric layer, the TSN layer, the N-type work function metal layer and the metal conductive material layer formed in the gate trench of the formation region of the NMOS.
[0042] A further improvement is that the gate trench is formed by removing the dummy gate structure.
[0043] A further improvement is that the material of the gate dielectric layer includes a high dielectric constant material (HK).
[0044] A further improvement is that an interface layer is formed between the gate dielectric layer and the top surface of the semiconductor substrate.
[0045] This invention adds an ozone oxidation step to the TSN layer after its formation, combined with a room temperature setting for wet etching, to reduce the etching rate of the TSN layer. This allows the TSN to be directly used as the etching stop layer for the P-type work function metal layer, eliminating the need for TaN as the etching stop layer. The TaN layer can be removed from the bottom barrier layer at the bottom of the P-type work function metal layer, thereby eliminating the high contact resistance and electromigration problems caused by the TaN layer and improving device reliability. Attached Figure Description
[0046] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0047] Figures 1A-1C This is a schematic diagram of the device structure in each step of the existing first method for manufacturing a metal gate;
[0048] Figures 2A-2C This is a schematic diagram of the device structure in each step of the existing second type of metal gate manufacturing method;
[0049] Figure 3 This is a flowchart of a method for manufacturing a metal grid according to an embodiment of the present invention;
[0050] Figures 4A-4E This is a schematic diagram of the device structure in each step of the manufacturing method of the metal gate according to an embodiment of the present invention. Detailed Implementation
[0051] like Figure 3 The diagram shown is a flowchart of a method for manufacturing a metal grid according to an embodiment of the present invention; as shown Figures 4A to 4E The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the metal gate according to an embodiment of the present invention. The manufacturing method of the metal gate according to an embodiment of the present invention includes the following steps:
[0052] Step S101, as follows Figure 4A As shown, a gate dielectric layer 201 and a TSN layer 202 are sequentially formed on the top surface of a semiconductor substrate (not shown).
[0053] In this embodiment of the invention, the material of the gate dielectric layer 201 includes a high dielectric constant material. Figure 4A In this context, the gate dielectric layer 201 is also represented by HK.
[0054] An interface layer is also formed between the gate dielectric layer 201 and the top surface of the semiconductor substrate. Figure 4A In this context, the structure below the gate dielectric layer 201 is omitted.
[0055] In this embodiment of the invention, a gate trench is formed on the semiconductor substrate. Figure 4A The image shows only the cross-sectional structure within the gate trench in the subsequent first region, i.e., the NMOS formation region.
[0056] The gate trench is formed by removing the dummy gate structure.
[0057] Step S102, as follows Figure 4B As shown, the top surface of the TSN layer 202 is oxidized with ozone, and the oxidized surface layer is marked with 202a.
[0058] Step S103, as follows Figure 4CAs shown, a P-type work function metal layer 203 is formed on the top surface of the TSN layer 202.
[0059] In this embodiment of the invention, the material of the p-type work function metal layer 203 includes TiN. Figure 4C In this context, the P-type work function metal layer 203 is also represented by TiN.
[0060] Step S104, as follows Figure 4D As shown, the first region is opened and wet etching is performed at room temperature to remove the P-type work function metal layer 203 in the first region. The wet etching liquid is SC2 or H2O2. The etching rate of the TSN is reduced by utilizing the characteristics of room temperature and the oxidation treatment of the top surface of the TSN, thereby increasing the etching selectivity of the P-type work function metal layer 203 to the TSN layer 202. The etching selectivity satisfies the requirement that the TSN layer 202 is an etching stop layer, so that the wet etching stops on the TSN layer 202.
[0061] In this embodiment of the invention, the first region is the formation region of NMOS, and the area outside the first region is the formation region of PMOS.
[0062] In some embodiments, the minimum deposition thickness of the TSN layer 202 is The above describes the process. After wet etching, the thickness of the TSN is... above.
[0063] Step S105, as follows Figure 4E As shown, an N-type work function metal layer 204 is formed, which covers the top surface of the TSN in the first region and the top surface of the P-type work function metal layer 203 outside the first region.
[0064] In this embodiment of the invention, the material of the N-type work function metal layer 204 includes TiAl. Figure 4E In this context, the N-type work function metal layer 204 is also represented by TiAl.
[0065] Step S106, as follows Figure 4E As shown, a metallic conductive material layer 206 is formed.
[0066] Before forming the metallic conductive material layer 206, the method further includes:
[0067] A top barrier layer 205 is formed. In some embodiments, the material of the top barrier layer 205 includes TiN. Figure 4E In this context, the top barrier layer 205 is also represented by TBM TiN.
[0068] In this embodiment of the invention, the material of the metal conductive material layer 206 is W. Figure 4E In this embodiment, the conductive metal material layer 206 is also represented by W. In other embodiments, the material of the conductive metal material layer 206 may also be Al.
[0069] The gate structure of the PMOS (not shown) includes a superimposed structure of the gate dielectric layer 201, the TSN layer 202, the P-type work function metal layer 203, the N-type work function metal layer 204 and the metal conductive material layer 206 formed in the gate trench of the formation region of the PMOS.
[0070] The gate structure of the NMOS includes a superimposed structure of the gate dielectric layer 201, the TSN layer 202, the N-type work function metal layer 204, the top barrier layer 205, and the metal conductive material layer 206 formed in the gate trench of the formation region of the NMOS.
[0071] In this embodiment of the invention, after the formation of the TSN layer 202, an oxidation step using ozone is added to the TSN layer 202, and combined with a room temperature setting for wet etching, the etching rate of the TSN layer 202 is reduced. This allows the TSN to be directly used as the etching stop layer of the P-type work function metal layer 203, eliminating the need to use TaN as the etching stop layer of the P-type work function metal layer 203. The TaN layer can be removed from the bottom barrier layer at the bottom of the P-type work function metal layer 203, thereby eliminating the high contact resistance and electromigration problems caused by the TaN layer, and thus improving the reliability of the device.
[0072] In this embodiment of the invention, after the TSN surface is treated with O3, the surface will be oxidized, which will greatly reduce the etching rate (ER) in the subsequent wet etching. By changing the temperature of H2O2 or SC2 from the original high temperature to a low temperature, i.e., room temperature, the selectivity is greatly improved, thereby achieving the effect of etching TiN and keeping it on the TSN. Therefore, in this embodiment of the invention, after DEP of the TSN layer, the surface of the TSN layer is incompletely oxidized with O3 before DEP of TiN. When removing TiN in the subsequent process, the TSN loss is minimized by using a low temperature SC2 (or H2O2) with a higher selectivity.
[0073] Through experiments, we can obtain the following:
[0074] In wet etching for removing the p-type work function metal layer, the etching rates for each material are as follows:
[0075] When wet etching is performed using low-temperature H2O2, the etching rate of TiN is 10.03, the etching rate of TSN without O3 oxidation is 17.60, and the etching rate of TSN with O3 oxidation is 3.04. Therefore, after ozone oxidation, the etching rate of TSN is greatly reduced, and the etching selectivity of TiN for TSN is greatly increased.
[0076] When wet etching is performed using low-temperature SC2, the etching rate of TiN is 14.36, the etching rate of TSN without O3 oxidation is 24.06, and the etching rate of TSN with O3 oxidation is 1.72. Therefore, after ozone oxidation, the etching rate of TSN is greatly reduced, and the etching selectivity of TiN for TSN is greatly increased.
[0077] Furthermore, the thickness of the TSN layer can be obtained through MOSCAP simulation, which simulates the capacitance of the MOS transistor. Tests on the TSN layer thickness under various conditions show that adding O3 in this embodiment reduces the loss of the TSN, and the Vt of the MOS transistor can be adjusted by regulating the thickness of the DEP TSN and the wet etching time. Taking the DEP thickness of the TSN as... For example:
[0078] The remaining thickness of TSN after wet etching, obtained from MOSCAP simulation results, are as follows:
[0079] When wet etching is performed using high-temperature SC2, the remaining thickness of the TSN is
[0080] When wet etching is performed using SC2 at room temperature and the TSN is not oxidized by ozone, the remaining thickness of the TSN is less than
[0081] When wet etching is performed using SC2 at room temperature and the TSN is oxidized by ozone, the remaining thickness of the TSN is approximately This is the remaining thickness of the TSN corresponding to the embodiment of the present invention. Therefore, the embodiment of the present invention can ensure the thickness of the TSN.
[0082] This invention provides a method for manufacturing TaN-free MG structures. Since TaN is absent, TSN is oxidized using O3. To reduce TSN loss, the wet etching solution used in the wet etching process is changed from high temperature to low temperature.
[0083] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A method for manufacturing a metal grid, characterized in that, Includes the following steps: A gate dielectric layer and a TSN layer are sequentially formed on the top surface of a semiconductor substrate; The top surface of the TSN layer is oxidized using ozone. A P-type work function metal layer is formed on the top surface of the TSN layer; The first region is opened and wet etching is performed at room temperature to remove the P-type work function metal layer in the first region. The wet etching liquid is SC2 or H2O2. The etching rate of the TSN is reduced by utilizing the characteristics of room temperature and the oxidation treatment of the top surface of the TSN, thereby increasing the etching selectivity of the P-type work function metal layer to the TSN layer. The etching selectivity satisfies the requirement of the TSN layer as an etching stop layer, so that the wet etching stops on the TSN layer. An N-type work function metal layer is formed, which covers the top surface of the TSN in the first region and the top surface of the P-type work function metal layer outside the first region. A layer of conductive metallic material is formed.
2. The method for manufacturing a metal grid as claimed in claim 1, characterized in that: The material of the P-type work function metal layer includes TiN.
3. The method for manufacturing a metal grid as claimed in claim 2, characterized in that: The first region is the formation region of NMOS, and the area outside the first region is the formation region of PMOS.
4. The method for manufacturing a metal grid as claimed in claim 3, characterized in that: The material of the N-type work function metal layer includes TiAl.
5. The method for manufacturing a metal grid as claimed in claim 1, characterized in that: The minimum deposition thickness of the TSN layer is above.
6. The method for manufacturing a metal grid as claimed in claim 5, characterized in that: After the wet etching, the thickness of the TSN is above.
7. The method for manufacturing a metal grid as claimed in claim 1, characterized in that: Before forming the metallic conductive material layer, the method further includes: A top barrier layer is formed.
8. The method for manufacturing a metal grid as claimed in claim 7, characterized in that: The material of the top barrier layer includes TiN.
9. The method for manufacturing a metal grid as claimed in claim 1, characterized in that: The material of the metallic conductive material layer includes Al or W.
10. The method for manufacturing a metal grid as claimed in claim 1, characterized in that: A gate trench is formed on the semiconductor substrate; The gate structure of the PMOS includes a superimposed structure of the gate dielectric layer, the TSN layer, the P-type work function metal layer, the N-type work function metal layer and the metal conductive material layer formed in the gate trench of the formation region of the PMOS; The gate structure of the NMOS includes a superimposed structure of the gate dielectric layer, the TSN layer, the N-type work function metal layer and the metal conductive material layer formed in the gate trench of the formation region of the NMOS.
11. The method for manufacturing a metal grid as claimed in claim 10, characterized in that: The gate trench is formed by removing the dummy gate structure.
12. The method for manufacturing a metal grid as claimed in claim 1, characterized in that: The material of the gate dielectric layer includes a high dielectric constant material.
13. The method for manufacturing a metal grid as claimed in claim 12, characterized in that: An interface layer is also formed between the gate dielectric layer and the top surface of the semiconductor substrate.