Semiconductor device with graphdiyne as gate dielectric layer and preparation method
By using graphyne material as the gate dielectric layer in semiconductor devices and preparing WS2 channels and graphyne films using dry transfer technology, the application challenges of two-dimensional high-k materials in gate dielectric layers are solved, achieving the effects of reducing gate leakage current and improving device performance.
Patent Information
- Application Number
- CN202411162670.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2026-03-03
AI Technical Summary
The application of existing two-dimensional high-k materials in gate dielectric layers faces challenges such as material preparation, interface engineering, and electrical performance optimization, making it difficult to effectively reduce gate leakage current and improve device switching speed and stability.
Graphdiyne material is used as the gate dielectric layer. Source and drain metal electrodes are formed on a silicon oxide substrate, and a semiconductor WS2 channel is prepared by dry transfer technology. Graphdiyne film is then transferred as the gate dielectric layer, and finally, a gate metal electrode is formed on it.
The high dielectric constant of graphdiyne films effectively reduces gate leakage current, improves the gate control capability and reliability of devices, and enhances device performance.
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Figure CN121604494A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor devices, and more specifically to semiconductor devices using graphyne material as the gate dielectric layer and their preparation methods. Background Technology
[0002] With the continuous development of integrated circuit technology, the requirements for gate dielectric materials are increasing. Two-dimensional high-k materials, due to their unique structure and excellent electrical properties, have become a potential alternative to traditional three-dimensional materials.
[0003] This study investigates two-dimensional high-k gate dielectric layer materials to explore their feasibility as gate dielectrics, aiming to effectively reduce gate leakage current and improve device switching speed and stability while maintaining high capacitance density.
[0004] Currently, research on two-dimensional high-k materials is still in its early stages, but some progress has been made, such as the exploration and application of materials like graphene and two-dimensional transition metal oxides.
[0005] However, its specific application in gate dielectric layers still faces many challenges, such as material preparation, interface engineering, and electrical performance optimization, which require further in-depth research and exploration by researchers.
[0006] Two-dimensional graphdiyne materials have a unique structure and potentially excellent electrical properties. Their application in high-k gate dielectric layers is expected to bring new breakthroughs to the development of integrated circuit technology.
[0007] In view of this, the present invention proposes a semiconductor device with graphyne material as the gate dielectric layer and a method for its preparation. Summary of the Invention
[0008] The purpose of this invention is to address the shortcomings of existing technologies by providing a semiconductor device with a graphdiyne material as the gate dielectric layer and a method for its fabrication.
[0009] To solve the above technical problems, the following technical solution is adopted:
[0010] A semiconductor device structure using graphyne material as the gate dielectric layer includes a silicon oxide substrate, wherein the silicon oxide substrate forms an active drain metal electrode.
[0011] Furthermore, the upper part of the source / drain metal electrodes has a dry-transfer semiconductor WS2 channel.
[0012] Furthermore, a transferred graphyne thin film dielectric layer is present on the upper part of the semiconductor WS2 channel, and a gate metal electrode is formed on the upper part of the graphyne thin film dielectric layer.
[0013] A method for fabricating a semiconductor device with graphdiyne material as the gate dielectric layer includes the following steps.
[0014] S1: Provide a silicon oxide substrate and clean it to obtain a silicon oxide substrate.
[0015] S2: Deposit source and drain metal electrodes using vacuum thermal evaporation equipment.
[0016] S3: Fabrication of semiconductor WS2 channels using a dry transfer platform.
[0017] S4: Transfer graphyne film as gate dielectric layer.
[0018] S5: Deposit gate metal electrodes using vacuum thermal evaporation equipment.
[0019] The above technical solution has the following beneficial effects:
[0020] This invention relates to a semiconductor device and its fabrication method using graphyne material as the gate dielectric layer. Source and drain electrodes are formed on a silicon oxide substrate; a semiconductor channel WS2 layer is formed using a dry transfer technique; a graphyne thin film is grown and fabricated, and then transferred as the gate dielectric layer. By utilizing the high dielectric constant of graphyne material, the gate leakage current is effectively reduced, thereby improving the gate control capability and reliability of the device. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of the semiconductor device structure in which graphdiyne is used as the gate dielectric layer in this invention.
[0022] Figure 2 This is an optical microscope image of the graphdiyne film transferred onto the WS2 semiconductor layer in Example 1.
[0023] Figure 3 The AFM morphology and thickness characterization of the edge of the graphdiyne film after transfer in Example 1 are shown.
[0024] Figure 4 The cyclic transfer characteristic curves and subthreshold characteristics of the graphdiyne gate dielectric layer transistor obtained in Example 1 are shown. Detailed Implementation
[0025] The present invention will be described below with reference to examples, but this does not limit the invention to the scope of the examples.
[0026] A schematic diagram of the semiconductor device using graphylene as the gate dielectric layer in this invention is shown below. Figure 1 As shown, from bottom to top, the layers are: the substrate after the bottom electrode is deposited, the two-dimensional semiconductor nanosheet, the graphdiyne thin film dielectric layer, and the top gate electrode thereon.
[0027] Example 1:
[0028] 1) Clean the 0.5×0.5cm Si / SiO2 substrate with deionized water, ethanol, acetone and isopropanol for 20 minutes each, and then dry the surface with a nitrogen gun.
[0029] 2) Using the laser direct writing method, a source / drain electrode mask with a channel length of 2μm was patterned on the surface of a clean substrate, and a 50nm thick gold bottom electrode was prepared by electron beam evaporation. The mask photoresist was removed by ultrasonic immersion in acetone to obtain a 2μm channel bottom electrode.
[0030] 3) Using 3M Magic Tape, repeatedly stick and peel off a 0.25×0.25cm WS2 two-dimensional crystal block until the WS2 block is peeled off into nanosheets uniformly scattered on the tape surface. Apply PDMS tightly to the tape surface to transfer the WS2 nanosheets to the PDMS surface. Under an optical microscope, align them with the channel of the bottom electrode. Transfer the nanosheets from the PDMS between the source and drain electrodes of the Si / SiO2 substrate by heating, thus creating a semiconductor functional layer.
[0031] 4) Dissolve (NH4)2S2O8 powder in deionized water to prepare an etching solution with a concentration of 0.25 mol / L.
[0032] 5) Cut the copper foil with the graphdiyne film grown on its surface into small pieces of 0.5×0.5cm, and place them on the surface of the etching liquid for about 4 hours until the copper foil substrate is completely removed and the graphdiyne film floats on the surface of the etching liquid. The etching is then complete. After the film is retrieved, it is wet-washed in deionized water.
[0033] 6) Soak in deionized water for a short time and repeat the transfer 2 to 3 times to thoroughly clean the ammonium persulfate solution and residual copper ions after etching.
[0034] Then, the graphdiyne film was lifted from the liquid surface using the Si / SiO2 substrate after WS2 transfer and dried rapidly in an oven for 3 minutes to obtain the graphdiyne gate dielectric layer attached to the WS2 semiconductor layer.
[0035] 7) Under an optical microscope, the mask was aligned perpendicular to the channel semiconductor layer and fixed onto the surface of the graphyne dielectric layer. Then, a 50 nm thick gold electrode was deposited by vacuum evaporation to obtain the top gate electrode. The above preparation yielded a WS2 semiconductor transistor device with graphyne as the gate dielectric layer.
[0036] 8) Use a semiconductor test analyzer to perform scanning tests on the semiconductor device.
[0037] Figure 1 This is a schematic diagram of the semiconductor device structure of the present invention, which uses graphylene as the gate dielectric layer.
[0038] In Example 1, after wet transfer of a graphdiyne film onto the WS2 semiconductor layer, it was observed under an optical microscope, as shown... Figure 2 As shown, a mask is fixed vertically above the semiconductor layer channel for evaporating the top gate electrode.
[0039] Figure 3 The AFM morphology and thickness characterization of the graphdiyne film at the edge transferred to the Si / SiO2 substrate in Example 1 were performed. The thickness of the graphdiyne was measured to be approximately 120 nm.
[0040] The device was tested using a Keithley 4200A semiconductor analyzer at room temperature.
[0041] The device is repeatedly scanned at a low operating voltage of 0.01V, such as... Figure 4 As shown, the device exhibits good repeatability after multiple scans, with a subthreshold swing of 1.1V / dec and an on / off ratio of 12.
[0042] With a threshold voltage of 0.12V, the device has a low operating voltage and turn-on voltage, low power consumption, and is easy to drive.
[0043] Cyclic transfer curve scanning tests demonstrate the switching characteristics of the transistor, indicating that the graphdiyne film, as the gate dielectric layer, plays a role in regulating the channel.
[0044] The dielectric constant of the graphdiyne film was further tested to illustrate its dielectric properties.
[0045] The graphite-diene capacitance per unit area was found to be 0.000802 F / mm² according to LCR testing. 2 The film thickness was obtained by AFM testing, and the dielectric constant was measured to be 11.506 F / m.
[0046] The high dielectric constant obtained proves that the graphdiyne film is a two-dimensional high-k material, suitable for use as a dielectric layer in semiconductor devices.
[0047] Based on the above data, combined with Figure 4 Based on the transfer curve test results shown, the electron mobility of the transistor prepared in Example 1 was calculated to be 1.06 × 10⁻⁶. 2 cm 2 / V·s.
[0048] The above demonstrates that using graphyne thin films as the dielectric layer and two-dimensional semiconductors as the functional layer can fabricate two-dimensional semiconductor devices with high-k dielectric layers, thus expanding the applications of graphyne thin films.
[0049] Example 2:
[0050] 1) Clean the 0.5×0.5cm Si / SiO2 substrate with deionized water, ethanol, acetone and isopropanol for 20 minutes each, and then dry the surface with a nitrogen gun.
[0051] 2) Using the laser direct writing method, a source / drain electrode mask with a channel length of 2μm was patterned on the surface of a clean substrate, and a 50nm thick gold bottom electrode was prepared by electron beam evaporation. The mask photoresist was removed by ultrasonic immersion in acetone to obtain a 2μm channel bottom electrode.
[0052] 3) Using 3M Magic Tape, repeatedly stick and peel off a 0.25×0.25cm long and wide WSe2 two-dimensional crystal block until the WSe2 block is peeled off into nanosheets that are evenly scattered on the surface of the tape.
[0053] WSe2 nanosheets were transferred onto the PDMS surface by attaching PDMS tightly to the tape surface, and then aligned with the channel of the bottom electrode under an optical microscope.
[0054] Nanosheets are transferred from PDMS to the source / drain electrodes of a Si / SiO2 substrate by heating to serve as a semiconductor functional layer.
[0055] 4) Dissolve (NH4)2S2O8 powder in deionized water to prepare an etching solution with a concentration of 0.25 mol / L.
[0056] 5) Cut the copper foil with the graphdiyne film grown on the surface into small pieces of 0.5×0.5cm, and place them on the surface of the etching liquid for about 4 hours until the copper foil substrate is completely removed and the graphdiyne film floats on the surface of the etching liquid. The etching can then be stopped. After the film is taken out, it is wet-washed in deionized water.
[0057] 6) Soak in deionized water for a short time and repeat the transfer 2 to 3 times to thoroughly clean the ammonium persulfate solution and residual copper ions after etching.
[0058] Then, the graphdiyne film was lifted from the liquid surface using the Si / SiO2 substrate after WSe2 transfer and dried rapidly in an oven for 3 minutes to obtain the graphdiyne gate dielectric layer attached to the WSe2 semiconductor layer.
[0059] 7) Under an optical microscope, the mask was aligned perpendicular to the channel semiconductor layer and fixed onto the surface of the graphyne dielectric layer. Then, a 50 nm thick gold electrode was deposited by vacuum evaporation to obtain the top gate electrode. The above preparation yielded a WSe2 semiconductor transistor device with graphyne as the gate dielectric layer.
[0060] 8) Use a semiconductor test analyzer to perform scanning tests on the semiconductor device.
[0061] Matters not covered in this invention are common knowledge.
Claims
1. A semiconductor device using graphylene as the gate dielectric layer, characterized by a top-gate structure, comprising, from top to bottom, a gate electrode, a dielectric layer, a semiconductor layer, and a substrate; in, The gate electrode is a vapor-deposited metal electrode with a thickness of approximately 50 nm. The dielectric layer is a high-k graphdiyne film. The semiconductor layer is a two-dimensional semiconductor nanosheet. The substrate is a rigid substrate such as a glass sheet or a silicon oxide wafer, or a flexible substrate.
2. The semiconductor device with graphdiyne as the dielectric layer as described in claim 1, characterized in that the gate dielectric layer is a graphdiyne thin film with a thickness of 80nm~140nm.
3. The semiconductor device using graphdiyne as the dielectric layer as described in claim 1, characterized in that: The method includes the following steps: 1) Clean the substrate with deionized water, ethanol, acetone and isopropanol for 20 minutes each, and blow the surface dry with a nitrogen gun to complete the substrate pretreatment. 2) Microchannel bottom electrodes are fabricated on a substrate using laser direct writing and electron beam evaporation. The electrodes are approximately 30-50 nm thick and uniformly spaced. The metal used can be gold, silver, aluminum, etc. 3) The two-dimensional semiconductor bulk material was repeatedly peeled apart using 3M Magic Tape, and a mechanical peeling method was used to separate the two-dimensional bulk material into nanosheets. The nanosheets on the tape were transferred onto PDMS, and the appropriately sized nanosheets were aligned with the bottom electrode channel under an optical microscope. After heating for 8 minutes, the nanosheets were transferred from PDMS to the space between the source and drain electrodes of the substrate, covering the channel and serving as a semiconductor functional layer; Two-dimensional semiconductors can be transition chalcogenides, etc. 4) Use wet etching to etch the copper foil substrate under the graphdiyne film, so that the graphdiyne film is peeled off from the copper foil and floats on the liquid surface; The etching liquid used was ammonium persulfate ((NH4)2S2O8) solution with a concentration of 0.1~0.3 mol / L. The etching time was approximately 4 hours, continuing until the copper foil substrate was completely etched and the graphdiyne film was self-supporting on the liquid surface, at which point the etching process was complete. 5) Clean the etched graphdiyne film; transfer the etched graphdiyne film from the liquid surface to deionized water, transfer and soak for a short time several times to completely remove the residual etching solution from the film. Remove the cleaned graphdiyne film from the liquid surface onto the pretreated substrate surface and quickly dry it to complete the wet transfer of the graphdiyne film. 6) Position the mask perpendicular to the channel and fix it in place. Vacuum-deposit a 50-nanometer-thick metal top gate onto the surface of the graphdiyne film obtained in step 5). This yields a semiconductor transistor device with a top gate structure and a graphdiyne dielectric layer.