Reverse conducting IGBT with electron blocking layer

Abstract

The invention discloses a reverse conducting IGBT with an electron blocking layer. An apparatus and related methods for reverse conducting insulated gate bipolar transistors and related structures. The device includes a substrate disposed between a front surface and a back surface, a diode pilot region disposed in the substrate, an insulated gate bipolar transistor (IGBT) region disposed in the substrate, and a diode region having a barrier layer disposed adjacent to and between each of the diode pilot region and the IGBT region. The barrier layer is configured to prevent electron flow at a first predetermined current and to allow electron flow at a second predetermined current.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor devices, particularly the manufacture of semiconductor devices, and even more specifically to reverse-conducting insulated-gate bipolar transistors. Background Technology

[0002] An insulated-gate bipolar transistor (IGBT) is a three-terminal power semiconductor device used as a highly efficient, fast electronic switch. It comprises four alternating layers (PNPN) controlled using a metal-oxide-semiconductor (MOS) gate structure. In most applications, IGBTs are used in conjunction with a fast anti-parallel diode to allow inductive load current to flow freely. In the case of a reverse-conducting IGBT (RC-IGBT), the diode is integrated into the IGBT structure. Typical operating states of an RC-IGBT include forward conduction (IGBT mode turn-on), reverse conduction (diode mode turn-on), forward turn-on (IGBT mode turn-on), forward turn-off (IGBT mode turn-off), and reverse recovery (diode mode reverse recovery). However, existing RC-IGBT-based devices often suffer from bounce-back issues. While these problems can often be addressed by incorporating a separate diode pilot region into the structure, adding one or more such pilot regions reduces the uniformity of RC-IGBT operation, thereby degrading overall performance. Summary of the Invention

[0003] The following overview is provided in a simplified form to introduce a series of concepts, which will be further described in the detailed description below. This overview is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0004] In some embodiments, the present subject matter relates to a semiconductor device. The device may include a substrate disposed between a front side and a back side, a diode pilot region disposed in the substrate, an insulated-gate bipolar transistor (IGBT) region disposed in the substrate, and a diode region having a barrier layer disposed adjacent to and between each of the diode pilot region and the IGBT region. The barrier layer may be configured to prevent electron flow under a first predetermined current and allow electron flow under a second predetermined current.

[0005] In some embodiments, the present subject matter relates to a method for manufacturing a semiconductor device. The method may include providing a substrate and forming at least one front structure and at least one back structure on the substrate, forming a diode pilot region in the substrate, forming an insulated-gate bipolar transistor (IGBT) region in the substrate, and forming a diode region with a barrier layer adjacent to and between each of the diode pilot region and the IGBT region. The barrier layer may be configured to prevent electron flow under a first predetermined current and allow electron flow under a second predetermined current. The method may further include forming a collector layer and a diode cathode layer in the substrate, which may include forming a first portion of the collector layer adjacent to the IGBT region, forming a first portion of the diode cathode layer adjacent to the diode pilot region, and forming a second portion of the collector layer and a second portion of the diode cathode layer below the diode region with the barrier layer, wherein the second portion of the collector layer is formed adjacent to the second portion of the diode cathode layer. The method may further include forming a buffer layer above the diode cathode layer and the collector layer and adjacent to the diode pilot region, the barrier layer, and the IGBT region.

[0006] In some implementations, the current topic may include one or more optional features, as described herein.

[0007] Details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the specification, the accompanying drawings, and the claims. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the specification, help explain some principles associated with the disclosed embodiments. In the drawings,

[0009] Figure 1A Examples of semiconductor devices according to some embodiments of the present topic are shown;

[0010] Figure 1B Another example of a semiconductor device according to some embodiments of the present topic is shown;

[0011] Figure 1C Examples of one or more back-diffusion embodiments of some implementations according to the current topic are shown, and

[0012] Figure 2 Example processes for manufacturing semiconductor devices, such as reverse-conducting insulated-gate bipolar transistors (RC-IGBTs), are shown according to some embodiments of the present topic. Detailed Implementation

[0013] Various methods according to this disclosure will be described more fully below with reference to the accompanying drawings, which illustrate embodiments of the systems and methods. Apparatus, one or more systems, one or more components, etc., may be embodied in many different forms and should not be construed as limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present subject matter to those skilled in the art.

[0014] To address these and other potential shortcomings of currently available solutions, one or more embodiments of the present subject matter relate to methods, systems, articles of manufacture, etc., which, among other possible advantages, can provide systems and methods for manufacturing semiconductor devices, particularly for manufacturing reverse-conducting insulated-gate bipolar transistors (RC IGBTs).

[0015] The reverse-conducting insulated-gate bipolar transistor (RCIGBT) is an advanced power semiconductor device that combines the properties of an insulated-gate bipolar transistor (IGBT) and a diode on a single chip. As described above, an IGBT comprises four alternating P, N layers controlled by a MOS gate structure. The IGBT cell has a structure similar to an n-channel vertically constructed power MOSFET; however, the n+ drain is replaced by a p+ collector layer, forming a vertical PNP bipolar junction transistor. The p+ region creates a cascaded connection between the PNP bipolar junction transistor and the surface-mount n-channel MOSFET. The IGBT structure is also similar to a MOS gate thyristor; however, thyristor operation is suppressed, and only transistor operation is allowed throughout the entire device operating range. IGBTs are designed to synthesize complex waveforms with pulse width modulation and low-pass filtering and can be used in switching amplifiers (e.g., motor control, multilevel inverters, industrial control systems, etc.) and / or any other devices, systems, etc. The integration of IGBTs and diodes allows for both forward and reverse conduction, making RC-IGBTs suitable for applications that may require bidirectional current flow (e.g., inverters for electric vehicles and / or industrial drives).

[0016] RC-IGBTs can handle various operating states, including forward conduction (IGBT mode), reverse conduction (diode mode), forward turn-on (turn-on mode), forward turn-off (turn-off mode), and diode reverse recovery (reverse recovery mode). In operation, the RC-IGBT functions by controlling the flow of electrons and holes within its layered semiconductor structure. When a positive voltage is applied to the gate, it turns on the MOSFET, allowing the collector voltage to drive base current through the bipolar transistor. This, in turn, activates the bipolar transistor, allowing load current to flow. This is known as IGBT mode. When a negative voltage is applied to the collector, the N-type layer acts as the diode cathode, and the p-type body diffusion of the MOSFET acts as the diode anode. This is known as diode mode, during which reverse conduction occurs.

[0017] Unlike power MOSFETs, IGBTs do not naturally conduct in reverse due to the PN junction on the collector side. In the case of MOSFETs, the body diode can conduct without being suppressed by the P-type diffusion on the back side. This means that in some IGBT applications, IGBTs can be used with a separate fast recovery anti-parallel diode, where the two chips are typically assembled in the same package.

[0018] As described above, in an RC-IGBT, the IGBT and diode are integrated on the same chip. This is achieved by adding N-type diffusion regions to the back side of the chip. These N+ regions then act as the cathodes of the diode regions. Elsewhere, the back side of the chip has p-type diffusion that serves as the collector of the IGBT.

[0019] One advantage of RC-IGBTs is that only one chip type is needed to perform the functions of forward current control (IGBT section) and allowing reverse current conduction (diode section). This makes the solution simpler and less expensive. Furthermore, the current distribution is more uniform, resulting in lower peak current density and a more uniform temperature distribution.

[0020] To achieve uniform current distribution, existing IGBT and diode regions are typically tightly integrated within the active region of the chip. Since the IGBT and diode regions are not electrically isolated from each other, undesirable interactions can occur between these regions during operation. Specifically, during the IGBT turn-on phase, a portion of the MOSFET's electronic current shifts from the back-side P-type collector region to the N-type cathode region, effectively creating a "short circuit." This loss of electronic current flowing to the cathode has a minimal impact when the IGBT region is fully on. However, at low currents, this shift of electronic current in a conventional RC-IGBT can delay hole injection from the P-type IGBT collector, thus suppressing IGBT operation and causing a bounce characteristic in the turn-on IV curve. This is undesirable and can lead to unstable current sharing during the IGBT turn-on phase.

[0021] IGBT bounce refers to the sudden drop in voltage across the IGBT after initially experiencing high voltage, while conducting current. This is similar to the bounce observed in thyristors and is characterized by the negative differential resistance region in the IGBT's output characteristics. During bounce, the IGBT transitions from a high-voltage, high-impedance state to a low-voltage, low-impedance state, allowing it to conduct large currents without experiencing a large voltage drop. In some cases, bounce (i.e., in the RC-IGBT current-voltage (IV) curve) may occur at low voltages (opposite to high voltages) and may lead to uneven device turn-on.

[0022] To overcome this undesirable bounce characteristic, existing devices typically incorporate an "IGBT pilot" region into the RC-IGBT design. This is one or more regions in the larger IGBT area that lack an n-type collector. This region then exhibits a smooth turn-on that extends into the standard RC-IGBT region. The entire RC-IGBT T1-V curve now has a smooth characteristic. However, adding one or more "pilot" regions reduces the uniformity of RC-IGBT operation. Even when fully turned on, the "pilot" region will operate at a higher current density because there is no N-type short circuit there. This non-uniformity limits the overall performance and rating of conventional RC-IGBTs.

[0023] To address these issues, in some embodiments, the present subject relates to semiconductor devices and methods of fabrication thereof. A semiconductor device may include an IGBT region, a diode pilot region, and a diode region disposed between the IGBT region and the diode pilot region, having an electron blocking region (hereinafter referred to as a "blocking region"). The blocking region may be an electron blocking region and may be configured to limit the collection of electrons by the N-type cathode region of the semiconductor device at low currents, which can help reduce and / or prevent backflow problems without requiring the IGBT pilot. The blocking region may be a P-type layer that can cover most of the N-type cathode region. These regions can create a barrier to electrons at low IGBT currents. A small portion of each N-type cathode may remain open to allow diode operation (otherwise, diode operation may be difficult to initiate at voltage reversal). This portion is referred to herein as the "diode pilot" region. The diode pilot region may be made small enough and far enough away from the IGBT region that the IGBT region has no (and / or substantially no) backflow problems. The hole blocking layer may be lightly doped so that it is effectively transparent to carrier flow at high currents.

[0024] Figure 1A Examples of semiconductor devices 100 according to some embodiments of the present subject are shown. Device 100 may be configured as a reverse-conducting insulated-gate bipolar transistor (RC-IGBT) semiconductor device. The RC-IGBT device 100 may include one or more MOS structures 102, an N-type layer 104, a diode pilot region 106, a blocking diode region 108, an IGBT region 110, an N-type buffer layer 112, a first N+ layer 114a, a second N+ layer 114b, a p-type blocking layer 126, a p-type collector layer 116, a diode cathode 118, an IGBT collector 120, and a contact metal layer 154 located on the back surface 124 of the device 100. Figure 1A The arrangement shown represents a section passing through a portion of the active region of a semiconductor device. The active region may include one or more such sections. Furthermore, the active region may be terminated by one or more guard rings, one or more JTEs, etc. In some example, non-limiting embodiments, the rated voltage of device 100 may be between 600 volts and 6500 volts.

[0025] The N-type layer 104 may be a substrate and / or a silicon wafer, which may be disposed between the front side 122 and the back side 124 of the device 100. It may be configured to accommodate the formation of one or more of the following through various diffusion and / or other semiconductor manufacturing techniques: diode pilot region 106, diode region 108 with a barrier, IGBT region 110, N-type buffer layer 112, N+ layer 114a, N+ layer 114b, P-type barrier layer 126, and P-type collector 116.

[0026] One or more MOS structures 102 may represent the front side 122 of the RC-IGBT device 100 and may include the emitter of the device 100, one or more gate contacts, and an array of MOSFET structures in one or more active regions, which may include, but are not limited to, trenches, planes, etc., having one or more varying geometries. One or more structures 102 may also include one or more termination structures (e.g., guard rings, junction termination extensions (JTEs)). As will be understood, any other front-side components may be included in one or more MOS structures 102.

[0027] The diode cathode 118 and IGBT collector 120 (both can be and / or can form continuous metal layers, rather than separate contacts) can be configured to be disposed on the back side 124 and / or substrate and / or wafer of one or more MOS structures 102. Specifically, the back side 124 of the device 100 can be arranged to align with a suitable front side region of the device 100. The IGBT region 110 can be defined by the location of the diffusion of the collector 116. One or more diode regions can be defined similarly. Although... Figure 1A The alignment of various regions is illustrated schematically, but it should be understood that there is no requirement to align the back layer with these regions. In some embodiments, back diffusion can be used to define the diode pilot region 106, the blocking diode region 108, and the IGBT region 110, which can be positioned relative to one or more corresponding active MOS structures 102. It is understood that... Figure 1A The alignment shown may or may not be aligned with a specific MOSFET cell of one or more MOS structures 102. In some example, non-limiting embodiments, alignment may be used to provide better performance of the semiconductor device 100. Figure 1A As shown, the diode cathode 118 can be aligned with regions 106 and 108. This region can be precisely aligned with the pattern on the front side 122 (i.e., IGBT region 110, the diode region 108 with obstruction, and the diode pilot region 106), or it can be imprecisely aligned.

[0028] For the purpose of forming the aforementioned regions, various options exist for implementing one or more back-side diffusions 124. For example, one option could be to perform a uniform P-type implantation and annealing to form the IGBT collector 120. Subsequently, two higher-concentration cathode mask implantations and anneals can be performed to form diode regions beneath N+ layers 114a and 114b: one can be deeper than the P-type layers, and the other can be shallower. The shallower N+ cathode annealing can be controlled to leave a P-type blocking layer, which can be configured to block electrons at low currents but not at high currents. Furthermore, different patterns can be used for back-side diffusion. For example, one pattern could include an array of circular diode regions, each with a diode pilot at its center. This geometry allows the diode pilot to be located away from the IGBT but has a minimal total diode pilot area.

[0029] Figure 1C Examples of one or more backside 124 diffusion embodiments according to some implementations of the current topic are shown. For example... Figure 1C As shown, the IGBT region 110 may include one or more regions 108 and one or more diode pilot regions 106. The diffusion of regions 106 and / or 108 can be set at any desired location / position on the back surface 124. As will be understood, the subject matter is not limited to the arrangement of regions 106 and / or 108 shown, and any other arrangement of the back surface 124 is possible.

[0030] like Figure 1A As shown, an N-type layer 104 may be disposed and / or formed between a front side 122 (as shown in one or more MOS structures 102) and a back side 124 (as shown in a diode cathode 118 and an IGBT collector 120). Alternatively or additionally, an N-type layer 104 may be provided, and various layers, regions, etc., including the front side 122 and / or the back side 124, may be formed therein and / or on it. It is understood that any order in which the various layers, regions, etc., of the device 100 are formed is permissible.

[0031] The N-type layer 104 may include a diode pilot region 106, a blocking diode region 108, and an IGBT region 110. Each of these regions may be formed substantially vertically ( wholly and / or at least partially) between the front side 122 and the back side 124 of the device 100. The blocking diode region 108 may be disposed between the diode pilot region 106 and the IGBT region 110.

[0032] The diode pilot region 106 can be positioned away from the IGBT region 110. It can be used to perform diode operation of the RC-IGBT device 100. In an RC-IGBT, the diode pilot region 106 can be forward biased and allows diode current to flow when reverse biased. The unidirectional behavior of the diode pilot region 106 is due to its diode-like structure (e.g., a pn junction), which facilitates electron flow from the n-type material to the p-type material when forward biased. In reverse bias, the junction impedes current flow except for minimal leakage. The diode pilot region 106 can be designed to be small enough and / or far enough away from the IGBT region 110 to keep the IGBT region 110 substantially free of snapback.

[0033] In some embodiments, the blocking diode region 108 may be configured to span (and / or cover) one or more substantially cathode regions, such as the N+ layer 114b. The blocking diode region 108 may include a P-type electron blocking layer 126 disposed above the N+ layer 114b. This can serve as a barrier to electron movement at low currents occurring in the IGBT region 110. The diode blocking region 126 may be lightly doped such that it can be configured to be substantially "transparent" to carrier flow at high currents (e.g., doping the blocking diode region 108 may allow for uniformity of high diode current operation between the diode pilot region 106 and the blocking diode region 108). In some embodiments, the open-circuit diode pilot region may be configured to be large enough to avoid bounce in the diode conduction IV curve, while being configured to be small enough to avoid (or minimize) bounce in the IGBT conduction IV curve. Advantageously, the blocking region 126 may be configured to prevent latch-up problems in the device 100.

[0034] An N-type buffer layer 112 can be disposed between the back surface 124 (particularly the p-type collector 116, N+ layers 114a and 114b) and regions 106-110. The N-type buffer layer 112 can be disposed above the p-type collector 116, N+ layers 114a and 114b. This layer 112 can be configured to protect the IGBT collector 120 during the off-state by preventing electric field penetration. It can also be used to reduce the overall width of the RC-IGBT device 100. In some example embodiments, the N-type buffer layer 112 can be formed across all regions 106-110, such as... Figure 1AAs shown. Alternatively or additionally, the N-type buffer layer 112 may be formed across some and / or portions of one or more regions 106-110. Furthermore, in some example, non-limiting embodiments, the N-type buffer layer 112 may have a substantially uniform width across the device 100 (i.e., below regions 106-110). Alternatively or additionally, layer 112 may have a substantially uniform width below the diode having the blocking region 108 and the IGBT region 110, and a smaller width below the diode pilot region 106. The smaller width of the N-type buffer layer 112 below the diode pilot region 106 compared to the N+ layer 114b allows for a larger N+ layer 114a. This can allow diode operation to occur when the voltage across the device 100 is reversed. In some example, non-limiting embodiments, the buffer layer 112 may be optional, for example, it may be removed. In this case, the width of the device 100 can be configured to be larger to, for example, prevent electric field penetration into the IGBT collector layer 116.

[0035] The p-type collector 116 may be disposed and / or formed (e.g., through p-diffusion in the N-type layer 104) below the N-type buffer layer 112 and above contacts 118 and 120 disposed and / or formed in the back surface 124 of the RC-IGBT device 100. At least a portion of the p-type collector 116 may be disposed across the IGBT collector 120, and a p-type blocking layer 126 of the p-type collector 116 may be disposed in a blocking diode region 108 and above the N+ layer 114b, which is part of the diode cathode 118. In some exemplary, non-limiting embodiments, for example, as Figure 1A As shown, the device 100 can be configured to include a p-type barrier layer 126, which can be uniformly distributed on the back side of the wafer. In the IGBT region, it can be diffused, and in the diode region with the barrier, it can be partially overdoped with a shallower N+ layer 114b, leaving a thin p-type barrier layer 126. In the pilot region, it may be completely overdoped with a deeper N+ layer 114a.

[0036] As shown in N+ layers 114a and 114b, the diode cathode layer (formed above the diode cathode 118) can be an N+ layer, which can be formed below the diode pilot region 106 and the blocking diode region 108. To allow diode operation, N+ layer 114a can be formed wider than N+ layer 114b. Specifically, the wider (and / or thicker and / or deeper) portion of the diode cathode layer—N+ layer 114a—can be formed below the diode pilot region 106. The narrower portion of the diode cathode layer—N+ layer 114b—can be formed below the p-type blocking layer 126. The arrangement of the p-type blocking layer 126 and N+ layer 114b can be configured to block electrons at low currents but allow them to pass through at higher currents. In some cases, N+ layer 114a can be made wider / thicker / deeper to provide full overdoping of the p-type blocking layer 126.

[0037] Compared to existing solutions, the structural composition of the RC-IGBT device 100 offers several technical advantages. Specifically, by including a blocking diode region 108 between the diode pilot region 106 and the IGBT region 110, the RC-IGBT device 100 can be configured to substantially eliminate IGBT bounce (i.e., the sudden drop in voltage across the IGBT after initially experiencing a high voltage, while conducting a high current). Furthermore, the RC-IGBT device 100 eliminates the need for the IGBT pilot region typically present in conventional semiconductor devices. Additionally, the use of region 108 ensures smoother integration of the diode and IGBT portions of the device 100. The structural composition of the device 100 can provide more uniform IGBT current and heat distribution during operation.

[0038] Figure 1B Another semiconductor device 150 according to some embodiments of the present topic is shown. Device 150 can be configured as similar to Figure 1A The semiconductor device 100 shown is an RC-IGBT semiconductor device. Similar to device 100, device 150 may include one or more MOS structures 102, an N-type layer 104, a diode pilot region 106, a diode region 108 with a barrier, an IGBT region 110, an N-type buffer layer 112, a p-type collector 116, a diode cathode 118, and an IGBT collector 120. Furthermore, device 150 may be configured to include a first N+ layer 146a, a second N+ layer 146b, a p-type barrier layer 148, and a contact metal layer 154. In addition to the formation of layers suitable for device 150, the N-type layer 104 may also be configured to be formed using various diffusion and / or any other semiconductor manufacturing techniques to accommodate the formation of the N+ layer 146a, N+ layer 146b, and p-type barrier layer 148. The contact metal layer 154 may be positioned on the back layer 104. The rated voltage of device 150 may be similar to... Figure 1AThe rated voltage of the device 100 shown.

[0039] like Figure 1B As shown, the N+ layer 146a can be disposed in the diode pilot region 106, and its depth / width / thickness can be substantially equal to the depth / width / thickness of the P-type collector layer 116. A P-type blocking layer 148 can be disposed above the N+ layer 146b, wherein the combined depth / width / thickness of the P-type blocking layer 148 and the N+ layer 146b can be substantially equal to the depth / width / thickness of the P-type collector layer 116. It is understood that these layers can have their own depth / width / thickness, and they do not necessarily have to be equal.

[0040] and Figure 1A Similar to the illustrated device 100, the diode portion of device 150 may consist of two regions—a diode pilot region 106 and a blocking diode region 108. The diode pilot region 106 may be configured to initiate current flow, and the blocking diode region 108 (which may include a P-type blocking layer 148 and an N+ layer 146b) may initiate operation upon reaching a predetermined current level (which may be defined according to the desired operating characteristics of device 150). In some embodiments, the predetermined current level may also depend on the width / thickness / depth of the diode pilot region 106 and the blocking diode region 108. In some example, non-limiting embodiments, the concentration of the N-type buffer layer 112 may also affect the predetermined current level. Device 150 is operated using the predetermined current level (and...). Figure 1A The device 100 shown can be configured to avoid device 150 (and / or Figure 1A The diode IV curve of the device 100 shown in the diagram shows a bounce (or small bounce).

[0041] In some examples and implementations, the p-type barrier layer 148 may also affect the predetermined current level, thereby affecting the operation of device 150. If layer 148 is too wide / too deep / too thick and / or heavily doped, the predetermined current level may be too high, preventing layer 148 from acting as a barrier to electrons during operation of device 150. Greater width / depth / thickness and / or doping of layer 148 may also trigger latch-up. Figure 1A and 1B Some examples of configurations of a semiconductor device including a blocking diode region (e.g., region 108) are shown. It will be understood that any other configuration of the semiconductor device is possible.

[0042] Figure 2 An example process 200 for manufacturing semiconductor devices, such as reverse-conducting insulated-gate bipolar transistors (RC-IGBTs), according to some embodiments of the present topic is shown. Process 200 can be used to manufacture... Figure 1AThe RC-IGBT device 100 is shown. It is understood that the operation of process 200 can be performed in any desired order, wherein one or more of the operations can be optional.

[0043] At position 202, a substrate (e.g., N-type layer 104) may be provided. One or more front-side structures (e.g., front-side 122) and / or back-side structures (e.g., back-side 124) may be formed in and / or on the substrate. The front-side may include one or more metal-oxide-semiconductor field-effect transistor (MOSFET) structures. The one or more MOSFET structures may include at least one of the following: emitter, gate, gate oxide, trench structure, planar structure, active structure, termination, guard ring, junction termination extension, and any combination thereof. The back-side may include a collector and / or a diode cathode. The collector may be disposed adjacent to the diode cathode.

[0044] At 204, a diode region (e.g., diode pilot region 106) can be formed in the substrate.

[0045] At 206, an insulated gate bipolar transistor (IGBT) region (e.g., IGBT region 110) can be formed in the substrate.

[0046] At 208, a barrier layer (e.g., a diode region 108 with a barrier) may be formed adjacent to and between each of the diode pilot region (e.g., diode pilot region 106) and the insulated gate bipolar transistor region (e.g., IGBT region 110). The barrier layer 126 may be configured to prevent electron flow under a first predetermined current (e.g., low IGBT current) and allow electron flow under a second predetermined current (e.g., high IGBT current). The barrier layer may be a p-type layer. Advantageously, the barrier layer may be configured to prevent latch-up.

[0047] At 210, a collector layer (e.g., p-type collector 116) and a diode cathode layer (e.g., represented by N+ layers 114a and 114b) may be formed in the substrate. The formation of the collector and diode cathode layers may include one or more of the following: At 212, a first portion of the collector layer may be formed below the IGBT region. At 214, a first portion of the diode cathode layer (e.g., N+ layer 114a) may be formed below the diode region (e.g., diode pilot region 106). At 216, a second portion of the collector layer (e.g., p-type blocking layer 126) and a second portion of the diode cathode layer (e.g., N+ layer 114b) may be adjacent to the blocking region (e.g., diode region 108 with blocking) (e.g., as shown in the image). Figure 1A-B is formed below it. The second portion of the collector layer (e.g., p-type barrier layer 126) may be adjacent to the second portion of the diode cathode layer (e.g., N+ layer 114b) (e.g., as shown below). Figure 1A -B is formed above it. Furthermore, the first portion of the collector layer can be disposed adjacent to the collector (e.g., as shown in Figure B). Figure 1A -B is shown above it), and the first portion of the diode cathode layer can be disposed adjacent to the diode cathode (as shown in Figure B). Figure 1A-1B As shown, above it). The collector layer can be a p-type collector layer, and the diode cathode layer can be an N+ type diode cathode layer.

[0048] At 218, a buffer layer (e.g., N-type buffer layer 112) may be formed above the diode cathode layer (e.g., p-type collector 116) and the collector layer (e.g., N+ layer 114a and N+ layer 114b) and below the diode region, the blocking layer and the IGBT region.

[0049] The components and features of the aforementioned devices can be implemented using any combination of discrete circuits, application-specific integrated circuits (ASICs), logic gates, and / or single-chip architectures. Furthermore, where appropriate, microcontrollers, programmable logic arrays, and / or microprocessors, or any combination thereof, can be used to implement the features of the devices. It should be noted that hardware, firmware, and / or software elements may be collectively referred to herein or individually as “logic” or “circuit”.

[0050] It should be understood that the exemplary device shown in the above block diagrams may represent a functional description example of many potential implementations. Therefore, the division, omission, or inclusion of block functions shown in the figures does not necessarily mean that hardware components, circuits, software, and / or elements used to implement these functions will be divided, omitted, or included in the embodiments.

[0051] Some embodiments may be described using the terms "one embodiment" or "embodiment," "implementation," or "some implementations," and their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. The phrase "in one embodiment" (or its derivatives) appearing in various places in the specification does not necessarily refer to the same embodiment. Furthermore, unless otherwise stated, the foregoing features are considered to be used in any combination. Thus, any feature discussed individually may be used in combination with each other unless it is noted that these features are incompatible with each other.

[0052] It should be emphasized that the abstract of this disclosure is provided to allow the reader to quickly determine the nature of the technical disclosure. The premise of this document is that it should not be used to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen from the above detailed description, various features are combined together in a single embodiment for the purpose of simplifying this disclosure. This method of disclosure should not be construed as reflecting an intention that the claimed embodiment requires more features than expressly referenced in each claim. Rather, as reflected in the following claims, the inventive subject matter lies in the fact that a single disclosed embodiment has fewer features than all features. Therefore, the following claims are hereby incorporated into the detailed description, wherein each claim stands independently as a separate embodiment. In the appended claims, the terms “comprising” and “therein” are used accordingly as plain English equivalents of the corresponding terms “including” and “wherein”. Furthermore, the terms “first,” “second,” “third,” etc., are used only as labels and are not intended to impose numerical requirements on their objects. Additionally, the terms “comprising,” “including,” or “having,” and variations thereof, as used herein, mean including the items listed below and their equivalents, as well as additional items. Therefore, the terms “comprising,” “including,” or “having,” and variations thereof are open-ended expressions and can be used interchangeably herein.

[0053] For convenience and clarity, terms such as “top,” “bottom,” “upper,” “lower,” “vertical,” “horizontal,” “lateral,” “transverse,” “radial,” “inner,” “outer,” “left,” and “right” may be used herein to describe the relative position and orientation of features and components, each term relating to the geometry and orientation of other features and components appearing in the perspective views, exploded perspective views, and cross-sectional views provided herein. The terms are not intended to be limiting and include words specifically mentioned, derivative words therein, and words with similar meanings.

[0054] The foregoing description includes examples of the disclosed architecture. It is certainly impossible to describe every conceivable combination of components and / or methods, but those skilled in the art will recognize that many other combinations and permutations are possible. Therefore, the novel architecture is intended to cover all such changes, modifications, and variations falling within the spirit and scope of the appended claims.

[0055] In one aspect, the semiconductor device may include a substrate disposed between a front side and a back side; a diode pilot region disposed in the substrate; an insulated gate bipolar transistor (IGBT) region disposed in the substrate; and a diode region having a barrier layer disposed adjacent to and between each of the diode pilot region and the IGBT region, wherein the barrier layer is configured to prevent electron flow under a first predetermined current and allow electron flow under a second predetermined current.

[0056] The device may include a barrier layer that is a p-type layer.

[0057] The device may include a first predetermined current, which is a low IGBT current.

[0058] The device may include a second predetermined current, which is a high IGBT current.

[0059] The device may include at least one of the first and second predetermined currents as a diode current.

[0060] The device may include one or more metal-oxide-semiconductor field-effect transistor (MOSFET) structures on its front side.

[0061] The device may include one or more MOSFET structures including at least one of the following: emitter, gate, gate oxide, trench structure, planar structure, active structure, termination, guard ring, junction termination extension, and any combination thereof.

[0062] The device may include a collector and a diode cathode on its back side.

[0063] The device may include a collector disposed adjacent to the cathode of a diode.

[0064] The device may include a collector layer and a diode cathode layer, wherein a first portion of the collector layer is disposed adjacent to the collector, and a first portion of the diode cathode layer is disposed adjacent to the diode cathode.

[0065] The device may include a collector layer and a diode cathode layer coupled using a contact metal layer.

[0066] The device may include a p-type collector layer.

[0067] The device may include an N+ type diode cathode layer.

[0068] The device may include a first portion of the collector layer disposed adjacent to the IGBT region.

[0069] The device may include a first portion of the diode cathode layer disposed adjacent to the diode region.

[0070] The device may include a second portion of the collector layer and a second portion of the diode cathode layer disposed adjacent to a diode region having a blocking layer.

[0071] The device may include a barrier layer formed in the collector layer.

[0072] The device may include a barrier layer that is separate from the collector layer.

[0073] The device may include a second portion of the collector layer disposed adjacent to a second portion of the diode cathode layer.

[0074] The device may include a buffer layer disposed above the diode cathode layer and collector layer and below the substrate.

[0075] The device may include a semiconductor device that is a reverse-conducting insulated-gate bipolar transistor.

[0076] In one aspect, a method for manufacturing a semiconductor device may include providing a substrate and forming at least one front structure and at least one back structure on the substrate; forming a diode pilot region in the substrate; forming an insulated gate bipolar transistor (IGBT) region in the substrate; forming a diode region with a barrier layer adjacent to and between each of the diode pilot region and the IGBT region, wherein the barrier layer is configured to prevent electron flow under a first predetermined current and allow electron flow under a second predetermined current; forming a collector layer and a diode cathode layer in the substrate, the formation including forming a first portion of a collector layer formed adjacent to the IGBT region, forming a first portion of a diode cathode layer adjacent to the diode pilot region, and forming a second portion of a collector layer and a second portion of a diode cathode layer below the diode region with the barrier layer, wherein the second portion of the collector layer is formed adjacent to the second portion of the diode cathode layer; and forming a buffer layer above the diode cathode layer and the collector layer and adjacent to the diode pilot region, the barrier layer, and the IGBT region.

[0077] The above description of exemplary embodiments has been given for purposes of illustration and description. It is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. Many modifications and variations are possible in view of this disclosure. It is intended that the scope of this disclosure be limited not by this detailed description, but by the appended claims. A future application claiming priority to this application may claim the disclosed subject matter in different ways and may generally include any one or more sets of limitations that are not disclosed herein or otherwise demonstrated.

[0078] All directional references (e.g., proximal, distal, upper, lower, upward, downward, left, right, lateral, longitudinal, front, rear, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are used for identification purposes only to aid the reader's understanding of this disclosure and do not constitute a limitation, particularly regarding the location, orientation, or use of this disclosure. Unless otherwise stated, connection references (e.g., attachment, coupling, connection, and engagement) are to be interpreted broadly and may include intermediate members between assemblies of elements and relative movement between elements. Therefore, a connection reference does not necessarily imply that two elements are directly connected and have a fixed relationship with each other.

[0079] Furthermore, reference numerals (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to suggest importance or priority, but rather to distinguish one feature from another. These figures are for illustrative purposes only, and the dimensions, positions, order, and relative sizes reflected in the figures may vary.

[0080] The scope of this disclosure is not limited to the specific embodiments described herein. In fact, various other embodiments and modifications of this disclosure, besides those described herein, will be apparent to those skilled in the art from the foregoing description and drawings. Therefore, these other embodiments and modifications are intended to fall within the scope of this disclosure. Furthermore, this disclosure has been described in the context of specific embodiments for specific purposes in specific settings. Those skilled in the art will recognize that its usefulness is not limited thereto, and that this disclosure can be advantageously practiced for any number of purposes in any number of settings. Therefore, the claims set forth below should be interpreted in accordance with the full breadth and spirit of the disclosure described herein.

Claims

1. A semiconductor device, comprising: A substrate disposed between the front and back sides; A diode pilot region is disposed in the substrate; An insulated gate bipolar transistor (IGBT) region is disposed in the substrate; as well as A diode region having a barrier layer is configured to be adjacent to and between the diode pilot region and the IGBT region, wherein the barrier layer is configured to prevent electron flow under a first predetermined current and allow electron flow under a second predetermined current.

2. The apparatus according to claim 1, wherein the blocking layer is a p-type layer.

3. The apparatus of claim 1, wherein the first predetermined current is a low IGBT current.

4. The apparatus of claim 3, wherein the second predetermined current is a high IGBT current.

5. The apparatus of claim 4, wherein at least one of the first predetermined current and the second predetermined current is a diode current.

6. The device of claim 1, wherein the front side comprises one or more metal-oxide-semiconductor field-effect transistor (MOSFET) structures.

7. The apparatus of claim 6, wherein the one or more MOSFET structures comprise at least one of the following: emitter, gate, gate oxide, trench structure, planar structure, active structure, termination, guard ring, junction termination extension, and any combination thereof.

8. The device of claim 1, wherein the back side comprises a collector and a diode cathode.

9. The apparatus of claim 8, wherein the collector is disposed adjacent to the diode cathode.

10. The apparatus of claim 9, further comprising a collector layer and a diode cathode layer, wherein a first portion of the collector layer is disposed adjacent to the collector, and a first portion of the diode cathode layer is disposed adjacent to the diode cathode.

11. The apparatus of claim 10, wherein the collector layer and the diode cathode layer are coupled using a contact metal layer.

12. The apparatus of claim 10, wherein the collector layer is a p-type collector layer.

13. The apparatus of claim 10, wherein the diode cathode layer is an N+ type diode cathode layer.

14. The apparatus of claim 10, wherein a first portion of the collector layer is disposed adjacent to the IGBT region.

15. The apparatus of claim 14, wherein a first portion of the diode cathode layer is disposed adjacent to the diode region.

16. The apparatus of claim 15, wherein the second portion of the collector layer and the second portion of the diode cathode layer are disposed adjacent to the diode region having the blocking layer.

17. The apparatus of claim 16, wherein the barrier layer is formed in the current collector layer.

18. The apparatus of claim 16, wherein the barrier layer is separate from the collector layer.

19. The apparatus of claim 16, wherein the second portion of the collector layer is disposed adjacent to the second portion of the diode cathode layer.

20. The apparatus of claim 10, further comprising a buffer layer disposed above the diode cathode layer and the collector layer and below the substrate.

21. The apparatus of claim 1, wherein the semiconductor apparatus is a reverse-biased insulated-gate bipolar transistor.

22. A method for manufacturing a semiconductor device, comprising: A substrate is provided, and at least one front structure and at least one back structure are formed on the substrate; A diode pilot region is formed in the substrate; An insulated gate bipolar transistor (IGBT) region is formed in the substrate; A diode region with a blocking layer is formed adjacent to and between each of the diode pilot region and the IGBT region, wherein the blocking layer is configured to prevent electron flow under a first predetermined current and allow electron flow under a second predetermined current. A collector layer and a diode cathode layer are formed in the substrate, the formation comprising: A first portion of the collector layer is formed adjacent to the IGBT region. A first portion of the diode cathode layer is formed adjacent to the diode pilot region, and A second portion of the collector layer and a second portion of the diode cathode layer are formed below the diode region having the blocking layer, wherein the second portion of the collector layer is formed adjacent to the second portion of the diode cathode layer; and A buffer layer is formed above the diode cathode layer and the collector layer, and adjacent to the diode pilot region, the blocking layer and the IGBT region.

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