Image sensor, method for forming capacitor and capacitor

Abstract

The invention relates to an image sensor, a method of forming a capacitor, and a capacitor. A system may include a capacitor. The capacitor may include a first electrode, a second electrode, and an insulator between the first electrode and the second electrode. The first electrode may have a peripheral edge laterally offset from a peripheral edge of the second electrode. Laterally offset peripheral edges of the first electrode and the second electrode may be formed using a single mask based etch process.

Description

Technical Field

[0001] The present invention relates generally to systems having capacitors, such as image sensors or imaging systems having capacitors. Background Technology

[0002] A capacitor may include conductive electrodes separated by an electrically insulating material. In one exemplary embodiment, an image sensor that generates image data for an electronic system or device may include such a capacitor. More specifically, an image sensor may include an image sensor array having image sensor pixels, each of which includes one or more such capacitors. Summary of the Invention

[0003] According to a first aspect, an image sensor is provided, the image sensor comprising: a plurality of image sensor pixels, a given image sensor pixel having a capacitor, wherein the capacitor comprises: a first electrode having a lateral edge; a second electrode having a lateral edge laterally offset from the lateral edge of the first electrode using a single-mask-based etching process; and an insulator located between the first electrode and the second electrode.

[0004] According to a second aspect, a method for forming a capacitor is provided, the method comprising: forming a first metal layer, an insulating layer, and a second metal layer on a substrate; forming an etch mask layer on a portion of the second metal layer; etching the second metal layer to form a top electrode for the capacitor while the etch mask layer is located on the portion of the second metal layer; etching the insulating layer to form an insulator for the capacitor while the etch mask layer is located on the portion of the second metal layer; and etching the first metal layer to form a bottom electrode for the capacitor while the etch mask layer is located on the portion of the second metal layer, wherein the top electrode has an edge and wherein the bottom electrode has an edge laterally offset from the edge of the top electrode.

[0005] According to a third aspect, a capacitor is provided, the capacitor comprising: a first electrode located on a substrate; an insulator located on the first electrode; and a second electrode located on the insulator, wherein the first electrode has a peripheral edge, and wherein the second electrode has a peripheral edge laterally offset from the peripheral edge of the first electrode by a spacing of less than 100 nm. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of an exemplary system having one or more image sensors according to some implementation schemes.

[0007] Figure 2 This is a schematic diagram of an exemplary image sensor circuit having an image sensor pixel array and control and readout circuitry for the pixel array, according to some implementation schemes.

[0008] Figure 3 This is a circuit diagram of an exemplary image sensor pixel having a capacitor coupled to a floating diffusion region, according to some implementation schemes.

[0009] Figure 4A This is a side view of an exemplary capacitor based on some implementation schemes.

[0010] Figure 4B This is a plan view of the exemplary electrodes of a capacitor according to some implementation schemes.

[0011] Figures 5A to 5C It is a diagram of an exemplary capacitor structure after various processing steps according to some implementation schemes.

[0012] Figure 6 This is a flowchart illustrating exemplary operations for forming a capacitor according to some implementation schemes. Detailed Implementation

[0013] An electronic system may include one or more capacitors. A capacitor may include a first electrical conductor and a second electrical conductor formed of a conductive material, the first and second electrical conductors sometimes referred to as electrodes. A capacitor may also include an electrical insulator formed of an electrically insulating material such as a dielectric.

[0014] The configuration in which a capacitor is formed as part of an electronic system having one or more image sensors that collect incident light to capture an image is sometimes described herein as an illustrative example. In one illustrative embodiment, the image sensor may include an array of image sensor pixels. Pixels in the image sensor may include photosensitive elements, such as photodiodes, that convert incident light into image signals. The image sensor may have any number of pixels. For example, an image sensor may have hundreds of thousands or millions of pixels. Each of these pixels may include one or more capacitors and other elements such as transistors.

[0015] Other types of electronic systems (such as those without image sensors) may also include capacitors. Generally, the formation and inclusion of capacitors of the types described in conjunction with embodiments herein can be applied to any suitable electronic system having one or more capacitors.

[0016] In the exemplary configurations described herein, the electronic system may include one or more capacitors, each having a first electrode and a second electrode separated by a dielectric material. For a given capacitor, the first electrode may have an edge laterally offset from the edge of the second electrode, such that the first electrode has a larger profile or outline than the second electrode. The design and patterning of the first and second electrodes of the capacitor with offset edges for manufacturing can help reduce the possibility of leakage or short circuits between the first and second electrodes.

[0017] To reduce manufacturing costs, it is desirable to use a single mask to form the capacitor. In other words, a single mask can be used to etch both the first and second electrodes (as well as the dielectric material) while still achieving the desired lateral offset between the edges of the first and second electrodes. In fact, compared to a two-mask method that uses two different masks to etch the first and second electrodes, a smaller lateral edge offset can be achieved using a single mask because the mask mismatch tolerance of the two masks is not required when using a single mask. Therefore, a capacitor with a smaller lateral edge offset between its two electrodes can increase energy storage density, thereby reducing the capacitor area to meet a given energy storage requirement.

[0018] As an illustrative example, this can be seen in electronic systems (such as...) Figure 1 The system provides capacitors of the types described above (e.g., those with laterally offset electrode edges, those with electrodes etched using a single mask, etc.). Details regarding the configuration, formation, and / or specific implementation of these types of capacitors are further described herein.

[0019] Figure 1 This is a functional block diagram of an exemplary imaging system (such as an electronic system) that uses an image sensor to capture images. Figure 1 The imaging system 10 may be a portable electronic device, such as a camera, cellular phone, tablet computer, webcam, camcorder, video surveillance system, vehicle imaging system, video game system with imaging capabilities, augmented reality and / or virtual reality system, unmanned aerial vehicle system (such as drone), industrial system, or any other desired imaging system or device for capturing image data.

[0020] Camera module 12 (sometimes referred to as an imaging module) is used to convert incident light into digital image data. Camera module 12 may include one or more lenses 14 and one or more image sensors 16. When capturing an image, light from the scene can be focused onto each image sensor 16 through one or more lenses 14. Image sensor 16 may include circuitry for converting analog pixel image signals into corresponding digital image data provided to storage and processing circuitry 18.

[0021] Storage and processing circuitry 18 may include one or more integrated circuits, each serving a data storage function and / or a data computation or processing function. As an example, one or more integrated circuits may include image processing circuitry (such as a digital signal processor), application-specific integrated circuits (ASICs), general-purpose processors, microprocessors, microcontrollers, storage devices (such as voltage-controlled memories and non-volatile memories), and / or other types of integrated circuits having a processor and / or memory.

[0022] The storage and processing circuitry 18 may be implemented using components separate from and / or part of the camera module 12. As an example, the storage and processing circuitry 18 may be implemented using circuitry that forms part of an integrated circuit, including the image sensor 16 or an integrated circuit within the camera module 12. When the storage and processing circuitry 18 is included on an integrated circuit different from the integrated circuit of the image sensor 16, the integrated circuit having the storage and processing circuitry 18 may be vertically stacked or packaged relative to the integrated circuit having the image sensor 16.

[0023] The processing circuitry 18 can be used to process and store image data acquired by the camera module 12. As an example, an image processing engine, an imaging mode selection engine, and / or other types of processing engines on the processing circuitry 18 can process the image data captured by the camera module 12. If needed, the processing circuitry 18 can provide the processed image data to external equipment (such as a computer, external display, or other device) using wired and / or wireless communication paths.

[0024] like Figure 2 As shown, image sensors (such as those included in...) Figure 1 The image sensor 16 within the imaging system 10 may include an image sensor pixel array, such as a pixel array 20 containing image sensor pixels 22, which are sometimes referred to as image pixels or pixels. These pixels 22 may be arranged in rows and columns. A row of pixels or a column of pixels may sometimes be collectively referred to as a row of pixels. The image sensor 16 may include control and processing circuitry 24 (sometimes referred to herein as control circuitry 24) that controls the operation of the pixel array 20. The pixel array 20 may contain, for example, hundreds or thousands of rows and / or hundreds or thousands of columns of image sensor pixels 22. If desired, the pixel array 20 may be provided with a filter array having multiple visible color filter elements and / or invisible filter elements, each corresponding to and overlapping a respective pixel 22, thereby allowing a single image sensor to sample light of different colors and / or different groups of wavelengths.

[0025] Image sensor pixels 22 can be formed in a semiconductor substrate using complementary metal-oxide-semiconductor (CMOS) technology, charge-coupled device (CCD) technology, or any other suitable photosensitive device technology. Image sensor pixels 22 can be front-illuminated (FSI) image sensor pixels or back-illuminated (BSI) image sensor pixels.

[0026] The control circuit 24 may be coupled to a pixel control circuit, such as a row control circuit 26, which includes a row driver that provides control signals to the pixel rows in the pixel array 20, and may be coupled to a pixel readout circuit, such as a column readout and control circuit 28, which reads signals from the pixel rows in the pixel array 20.

[0027] The row control circuit 26 can receive row address and / or signal indicating the row address from the control circuit 24, and supply corresponding row control signals (such as reset control signals, anti-halo control signals, row selection control signals, charge transfer control signals, double conversion gain control signals, and readout control signals) to the pixel 22 via conductive lines or conductive paths 30 (such as pixel row control paths). Specifically, each pixel row can receive different control signals through multiple corresponding control paths, such that each pixel row is coupled to multiple conductive paths 30. One or more conductive lines or conductive paths 32 (such as pixel column readout paths) can be coupled to each column of the pixel 22. The conductive paths 32 can be used to read out image signals from the pixel 22 and to supply bias signals (such as bias current or bias voltage) to the pixel 22. As an example, when performing a pixel readout operation, the row control circuit 26 can be used to select a pixel row in the pixel array 20, and the image signal generated by the selected image pixel 22 in that pixel row can be read out along the conductive path 32.

[0028] Column readout circuit 28 can receive image signals (such as analog pixel values ​​generated by pixel 22) via conductive path 32. Column readout circuit 28 may include memory or buffer circuitry for temporarily storing calibration signals (such as reset level signals, reference level signals, and / or other non-image signals) read from array 20 and image level signals read from array 20, amplifier or multiplier circuitry, analog-to-digital converter (ADC) circuitry, bias circuitry, latching circuitry for selectively enabling or disabling portions of column readout circuit 28, and / or other circuitry coupled to one or more pixel columns in array 20 for operating pixel 22 and / or for reading image signals from pixel 22. The ADC circuitry in readout circuit 28 can convert the analog pixel values ​​received from array 20 into corresponding digital pixel values ​​(sometimes referred to as digital image data or digital pixel data). Column readout circuit 28 can provide digital pixel data from pixels 22 in one or more pixel columns to control and processing circuitry 24 and / or processor 18. Figure 1 ( ) for further processing and / or storage.

[0029] Figure 3 For example, forming Figure 2 A circuit diagram illustrating the type of one or more image sensor pixels 22 in the image sensor. (e.g.) Figure 3 As shown, pixel 22 may include a photosensitive element, such as a photodiode 40. The photodiode 40 has a first terminal and a second terminal, the first terminal being coupled to a voltage terminal 39 that receives a reference voltage (such as ground voltage), at which image charge is stored. In response to receiving incident light, the photodiode 40 may generate charge. The amount of charge generated by the photodiode 40 may depend on the exposure duration or build-up time and the intensity of the incident light.

[0030] Figure 3 Pixel 22 may include a floating diffusion region, such as floating diffusion region 44. Floating diffusion region 44 may be a doped semiconductor region, such as a region in a silicon substrate doped by ion implantation, impurity diffusion, and / or any other doping technique. Therefore, floating diffusion region 44 may have an associated charge storage capacity, which in Figure 3 The diagram is schematically shown as having a capacitance C. FD The capacitor. The charge and / or other charge (such as reset voltage level charge or dark current charge) generated by the photodiode can be generated on the floating diffusion region 44, transferred to and / or stored in the floating diffusion region for use in one or more pixel readout operations.

[0031] exist Figure 3 In the example, a charge transfer transistor 42, which receives a control signal “transfer” at its gate terminal, can couple a photodiode 40 to a floating diffusion region 44. Therefore, transistor 42 can be activated when the control signal “transfer” is asserted to transfer the charge generated by the photodiode to the floating diffusion region 44.

[0032] For high dynamic range applications, it may be desirable to extend the storage capacity of the floating diffusion region 44 and operate pixel 22 in a low conversion gain operating mode by including one or more conversion gain charge storage structures. For example... Figure 3 As shown, pixel 22 includes a charge storage structure, such as capacitor 48. Capacitor 48 may have a first terminal coupled to voltage terminal 47 and a second terminal serving as its charge storage terminal. Voltage terminal 47 may supply a fixed voltage, such as ground or supply voltage, or may supply a controllable and / or variable voltage signal exhibiting different voltages at different times.

[0033] Capacitor 48 can be coupled to floating diffusion region 44 via transistor 46, which receives a control signal "gain_ctrl" at its control terminal. When transistor 46 is activated by the asserted control signal "gain_ctrl", capacitor 48 can be electrically connected to floating diffusion region 44, thereby expanding the charge storage capacity of floating diffusion region 44. Additionally, when both transistors 42 and 46 are activated, and when both control signals "transfer" and "gain_ctrl" are asserted, a portion of the charge generated by photodiode 40 can be transferred from photodiode 40 to capacitor 48.

[0034] To reset one or more pixel elements to a reset voltage level, pixel 22 may include one or more reset transistors, such as transistor 50, which receives a control signal "reset" at its gate terminal. Figure 3 As shown, transistor 50 couples voltage terminal 52, which receives a reference voltage (such as a power supply voltage associated with a reset voltage level), to floating diffusion region 44 via intermediate transistor 46. When transistors 46 and 50 are both activated (such as when the control signals "reset" and "gain_ctrl" are asserted), floating diffusion region 44 can be reset to the reset voltage level. Additionally, transistor 50 couples capacitor 48 to voltage terminal 52, and thus also resets capacitor 48 to the reset voltage level. When activated together with transistors 42 and 46, transistor 50 can also reset photodiode 40 to the photodiode reset voltage level.

[0035] Figure 3 Pixel 22 may include a source follower transistor 54 coupled to a voltage terminal 52 and a pixel select (or row select) transistor 56. Transistors 54 and 56 may together form the readout portion of pixel 22. Specifically, the select transistor 56 has a gate terminal controlled by a control signal “select”. When the control signal “select” is asserted and transistor 56 is activated, a corresponding pixel output signal having an amount proportional to the amount of charge at the floating diffusion region 44 and / or capacitor 48 is transmitted via the source follower transistor 54 to the pixel output path (such as forming a pixel). Figure 2 On column line 58, which is part of path 32 in the middle.

[0036] In the exemplary image pixel array configuration, there are multiple rows and columns of pixels 22. Column lines 58 can be associated with and coupled to each column of pixels 22. Therefore, each image pixel 22 in a column can be coupled to the same column line 58 via a corresponding row selection transistor 56. A control signal “select” can be asserted to read a pixel output signal from the selected image pixel 22 onto the shared column line 58. The pixel output signal can be provided to the readout circuit 28 ( Figure 2 ), and then provide it to the processing circuit 18 ( Figure 1 (For further processing)

[0037] like Figure 3 As described in the example, image sensor pixel 22 may include capacitors, such as capacitor 48. In other examples, Figure 2 Another type of image sensor pixel 22 may include other types of capacitors, or more generally, Figure 2 Image sensor 16 in Figure 1 The imaging system 10 and / or other electronic systems may replace capacitor 48, or may include other types of capacitors besides that capacitor. Any of these types of capacitors may be combined with those shown in Figures 4 to 5. Figure 6 The described method is formed. This article describes it as an example, in conjunction with Figures 4 to 5. Figure 6 The described manner forms an exemplary configuration of the capacitor 48 in the corresponding pixel 22.

[0038] Figure 4A This is a side view of an exemplary capacitor, such as capacitor 70. As an example, capacitor 70 can be used to implement... Figure 3 The capacitor 48 is included. The capacitor 70 may include a capacitor structure formed on the underlying substrate 60. The substrate 60 may include a silicon dioxide layer such as a carbon-doped silicon dioxide layer, a silicon nitride layer, a polymer dielectric layer, and / or another type of dielectric layer. If desired, the layers of the substrate 60 may be supported and supported by the surface of the underlying silicon substrate and / or may be grown or deposited on the surface of the underlying silicon substrate.

[0039] Figure 4 shows an exemplary portion of a substrate 60 on which a capacitor structure is disposed. Other portions of the substrate 60 may support or provide the underlying substrate layer for use with and / or generally facilitate the formation of other structures in the same device or system as the capacitor 70. Specifically, when the capacitor 70 is implemented... Figure 3 When capacitor 48 is used, other elements of the same pixel 22 may also be formed on substrate 60 and / or elements of other pixels in the same pixel array 20 (such as multiple instances of capacitor 70 forming capacitor 48 for different pixels in the same array 20) may be formed on substrate 60. The formation and / or inclusion of a single instance of capacitor 70 are sometimes described and illustrated herein as an example so as not to unnecessarily obscure the embodiments described herein. In general, multiple instances of capacitor 70 for the same or multiple image sensors, for the same or multiple dies, for the same wafer and / or for the same system being processed may be formed in the same manner and / or may be formed in parallel.

[0040] like Figure 4AAs shown, the capacitor 70 may include a first electrical conductor 62 (sometimes referred to as electrode 62) and a second electrical conductor 66 (sometimes referred to as electrode 66). Electrodes 62 and 66 may be formed of conductive materials such as metals and certain metal compounds. Configurations in which electrodes 62 and 66 each comprise one or more refractory metals and / or refractory metal compounds are sometimes described herein as illustrative examples. By way of a few examples only, electrodes 62 and 66 may each be formed from and comprise titanium, titanium nitride, titanium alloys, tantalum, tantalum nitride, tantalum alloys, niobium, niobium-based compounds, other types of refractory metals and / or other types of refractory metal-based compounds. While some metal compounds such as titanium nitride, tantalum nitride, some niobium-based compounds and / or some other refractory metal-based compounds may not necessarily be metals, they may still form at least a portion of the metal layer or electrode to enhance the functionality and / or performance of the metal layer or electrode, for example, by forming a diffusion barrier for the metal layer and thus referred to as a barrier layer "metal". If desired, the metal layer or electrode may comprise only combinations of these refractory metal-based compounds, such as a combination of titanium nitride and tantalum nitride.

[0041] The capacitor 70 may also include an intermediate insulator 64 between electrodes 62 and 64. The insulator 64 may be formed of an electrically insulating material, such as a dielectric or dielectric material. Configurations in which the insulator 64 is formed of one or more dielectric materials having a dielectric constant greater than 5, greater than 8, greater than 10, or greater than 12 and / or less than 50, less than 40, less than 30, less than 25, less than 20, or less than 15 are sometimes described herein as illustrative examples. In other cases, other types of dielectric materials may be used. By way of a few examples only, the insulator 64 may include hafnium dioxide, alumina, other dielectric materials having a higher dielectric constant than silicon dioxide, silicon nitride, silicon dioxide, and / or other dielectric materials suitable for the application.

[0042] exist Figure 4A In the example, each of electrode 62, insulator 64, and electrode 66 may be a planar structure or layer (sometimes referred to as a plate) and may have a thickness greater than 3 nm, greater than 5 nm, or greater than 10 nm and / or less than 200 nm, less than 100 nm, or less than 50 nm. In other words, electrode 62 may be a bottom plate contacting the top surface of substrate 60, insulator 64 may be an intermediate planar layer contacting electrode 62 on the bottom side and electrode 66 on the top side, and electrode 66 may be a top plate. If desired, additional structures such as additional dielectric material and / or electrical contacts for electrodes 66 and 62 may contact and / or surround any of electrode 62, insulator 64, and electrode 66.

[0043] Although Figure 4AThe example shown is a capacitor 70 with only a planar structure (sometimes referred to as a two-dimensional capacitor structure), but this is merely illustrative. If desired, portions of the electrodes 62, 64, and 66 may extend into trenches in the substrate 60 or generally away from it. Figure 4A The plane containing the planar structure of capacitor 70 shown in the figure forms a three-dimensional capacitor structure. In other words, electrode 62, insulator 64, and electrode 66 may have planar structures (or portions) in a given plane, as well as tortuous portions optionally extending away from the given plane.

[0044] Electrode 62 may have an edge 72 connecting its top and bottom surfaces on its lateral side. Insulator 64 may have an edge 74 connecting its top and bottom surfaces on its lateral side. Electrode 6 may have an edge 76 connecting its top and bottom surfaces on its lateral side. Exemplary lateral edges 72, 74, and 76 are combined on one side of electrode 62, insulator 64, and electrode 66, respectively. Figure 4A Examples and descriptions are provided. These lateral edges may sometimes be referred to as peripheral edges or sidewalls.

[0045] like Figure 4A As shown, the lateral edge 76 of electrode 66 may be laterally offset or laterally displaced relative to the lateral edge 72 of electrode 62. This lateral offset is designed to help prevent unwanted electrical connections between electrodes 62 and 66 during the manufacturing process. However, this lateral offset may also be desired to reduce or minimize to increase the overlap between electrodes 62 and 66, thereby increasing capacitance and energy storage capacity (over the same total capacitor coverage area or profile provided by the larger electrode 62).

[0046] Therefore, capacitor 70 can be formed to exhibit a lateral offset spacing 78 between lateral edges 76 and 72 (and between lateral edges 76 and 74). As an example, spacing 78 can be a distance less than 100 nm, less than 90 nm, less than 80 nm, less than 50 nm, or less than 30 nm and / or greater than 3 nm, greater than 5 nm, greater than 10 nm, or greater than 15 nm. As a more specific example, spacing 78 can be a distance between 10 nm and 30 nm.

[0047] Although the lateral edges 72, 74 and 76 are Figure 4A The lateral edges are shown as vertical, but this is merely illustrative. Depending on the mask and / or process used for etching or generally fabricating electrodes 62, 64, and 66, one or more or all of their lateral edges may be slanted, curved, and / or generally non-vertical. For example, as... Figure 4AAs shown, electrode 66 may have a slanted or tilted lateral edge 76' instead of a vertical edge 76, and insulator 64 may have a slanted or tilted lateral edge 74' instead of a vertical edge 74.

[0048] This is achieved using a single mask (e.g., etching). Figure 4A The configuration of the structure of capacitor 70 is sometimes described herein as an illustrative example. Specifically, when forming electrodes 66, insulator 64, and electrode 62 based on a single mask, the etching process can result in at least the insulator 64 having a sloping lateral edge 74', which in turn helps to define and provide a lateral offset between the edge 76 of electrode 66 and the edge 72 of electrode 62, even when using a single mask. A single-mask-based etching process can help provide, but reduce, the offset to the pitch 78, which might be impossible if a multi-mask etching process were used, because multiple masks would require alignment tolerances larger than the feature size required to form the lateral pitch 78 between the lateral edges 72 and 76. The following description, in conjunction with Figure 5 and Figure 6 Further details are provided for the exemplary single-mask-based etching process.

[0049] The capacitor 70 may have any suitable lateral profile or coverage area (defined by the lateral edges 72 on all sides), depending on adjacent structures, space constraints, performance requirements, and / or other factors. Figure 4B The diagram shows a plan view of an exemplary capacitor 70 (when in...). Figure 4A (Observed from direction 68 in the middle, with substrate 60 omitted). Figure 4B In the example, capacitor 70 may have a total coverage area defined by rectangular profile 63. Profile 63 may be defined by lateral edges (such as vertical edges 72 and / or sloping edges) on all (four) sides of rectangular electrode 62. In some exemplary configurations, insulator 64 may have the same profile 63 or may have a different (e.g., smaller) profile. Bottom electrode 62 may overlap with top electrode 66 having a smaller rectangular profile 67. In other words, top electrode 66 may completely overlap bottom electrode 62. The difference between profiles 63 and 67 may define a lateral offset spacing between electrodes 62 and 66. The lateral offset spacing may be the same and / or may be different along the different lateral edges.

[0050] The rectangular shapes of electrodes 62 and 66, and typically the rectangular shape of capacitor 70, are merely illustrative. Contours 63 and 67 may have other shapes if desired; they may be curved, have irregular or zigzag sides, and / or may be typically adapted to a particular image sensor pixel layout or a particular device layout. In some configurations described herein as examples, the length and / or width of contour 63 (and / or contour 67) may be greater than 0.25 micrometers, greater than 0.5 micrometers, greater than 1 micrometer, or greater than 2 micrometers, and / or less than 10 micrometers, less than 8 micrometers, less than 5 micrometers, or less than 3 micrometers.

[0051] Any suitable type of processing can be used to form a bond. Figure 4A and Figure 4B Capacitors of that type. Combined Figures 5A to 5C An exemplary process for forming capacitor 70 is described. Although combined Figures 5A to 5C The processing of a single capacitor 70 is described, but this is merely illustrative. The processing of capacitor 70 can be performed at the wafer level, where the wafer contains multiple unchoped dies, each of which also contains elements for bonding... Figures 5A to 5C The method described involves the joint processing of multiple capacitors 70.

[0052] Figure 5A This is a diagram illustrating exemplary metal and insulating layers on a substrate from which a capacitor structure is formed. Specifically, the process for forming capacitor 70 may begin with forming or otherwise providing a substrate, such as Figure 4A Substrate 60. A first conductive material layer 82, an electrically insulating material layer 84, and a second conductive material layer 86 may be deposited, formed, or otherwise provided on substrate 60 in sequence. Any suitable thin film deposition technique (such as chemical and / or physical deposition techniques for forming films having at least the aforementioned thicknesses of conductor 62, insulator 64, and conductor 66) may be used to form layers 82, 84, and 86. The material in layer 82 may be used in conjunction with the material used to form... Figure 4A The material of conductor 62 is the same as that used to form the layer 84, and the material of layer 84 can be the same as that used to form the layer 62. Figure 4A The material of insulator 64 is the same as that used to form the layer 86, and the material of layer 86 can be the same as that used to form the layer 84. Figure 4A The material of conductor 66 in the middle is the same.

[0053] To form the desired capacitor characteristics, metal and insulating layers 82, 84 and 86 can be selectively etched in certain areas. Figure 5BThis is an illustration of an etch mask or etch mask layer formed on metal and insulating layers 82, 84, and 86 to facilitate selective etching of certain regions of the metal and insulating layers 82, 84, and 86. As an example, the mask layer may be formed of a photoresist material 88 (such as a mid-ultraviolet or deep-ultraviolet photoresist). In other words, the photoresist material layer 88 may be coated, deposited, or otherwise provided on the metal layer 86. The photoresist layer 88 may then be patterned using a patterned mask by selectively exposing portions of layer 88 (not covered by the patterned mask) to corresponding light to which the photoresist material is sensitive. The photoresist material 88 may be a positive or negative photoresist material. After patterning, the photoresist layer 88 may be developed to remove certain portions (such as portion 88-2) while other portions (such as portion 88-1) remain on the metal layer 86. Therefore, a portion of 88-1 (sometimes referred to as etch mask layer 88-1) can be formed for etching capacitor features to form Figure 4A The etched mask layer of capacitor 70 in the middle.

[0054] After forming an etching mask layer (such as etching mask layer 88-1) on the metal and insulating layers 82, 84 and 86, the etching process can continue. Figure 5C This is a diagram of an exemplary etching system configured to perform etching of metal and insulating layers 82, 84, and 86 based on a single etch mask layer. The configuration in which single-mask-based etching of metal and insulating layers 82, 84, and 86 is performed using a reactive ion etching process is sometimes described herein as an exemplary example.

[0055] In this example, combined Figure 5B The described structure (or more specifically, the structure containing the combination) Figure 5B The wafers of several instances of the described structure can be placed in a reactive ion etching system, which includes a chamber such as a vacuum chamber 90 (sometimes referred to as a reactive ion etching chamber 90). The chamber 90 can be maintained at a gas pressure ranging from 1 mTorr to 300 mTorr, and in one exemplary example, from 3 mTorr to 50 mTorr. The chamber 90 may have one or more inlets 91 and one or more outlets 93, the inlets being used to supply reactive gases (sometimes referred to as reacted gases) for the reactive ion etching process, and the outlets being used to remove waste gases.

[0056] As just a few examples, gases supplied to chamber 90 for reactive ion etching processes may include chlorine, fluorine, boron trichloride, sulfur hexafluoride, trifluoromethane, carbon tetrafluoride, helium, and / or nitrogen. Configurations in which boron trichloride, sulfur hexafluoride, helium, trifluoromethane, and / or carbon tetrafluoride are supplied to chamber 90 when etching metals and / or metal-based materials (such as those in layers 82 and 86) are sometimes described herein as an example. Configurations in which chlorine, boron trichloride, and / or helium are supplied to chamber 90 when etching dielectric or other insulating materials (such as those in layer 84) are sometimes described herein as an example.

[0057] After a suitable reactive gas for etching metals or dielectrics is supplied to chamber 90, the reactive ion etching system may provide an electromagnetic field within chamber 90 to ionize the reactive gas and generate plasma 92. For example, the reactive ion etching system may be an inductively coupled plasma or a transformer-coupled plasma reactive ion etching system.

[0058] A reactive ion etching system provides a directional electric field within chamber 90, near layers 82, 84, and 86, and substrate 60, causing charged ions from plasma 92 to be accelerated toward layers 82, 84, and / or 86 in the presence of the directional electric field (in direction 94). The strength or magnitude of the directional electric field can be controlled using a bias power (such as a relative bias power) applied between two electrodes (radio frequency or typically AC), one coupled to substrate 60 and the other displaced from substrate 60. Charged ions can bombard the etched metal or insulating layers, physically and / or chemically etching away portions of the metal or insulating layers (dashed lines), leaving the remaining portions to form corresponding capacitor structures.

[0059] exist Figure 5C In the example, three different etching operations can be performed sequentially on metal layer 86, insulating layer 84, and metal layer 82, all simultaneously using mask layer 88-1 to cover and protect portions of metal layer 86, insulating layer 84, and metal layer 82. Specifically, the reactive ion etching system can first etch layer 86 using a first set of parameters to leave conductor 66 for capacitor 70, then etch layer 84 using a second set of parameters to leave insulator 64 for capacitor 70, and finally etch layer 82 using a third set of parameters. As just a few illustrative examples, the parameters used for etching layers may include the selected gas combination, the flow rate of each gas, the total reactive gas flow rate, the pressure of chamber 90, the strength or magnitude of the electromagnetic field for ionizing gases (characterized by the power supplied to provide the electromagnetic field), the strength or magnitude of the directional electric field for accelerating the ions of the plasma toward the layer being etched, and the etching time.

[0060] At least some of these exemplary parameters may be the same as the first, second, and third sets of parameters used for etching layers 86, 84, and 82, and / or at least some of these parameters may be different from the first, second, and third sets of parameters used for etching layers 86, 84, and 82. For example, the first and third sets of parameters may be completely or substantially the same because layers 86 and 82 have the same or similar materials, dimensions, and / or other properties, while the first and second sets of parameters may be completely or substantially different because layers 86 and 84 have different materials, dimensions, and / or other properties.

[0061] In an exemplary configuration sometimes described herein as an example, the first set of parameters for etching layer 86 may include using boron trichloride (at a first flow rate) and sulfur hexafluoride as input reactive gases, the second set of parameters for etching layer 84 may include using boron trichloride (at a second flow rate greater than the first flow rate) and chlorine as input reactive gases without using sulfur hexafluoride as input reactive gas, and the third set of parameters for etching layer 82 may include using boron trichloride (at a first flow rate) and sulfur hexafluoride as input reactive gases.

[0062] By using sulfur hexafluoride as the reactive gas in the first set of parameters, sputtering of etched material in layer 86 onto other structures (such as photoresist 88-1) can be reduced or minimized, thereby reducing the risk of short circuits caused by under-release layer 86 and / or stringers. By using boron trichloride (at a higher flow rate) and chlorine as reactive gases in the second set of parameters instead of sulfur hexafluoride, sputtering of etched material in layer 84 onto other structures (such as photoresist 88-1) can be reduced or minimized, thereby reducing the risk of under-release layer 84. By using sulfur hexafluoride as the reactive gas in the third set of parameters, sputtering of etched material in layer 82 onto other structures (such as insulator 64 and / or electrode 66) can be reduced or minimized, thereby reducing the risk of short circuits caused by stringers between under-release layer 82 and / or electrode 62 and other conductive structures (such as electrode 66).

[0063] The examples described above, which use boron trichloride, sulfur hexafluoride, and chlorine as reactive gases for reactive ion etching of layers 86, 84, and 82, are merely illustrative. Other reactive gases may be used, in addition to or in place of one or more of these three reactive gases, if desired.

[0064] Such as combination Figure 4A As described, the peripheral edge 76 of conductor 66 may be formed with a lateral offset from the peripheral edge 72 of conductor 62 (by... Figure 4A The spacing 78 in the middle is characterized. This lateral offset between edges 72 and 76 can be represented by combining... Figure 5C This is achieved using the described single-mask etching process.

[0065] As an illustrative example of achieving this lateral offset, a second set of parameters for etching the insulating layer 84 can be configured to form a slanted edge profile after etching, as indicated by the slanted or skewed edge 74', rather than a vertical edge 74. The insulator 64 can be etched to exhibit the slanted edge profile, gradually widening along all peripheral edges toward layer 82. In other words, the slanted edge 74' can extend laterally beyond the edge 76 of the conductor 66 and can cover the peripheral portion of layer 82 that extends laterally beyond edge 76. The covered peripheral portion of the first metal layer at least partially defines the lateral offset between the edge 76 of the top electrode 66 and the ultimately formed edge 72 of the bottom electrode 62.

[0066] In some exemplary configurations described herein as examples, the second set of parameters may include a bias power for providing a directional electric field, which is greater than the bias power used in the first and / or third set of parameters; a maintained chamber gas pressure, which is less than the maintained chamber gas pressure used in the first and / or third set of parameters; and a total intake or supply reactive gas flow rate, which is greater than the total intake or supply reactive gas flow rate used in the first and / or third set of parameters. As layer 84 is progressively etched, this is expected to generate more sidewall (edge) polymer on insulator 64, thereby contributing to the sloping edge profile of insulator 64. The sloping or widened edge profile of insulator 64 toward metal layer 82 can be used to form a smaller etched area in layer 82 relative to a larger etched area in layer 86 formed by mask layer 88-1. In other words, the sloping edge profile of insulator 64 effectively serves as a mask layer for layer 82, which has a larger coverage area than the mask layer 88-1 of layer 86, thereby causing a lateral offset between conductors 62 and 66 when layer 82 is etched.

[0067] As a complement and alternative to using the sloping edge profile of insulator 64 to induce lateral offset, the third set of parameters can be configured to exhibit some, or more specifically, a slight degree of, isotropic (lateral) etching in addition to the predominantly anisotropic etching typically attributed to reactive ion etching in the downward direction. Therefore, when layer 82 is etched using the third set of parameters to form conductor 62, the slight isotropic nature of the same etching can cause the peripheral edges of conductor 66 to also be etched, resulting in the peripheral edges of conductor 66 receding, for example, to the sloping peripheral edge 76' rather than the edge 76 initially formed when layer 86 is etched using the first set of parameters. This slight isotropic etching may contribute to the lateral offset between the peripheral edges of conductors 66 and 62.

[0068] After etching layers 82, 84, and 86, the reactive ion etching system can remove from chamber 90 the assembly containing the capacitor structure on substrate 60 (and including mask layer 88-1). Mask layer 88-1 can be further removed to create capacitor 70 on substrate 60, as in... Figure 4A As shown in the figure and described in conjunction with it.

[0069] Because a single etch mask layer 88-1 is used instead of two (or more) masks to impart lateral offsets to the peripheral edges 72 and 76, the spacing of the lateral offsets can be reduced compared to scenarios using multiple etch masks, which require minimal alignment or other types of tolerances. For a given area, the smaller lateral offsets contribute to greater overlap between the two conductors of the capacitor, allowing for a more efficient and compact device layout. This efficient use of the capacitor area is particularly beneficial in devices where there is a high demand for area dedicated to active components such as photosensitive elements. Additionally, using a single etch mask reduces processing costs, among other advantages.

[0070] Figure 6 This is a flowchart illustrating the operations used to form a capacitor structure (such as a capacitor structure for capacitor 70). Combined with... Figure 6 The exemplary operations described herein can be performed by a semiconductor device processing system, which is automated to perform one or more of these operations and / or manually controlled to perform one or more of these operations. The semiconductor device processing system may include various types of specialized equipment, such as metal and insulating thin film deposition equipment, mid-ultraviolet or deep-ultraviolet photoresist coating equipment, mid-ultraviolet or deep-ultraviolet lithography equipment, and reactive ion etching equipment (such as bonding...). Figure 5C The described reactive ion etching system is only a few examples. (Combined) Figure 6 The exemplary operations described may be performed as part of a larger processing operation generally used to form the elements of the image sensor 16 at the wafer level, or as part of other types of processing operations, or may be performed separately from other types of processing operations.

[0071] At box 100, the semiconductor device processing system may provide a substrate having metal and insulating layers on it. For example, the substrate may be... Figure 4A and Figure 5A Substrate 60 in the middle. First metal layer (such as...) Figure 5A The metal layer 82) can be deposited onto the substrate, and the insulating layer (such as...) Figure 5A The insulating layer 84 in the middle can be deposited on the first metal layer, and the second metal layer (such as...) Figure 5A The metal layer 86 in the middle can be deposited onto the insulating layer.

[0072] At block 102, the semiconductor device processing system may provide and pattern a photoresist layer. For example, at block 100, the photoresist layer may be coated or otherwise provided on the topmost metal layer provided on the substrate. The topmost metal layer may be... Figure 5B The metal layer 86 in the middle, and the photoresist layer can be Figure 5B The photoresist layer 88 in the middle.

[0073] Photolithography and development can be used to pattern the photoresist layer to remove certain portions of the photoresist layer while retaining others, which will be used as an etching mask for etching the metal and insulating layers on the substrate provided at frame 100. For example, it is possible to... Figure 5B The photoresist layer 88 is patterned to remove portion 88-2, while leaving portion 88-1 on the metal layer 86. The remaining portion 88-1 can serve as an etch mask layer during the subsequent etching of the metal and insulating layers on the substrate at frame 104.

[0074] At block 104, the semiconductor device processing system can perform a reactive ion etching process on the metal and insulating layers to provide a lateral edge offset between the top capacitor electrode and the bottom capacitor electrode. When performing reactive ion etching on each of the metal and insulating layers, the reactive ion etching process can use the same etch mask provided by the photoresist layer patterned at block 102. For example, etching the metal and insulating layers can make... Figure 5C The capacitor 70 has a bottom electrode 62, an intermediate insulator 64, and a top electrode 66, wherein the bottom electrode 62 has a peripheral edge 72 that is laterally offset from the peripheral edge 76 of the top electrode 66, as combined Figure 4A As described. Combined Figure 5C The exemplary operation described herein may be performed as part of the reactive ion etching process of box 104 to etch the metal and insulating layers.

[0075] At frame 106, the semiconductor device processing system can remove the (patterned) photoresist layer formed at frame 102, thereby creating a capacitor structure on the substrate, for example... Figure 4A Electrode 66, insulator 64 and electrode 62 of capacitor 70 on substrate 60.

[0076] Various embodiments of a capacitor having a first conductor and a second conductor having offset lateral edges have been described.

[0077] As a first example, an image sensor may include a plurality of image sensor pixels. A given image sensor pixel among the plurality of image sensor pixels may have a capacitor. The capacitor may include a first electrode having a lateral edge, a second electrode having a lateral edge laterally offset from the lateral edge of the first electrode using a single-mask-based etching process, and an insulator between the first electrode and the second electrode.

[0078] If desired, the lateral edge of the second electrode may be laterally separated from the lateral edge of the first electrode by a distance of less than 100 nm. If desired, the insulator may have a sloping lateral edge between the lateral edges of the second electrode and the first electrode. If desired, the second electrode may have a smaller profile than the first electrode, and the sloping lateral edge of the insulator may overlap with the first electrode. If desired, the capacitor may be formed on the substrate, the second electrode being the top electrode, and the first electrode being the bottom electrode located between the top electrode and the substrate. If desired, a given image sensor pixel includes a photosensitive element, a floating diffusion region, and a transistor coupling the capacitor to the floating diffusion region. If desired, the first and second electrodes may each comprise a refractory metal, and the insulator may comprise a dielectric material having a dielectric constant greater than 5 and less than 50.

[0079] As a second example, a method of forming a capacitor may include: forming a first metal layer, an insulating layer, and a second metal layer on a substrate; forming an etch mask layer on a portion of the second metal layer; etching the second metal layer to form a top electrode for the capacitor while the etch mask layer is located on that portion of the second metal layer; etching the insulating layer to form an insulator for the capacitor while the etch mask layer is located on that portion of the second metal layer; and etching the first metal layer to form a bottom electrode for the capacitor while the etch mask layer is located on that portion of the second metal layer. The top electrode may have an edge, and the bottom electrode may have an edge laterally offset from the edge of the top electrode.

[0080] If desired, etching the second metal layer may include performing reactive ion etching using a first reactive gas and a second reactive gas (such as boron trichloride and sulfur hexafluoride), and etching the insulating layer may include performing reactive ion etching using a first reactive gas and a third reactive gas (such as boron trichloride and chlorine). If desired, etching the second metal layer may include performing reactive ion etching using a first total reactive gas flow rate, and etching the insulating layer may include performing reactive ion etching using a second total reactive gas flow rate greater than the first total reactive gas flow rate. If desired, etching the second metal layer may include performing reactive ion etching while providing a first gas pressure in the reactive ion etching chamber, and etching the insulating layer may include performing reactive ion etching while providing a second gas pressure less than the first gas pressure in the reactive ion etching chamber. If desired, etching the second metal layer may include performing reactive ion etching while providing a directional electric field having a first magnitude toward the substrate, and etching the insulating layer may include performing reactive ion etching while providing a directional electric field having a second magnitude greater than the first magnitude. If desired, the etched insulating layer forms an insulator with a sloping edge that covers a portion of the first metal layer laterally extending beyond the edge of the top electrode, and the covered portion of the first metal layer at least partially defines a lateral offset between the edge of the top electrode and the edge of the bottom electrode. If desired, etching the first metal layer may include performing reactive ion etching after etching the insulating layer, and the reactive ion etching etches a portion of the top electrode to form the edge of the top electrode. If desired, the edge of the bottom electrode is laterally offset from the edge of the top electrode by a distance of less than 50 nm. If desired, the first and second metal layers may each comprise a refractory metal, and the insulating layer may comprise a dielectric material having a dielectric constant greater than 5 and less than 50.

[0081] As a third example, the capacitor may include a first electrode on a substrate, an insulator on the first electrode, and a second electrode on the insulator. The first electrode may have a peripheral edge, and the second electrode may have a peripheral edge laterally offset from the peripheral edge of the first electrode by a spacing of less than 100 nm.

[0082] If desired, the insulator may have a sloping peripheral edge between the peripheral edges of the first electrode and the second electrode. If desired, the first and second electrodes may each comprise a refractory metal, and the insulating layer may comprise a dielectric material having a dielectric constant greater than 5 and less than 50.

[0083] Those skilled in the art will understand that exemplary embodiments of the present invention can be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the invention.

[0084] The above description is merely illustrative and various modifications can be made to the described implementation scheme. The above implementation scheme can be implemented individually or in any combination.

Claims

1. An image sensor, the image sensor comprising: A plurality of image sensor pixels, wherein a given image sensor pixel has a capacitor, wherein the capacitor comprises: A first electrode, the first electrode having a lateral edge; A second electrode, the second electrode having a lateral edge laterally offset from the lateral edge of the first electrode using a single-mask-based etching process; and An insulator located between the first electrode and the second electrode.

2. The image sensor of claim 1, wherein the lateral edge of the second electrode is laterally separated from the lateral edge of the first electrode by a distance of less than 100 nm.

3. The image sensor of claim 1, wherein the insulator has an inclined lateral edge between the lateral edge of the second electrode and the lateral edge of the first electrode.

4. The image sensor of claim 3, wherein the second electrode has a smaller profile than the first electrode, and wherein the inclined lateral edge of the insulator overlaps with the first electrode.

5. The image sensor of claim 4, wherein the capacitor is formed on a substrate, wherein the second electrode is a top electrode, and wherein the first electrode is a bottom electrode located between the top electrode and the substrate.

6. The image sensor of claim 1, wherein the given image sensor pixel comprises a photosensitive element, a floating diffusion region, and a transistor coupling the capacitor to the floating diffusion region.

7. The image sensor of claim 1, wherein the first electrode and the second electrode each comprise a refractory metal, and wherein the insulator comprises a dielectric material having a dielectric constant greater than 5 and less than 50.

8. A method of forming a capacitor, the method comprising: A first metal layer, an insulating layer, and a second metal layer are formed on a substrate; An etching mask layer is formed on a portion of the second metal layer; While the etch mask layer is located on the portion of the second metal layer, the second metal layer is etched to form the top electrode for the capacitor; While the etch mask layer is located on the portion of the second metal layer, the insulating layer is etched to form an insulator for the capacitor; as well as While the etch mask layer is located on the portion of the second metal layer, the first metal layer is etched to form a bottom electrode for the capacitor, wherein the top electrode is formed with an edge, and wherein the bottom electrode is formed with an edge laterally offset from the edge of the top electrode.

9. The method of claim 8, wherein etching the second metal layer comprises: Reactive ion etching is performed using a first reactive gas and a second reactive gas, and The etching of the insulating layer includes performing reactive ion etching using the first reactive gas and the third reactive gas.

10. The method according to claim 9, wherein the first reactive gas is boron trichloride, the second reactive gas is sulfur hexafluoride, and the third reactive gas is chlorine.

11. The method of claim 8, wherein etching the second metal layer comprises: Reactive ion etching is performed using a first total reactive gas flow rate, and The etching of the insulating layer includes performing reactive ion etching using a second total reactive gas flow rate greater than the first total reactive gas flow rate.

12. The method of claim 8, wherein etching the second metal layer comprises: Reactive ion etching is performed when a first gas pressure is provided in the reactive ion etching chamber, and The etching of the insulating layer includes performing reactive ion etching while providing a second gas pressure lower than the first gas pressure in the reactive ion etching chamber.

13. The method of claim 8, wherein etching the second metal layer comprises: Reactive ion etching is performed when a directional electric field of a first magnitude is provided toward the substrate, and The etching of the insulating layer includes performing reactive ion etching while providing a directional electric field having a second value greater than the first value.

14. The method of claim 8, wherein etching the insulating layer forms an insulator with a sloping edge that covers a portion of the first metal layer laterally extending beyond the edge of the top electrode, and wherein the covered portion of the first metal layer at least partially defines a lateral offset between the edge of the top electrode and the edge of the bottom electrode.

15. The method of claim 8, wherein etching the first metal layer comprises: After etching the insulating layer, reactive ion etching is performed, wherein the reactive ion etching etches a portion of the top electrode to form the edge of the top electrode.

16. The method of claim 8, wherein the edge of the bottom electrode is laterally offset from the edge of the top electrode by a distance of less than 50 nm.

17. The method of claim 8, wherein the first metal layer and the second metal layer each comprise a refractory metal, and wherein the insulating layer comprises a dielectric material having a dielectric constant greater than 5 and less than 50.

18. A capacitor, the capacitor comprising: A first electrode, wherein the first electrode is located on a substrate; An insulator, the insulator being located on the first electrode; and A second electrode is located on the insulator, wherein the first electrode has a peripheral edge, and wherein the peripheral edge of the second electrode is laterally offset from the peripheral edge of the first electrode by a distance of less than 100 nm.

19. The capacitor of claim 18, wherein the insulator has a sloping peripheral edge between the peripheral edge of the first electrode and the peripheral edge of the second electrode.

20. The capacitor of claim 18, wherein the first electrode and the second electrode each comprise a refractory metal, and wherein the insulator comprises a dielectric material having a dielectric constant greater than 5 and less than 50.

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