Display panel and electronic device including the same

Abstract

The invention provides a display panel and an electronic device including the same. The display panel includes: a base substrate; a circuit layer including a transistor; a pixel defining layer defining an emission opening portion; an auxiliary layer including a transparent metal oxide; a separator including a black component and having an edge protruding further toward the emission opening portion than an edge of the auxiliary layer; and a light emitting element over the circuit layer and including a first electrode in the emission opening portion, a second electrode facing the first electrode, a plurality of emission structures between the first electrode and the second electrode, and a plurality of charge generation layers between the first electrode and the second electrode, a step space is defined by a portion of a bottom surface of the separator, an edge of the auxiliary layer, and a portion of an upper surface of the pixel defining layer, and wherein at least one charge generating layer of the plurality of charge generating layers is broken at the step space.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0110421, filed on August 19, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display panel including a light-emitting element and an electronic device including the display panel, the light-emitting element including a functional layer commonly disposed in an adjacent emitting area. Background Technology

[0003] Multimedia electronic devices (such as televisions, mobile phones, tablet computers, navigation devices, game consoles, or wearable devices) may include display panels that display images. These display panels use so-called self-emitting display elements, which emit light by causing a light-emitting material, such as an organic compound or quantum dots, to be contained in an emitting layer located between electrodes facing each other.

[0004] In addition, with the increasing demand for high definition in multimedia electronic devices, the arrangement gap between adjacent light-emitting elements is reduced in order to achieve high resolution display quality. This may lead to leakage emission that could affect the light-emitting characteristics of adjacent pixels, thus reducing display quality. Summary of the Invention

[0005] This disclosure provides a display panel with excellent display quality and high resolution, as well as an electronic device including the display panel.

[0006] One or more embodiments of this disclosure provide a display panel comprising: a substrate; a circuit layer above the substrate and including transistors; a pixel defining layer above the circuit layer and defining an emission opening portion; an auxiliary layer above the pixel defining layer and including a transparent metal oxide; a separator above the auxiliary layer, including a black component and having an edge that protrudes further toward the emission opening portion than the edge of the auxiliary layer; and a light-emitting element above the circuit layer and including a first electrode in the emission opening portion, a second electrode facing the first electrode, a plurality of emission structures between the first electrode and the second electrode, and a plurality of charge-generating layers between the first electrode and the second electrode, wherein a step space is defined by a portion of the bottom surface of the separator, an edge of the auxiliary layer, and a portion of the upper surface of the pixel defining layer, and wherein at least one of the plurality of charge-generating layers is interrupted at the step space.

[0007] The display panel may also include cavitation in the stepped space, where multiple emitting structures and multiple charge-generating layers are discontinuous.

[0008] At least one of the multiple charge generation layers may include one end above the pixel defining layer and the other end above the separator.

[0009] Multiple emission structures may include a first emission structure, a second emission structure, a third emission structure, and a fourth emission structure stacked in the thickness direction and including emission layers, wherein multiple charge generation layers include a first charge generation layer between the first emission structure and the second emission structure, a second charge generation layer between the second emission structure and the third emission structure, and a third charge generation layer between the third emission structure and the fourth emission structure, and wherein at least one of the first emission structure, the second emission structure, the third emission structure, and the fourth emission structure is disconnected from at least one of the first charge generation layer, the second charge generation layer, and the third charge generation layer at a step space.

[0010] The separator may include an organic membrane, which may include a black component.

[0011] The separator can be superimposed only on a portion of the pixel-defined layer.

[0012] The auxiliary layer may include: a transparent conductive oxide material, crystallized at a temperature of about 260°C or higher; and the transparent conductive oxide material includes indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO) having an indium to zinc weight ratio of about 9:1 to about 1:1.

[0013] The thickness of the auxiliary layer can be from about 100 Å to about 1000 Å.

[0014] The angle of inclination between the side surface of the separator and the base plate can be from about 50 degrees to about 90 degrees.

[0015] A transistor may include a semiconductor pattern and a gate above the semiconductor pattern. The semiconductor pattern includes a metal oxide, which includes at least one of indium, gallium, zinc, tin, and titanium. The semiconductor pattern is divided into an active body, a source, and a drain.

[0016] In one or more embodiments of this disclosure, the display panel includes: a substrate; a circuit layer above the substrate and including transistors; and a display layer above the circuit layer defining emission regions separated from each other. The display layer includes: a pixel defining layer above the circuit layer and defining emission opening portions corresponding to the emission regions; an auxiliary layer above the pixel defining layer and including a transparent metal oxide; a separator above the auxiliary layer, including a black component and having an edge that protrudes further towards the emission opening portions than the edge of the auxiliary layer; and a light-emitting element above the circuit layer and including a first electrode, a second electrode facing the first electrode, a plurality of emission structures between the first and second electrodes, and a plurality of charge-generating layers between the first and second electrodes. A stepped space having an undercut shape is defined by a portion of the bottom surface of the separator, an edge of the auxiliary layer, and a portion of the upper surface of the pixel defining layer, wherein at least one of the plurality of charge-generating layers is interrupted at the stepped space.

[0017] On a plane, the emission region may have a polygonal shape having a short side extending in a first direction and a long side extending in a second direction intersecting the first direction, wherein the separator has a shape extending in the second direction between adjacent emission regions in the first direction and includes: a main portion between adjacent emission regions in the emission region; and a secondary portion spaced apart from the main portion and spaced apart in the second direction from at least one emission region in the adjacent emission regions in the emission region, wherein the main portion includes a curved portion having a shape that surrounds at least a portion of a corner of at least one emission region in the adjacent emission regions in the emission region.

[0018] The separator may include an organic membrane, which may include a black component.

[0019] The auxiliary layer may include indium zinc oxide having an indium to zinc weight ratio of about 9:1 to about 1:1.

[0020] The emission structure may include at least one green emission structure and at least one blue emission structure.

[0021] In one or more embodiments of this disclosure, an electronic device includes: a display panel including a first emitting region, a second emitting region, and a third emitting region spaced apart in a plane, sequentially arranged in a first direction, and configured to emit source light; and a light control panel above the display panel and configured to transmit source light or convert the wavelength of the source light. The display panel includes: a substrate; a circuit layer above the substrate and including transistors; a pixel defining layer above the circuit layer and defining an emission opening portion; an auxiliary layer above the pixel defining layer and including a transparent metal oxide; a separator above the auxiliary layer, including a black component, and having an edge that protrudes further into the emission opening portion than the edge of the auxiliary layer; and a light-emitting element above the circuit layer and including a first electrode in the emission opening portion, a second electrode facing the first electrode, a plurality of emitting structures between the first and second electrodes, and a plurality of charge-generating layers between the first and second electrodes. A step space is defined by a portion of the bottom surface of the separator, an edge of the auxiliary layer, and a portion of the upper surface of the pixel defining layer, and wherein at least one of the plurality of charge-generating layers is interrupted at the step space.

[0022] Electronic devices may also include at least one of a processor, memory, and power module.

[0023] Electronic devices can be image display devices, wearable devices, or devices used in vehicles.

[0024] The electronic device may also include a cavity in a step space, where the plurality of emitting structures and the plurality of charge generating layers are discontinuous, wherein at least one of the plurality of charge generating layers includes one end above the pixel defining layer and the other end above the separator.

[0025] The separator may include an organic membrane comprising a black component, wherein the separators are configured in a plurality of spaces, respectively between the first emission region and the second emission region and between the second emission region and the third emission region.

[0026] The auxiliary layer may include indium zinc oxide having an indium to zinc weight ratio of about 9:1 to about 1:1.

[0027] The electronic device may further include a first pixel region, a second pixel region, and a third pixel region. The light control panel includes a light control layer and a color filter layer above the light control layer. The light control layer includes a light control unit and a segmentation pattern. The segmentation pattern defines a first segmentation opening corresponding to the first pixel region, a second segmentation opening corresponding to the second pixel region, and a third segmentation opening corresponding to the third pixel region. The color filter layer includes a first color filter, a second color filter, and a third color filter. The light control unit includes a first light control unit in the first segmentation opening that corresponds to the first color filter and includes a first quantum dot, a second light control unit in the second segmentation opening that corresponds to the second color filter and includes a second quantum dot, and a third light control unit in the third segmentation opening that corresponds to the third color filter and includes a third quantum dot. The first pixel region, the second pixel region, and the third pixel region emit light in different corresponding wavelength regions. The separators are configured as a plurality of separators, each corresponding to a space between the first pixel region and the second pixel region, and between the second pixel region and the third pixel region. Attached Figure Description

[0028] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain aspects of the disclosure. In the drawings: Figure 1 It is a perspective view of an electronic device according to one or more embodiments; Figure 2A It is a perspective view of a display module according to one or more embodiments; Figure 2B It is a cross-sectional view of a display module according to one or more embodiments; Figure 2C It is a plan view of a display module according to one or more embodiments; Figure 3 This is an enlarged plan view of a portion of a display module according to one or more embodiments; Figure 4 This is a cross-sectional view of a portion of a display module according to one or more embodiments; Figures 5A to 5C All are cross-sectional views of a display module according to one or more embodiments; Figure 6 It is a cross-sectional view of a light-emitting element according to one or more embodiments; Figure 7 It is a cross-sectional view of a portion of a display panel according to one or more embodiments; Figure 8It is a cross-sectional view of a portion of a display panel according to one or more embodiments; Figure 9A It is a cross-sectional view of a portion of a display panel according to one or more embodiments; Figure 9B It is a cross-sectional view of a portion of a display panel according to one or more embodiments; Figure 10A It is a plan view of a portion of a display panel according to one or more embodiments; Figure 10B It is a plan view of a portion of a display panel according to one or more embodiments; Figures 11A to 11D These are all diagrams illustrating one operation of a method for manufacturing a display panel according to one or more embodiments; Figure 12 This is a block diagram of an electronic device according to an embodiment; and Figure 13 A schematic diagram of an electronic device according to an embodiment is shown. Detailed Implementation

[0029] Some aspects of this disclosure and methods of implementing some embodiments can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and the described embodiments will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential for a person of ordinary skill in the art to fully understand aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated description may be omitted.

[0030] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the use of "can," "may," or "may not" corresponds to one or more embodiments of this disclosure.

[0031] It will be understood by those skilled in the art that, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined or combined with each other in part or in whole, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently or in combination with each other in any suitable way, unless otherwise stated or implied.

[0032] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of interpretation. Additionally, the use of crosshairs and / or shading in the drawings is generally intended to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement regarding the specific material, material properties, dimensions, scale, commonalities between the elements shown, or any other characteristics, properties, or characteristics of the elements.

[0033] Various embodiments are described herein with reference to sectional views that serve as schematic illustrations and / or intermediate structures. Thus, variations in the shape of the illustrations, for example, due to manufacturing techniques and / or tolerances, will be anticipated. Furthermore, the specific structural and functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the elements, layers, or regions shown, but will include deviations in shape due to, for example, manufacturing processes.

[0034] For example, an injection region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from the injection region to the non-injection region. Similarly, a buried region formed by injection can induce some injection in the region between the buried region and the surface through which the injection occurs.

[0035] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above / overall,” “higher,” “upper side,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element or feature as shown in the accompanying drawings to another element or feature. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are also intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below” or “under” or “below” other elements or features will then be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first component is described as being arranged "on" the second component, this indicates that the first component is arranged on the upper or lower side of the second component based on the direction of gravity, and is not limited to the upper side of the second component.

[0036] Furthermore, the phrase "in a plan view" means when viewing a portion of an object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting a portion of an object from the side. The term "overlapping" or variations thereof means that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlapping" can include stacking, facing, or variations thereof, extending over, covering, or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include terms such as "separated," "away from," or "offset," and any other suitable equivalents as will be understood and appreciated by one of ordinary skill in the art. The term "facing" or variations thereof can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, although still facing each other.

[0037] It will be understood that when an element, layer, region, or component (e.g., device, apparatus, circuit, line, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "combined (operably, functionally, or communicatively)" with another element, layer, region, or component, that element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly combined with the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly combined with the other element, layer, region, or component, such that one or more intermediary elements, intermediary layers, intermediary regions, or intermediary components may exist. Furthermore, this can collectively mean direct combination or connection, indirect combination or connection, and integral combination or connection or non-integral combination or connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, that layer, region, or component may be directly electrically connected or directly electrically bonded to the other layer, region, and / or component, or one or more intermediary layers, intermediary regions, or intermediary components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, the connection is not limited to the connections shown in the accompanying drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on..." means that one component is directly connected to or directly bonded to another component, or on another component, without an intermediary component.

[0038] Furthermore, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the formation direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where another portion exists between the portion and the other portion. Similarly, other expressions describing relationships between components, such as "between," "directly between," or "adjacent to" and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0039] For the purposes of this disclosure, when expressions such as “at least one of…” or “any one of…” or “one or more of…” follow a list of elements, they modify the entire list of elements without modifying individual elements within the list. For example, “at least one of X, Y, and Z”, “at least one of X, Y, or Z”, “at least one selected from the group consisting of X, Y, and Z”, and “at least one selected from the group consisting of X, Y, or Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ), or any variations thereof. Similarly, expressions such as “at least one of A and B” and “at least one of A or B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when expressions such as "at least one of...", "multiple...", "one of...", and other prepositional phrases appear before / after a column of elements, such expressions modify the entire column of elements without modifying individual elements within the column. In the case of the statement "C to D", unless otherwise specified, it means C or greater and D or less.

[0040] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a particular order, position, or superiority, and are used only to distinguish one element, component, assembly, region, surface, layer, section, or part from another element, component, assembly, region, area, layer, section, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, first assembly, first region, first layer, or first part described below may be referred to as a second element, second assembly, second region, second layer, or second part. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or sets of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively mean “first category (or first set),” “second category (or second set),” etc.

[0041] In this example, the DR1, DR2, and / or DR3 axes are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the DR1, DR2, and / or DR3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0042] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well. It will also be understood that when the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] When one or more embodiments can be implemented differently, the specific process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0044] As used herein, the terms “substantially,” “approximately,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% for the corresponding value. Taking into account the measurement being discussed and the errors associated with the measurement of a specific quantity (i.e., the limitations of the measurement system), “approximately” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation from the specific value as determined by one of ordinary skill in the art. For example, “approximately” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that would be tolerated by one of ordinary skill in the art. Other expressions may also omit the word “substantially.”

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless so explicitly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or in the context of this specification, and not in an idealized or overly formal sense.

[0046] In the following description, a display panel according to one or more embodiments and an electronic device according to one or more embodiments will be described with reference to the accompanying drawings.

[0047] Figure 1 This is a perspective view of an electronic device ED according to one or more embodiments of the present disclosure. Figure 1 As shown, the electronic device ED may include a display module DM that displays an image via a display surface ED-IS. The display module DM may be housed within and located within a housing HAU.

[0048] The display surface ED-IS of the electronic device ED can have a rectangular shape having a long side extending in a first direction DR1 in a plan view / when viewed on a plane and a short side extending in a second direction DR2 intersecting the first direction DR1. However, one or more embodiments of this disclosure are not limited thereto, and the display surface ED-IS can have various shapes (such as circular and polygonal shapes).

[0049] In this disclosure, the third direction DR3 can be defined as a direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2. The front (or top) and rear (or bottom) surfaces of each component constituting the electronic device ED can be opposite each other on the third direction DR3, and the normal direction of each of the front and rear surfaces can be substantially parallel to the third direction DR3. The spacing between the front and rear surfaces defined on the third direction DR3 can correspond to the thickness of the component.

[0050] The term "in a plane" as used herein can be defined as the state as viewed from a third direction DR3. That is, "in a plane" can be described based on the plane defined by the first direction DR1 and the second direction DR2 together. The term "in a section" as used herein can be defined as the state as viewed from the first direction DR1 or the second direction DR2. Furthermore, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be changed to other directions.

[0051] In one or more embodiments, the electronic device ED is shown as an electronic device having a flat display surface and including a display module DM, but is not limited thereto. Optionally, the electronic device ED may include a curved display surface or a three-dimensional display surface. For example, a three-dimensional display surface may include multiple display areas oriented in different directions and may include a curved display surface. The electronic device ED may be a flexible electronic device. A flexible electronic device may be a foldable electronic device.

[0052] Figure 1 Examples of tablet terminals as electronic devices (EDs) are shown. Electronic modules, camera modules, power modules, etc., mounted on a motherboard can be housed together with a display module (DM) in a bracket / casing, etc., thus constituting a tablet terminal. However, one or more embodiments are not limited thereto, and the display module (DD) can be applied to large-sized electronic devices (such as televisions or monitors), and also to small-to-medium-sized electronic devices (such as mobile phones, vehicle navigation devices, game consoles, or smartwatches). An electronic device (ED) including a display module (DM) can also be referred to as a display device.

[0053] like Figure 1 As shown, the display surface ED-IS includes an effective area ED-DA on which images are displayed and a border area ED-NDA adjacent to the effective area ED-DA. The border area ED-NDA is the area on which no images are displayed. Figure 1 The icon image is shown as an example of an image. The active area ED-DA can be referred to as the display area of ​​the display module DM, and the border area ED-NDA can be referred to as the non-display area of ​​the display module DM.

[0054] like Figure 1 As shown, the effective region ED-DA can have a substantially rectangular shape. “Substantially rectangular shape” includes not only a mathematically rectangular shape, but also a rectangular shape that defines curved boundaries rather than vertices on the vertex region (or corner region).

[0055] The border region ED-NDA may surround the effective region ED-DA (e.g., in a plan view). However, one or more embodiments of this disclosure are not limited thereto, and the shape of the border region ED-NDA may be varied. For example, the border region ED-NDA may be located only on one side of the effective region ED-DA.

[0056] Figure 2A This is a perspective view of a display module according to one or more embodiments of the present disclosure. Figure 2B It is a cross-sectional view of a display module according to one or more embodiments. Figure 2C It is a plan view of a display module according to one or more embodiments.

[0057] Reference Figure 2A The display module DM may include a display surface IS, and the display module DM can display images through the display surface IS. The display surface IS of the display module DM may correspond to the display surface ED-IS of the electronic device ED.

[0058] The display surface IS may include a display area DA and a non-display area NDA. A plurality of pixel units PXU may be located in the display area DA. Each of the plurality of pixel units PXU may include a plurality of pixels. Pixels are not located in the non-display area NDA. The non-display area NDA may surround the display area DA (e.g., in a plan view). However, one or more embodiments of this disclosure are not limited thereto, and in one or more embodiments of this disclosure, the non-display area NDA may be omitted or located only on one side of the display area DA.

[0059] Reference Figure 2B According to one or more embodiments, the display module DM may include a display panel DP and an optical control panel OSL located on the display panel DP. The display panel DP may include a substrate BS, a circuit layer DP-CL, and a display layer DP-ED sequentially stacked on a third-direction DR3. The optical control panel OSL may be located on the display layer DP-ED.

[0060] In one or more embodiments, the display panel DP may be referred to as the lower panel or lower display substrate, and the light control panel OSL may be referred to as the upper panel or upper display substrate.

[0061] In one or more embodiments, the fill layer FML (see...) Figure 5BThe display panel (DP) and the light control panel (OSL) can be located between the display panel (DP) and the light control panel (OSL). The display panel (DP) and the light control panel (OSL) can be positioned spaced apart from each other, with a fill layer (FML) (see [link to FML]). Figure 5B The optical control panel (OSL) is located between them. In this case, the OSL can be manufactured in a separate process and then set on the display panel (DP).

[0062] Optionally, in the display module DM according to one or more embodiments, the optical control panel OSL may be directly located on the display layer DP-ED. In this disclosure, when a component is referred to as being "directly located / set" on another component, it means that the third component is not located between the component and the other component. That is, when a component is referred to as being "directly located / directly set" on another component, it means that the component and the other component are "in contact" with each other.

[0063] In one or more embodiments, the substrate BS may be a support substrate on which a circuit layer DP-CL and a display layer DP-ED are disposed.

[0064] The DP-CL circuit layer may include at least one insulating layer and circuit elements. Circuit elements include signal lines and pixel driving circuitry, etc. The DP-CL circuit layer can be formed by processes such as coating or deposition to form insulating, semiconductor, and conductive layers, and by processes such as photolithography to pattern the insulating, semiconductor, and conductive layers.

[0065] The display layer DP-ED includes display elements. These display elements may include light-emitting elements that generate light and supply the light to the light control panel OSL. The display panel DP, including the display layer DP-ED, can supply source light to the light control panel OSL located above the display panel DP.

[0066] An optical control panel (OSL) can convert the wavelength of light supplied from a display panel (DP), or can transmit a portion of the supplied light. An OSL may include a light control unit for converting or transmitting wavelengths of light, as well as structures for increasing the light conversion efficiency of the emitted light.

[0067] Figure 2C The planar arrangement of signal lines GL1 to GLn and DL1 to DLm with pixels PX11 to PXnm is shown. Signal lines GL1 to GLn and DL1 to DLm may include multiple gate lines GL1 to GLn and multiple data lines DL1 to DLm.

[0068] Each of pixels PX11 to PXnm is connected to a corresponding gate line among multiple gate lines GL1 to GLn and a corresponding data line among multiple data lines DL1 to DLm. Each of pixels PX11 to PXnm may include a pixel driving circuit and a display element. Depending on the configuration of the pixel driving circuit of pixels PX11 to PXnm, more types of signal lines can be arranged in the display panel DP.

[0069] The gate drive circuit (GDC) can be integrated onto the display panel (DP) using either an oxide silicon gate (OSG) driver circuit or an amorphous silicon gate (ASG) driver circuit.

[0070] Figure 3 It is an enlarged plan view of a portion of a display module according to one or more embodiments.

[0071] Figure 3 The following illustration shows the location of the display module DM (see one or more embodiments) according to one or more embodiments. Figure 2A The arrangement relationship of multiple pixel regions in the display area DA in the diagram. In one or more embodiments, Figure 3 The three types of pixel regions shown, PXA-R, PXA-G, and PXA-B, can be repeatedly located throughout the entire display area DA (see [link]). Figure 2A In the image, pixel regions PXA-R, PXA-G, and PXA-B can be referred to as emission regions.

[0072] In one or more embodiments, the electronic device ED (see Figure 1 The image can include a first pixel region PXA-R, a second pixel region PXA-G, and a third pixel region PXA-B that emit light in different corresponding wavelength regions. When viewed on a plane, the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B can be divided without overlapping each other.

[0073] The first pixel region PXA-R can emit light with an emission wavelength of about 610 nm to about 700 nm, the second pixel region PXA-G can emit light with an emission wavelength of about 500 nm to about 590 nm, and the third pixel region PXA-B can emit light with an emission wavelength of about 410 nm to about 480 nm.

[0074] In one or more embodiments, the first pixel region PXA-R may be a red pixel region emitting red light, the second pixel region PXA-G may be a green pixel region emitting green light, and the third pixel region PXA-B may be a blue pixel region emitting blue light. However, one or more embodiments are not limited thereto, and in one or more embodiments, in addition to the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B, a pixel region emitting white light may also be included in the display region DA.

[0075] In one or more embodiments, a first pixel region PXA-R, a second pixel region PXA-G, and a third pixel region PXA-B can be grouped to form a pixel unit PXU. Figure 3 The arrangement of pixel regions shown is an example, and unlike the illustrated embodiment, in addition to the first to third pixel regions, a pixel unit PXU may also include pixel regions that emit light in different wavelength regions. Optionally, the number of at least one pixel region included in the first to third pixel regions in a pixel unit PXU may be two or more.

[0076] The peripheral region NPXA is located around the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. The peripheral region NPXA may be referred to as a non-emissive region. The peripheral region NPXA may be positioned in a shape surrounding each of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. The peripheral region NPXA may define the boundaries of each of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B, and may reduce or prevent color mixing between the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B. Within the peripheral region NPXA, structures (e.g., pixel-defining layers (e.g., pixel-defining films) PDL or segmented pattern BMPs) for reducing or preventing color mixing between the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may be positioned. Figure 4 )).

[0077] exist Figure 3In one or more embodiments shown, a portion of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have a rectangular shape. The remaining portions of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have a polygonal shape with protrusions extending from the rectangular shape. At least a portion of each of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have a polygonal shape with a short side extending in a first direction DR1 and a long side extending in a second direction DR2. The respective surface areas of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may be set according to the emitted color. The surface area of ​​the pixel region emitting blue light, one of the primary colors, may be the smallest, and the surface area of ​​the pixel region emitting red light, one of the primary colors, may be the largest. Optionally, the surface areas of the pixel regions emitting red light and the pixel regions emitting green light may be substantially the same.

[0078] Figure 3 A first pixel region PXA-R, a second pixel region PXA-G, and a third pixel region PXA-B having rectangular or polygonal shapes are shown, but one or more embodiments of this disclosure are not limited thereto. A portion of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have polygonal shapes (including substantially polygonal shapes) with different shapes on a plane. In one or more embodiments, each of the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B may have a rectangular shape (substantially rectangular shape) with rounded (rounded) corner regions or a polygonal shape (substantially polygonal shape) with rounded (rounded) corner regions on a plane.

[0079] In one or more embodiments, a dammed area may be defined within the display area DA. The dammed area may be the region in which the dammed area is defined to reduce or avoid printing defects included in the light control layer CCL (see [link to documentation]). Figure 5A The multiple optical control units CCP-R, CCP-G, and CCP-B (see) Figure 5A The possibility of defects due to incorrect ink application during part of the process. That is, the embankment area can be defined by removing the segmented pattern BMP (see...). Figure 5A The area formed by the dike is part of the dike.

[0080] Figure 4 It is a cross-sectional view of a portion of a display module according to one or more embodiments. Figures 5A to 5CThese are all cross-sectional views of a portion of a display module according to one or more embodiments. Figure 4 Can be with Figure 3 The cross-section corresponding to the cutting line I-I' shown corresponds to that, and Figures 5A to 5C Both can be with the same Figure 3 The section corresponding to the cutting line II-II' shown in the diagram. Figure 4 A cross-section of a display module corresponding to a pixel region is shown, and Figures 5A to 5C Each shows a cross-section of the display module corresponding to three adjacent pixel regions.

[0081] and Figure 4 different, Figures 5A to 5C The structures of the circuit layer DP-CL, the encapsulation layer TFE, and the light-emitting element LED are schematically shown. Figure 4 The same detailed structure of the display layer DP-ED shown can be applied to Figures 5A to 5C The construction of the display layer DP-ED in multiple pixel regions.

[0082] Reference Figures 4 to 5C According to one or more embodiments, the display panel DP may include a substrate BS, a circuit layer DP-CL on the substrate BS, and a display layer DP-ED on the circuit layer DP-CL (as used herein, "on" can mean "above"). The display layer DP-ED may include a discrete structure SPU, light-emitting elements LEDs including portions therein that are at least partially disconnected by the discrete structure SPU, and an encapsulation layer TFE covering the upper portion of the light-emitting elements LEDs.

[0083] The split structure SPU may include a pixel defining layer PDL, an auxiliary layer APL located on the pixel defining layer PDL, and a separator SLB located on the auxiliary layer APL. The corresponding edges of the pixel defining layer PDL, the auxiliary layer APL, and the separator SLB stacked on the third direction DR3, which is the thickness direction, may not overlap each other.

[0084] The stepped space STP can be defined on the pixel-defining layer PDL adjacent to one side of the emission opening portion OH. The stepped space STP can be a portion having an undercut shape defined by the edge of the auxiliary layer APL and the edge of the separator SLB.

[0085] A portion of the functional layer of the light-emitting element (LED) can be disconnected and positioned based on a stepped space (STP). The cavity APK can be defined by a space surrounded by a portion of the disconnected and exposed functional layer of the LED, the side surface of the auxiliary layer (APL), the bottom surface of the separator layer (SLB), and the exposed top surface of the pixel defining layer (PDL). The LED assembly may not be located within the cavity APK. The cavity APK can be a portion corresponding to an empty space in which no organic or inorganic layer is positioned.

[0086] The arrangement of the stepped space STP and the LEDs around the stepped space STP will be described in detail later.

[0087] In a display panel DP according to one or more embodiments, the substrate BS may be a component providing a reference surface on which components including those in the circuit layer DP-CL are positioned. In one or more embodiments, the substrate BS may be a glass substrate, a metal substrate, or a polymer substrate, etc. However, one or more embodiments are not limited thereto, and the substrate BS may include an inorganic layer, a functional layer, or a composite material layer.

[0088] The substrate BS can have a multilayer structure. For example, the substrate BS can have a three-layer structure comprising a polymer resin layer, an adhesive layer, and a polymer resin layer. For example, the polymer resin layer can comprise a polyimide resin. The polymer resin layer can comprise at least one of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. As used herein, the term "α-type" resin indicates a resin comprising the functional group "α".

[0089] The circuit layer DP-CL can be located on the substrate BS, and the circuit layer DP-CL can include transistors TD as circuit elements. When designing the pixel driving circuit, the construction of the circuit layer DP-CL can be changed, and in one or more embodiments, the circuit layer DP-CL can include multiple types of transistors that perform different functions.

[0090] As an example, Figure 4 A transistor TD is shown. In one or more embodiments, Figure 4 The transistor TD shown can be a driver transistor electrically connected to the light-emitting element LED. As an example, Figure 4 The arrangement of the active body AD, source SD, drain DD, and gate GD constituting the transistor TD is shown. The active body AD, source SD, and drain DD can be regions defined according to the doping concentration or conductivity of the semiconductor pattern.

[0091] In one or more embodiments, the semiconductor pattern in the transistor TD may include a metal oxide. For example, the semiconductor pattern constituting the active body AD, source SD, and drain DD of the transistor TD may include a metal oxide comprising at least one of indium, gallium, zinc, tin, and titanium. Although Figure 4 Only one transistor is shown, but the circuit layer DP-CL may include multiple transistors, and in at least one of the multiple transistors, the semiconductor pattern may include metal oxide.

[0092] Additionally, in one or more embodiments, the transistor TD may have a top-gate structure in which the gate GD is located above the semiconductor pattern.

[0093] The circuit layer DP-CL may include a lower buffer layer BRL, a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30 located on the substrate BS. For example, the lower buffer layer BRL, the first insulating layer 10, and the second insulating layer 20 may be inorganic layers, and the third insulating layer 30 may be an organic layer.

[0094] The display layer DP-ED may include light-emitting elements (LEDs) as display elements. The LEDs can generate source light. The source light generated and emitted by the LEDs can be provided to the optical control layer OSL, and in the optical control layer CCL of the OSL, at least a portion of the source light can be converted into light having a different wavelength than the source light, or at least a portion of the source light can be transmitted without wavelength conversion.

[0095] In one or more embodiments, the source light may include blue light. In one or more embodiments, the source light may be light in which blue light and light from different wavelength regions different from blue light are mixed. In one or more embodiments, the display layer DP-ED may include an organic light-emitting diode as a light-emitting element. The light-emitting element LED may include an organic light-emitting material as a light-emitting material.

[0096] The light-emitting element (LED) includes a first electrode EL1, a second electrode EL2 facing the first electrode EL1, and an emitting unit (EMU) located between the first electrode EL1 and the second electrode EL2. The LED may also include a capping layer (CPL) located on the second electrode EL2.

[0097] In one or more embodiments, the emitting unit (EMU) may include two or more emitting structures ST1, ST2, ST3, and ST4 that are separated from each other and stacked in the thickness direction. Each of the emitting structures ST1, ST2, ST3, and ST4 may include an emitting layer. That is, the light-emitting element (LED) according to one or more embodiments may be a series light-emitting element comprising multiple emitting layers stacked in the thickness direction. Additionally, the emitting unit (EMU) according to one or more embodiments may include one or more charge-generating layers CGL1, CGL2, and CGL3. Each of the charge-generating layers CGL1, CGL2, and CGL3 may be located between the stacked emitting structures ST1, ST2, ST3, and ST4.

[0098] Figure 6 This is a cross-sectional view of a light-emitting element (LED) according to one or more embodiments. (See reference...) Figure 6 According to one or more embodiments, a light-emitting element LED may include a first electrode EL1, a second electrode EL2 facing the first electrode EL1, and a first emission structure ST1, a second emission structure ST2, a third emission structure ST3 and a fourth emission structure ST4 located between the first electrode EL1 and the second electrode EL2, as well as a first charge generation layer CGL1, a second charge generation layer CGL2 and a third charge generation layer CGL3. Figure 6 The structure of the light-emitting element (LED) shown is illustrative, and the number of emitting structures constituting the LED and therefore the number of stacked charge-generating layers can vary. For example, the LED may include two or three emitting structures, or five or more emitting structures.

[0099] A stacked structure of multiple emission structures ST1, ST2, ST3, and ST4, and their respective charge generation layers CGL1, CGL2, and CGL3 located between them, can be... Figures 4 to 5C The part corresponding to the transmitting unit (EMU) shown in the diagram.

[0100] Reference Figure 6 The first charge generation layer CGL1 can be located between the first emission structure ST1 and the second emission structure ST2, the second charge generation layer CGL2 can be located between the second emission structure ST2 and the third emission structure ST3, and the third charge generation layer CGL3 can be located between the third emission structure ST3 and the fourth emission structure ST4.

[0101] Multiple emitting structures ST1, ST2, ST3, and ST4 may each include emitting layers BEML1, BEML2, BEML3, and GEML. That is, a light-emitting element LED according to one or more embodiments includes multiple emitting layers stacked in the thickness direction and may be referred to as a series light-emitting element.

[0102] In one or more embodiments, the light-emitting element (LED) can emit light in a direction from the first electrode EL1 to the second electrode EL2. The first emitting structure ST1 may include a first emitting layer BEML1, the second emitting structure ST2 may include a second emitting layer BEML2, the third emitting structure ST3 may include a third emitting layer BEML3, and the fourth emitting structure ST4 may include a fourth emitting layer GEML. Some of the emitting layers included in the first emitting structure ST1, the second emitting structure ST2, the third emitting structure ST3, and the fourth emitting structure ST4 can emit light of substantially the same color, and some of them can emit light of a different color than the remaining emitting layers.

[0103] In one or more embodiments, the first emission layer BEML1 of the first emission structure ST1, the second emission layer BEML2 of the second emission structure ST2, and the third emission layer BEML3 of the third emission structure ST3 can emit light of substantially the same first color. For example, the first color of light can be blue light. The light emitted by the first emission layer BEML1, the second emission layer BEML2, and the third emission layer BEML3 can have a wavelength range of about 420 nm to about 480 nm.

[0104] The fourth emission layer GEML of the fourth emission structure ST4 can emit light of a second color, different from the first color. For example, the second color could be green light. The light emitted by the fourth emission layer GEML can have a wavelength range of approximately 520 nm to approximately 600 nm.

[0105] The light-emitting element LED according to one or more embodiments may include at least one blue emitting structure that emits blue light and at least one green emitting structure that emits green light, and according to Figure 6 In one or more embodiments of the LED light-emitting element shown, the first emitting structure ST1, the second emitting structure ST2, and the third emitting structure ST3 can all be blue emitting structures, and the fourth emitting structure ST4 can be a green emitting structure. However, the arrangement characteristics of the emitting structures in the LED light-emitting element are not limited to the embodiments shown. (The last sentence appears to be incomplete and possibly refers to a different context.) Figure 6 Different embodiments include a number of blue and green emitting structures in the LED, and the arrangement positions of the blue and green emitting structures can be combined differently.

[0106] In the case where at least one of the multiple emitting structures ST1, ST2, ST3, and ST4 is a green emitting structure, and at least one of the remaining emitting structures is a blue emitting structure, the number of each of the green and blue emitting structures included in the light-emitting element LED and their stacking order, etc., can be determined according to the display panel DP (see...). Figure 4 The characteristics of the source light required are changed.

[0107] according to Figure 6 The light-emitting element LED shown in one or more embodiments may include, according to Figures 4 to 5C The display layer DP-ED of each of the display modules DM, DM-1, and DM-2 shown in one or more embodiments. The display layer DP-ED according to one or more embodiments, which includes light-emitting elements LEDs, may include emitted green light and emitted blue light as source light, and the source light may be transmitted to the light control layer CCL.

[0108] In an LED light-emitting element according to one or more embodiments, a plurality of emitting structures ST1, ST2, ST3, and ST4 may respectively include hole transport regions HTR1, HTR2, HTR3, and HTR4 and electron transport regions ETR1, ETR2, ETR3, and ETR4. The hole transport regions HTR1, HTR2, HTR3, and HTR4 can transport holes provided from the first electrode EL1 or the charge generation layers CGL1, CGL2, and CGL3 to the emitting layer. The electron transport regions ETR1, ETR2, ETR3, and ETR4 can transport electrons provided from the second electrode EL2 or the charge generation layers CGL1, CGL2, and CGL3 to the emitting layer.

[0109] As an example, a light-emitting element (LED) according to one or more embodiments is shown as having a structure in which hole transport regions HTR1, HTR2, HTR3, and HTR4, based on the direction of light emission, are located below emission layers BEML1, BEML2, BEML3, and GEML included in multiple emission structures ST1, ST2, ST3, and ST4, respectively, and electron transport regions ETR1, ETR2, ETR3, and ETR4 are located above emission layers BEML1, BEML2, BEML3, and GEML included in multiple emission structures ST1, ST2, ST3, and ST4, respectively. That is, the light-emitting element (LED) according to one or more embodiments can have a forward-biased device structure. However, one or more embodiments of this disclosure are not limited thereto, and the light-emitting element LED may have an inverted device structure in which electron transport regions ETR1, ETR2, ETR3 and ETR4 based on the direction of light emission are located below the emission layers BEML1, BEML2, BEML3 and GEML included in the plurality of emission structures ST1, ST2, ST3 and ST4, respectively, and hole transport regions HTR1, HTR2, HTR3 and HTR4 are located above the emission layers BEML1, BEML2, BEML3 and GEML included in the plurality of emission structures ST1, ST2, ST3 and ST4, respectively.

[0110] Hole transport regions HTR1, HTR2, HTR3, and HTR4 may include hole injection layers HIL1, HIL2, HIL3, and HIL4, and hole transport layers HTL1, HTL2, HTL3, and HTL4 respectively located on the hole injection layers HIL1, HIL2, HIL3, and HIL4. Each of the hole transport layers HTL1, HTL2, HTL3, and HTL4 may be in contact with the bottom surface of the emitter layer. However, one or more embodiments of this disclosure are not limited thereto, and hole transport regions HTR1, HTR2, HTR3, and HTR4 may also include hole-side additional layers respectively located on the hole transport layers HTL1, HTL2, HTL3, and HTL4. The hole-side additional layers may include at least one of a hole buffer layer, an emitter aid layer, and an electron blocking layer. The hole buffer layer may be a layer that compensates for the resonant distance and improves luminous efficiency according to the wavelength of light emitted from the emitter layer. The electron blocking layer may be a layer used to reduce or prevent electrons from being injected from the electron transport region into the hole transport region. Optionally, at least one of the hole transport regions HTR1, HTR2, HTR3 and HTR4 may include only one layer, and for example, the hole transport regions HTR1, HTR2, HTR3 and HTR4 may be composed of hole transport layers HTL1, HTL2, HTL3 and HTL4.

[0111] Electron transport regions ETR1, ETR2, ETR3, and ETR4 may include electron transport layers. Electron transport regions ETR1, ETR2, ETR3, and ETR4 may also include electron injection layers located on the electron transport layers. For example, the fourth electron transport region ETR4 included in the fourth emission structure ST4 may also include a fourth electron injection layer EIL4 located on the fourth electron transport layer ETL4. Electron transport regions ETR1, ETR2, ETR3, and ETR4 may also include an electron-side supplementary layer located between the electron transport layer and the emission layer. The electron-side supplementary layer may include at least one of an electron buffer layer and a hole blocking layer.

[0112] In an LED light-emitting element according to one or more embodiments, the first electrode EL1 may be a reflective electrode. For example, the first electrode EL1 may include materials with high reflectivity such as Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Zn, or Sn, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg), or materials having a multilayer structure such as LiF / Ca or LiF / Al. Optionally, the first electrode EL1 may have a multilayer structure including a reflective film and a transparent conductive film, wherein the reflective film includes the aforementioned materials, and the transparent conductive film includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), etc. For example, the first electrode EL1 may have a two-layer structure of ITO / Ag and a three-layer structure of ITO / Ag / ITO, but is not limited thereto. Furthermore, one or more embodiments are not limited thereto, and the first electrode EL1 may include the aforementioned metal material, a combination of two or more metal materials selected from the aforementioned metal materials, or an oxide of the aforementioned metal material, etc.

[0113] In an LED light-emitting element according to one or more embodiments, the second electrode EL2 can be a semi-transparent electrode or a transmissive electrode. Where the second electrode EL2 is a transmissive electrode, it can comprise a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO).

[0114] When the second electrode EL2 is a semi-transparent electrode or a reflective electrode, the second electrode EL2 may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, Yb, W, In, Zn, Sn, or compounds or mixtures thereof (e.g., AgMg, AgYb, or MgAg) or materials having a multilayer structure such as LiF / Ca or LiF / Al. Optionally, the second electrode EL2 may have a multilayer structure including a reflective film or a semi-transparent film and a transparent conductive film. The reflective film or semi-transparent film includes the aforementioned materials, and the transparent conductive film includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), etc. For example, the second electrode EL2 may include the aforementioned metallic materials, a combination of two or more metallic materials selected from the aforementioned metallic materials, or oxides of the aforementioned metallic materials, etc.

[0115] In an LED light-emitting element according to one or more embodiments, the emitting structures ST1, ST2, ST3, and ST4 may each include hole transport regions HTR1, HTR2, HTR3, and HTR4. The hole transport regions HTR1, HTR2, HTR3, and HTR4 may all comprise common hole transport materials. Each of the hole transport regions HTR1, HTR2, HTR3, and HTR4 may be formed using various methods, such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) methods, inkjet printing, laser printing, or laser-induced thermal imaging.

[0116] Each of the hole transport regions HTR1, HTR2, HTR3 and HTR4 may have a single layer made of a single material, or a single layer made of multiple different materials, or a multilayer structure with multiple layers made of multiple different materials.

[0117] Each of the emitting layers BEML1, BEML2, BEML3, and GEML may have a monolayer made of a single material, a monolayer made of multiple different materials, or a multilayer structure having multiple layers made of multiple different materials. Each of the emitting layers BEML1, BEML2, BEML3, and GEML may include a fluorescent material or a phosphorescent material. In the light-emitting element according to one or more embodiments, each of the emitting layers BEML1, BEML2, BEML3, and GEML may include a light-emitting material (such as an organic light-emitting material, an organometallic complex, or a quantum dot).

[0118] In the light-emitting element LED according to one or more embodiments, each of the emitting layers BEML1, BEML2, BEML3 and GEML may include anthracene derivatives, pyrene derivatives, fluoranthene derivatives, β-derived derivatives, dihydrobenzanthene derivatives, or triphenylene derivatives, etc. However, one or more embodiments are not limited thereto, and the emitting layers BEML1, BEML2, BEML3 and GEML may include common light-emitting materials.

[0119] The emitting structures ST1, ST2, ST3, and ST4 of the light-emitting element LED according to one or more embodiments may each include electron transport regions ETR1, ETR2, ETR3, and ETR4. Each of the electron transport regions ETR1, ETR2, ETR3, and ETR4 may have a single layer made of a single material, a single layer made of multiple different materials, or a multilayer structure having multiple layers made of multiple different materials. For example, at least a portion of the electron transport regions ETR1, ETR2, ETR3, and ETR4 may include an electron transport layer ETL4 and an electron injection layer EIL4.

[0120] Electron transport regions ETR1, ETR2, ETR3, and ETR4 can all comprise common electron transport materials. Each of the electron transport regions ETR1, ETR2, ETR3, and ETR4 can be formed using various methods, such as vacuum deposition, spin coating, casting, LB, inkjet printing, laser printing, or laser-induced thermal imaging.

[0121] The capping layer CPL may also be located on the second electrode EL2 of the light-emitting element LED according to one or more embodiments. The capping layer CPL may have a multilayer structure or a single-layer structure. In one or more embodiments, the capping layer CPL may be an organic layer or an inorganic layer. For example, in cases where the capping layer CPL comprises an inorganic material, the inorganic material may include alkali metal compounds (such as LiF) or alkaline earth metal compounds (such as MgF2), SiON, SiN. x SiO y wait.

[0122] For example, when the capping CPL includes an organic material, the organic material may include α-NPD, NPB, TPD, m-MTDATA, Alq3, CuPc, N4,N4,N4',N4'-tetra(biphenyl-4-yl)biphenyl-4,4'-diamine (TPD15) or 4,4',4"-tris(carbazole sol-9-yl)triphenylamine (TCTA), or may include epoxy resins or acrylates (such as methacrylates). The capping CPL may include aromatic amine compounds.

[0123] The capping CPL can have a refractive index of about 1.6 or greater. For example, the refractive index of the capping CPL for light with wavelengths ranging from about 550 nm to about 660 nm can be about 1.6 or greater.

[0124] When a voltage is applied, each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 can generate charges (electrons and holes) by forming complexes via a redox reaction. Subsequently, each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 can provide the generated charges to adjacent emitter structures ST1, ST2, ST3, and ST4. The first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 can double the efficiency of current generation in adjacent emitter structures ST1, ST2, ST3, and ST4, and can be used to adjust the charge balance among adjacent emitter structures ST1, ST2, ST3, and ST4.

[0125] Each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may include an n-type layer and a p-type layer. The first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may have a structure in which the n-type layer and the p-type layer are bonded to each other. However, one or more embodiments of this disclosure are not limited thereto, and the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may include only one of an n-type layer or a p-type layer. An n-type layer may be a charge generation layer that provides electrons to an adjacent stack of charge generation layers. An n-type layer may be a layer in which the substrate material is doped with an n-dopane. A p-type layer may be a charge generation layer that provides holes to an adjacent stack of charge generation layers. A p-type layer may be a layer in which the substrate material is doped with a p-dopane.

[0126] In one or more embodiments, each of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may have a thickness of about 1 angstrom (Å) to about 150 angstroms (Å). The n-dopant doped in the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 may have a concentration of about 0.1% to about 3% (and, for example, about 1% or less). When the concentration is less than about 0.1%, the effect of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 in adjusting the charge balance may be negligible. When the concentration is greater than about 3%, the luminous efficiency of the light-emitting element LED may decrease.

[0127] Each of the first charge-generating layer CGL1, the second charge-generating layer CGL2, and the third charge-generating layer CGL3 may include a charge-generating compound, which may include arylamine organic compounds, metals, metal oxides, metal carbides, or metal fluorides, or mixtures thereof. For example, arylamine organic compounds may include α-NPD, 2-TNATA, TDATA, MTDATA, spiro-TAD, or spiro-NPB. Metals may include cesium (Cs), molybdenum (Mo), vanadium (V), titanium (Ti), tungsten (W), barium (Ba), or lithium (Li). Metal oxides, metal carbides, and metal fluorides may include Re2O7, MoO3, V2O5, WO3, TiO2, Cs2CO3, BaF2, LiF, or CsF. However, the materials of the first charge-generating layer CGL1, the second charge-generating layer CGL2, and the third charge-generating layer CGL3 are not limited to the foregoing examples.

[0128] Refer again Figures 4 to 5C The first electrode EL1 of the light-emitting element LED can be directly or indirectly connected to the transistor TD, and the connection structure between the first electrode EL1 and the transistor TD can vary in one or more embodiments. The first electrode EL1 can be an anode or a cathode. The first electrode EL1 can be a pixel electrode. The first electrode EL1 can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0129] The second electrode EL2 may be opposite the first electrode EL1, with the transmitting unit (EMU) positioned between them. The second electrode EL2 may be a common electrode. The second electrode EL2 may be a cathode or an anode, but one or more embodiments are not limited thereto. For example, in the case where the first electrode EL1 is an anode, the second electrode EL2 may be a cathode, and in the case where the first electrode EL1 is a cathode, the second electrode EL2 may be an anode. The second electrode EL2 may be a transmission electrode, a semi-transmission electrode, or a reflection electrode.

[0130] The first electrode EL1 can be divided and positioned to correspond to each of the pixel regions PXA-R, PXA-G, and PXA-B. The second electrode EL2 can be configured as a common layer for the entirety of the pixel regions PXA-R, PXA-G, and PXA-B. Additionally, in one or more embodiments, the capping layer CPL can be configured as a common layer on the second electrode EL2 for the entirety of the pixel regions PXA-R, PXA-G, and PXA-B.

[0131] In a display panel DP according to one or more embodiments, the emitting unit (EMU) can be configured as a common layer for the entire pixel regions PXA-R, PXA-G, and PXA-B. However, one or more embodiments are not limited thereto, and a portion of the functional layer of the light-emitting element included in the emitting unit EMU can be divided and positioned to correspond to each of the pixel regions PXA-R, PXA-G, and PXA-B. In one or more embodiments, the charge generation layers CGL1, CGL2, and CGL3 of the light-emitting element LED can all be configured as a common layer for the entire pixel regions PXA-R, PXA-G, and PXA-B, and at least one of the charge generation layers CGL1, CGL2, and CGL3 can have a structure that is broken at the portion corresponding to the separate structure SPU that divides the pixel regions PXA-R, PXA-G, and PXA-B.

[0132] Reference Figure 4 and Figure 5A The display layer DP-ED may include a TFE (Transformer Electrode Frame) encapsulation layer that protects the LED light-emitting element. The TFE encapsulation layer may include organic or inorganic materials. The TFE encapsulation layer may have a multilayer structure in which inorganic / organic layers repeat.

[0133] Reference Figure 4 In one or more embodiments, the encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2 stacked sequentially. However, the layers constituting the encapsulation layer TFE are not limited thereto. The encapsulation layer TFE may be directly applied to the light-emitting element LED in a continuous process.

[0134] The first inorganic layer IOL1 and the second inorganic layer IOL2 protect the light-emitting element (LED) from moisture and oxygen, and the organic layer OL protects the LED from foreign matter such as dust particles. For example, the organic layer OL can reduce or avoid the possibility of dent defects in the LED caused by foreign matter introduced during the manufacturing process. In one or more embodiments, the display panel DP may also include a refractive index control layer located on the encapsulation layer TFE and improving luminous efficiency.

[0135] Both inorganic layers IOL1 and IOL2 may comprise at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium dioxide, and aluminum oxide. The organic layer OL may comprise an acrylic organic material. However, the types of materials constituting inorganic layers IOL1 and IOL2, as well as the organic layer OL, are not limited to these.

[0136] Reference Figures 4 to 5C In the display modules DM, DM-1 and DM-2 according to one or more embodiments, the optical control panels OSL, OSL-1 and OSL-2 may all be located on the encapsulation layer TFE.

[0137] Reference Figure 4 and Figure 5A In a display module DM according to one or more embodiments, the optical control panel OSL may include an optical control layer CCL comprising quantum dots. In one or more embodiments, the optical control layer CCL may be located on an encapsulation layer TFE. The optical control panel OSL may also include a color filter layer CFL located on the optical control layer CCL. The optical control panel OSL may also include a substrate layer BL.

[0138] The light control layer CCL may include a segmented pattern BMP and multiple light control units CCP-R, CCP-G, and CCP-B. The light control layer CCL may also include at least one of a first blocking layer CAP1 and a second blocking layer CAP2.

[0139] A segmented patterned photomask (BMP) can be an assembly that separates multiple photocontrol units (CCP-R, CCP-G, and CCP-B) from each other. A segmented patterned BMP can include a matrix resin and additives. The matrix resin can include various resin compositions that can be broadly referred to as binders. Additives can include binders and / or photoinitiators. Additives may also include dispersants.

[0140] The segmented pattern BMP may include a black component for blocking light. The segmented pattern BMP may include a black dye or black pigment, each of which is mixed in a matrix resin. In one or more embodiments, the black component may include carbon black, a metal (e.g., chromium), or an oxide thereof.

[0141] Segmented openings BOH1, BOH2, and BOH3, each corresponding to an emission opening OH, can be defined within the segmented pattern BMP. On a plane, each of the segmented openings BOH1, BOH2, and BOH3 can be superimposed on the emission opening OH and can have a larger surface area than the emission opening OH. That is, the segmented openings BOH1, BOH2, and BOH3 can have a larger surface area than the emission regions EA1, EA2, and EA3, respectively defined by the emission opening OH. Optical control units CCP-R, CCP-G, and CCP-B can be located inside the segmented openings BOH1, BOH2, and BOH3, respectively.

[0142] In one or more embodiments, the light control layer CCL may include a first light control unit CCP-R corresponding to the first pixel region PXA-R, a second light control unit CCP-G corresponding to the second pixel region PXA-G, and a third light control unit CCP-B corresponding to the third pixel region PXA-B. The first light control unit CCP-R may be a red light control unit that emits red light. The second light control unit CCP-G may be a green light control unit that emits green light. The third light control unit CCP-B may be a blue light control unit that emits blue light. Optionally, the third light control unit CCP-B may be a transmission light control unit that transmits and emits source light. At least one of the first light control unit CCP-R, the second light control unit CCP-G, and the third light control unit CCP-B of the light control layer CCL may include a quantum dot that converts the optical properties of the source light.

[0143] The first optical control unit CCP-R may include a first quantum dot that converts source light into light with different wavelengths. The second optical control unit CCP-G may include a second quantum dot that converts source light into light with different wavelengths. In one or more embodiments, the first quantum dot can convert source light into red light, and the second quantum dot can convert source light into green light. In one or more embodiments, the first quantum dot may be a red quantum dot, and the second quantum dot may be a green quantum dot.

[0144] In this disclosure, quantum dot refers to a crystal of a semiconductor compound. Quantum dots can emit light with various emission wavelengths depending on the size of the crystal. Quantum dots can emit light with various emission wavelengths by adjusting the ratio of elements in the semiconductor compound.

[0145] The diameter of quantum dots can range from, for example, from about 1 nm to about 10 nm. Quantum dots can be synthesized by wet chemical processes, organometallic chemical vapor deposition processes, molecular beam epitaxy processes, or similar processes.

[0146] In quantum dot manufacturing processes, wet chemistry involves mixing organic solvents and precursor materials to grow quantum dot grains. During quantum dot grain growth, the organic solvent naturally acts as a dispersant on the surface of the quantum dot crystals and allows for control of grain growth. Therefore, in wet chemistry processes, quantum dot grain growth can be controlled more effectively and at a lower cost than vapor deposition processes such as metal-organic chemical vapor deposition or molecular beam epitaxy.

[0147] The nucleus of a quantum dot can be selected from group II-VI compounds, group III-V compounds, group III-VI compounds, group I-III-VI compounds, group IV-VI compounds, group IV elements, group IV compounds and / or combinations thereof.

[0148] Group II-VI compounds may be selected from the group consisting of binary, ternary, and quaternary compounds. Binary compounds are selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and / or mixtures thereof. Ternary compounds are selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnSeS, CdSeTe, CdSeS, CdTe ... The group consisting of nS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and / or mixtures thereof, and the quaternary compound consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and / or mixtures thereof. Furthermore, group II-VI semiconductor compounds may also include group I metals and / or group IV elements. Group I-II-VI compounds may be selected from CuSnS or CuZnS, and group II-IV-VI compounds may be selected from ZnSnS, etc. Group I-II-IV-VI compounds may be selected from quaternary compounds, which are selected from the group consisting of Cu2ZnSnS2, Cu2ZnSnS4, Cu2ZnSnSe4, Ag2ZnSnS2 and / or mixtures thereof.

[0149] III-VI compounds may include binary compounds (such as In2S3 or In2Se3), ternary compounds (InGaS3 or InGaSe3), or any combination thereof.

[0150] Group I-III-VI compounds may be selected from ternary or quaternary compounds (such as AgInGaS2 or CuInGaS2), with ternary compounds selected from the group consisting of AgInS, AgInS2, CuInS, CuInS2, AgGaS2, CuGaS2, CuGaO2, AgGaO2, AgAlO2 and / or mixtures thereof.

[0151] III-V group compounds may be selected from the group consisting of binary, ternary and quaternary compounds. Binary compounds are selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and / or mixtures thereof. Ternary compounds are selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb and / or mixtures thereof. Quaternary compounds are selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and / or mixtures thereof. Furthermore, group III-V compounds may also include group II metals. For example, group III-II-V compounds may be selected from InZnP, etc.

[0152] Group IV-VI compounds may be selected from the group consisting of binary, ternary, and quaternary compounds. Binary compounds are selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and / or mixtures thereof. Ternary compounds are selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and / or mixtures thereof. Quaternary compounds are selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and / or mixtures thereof.

[0153] Examples of II-IV-V group compounds may include ternary compounds selected from the group consisting of ZnSnP, ZnSnP2, ZnSnAs2, ZnGeP2, ZnGeAs2, CdSnP2 and CdGeP2 and / or mixtures thereof.

[0154] Group IV elements may be selected from the group consisting of Si, Ge, and / or mixtures thereof. Group IV compounds may be binary compounds selected from the group consisting of SiC, SiGe, and / or mixtures thereof.

[0155] Each element included in a multi-element compound (such as binary, ternary, and quaternary compounds) can exist in the particles at a uniform or non-uniform concentration. That is, the chemical formula representing a quantum dot indicates the type of element included in the quantum dot compound, and the ratio of elements in the compound can vary.

[0156] Here, binary, ternary, or quaternary compounds can exist in the particle at a uniform concentration, or they can exist in the same particle while being divided into different concentration distributions. Furthermore, quantum dots can have a core-shell structure in which one quantum dot surrounds another. In the core-shell structure, the quantum dots can have a concentration gradient in which the concentration of the elements present in the shell gradually decreases towards the core.

[0157] In some embodiments, quantum dots may have the aforementioned core-shell structure, comprising a core with nanocrystals and a shell surrounding the core. The shell of the quantum dot can serve as a protective layer to reduce or prevent chemical modification of the core to maintain semiconductor properties and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell can have a single-layer or multi-layer structure. Examples of shells for quantum dots may include metal oxides or non-metal oxides, semiconductor compounds, or combinations thereof.

[0158] For example, metal oxides or non-metal oxides may include binary compounds (such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, or NiO) or ternary compounds (such as MgAl2O4, CoFe2O4, NiFe2O4, or CoMn2O4), but one or more embodiments of this disclosure are not limited thereto.

[0159] Additionally, examples of semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, and AlSb, but one or more embodiments of this disclosure are not limited thereto.

[0160] For example, in cases where the quantum dots of group III-VI compounds have a core-shell structure, the core may comprise InP or InZnP, and the shell may comprise ZnSeS or a double-shell structure having ZnSe / ZnS. However, one or more embodiments are not limited thereto, and the quantum dots may have a combination of core and shell selected from the aforementioned semiconductor compounds.

[0161] Quantum dots can have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or smaller (e.g., about 40 nm or smaller, or even 30 nm or smaller), and within this range, color purity or color reproducibility can be improved. Furthermore, light emitted through such quantum dots is emitted in all directions, thereby improving the viewing angle of light.

[0162] The form of quantum dots is the commonly used form in related fields and is not particularly limited. For example, spherical, conical, multi-branched, or cubic nanoparticles, or nanotubes, nanowires, nanofibers, or nanoplates can be used.

[0163] In quantum dots, the band gap can be adjusted by modifying the size of the quantum dots or the ratio of elements in the quantum dot compound, thus allowing light to be obtained in various wavelengths within the quantum dot emitting layer. Therefore, quantum dots as described above (with different sizes or different element ratios in the quantum dot compound) can be used to realize light-emitting elements that emit light with several wavelengths. For example, the size of the quantum dots or the ratio of elements in the quantum dot compound can be selectively adjusted to emit red, green, and / or blue light. Quantum dots can be constructed to emit white light by combining various colors of light.

[0164] In one or more embodiments, as the particle size of the quantum dots decreases, the quantum dots can emit light in a shorter wavelength range. For example, among quantum dots with the same core, the particle size of quantum dots emitting green light can be smaller than the particle size of quantum dots emitting red light. Similarly, among quantum dots with the same core, the particle size of quantum dots emitting blue light can be smaller than the particle size of quantum dots emitting green light. However, one or more embodiments are not limited to this, and even among quantum dots with the same core, their particle size can be adjusted according to the material constituting the shell and the shell thickness, etc.

[0165] Furthermore, in cases where quantum dots have various emission colors (such as blue, red, and green), quantum dots with different emission colors can be different from each other in terms of nuclear materials.

[0166] The first optical control unit CCP-R can correspond to the first pixel area (red emission area) PXA-R (see...). Figure 5A The second light control unit CCP-G can correspond to the second pixel area (green emission area) PXA-G (see...). Figure 5A The third light control unit CCP-B can correspond to the third pixel area (blue emission area) PXA-B (see...). Figure 5A ).

[0167] In one or more embodiments, the first light control unit CCP-R may include red quantum dots, and the second light control unit CCP-G may include green quantum dots. The first light control unit CCP-R, the second light control unit CCP-G, and the third light control unit CCP-B may all include a matrix resin. The first light control unit CCP-R, the second light control unit CCP-G, and the third light control unit CCP-B may also each include a scattering element.

[0168] In one or more embodiments, the third optical control unit CCP-B may not include quantum dots. However, one or more embodiments are not limited thereto, and the third optical control unit CCP-B may also include quantum dots in which light undergoes wavelength conversion to a wavelength region different from the wavelength regions of the first optical control unit CCP-R and the second optical control unit CCP-G.

[0169] In one or more embodiments, the scatterer can uniformly scatter and emit light incident on the optical control units CCP-R, CCP-G, and CCP-B. The scatterer can scatter and emit source light, or scatter and emit light converted from the wavelength of the source light.

[0170] The scatterer can have a spherical shape with a diameter between tens and hundreds of nanometers. For example, in one or more embodiments, the diameter of the scatterer can be from about 50 nm to about 300 nm. For example, in one or more embodiments, the diameter of the scatterer can be about 200 nm.

[0171] The scatterer may include inorganic particles. For example, the scatterer may include TiO2, BaTiO3, ZnO, ZnS, Al2O3, SiO2, or hollow silicon dioxide, etc.

[0172] The matrix resin is the medium in which quantum dots and scatterers are dispersed, and may include various resin compositions commonly referred to as binders. For example, the matrix resin may be an acrylate resin portion, a urethane resin portion, a silicone resin portion, or an epoxy resin portion, etc. The matrix resins included in the first light control unit CCP-R, the second light control unit CCP-G, and the third light control unit CCP-B may be the same, or the matrix resin portion in at least one light control unit may be different from the matrix resin portions in the other light control units.

[0173] In one or more embodiments, the optical control layer CCL may include barrier layers CAP1 and CAP2. Barrier layers CAP1 and CAP2 can be used to reduce or prevent the penetration of moisture and / or oxygen (hereinafter referred to as "moisture / oxygen") and adjust the refractive index to improve the optical properties of the optical control layer CCL. Barrier layers CAP1 and CAP2 may be located above or below the optical control units CCP-R, CCP-G, and CCP-B. Barrier layers CAP1 and CAP2 may be located on an upper surface or a lower surface of the optical control units CCP-R, CCP-G, and CCP-B, thereby reducing or preventing the optical control units CCP-R, CCP-G, and CCP-B from being exposed to moisture / oxygen. For example, barrier layers CAP1 and CAP2 can reduce or prevent the quantum dots included in the optical control units CCP-R, CCP-G, and CCP-B from being exposed to moisture / oxygen. Barrier layers CAP1 and CAP2 can also protect the optical control units CCP-R, CCP-G, and CCP-B from external impacts.

[0174] In one or more embodiments, a first blocking layer CAP1 may be positioned spaced apart from the display layer DP-ED, with the light control units CCP-R, CCP-G, and CCP-B located between them. That is, the first blocking layer CAP1 may be located on the respective top surfaces of the light control units CCP-R, CCP-G, and CCP-B. In one or more embodiments, the light control panel OSL may further include a second blocking layer CAP2 located between the light control units CCP-R, CCP-G, and CCP-B and the display layer DP-ED. In one or more embodiments, the first blocking layer CAP1 may cover the top surfaces of the light control units CCP-R, CCP-G, and CCP-B, and the second blocking layer CAP2 may cover the respective bottom surfaces of the light control units CCP-R, CCP-G, and CCP-B adjacent to the display layer DP-ED. Furthermore, in this disclosure, the term "top surface" may refer to a surface placed on top of the third-direction DR3, and the term "bottom surface" may refer to a surface placed on the bottom of the third-direction DR3.

[0175] In addition to the light control units CCP-R, CCP-G, and CCP-B, each of the first blocking layer CAP1 and the second blocking layer CAP2 can also cover one surface of the segmented pattern BMP.

[0176] Both the first barrier layer CAP1 and the second barrier layer CAP2 may comprise inorganic materials. In one or more embodiments, the first barrier layer CAP1 comprises silicon oxynitride (SiON). Each of the first barrier layer CAP1 and the second barrier layer CAP2 may comprise silicon oxynitride. However, one or more embodiments of this disclosure are not limited thereto. For example, the first barrier layer CAP1 may comprise silicon oxynitride, and the second barrier layer CAP2 may comprise silicon oxide (SiO2). x ).

[0177] The optical control panel OSL may also include a color filter layer CFL located on the optical control layer CCL. The color filter layer CFL includes one or more color filters CF1, CF2, and CF3. The color filters transmit light within a corresponding wavelength range and block light within wavelength ranges other than their corresponding wavelength range. In one or more embodiments, the first color filter CF1 may be a red color filter that transmits red light, the second color filter CF2 may be a green color filter that transmits green light, and the third color filter CF3 may be a blue color filter that transmits blue light.

[0178] Each of the color filters CF1, CF2, and CF3 includes a polymeric photosensitive resin and a colorant. The colorant may include a pigment or a dye. The first color filter CF1 may include a red pigment or a red dye, the second color filter CF2 may include a green pigment or a green dye, and the third color filter CF3 may include a blue pigment or a blue dye. In one or more embodiments, the third color filter CF3 may not contain a pigment or dye.

[0179] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can correspond to the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B, respectively. Furthermore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be superimposed on the first light control unit CCP-R, the second light control unit CCP-G, and the third light control unit CCP-B, respectively.

[0180] In the color filter layer CFL, multiple color filters CF1, CF2, and CF3 that transmit different light can be stacked on top of each other when corresponding to the peripheral region NPXA. When corresponding to the peripheral region NPXA, the multiple color filters CF1, CF2, and CF3 can be stacked on top of each other on the third direction DR3, which is the thickness direction, thereby defining the boundaries between adjacent pixel regions PXA-R, PXA-G, and PXA-B. In one or more embodiments, the color filter layer CFL may include light-blocking portions as components that define the boundaries between adjacent color filters among the color filters CF1, CF2, and CF3. In one or more embodiments, the light-blocking portions may be configured as blue color filters or include organic or inorganic light-blocking materials that all contain black pigments or black dyes.

[0181] The optical control panel OSL may also include a low-refractive-index layer LR located between the optical control layer CCL and the color filter layer CFL. The low-refractive-index layer LR may be located directly on the first blocking layer CAP1, and the color filter layer CFL may be located directly on the low-refractive-index layer LR.

[0182] The low-refractive-index layer LR can be located above the optical control layer CCL and can reduce or prevent the optical control units CCP-R, CCP-G, and CCP-B from being exposed to moisture / oxygen. Additionally, the low-refractive-index layer LR can serve as an optical functional layer located between the optical control units CCP-R, CCP-G, and CCP-B and the color filters CF1, CF2, and CF3, increasing light extraction efficiency or reducing or preventing reflected light from incident on the optical control layer CCL. The low-refractive-index layer LR can be a layer with a lower refractive index than adjacent layers.

[0183] The low-refractive-index layer (LR) may include at least one inorganic layer. For example, the LR may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride, as well as a metal thin film with light transmittance. However, one or more embodiments are not limited thereto, and the LR may include an organic film. The LR may have a structure in which, for example, multiple hollow particles are dispersed in an organic polymer resin. The LR may include a single layer or multiple layers.

[0184] In the optical control panel OSL according to one or more embodiments, the substrate layer BL may be a component providing a reference surface on which color filter layers CFL and light control layers CCL, etc., are positioned. The substrate layer BL may be a glass substrate, a metal substrate, or a plastic substrate, etc. However, one or more embodiments are not limited thereto, and the substrate layer BL may be an inorganic layer, an organic layer, or a composite material layer. Optionally, unlike the embodiments shown, the substrate layer BL may be omitted in one or more embodiments.

[0185] Figure 5B and Figure 5C Each of these is a cross-sectional view showing a portion of a display module according to one or more embodiments. Figure 5B and Figure 5C The display module shown according to one or more embodiments is similar in construction to the reference optics control panel. Figure 4 and Figure 5A The description of the display module varies according to one or more embodiments. In the following, reference will be made to... Figure 5B and Figure 5C By avoiding reference Figure 4 and Figure 5A The description focuses on commonalities and primarily on differences in the display modules according to one or more embodiments.

[0186] Reference Figure 5B According to one or more embodiments, the display module DM-1 may include a display panel DP and a light control panel OSL-1 located on the display panel DP. The display panel DP includes a substrate BS, a circuit layer DP-CL located on the substrate BS, and a display layer DP-ED located on the circuit layer DP-CL. The light control panel OSL-1 may include a light control layer CCL, a low refractive index layer LR, a color filter layer CFL, and a substrate layer BL. According to one or more embodiments, the display module DM-1 may also include a fill layer FML located between the display panel DP and the light control panel OSL-1.

[0187] Figure 5B The display module DM-1 can be set up by manufacturing a display panel DP, manufacturing a light control panel OSL-1, and then combining the display panel DP and the light control panel OSL-1 with a filler layer FML between them. In the display panel DP, the circuit layer DP-CL and the display layer DP-ED are located on the top surface of the substrate BS, which serves as the substrate surface. In the light control panel OSL-1, the color filter layer CFL and the light control layer CCL are located on one surface of the substrate layer BL, which serves as the substrate surface.

[0188] In one or more embodiments, the fill layer FML can fill the space between the display panel DP and the light control panel OSL-1. The fill layer FML can be located directly on the encapsulation layer TFE, and the second barrier layer CAP2 can be located directly on the fill layer FML.

[0189] In one or more embodiments, the filler layer FML can perform shock absorption functions, etc., and can increase the strength of the display module DM-1. The filler layer FML can be made of a filler resin including a polymer resin. For example, the filler layer FML can be made of a filler resin including acrylic resin or epoxy resin, etc.

[0190] In the display module DM-1 according to one or more embodiments, a stepped portion may be formed between the bottom surface of the segmented pattern BMP and the bottom surface of each of the light control units CCP-R, CCP-G, and CCP-B. A second blocking layer CAP2 may be positioned between the segmented pattern BMP and each of the light control units CCP-R, CCP-G, and CCP-B simultaneously with the stepped portion. In the second blocking layer CAP2, a fill layer FML may be located directly below the second blocking layer CAP2 and cover the stepped portion of the light control layer CCL.

[0191] Reference Figure 5C The display module DM-2 according to one or more embodiments may include a display panel DP and a light control panel OSL-2 located on the display panel DP. The display panel DP includes a substrate BS, a circuit layer DP-CL located on the substrate BS, and a display layer DP-ED located on the circuit layer DP-CL. In the display module DM-2 according to one or more embodiments, the light control panel OSL-2 may include a light control layer CCL, a low refractive index layer LR, a color filter layer CFL-1, and a substrate layer BL, which are sequentially stacked on the encapsulation layer TFE.

[0192] The light control layer CCL may include a segmented pattern BMP and light control units CCP-R, CCP-G, and CCP-B, each of which is located between the segmented patterns BMP. The light control layer CCL may include a first blocking layer CAP1 and a second blocking layer CAP2 located on the top and bottom surfaces of each of the light control units CCP-R, CCP-G, and CCP-B (e.g., contacting the top and bottom surfaces of each of the light control units CCP-R, CCP-G, and CCP-B).

[0193] The light control layer CCL can be located on the display layer DP-ED. The low refractive index layer LR can be located on the light control layer CCL. The color filter layer CFL-1 may include multiple color filters CF1, CF2 and CF3 and a light blocking part BM.

[0194] and Figure 5B Compared to the display module DM-1 shown, according to Figure 5C The display module DM-2 shown in one or more embodiments corresponds to one or more embodiments in which the light control layer CCL, the low refractive index layer LR, and the color filter layer CFL-1 are located on the top surface of the encapsulation layer TFE, which serves as the substrate surface. That is, the light control layer CCL can be formed on the encapsulation layer TFE by a continuous process, and the low refractive index layer LR and the color filters CF1, CF2, and CF3 of the color filter layer CFL-1 can be formed sequentially on the light control layer CCL by a continuous process.

[0195] exist Figure 5C In one or more embodiments shown, the color filter layer CFL-1 may have the same characteristics as according to... Figure 5A and Figure 5B The color filter layers (CFLs) in each of the one or more embodiments shown in the figure have different shapes.

[0196] In the color filter layer CFL-1 according to one or more embodiments, the light-blocking portion BM can be a black matrix. The light-blocking portion BM can include organic or inorganic light-blocking materials, each containing black pigment or black dye. The light-blocking portion BM can reduce or prevent light leakage and can define the boundaries between adjacent color filters among color filters CF1, CF2, and CF3.

[0197] exist Figures 4 to 5C In one or more embodiments shown, the pixel defining layer (PDL) included in the display panel (DP) may be an organic layer. An emission opening portion (OH) is defined in the pixel defining layer (PDL). The emission opening portion (OH) of the pixel defining layer (PDL) exposes at least a portion of the first electrode (EL1). Emission regions (EA1, EA2, and EA3) may be defined by the emission opening portion (OH).

[0198] The pixel defining layer (PDL) can be made of a polymer resin. For example, the pixel defining layer PDL may include a polyacrylate resin or a polyimide resin. In addition to polymer resins, the pixel defining layer PDL may also include inorganic materials. The pixel defining layer PDL may include light-absorbing materials or include black pigments or black dyes. A pixel defining layer PDL including black pigments or black dyes can constitute a black pixel defining layer. When forming the pixel defining layer PDL, carbon black or the like can be used as a black pigment or black dye, but one or more embodiments are not limited thereto.

[0199] The pixel-defining layer (PDL) can be made of inorganic materials. For example, the pixel-defining layer (PDL) can be made of inorganic materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y Made from ).

[0200] The display layer DP-ED may include a first emission region EA1, a second emission region EA2, and a third emission region EA3. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may be regions defined by a pixel definition layer (PDL). The first emission region EA1, the second emission region EA2, and the third emission region EA3 may correspond to a first pixel region PXA-R, a second pixel region PXA-G, and a third pixel region PXA-B, respectively. In one or more embodiments, pixel regions PXA-R, PXA-G, and PXA-B may be regions defined by color filters CF1, CF2, and CF3.

[0201] The first pixel region PXA-R may be the region corresponding to the first emission region EA1 and the first light control unit CCP-R, the second pixel region PXA-G may be the region corresponding to the second emission region EA2 and the second light control unit CCP-G, and the third pixel region PXA-B may be the region corresponding to the third emission region EA3 and the third light control unit CCP-B. According to one or more embodiments of the electronic device, the first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B, which respectively emit light in different wavelength regions, may be arranged sequentially in the first direction DR1.

[0202] In this disclosure, when two components are “corresponding” to each other, it can mean that the two components are stacked on top of each other when viewed in the thickness direction of the electronic device ED, and is not limited to the meaning that the two components have the same surface area.

[0203] The auxiliary layer (APL) can be located on the pixel limiting layer (PDL). The auxiliary layer (APL) can be located directly between the pixel limiting layer (PDL) and the separator (SLB). The auxiliary layer (APL) can be a sacrificial layer used to pattern the separator (SLB) and other elements above it.

[0204] The auxiliary layer (APL) can be a layer comprising a transparent metal oxide. Alternatively, the auxiliary layer (APL) can be a layer comprising an amorphous transparent metal oxide.

[0205] In one or more embodiments, the transparent metal oxide included in the auxiliary layer APL can crystallize at a temperature of about 260°C or higher. Because the auxiliary layer APL includes a metal oxide material that crystallizes at a temperature of about 260°C or higher, the auxiliary layer APL can be etched appropriately after the curing process for the spacer SLB above the auxiliary layer APL, exhibiting excellent selectivity.

[0206] The auxiliary layer APL may comprise indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO). In one or more embodiments, the auxiliary layer APL may be made of indium zinc oxide. When the auxiliary layer APL is made of indium zinc oxide, the weight ratio of indium to zinc may be from about 9:1 to about 1:1. For example, the weight ratio of indium to zinc may be about 9:1, about 4:1, about 7:3, about 3:2, or about 1:1. Alternatively, when the auxiliary layer APL is made of indium gallium zinc oxide, the weight ratio of indium to zinc may be from about 9:1 to about 1:1. For example, the weight ratio of indium to zinc may be about 9:1, about 4:1, about 7:3, about 3:2, or about 1:1.

[0207] In one or more embodiments, where the auxiliary layer APL is made of indium zinc oxide, the weight of indium can be greater than the weight of zinc. Therefore, the auxiliary layer APL can exhibit the property of crystallizing at temperatures of about 260°C or higher.

[0208] In one or more embodiments, the separator SLB may be located on the auxiliary layer APL, and the edge of the separator SLB may protrude further than the edge of the auxiliary layer APL toward the emission opening portion OH. The separator SLB may be an organic film comprising a black component.

[0209] The separator SLB may include a black dye or a black pigment, each of which is mixed in the matrix resin. In one or more embodiments, the black component may include carbon black, a metal (such as chromium), or an oxide thereof.

[0210] The spacer SLB can be located on the pixel definition layer PDL, without overlapping with the emission regions EA1, EA2, and EA3. The spacer SLB can be located between adjacent emission regions EA1, EA2, and EA3 in the first direction DR1, such that the spacer SLBs are spaced apart from each other. Furthermore, each spacer SLB can correspond to the space between adjacent pixel regions PXA-R, PXA-G, and PXA-B in the first direction DR1.

[0211] Because the separator SLB includes a black component, it can reduce or prevent light generated and emitted from each of the emission regions EA1, EA2, and EA3 from propagating to adjacent pixel regions. The separator SLB can also absorb light generated and emitted from each of the emission regions EA1, EA2, and EA3 onto the side surface.

[0212] The display panel according to one or more embodiments may include a separator SLB containing a black component, thereby reducing reflections due to external light and reducing color mixing between adjacent pixel areas to achieve excellent color matching rate and color reproduction.

[0213] In one or more embodiments, the separator SLB may include a black component and may define a space having an undercut shape on the pixel definition layer PDL, thereby serving as a separator structure for the emission region and as a light blocking structure for blocking light incident in the lateral direction.

[0214] Figure 7 It is a cross-sectional view showing a portion of a display panel according to one or more embodiments. Figure 8 It is shown Figure 7 An enlarged sectional view of region XX in the diagram. Figure 7 and Figure 8 Selectively shown Figures 4 to 5C The components shown are only some of the components in the display layer.

[0215] Reference Figure 7 and Figure 8 In a display panel according to one or more embodiments, the auxiliary layer APL and the separator SLB may be stacked on top of each other on the pixel defining layer PDL. The edge SLB-E of the separator SLB may be exposed to one side of the emission opening portion OH, and the edge SLB-E of the separator SLB may protrude further to the side of the emission opening portion OH than the edge APL-E of the auxiliary layer APL.

[0216] The stepped space STP can be a space defined by the bottom surface BS-SLB of the separator SLB and the side surface of the auxiliary layer APL, the side surface of the auxiliary layer APL being the edge APL-E of the auxiliary layer APL exposed to the side of the emission opening portion OH. The stepped space STP defined by the separator SLB and the auxiliary layer APL can have an undercut shape. That is, the separator SLB can include a region that does not overlap with the auxiliary layer APL, such that a portion of the bottom surface of the separator SLB is exposed.

[0217] The auxiliary layer APL can have a thickness of approximately 100 Å to approximately 1000 Å. AP For example, the thickness t of the auxiliary layer APL AP The thickness can be from approximately 300 Å to approximately 500 Å. Since the auxiliary layer APL has a thickness of approximately 100 Å to approximately 1000 Å, the step space STP can be stably defined when the spacer SLB is provided. Furthermore, since the auxiliary layer APL has a thickness of approximately 100 Å to approximately 1000 Å, the encapsulation layer TFE (see...) can be reduced or prevented. Figure 4 Wrinkling or folding at the STP portion of the stepped space.

[0218] The stepped space STP can have a width W of approximately 0.5 μm or greater. AP The width W of the stepped space STP APThis corresponds to the width of the exposed portion of the bottom surface BS-SLB of the separator SLB that is not superimposed on the auxiliary layer APL. The separator SLB is configured such that the width W of the step space STP... AP With a thickness of approximately 0.5 μm or greater, at least a portion of the components of the emitter unit can be disconnected within the step space STP, and the TFE of the encapsulation layer can be reduced or prevented (see [link to encapsulation layer]). Figure 4 Wrinkling or folding at the STP portion of the stepped space.

[0219] The side surface SS-SLB of the separator SLB can have a tilt angle θ of about 50 degrees to about 90 degrees. For example, the side surface SS-SLB of the separator SLB can have a tilt angle θ of about 55 degrees or greater, thereby providing an undercut structure below the separator SLB, allowing the charge generation layer, etc., to be properly disconnected. The tilt angle θ of the side surface SS-SLB of the separator SLB can be based on the substrate BS (see [reference]) on a cross-section defined by the first direction DR1 and the third direction DR3. Figure 4 (From the angle of)

[0220] When forming the spacer SLB, the tilt angle θ of the side surface SS-SLB of the spacer SLB can be adjusted according to changes in process conditions. The tilt angle θ, which is the cone angle, can be controlled by adjusting the curing process after setting the resin used to form the spacer SLB.

[0221] At least one of the charge-generating layers CGL1, CGL2, and CGL3 can be disconnected in the step space STP. (Refer to...) Figure 7 and Figure 8 In one or more embodiments, among the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3, the first charge generation layer CGL1 and the second charge generation layer CGL2 may be disconnected based on the step space STP. Additionally, the third charge generation layer CGL3 may remain connected to be stacked with the separator SLB and the first electrode EL1, etc. However, Figure 7 and Figure 8 This is illustrative, and unlike the illustrated embodiment, only the first charge generation layer CGL1 can be disconnected, or instead, all of the first charge generation layer CGL1, the second charge generation layer CGL2, and the third charge generation layer CGL3 can be disconnected.

[0222] Reference Figure 7 and Figure 8At least one of the emitter structures ST1, ST2, ST3, and ST4 can be disconnected based on the step space STP. In one or more embodiments, among the first emitter structure ST1, the second emitter structure ST2, the third emitter structure ST3, and the fourth emitter structure ST4, the first emitter structure ST1 and the second emitter structure ST2 can be disconnected based on the step space STP. Additionally, the third emitter structure ST3 and the fourth emitter structure ST4 can be continuously connected to be stacked with the separator SLB and the first electrode EL1, etc. However, Figure 7 and Figure 8 This is illustrative; unlike the illustrated embodiment, only the first transmitting structure ST1 can be disconnected, or instead, all of the first transmitting structure ST1, the second transmitting structure ST2, and the third transmitting structure ST3, or even all of the first transmitting structure ST1, the second transmitting structure ST2, the third transmitting structure ST3, and the fourth transmitting structure ST4, can be disconnected. Furthermore, when a transmitting structure is disconnected, it is not limited to the complete disconnection of the hole transport region, the emission layer, and the electron transport region constituting the transmitting structure. For example, only a portion of the hole transport region, the emission layer, and the electron transport region constituting the transmitting structure can be disconnected, and even if the transmitting structure remains stationary without disconnection, a portion of the hole transport region, the emission layer, and the electron transport region can be disconnected.

[0223] In the components of the light-emitting element, only the charge generation layers CGL1, CGL2, and CGL3 can be disconnected within the step space STP, while the emitting structures ST1, ST2, ST3, and ST4 can all be set to share the same layer without being disconnected.

[0224] Reference Figure 7 and Figure 8 In one or more embodiments, the cavity APK may be defined by a space surrounded by a portion of the third emitting structure ST3 of the light-emitting element LED, the edge APL-E of the auxiliary layer APL, a portion of the bottom surface BS-SLB of the separator SLB, and an exposed portion of the top surface of the pixel defining layer PDL. The assembly of the light-emitting element LED may not be located within the cavity APK. The cavity APK may be an empty space in which the emitting structure and the charge generating layer are not located. The cavity APK may not be a completely sealed space, and cracks or holes may have formed in the portion of the cavity APK defining the assembly of the light-emitting element LED.

[0225] In one or more embodiments, one end CL-a of the charge generation layer disconnected in the step space STP (e.g., one end of the first portion CGL1-a) may be located on or above the pixel defining layer PDL, and the other end CL-b of the charge generation layer disconnected in the step space STP (e.g., one end of the second portion CGL1-b) may be located on or above the separator SLB.

[0226] exist Figure 7 and Figure 8 In one or more embodiments shown, the first charge generation layer CGL1 and the second charge generation layer CGL2 may each include first portions CGL1-a and CGL2-a and second portions CGL1-b and CGL2-b, each of which is disconnected and separated. The first portions CGL1-a and CGL2-a may be located in the emission opening portion OH, and their second portions CGL1-b and CGL2-b may be located on the upper side of the separator SLB.

[0227] Additionally, the first emission structure ST1 and the second emission structure ST2 may each include first portions ST1-a and ST2-a and second portions ST1-b and ST2-b, each of which can be disconnected and separated. One end of each of the first portions ST1-a and ST2-a may be located on or above the pixel defining layer PDL, and one end of each of the second portions ST1-b and ST2-b may be located on or above the separator SLB. The first portions ST1-a and ST2-a of the first emission structure ST1 and the second emission structure ST2 may be located in the emission opening portion OH, and their second portions ST1-b and ST2-b may be located on the upper side of the separator SLB. Cracks CRL can be generated in the third emission structure ST3, the fourth emission structure ST4, and the third charge generation layer CGL3. Cracks CRL can be generated by bending due to the step space STP. Due to the cracks CRL, each of the third emission structure ST3, the fourth emission structure ST4, and the third charge generation layer CGL3 may include portions that do not easily allow charge transfer, etc.

[0228] The third emission structure ST3 and the fourth emission structure ST4 may each comprise a first portion ST3-a and ST4-a, and a second portion ST3-b and ST4-b, respectively, based on the crack CRL division. Additionally, the third charge generation layer CGL3 may comprise a first portion CGL3-a and a second portion CGL3-b, also based on the crack CRL division. Therefore, as an example, the emission structures ST1, ST2, ST3, and ST4, and the charge generation layers CGL1, CGL2, and CGL3, may be discontinuous due to the crack CRL.

[0229] Figure 8The illustration shows the generation of cracks CRLs throughout the third emitter structure ST3, the third charge generation layer CGL3, and the fourth emitter structure ST4 to correspond to the broken portions; however, one or more embodiments are not limited thereto. For example, cracks CRLs may be generated only in a portion of the third emitter structure ST3, the third charge generation layer CGL3, and / or the fourth emitter structure ST4, or each of the third emitter structure ST3, the third charge generation layer CGL3, and the fourth emitter structure ST4 may be configured as a common layer for the entire emitter region without cracks CRLs.

[0230] In one or more embodiments, a portion of the charge generation layers CGL1, CGL2, and CGL3 may be disconnected in the step space STP, thereby reducing or preventing charge transfer along the charge generation layers to adjacent emission regions. Therefore, even if the emission unit EMU (see...) is located within this space... Figure 4 For pixel regions PXA-R, PXA-G, and PXA-B (see...) Figure 4 When the layer is set to a common layer, it can also reduce or prevent the number of transmission units (EMU) from being in the EMU (see...). Figure 4 The transfer of charge or excitons in the emission region to adjacent pixel regions can reduce or prevent leakage emission in adjacent emission regions when driving the selected emission region.

[0231] In other words, in a display panel according to one or more embodiments, the display layer may include an auxiliary layer APL and a separator SLB defining a step space STP, thereby causing a portion of the functional layer of the light-emitting element LED to be disconnected in the step space STP, thereby reducing or preventing unwanted leakage emission in the emission area to present excellent display quality and color reproduction.

[0232] Figure 9A and Figure 9B All are cross-sectional views showing a portion of a display panel according to one or more embodiments. Figure 9A and Figure 9B Selectively, only the stacked structure of each of the separators SLB-1 and SLB-2 located on the pixel-defined layer PDL and the auxiliary layer APL is shown.

[0233] according to Figure 9A and Figure 9B The display panels DP-a and DP-b of one or more embodiments shown are similar in shape to those according to reference. Figures 4 to 8 The display panels described in one or more embodiments differ. (See also...) Figure 9AThe tilt angle θ of the side surface SS-SLB of the separator SLB-1 can be approximately 90 degrees. Optionally, in one or more embodiments, the tilt angle θ of the side surface SS-SLB of the separator SLB-1 can be greater than approximately 90 degrees, and the separator SLB-1 can have an inverted conical shape in cross-section.

[0234] Reference Figure 9B The side surface SS-SLB of the separator SLB-2 may include a curved surface, and the tilt angle θ of the side surface SS-SLB may be greater than approximately 90 degrees. Here, the tilt angle θ of the side surface SS-SLB may be a tilt angle formed by the tangent of the side surface SS-SLB.

[0235] In addition, Figure 9A and Figure 9B In one or more embodiments, the step space STP may be defined between each of the separators SLB-1 and SLB-2 and the auxiliary layer APL. See reference... Figures 4 to 8 As described, a portion of the functional layer of the light-emitting element can be disconnected in the step space STP.

[0236] In one or more embodiments, the tilt angle θ of the side surface SS-SLB of the separator SLB-1 may be greater than about 90 degrees, and the separator SLB-1 may have an inverted conical shape in cross-section.

[0237] Figure 10A and Figure 10B These are all plan views showing a portion of a display panel according to one or more embodiments. As an example, Figure 10A and Figure 10B The planar arrangement shape of the launch area and spacers is shown in both.

[0238] Reference Figure 10A and Figure 10B The display panel may include a first emission region EA1, a second emission region EA2 and a third emission region EA3 located on a plane defined by a first direction DR1 and a second direction DR2 and spaced apart from each other in the first direction DR1. Figure 10A and Figure 10B The planar shapes of the first emission region EA1, the second emission region EA2, and the third emission region EA3 shown can respectively correspond to the reference. Figure 3 The first pixel region PXA-R, the second pixel region PXA-G, and the third pixel region PXA-B are described.

[0239] The edge of each of the emission regions EA1, EA2, and EA3 can be defined as the edge PDL-E of the pixel-defined layer PDL. Each of the emission regions EA1, EA2, and EA3 can be a region located inside the pixel-defined layer PDL and surrounded by the edge PDL-E of the pixel-defined layer PDL.

[0240] On the plane, each of the emission regions EA1, EA2 and EA3 may have a polygonal shape, the polygonal shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1.

[0241] Reference Figure 10A The separator SLB may have a shape extending in a second direction DR2 between the emission regions EA1, EA2, and EA3 that are adjacent to each other in a first direction DR1. The separator SLB may not be connected to another separator (e.g., it may be separate from other separators) and may correspond to each of the following: the space between the first emission region EA1 and the second emission region EA2; the space between the second emission region EA2 and the third emission region EA3; the space on one side of the first emission region EA1; and the space on one side of the third emission region EA3.

[0242] The planar shape of the separator SLB can correspond to the shape of the region between emission regions EA1, EA2, and EA3, which are positioned spaced apart from each other in a first direction DR1, with the separator SLB located between them. However, one or more embodiments are not limited thereto, and the separator SLB can be applied without limitation, as long as it has a shape that is long enough to separate adjacent emission regions from each other between emission regions corresponding to pixel regions that emit light in different wavelength regions.

[0243] The spacer SLB can sufficiently reduce or prevent contact between the corresponding side surfaces of adjacent emitting regions EA1, EA2, and EA3 arranged in the first direction DR1. Furthermore, since the spacer SLB is positioned to correspond to each of the spaces between emitting regions EA1, EA2, and EA3, it can disconnect at least a portion of the light-emitting element assembly, each of which is configured as a common layer for emitting regions EA1, EA2, and EA3. Therefore, leakage emission due to the influence of adjacent emitting regions in the first direction DR1, which is the lateral direction, can be reduced.

[0244] Furthermore, since the separator SLB is positioned to correspond to each of the adjacent emission regions EA1, EA2, and EA3 in the space between them, the separator SLB can absorb the portion of light emitted by emission regions EA1, EA2, and EA3 at its side surface that is not parallel to the forward direction (third direction DR3). Therefore, color mixing between pixel regions emitting light in different wavelength regions can be reduced or prevented, thereby improving color matching and color reproducibility.

[0245] Figure 10B This illustrates the arrangement and shape of the separators in relation to... Figure 10A One or more embodiments differ from the previous ones. In one or more embodiments, the separator may include a main portion SLB-a located in the space between each of the transmission regions EA1, EA2, and EA3 that are adjacent to each other in the first direction DR1, and may also include a secondary portion SLB-s spaced apart from the main portion SLB-a and spaced apart from at least one of the transmission regions EA1, EA2, and EA3 in the second direction DR2. In one or more embodiments, the main portion SLB-a and the secondary portion SLB-s of the separator may be spaced apart from each other.

[0246] Additionally, the main part of the separator, SLB-a, may include a curved portion, BP, which has a shape that surrounds at least a portion of the corners of the emission regions EA1, EA2, and EA3.

[0247] Figure 10A and Figure 10B An example of the planar shape of the separator is shown, but this disclosure is not limited thereto. The planar shape of the separator can be varied depending on the planar shape of the emitting region, the arrangement shape of the emitting region, and the arrangement gap between the emitting regions, etc.

[0248] Figures 11A to 11D These are all diagrams illustrating an operation of a method for manufacturing a display panel according to one or more embodiments. As an example, Figures 11A to 11D Each illustrates an operation for manufacturing a display layer in a display panel according to one or more embodiments.

[0249] Reference Figure 11A A preliminary auxiliary layer P-APL can be deposited on the stacked structure of the substrate BS and the circuit layer DP-CL. The preliminary auxiliary layer P-APL can cover the entire pixel defining layer PDL and the first electrode EL1. That is, the preliminary auxiliary layer P-APL can be completely deposited on the circuit layer DP-CL. A transparent conductive oxide material can be deposited to form the preliminary auxiliary layer P-APL.

[0250] Reference Figure 11BThe separator SLB can be formed on the initial auxiliary layer P-APL. The separator SLB can be formed as an organic film including a black component. The separator SLB can be formed by a patterning process using coating (utilizing a resin composition) and UV curing. The thickness and cone angle of the separator SLB can be adjusted by controlling the process conditions of the patterning process (such as UV curing).

[0251] Figure 11C The operation of forming a stepped space STP below the separator SLB is illustrated. The stepped space STP can correspond to the space defined above the pixel defining layer PDL by a portion of the bottom surface of the separator SLB and the side surface of the auxiliary layer APL (and, for example, a portion of the top surface of the pixel defining layer PDL).

[0252] The step space STP can be defined by etching the preliminary auxiliary layer P-APL using wet etching after the spacer SLB is formed, thus forming the auxiliary layer APL. When the side surfaces of the spacer SLB and the auxiliary layer APL do not overlap, the step space STP can be defined as a portion with an undercut shape. The preliminary auxiliary layer P-APL can be formed from a transparent conductive oxide material that crystallizes at approximately 260°C or higher, thereby increasing the selectivity of the preliminary auxiliary layer P-APL during wet etching. Therefore, a step space STP with an undercut shape can be defined.

[0253] Figure 11D The operation of setting up the emitter unit (EMU) is illustrated. The emitter unit (EMU) may cover both the emitter opening portion (OH) and the separator (SLB). At least a portion of the emitter unit (EMU) may be disconnected in the step space (STP), and a cavity (APK) surrounded by a portion of the emitter unit (EMU), a portion of the bottom surface of the separator (SLB), the edge of the auxiliary layer (APL), and a portion of the top surface of the pixel defining layer (PDL) may be formed in the step space (STP).

[0254] In one or more embodiments, a second electrode, a cover layer, and an encapsulation layer can be sequentially disposed on the transmitter unit (EMU) to manufacture a display panel.

[0255] Table 1 shows examples (e.g., one or more embodiments of this disclosure) and comparison examples 1 and 2, along with display quality evaluation results. In Table 1, color reproducibility is evaluated based on the CIE 1976 color coordinate system. In luminance and gray crushing, luminance and gray crushing in the monochromatic emission of each of red (R), green (G), and blue (B) are evaluated, and luminance and gray crushing in the monochromatic emission of each of red (R), green (G), and blue (B) can be defined by Equation 1 below.

[0256] Equation 1 Grayscale compression = Measured brightness / Target brightness In Table 1, where white has a brightness of approximately 0.4 nits, the grayscale extrusion corresponds to the ratio of leakage brightness of each of red (R), green (G), and blue (B).

[0257] Parasitic emission is obtained by evaluating the brightness change caused by parasitic current. In Table 1, parasitic emission indicates the brightness change when the parasitic current is about 0.4 nits and about 1.0 nits, relative to the case where the white light brightness is about 100 nits.

[0258] Low grayscale overshoot is obtained by evaluating the phenomenon of unexpected brightness increase when achieving low grayscale. FFR represents the ratio of brightness to saturation (Sat. frame) brightness in the first frame. Table 1 shows all items in the bottom 20% of display quality as low grayscale overshoot evaluation items, as well as the results of evaluating low grayscale overshoot for each of red (R), green (G), and blue (B).

[0259] Table 1 shows the results of evaluating FFR by dividing the spectrum into segments with luminance from about 1 nit to about 100 nits and segments with luminance from about 0.026 nits to about 1 nit.

[0260] Furthermore, in Table 1, Comparative Example 1 corresponds to a display panel in which neither the auxiliary layer nor the separator is located on the pixel defining layer, and Comparative Example 2 corresponds to a display panel in which the separator is directly located on the pixel defining layer without an auxiliary layer. The examples correspond to display panels including light-emitting elements, which include... Figure 4 The stacked structure of the auxiliary layers and separators is shown. The display panels of Comparative Example 1, Comparative Example 2, and each of the examples evaluated in Table 1 below correspond to a 27" display panel with a resolution of approximately 160ppi.

[0261] Table 1

[0262] Referring to the results in Table 1, it can be confirmed that the example (e.g., according to one or more embodiments of this disclosure) exhibits superior color reproduction compared to Comparative Example 1. It can be confirmed that, compared to Comparative Examples 1 and 2, the brightness variation in the example is reduced due to parasitic emissions. It can also be seen that, compared to Comparative Examples 1 and 2, the example shows a significant improvement in low-grayscale overshoot. Regarding FFR, it can be confirmed that the example shows a larger value than the comparative example.

[0263] Based on the results in Table 1, it can be confirmed that, compared with Comparative Examples 1 and 2, the examples demonstrate excellent color reproduction and improved image characteristics due to leakage emission.

[0264] In the display panel and electronic device according to one or more embodiments, the display layer may include an auxiliary layer and a separator defining a step space, thereby disconnecting a portion of the light-emitting element assembly based on the step space. Therefore, leakage emission due to adjacent emitting areas can be reduced or minimized. Additionally, the display panel and electronic device according to one or more embodiments may include a separator containing a black component, thereby absorbing light provided in the lateral direction. Therefore, the display panel and electronic device according to one or more embodiments can achieve improved color matching ratio and color reproduction, and exhibit excellent display quality with reduced reflected light.

[0265] The display panel according to the disclosed embodiments may include a separator located on the pixel defining layer and defining a step space, thereby disconnecting a portion of the common layer of the light-emitting elements based on the step space. Therefore, leakage emission in the direction of adjacent emission regions can be reduced to achieve excellent display quality.

[0266] The electronic device according to the disclosed embodiments may include a separator defining a step space that breaks a portion of the common layer of the light-emitting elements, thereby reducing leakage emission between adjacent pixel regions that emit light in different wavelength regions, so as to present excellent display quality even at high resolution.

[0267] Figure 12 This is a block diagram of an electronic device according to an embodiment. (Refer to...) Figure 12 The electronic device ED according to the embodiment may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0268] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0269] The memory 15 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 15, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen. The display module 11 may include a display panel for displaying images.

[0270] The power module 14 may include a power module (such as a power adapter or battery device) and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device ED.

[0271] At least one of the components of the aforementioned electronic device ED may be included in a display device that includes a display panel according to an embodiment described later. Additionally, some of the modules functionally included in a single module may be included in the display device, and other modules may be disposed separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may not be disposed in the display device, but rather in another type of device within the electronic device ED.

[0272] Figure 13 Schematic diagrams of electronic devices according to various embodiments are shown.

[0273] Reference Figure 13 The various electronic devices including the display device according to the embodiments may include not only electronic devices for image display (e.g., smartphone 10_1a, tablet computer (PC) 10_1b, laptop computer 10_1c, TV 10_1d and monitor for desktop computer 10_1e), but also wearable electronic devices including display modules (e.g., smart glasses 10_2a, head-mounted display 10_2b and smartwatch 10_2c) and electronic devices for vehicles including display modules 10_3 (e.g., vehicle dashboard, central compass, interior mirror display and central information display (CID) disposed on the dashboard).

[0274] Although embodiments have been described, it is understood that this disclosure should not be limited to these embodiments in the spirit and scope of this disclosure, but rather various changes and modifications can be made by those skilled in the art.

[0275] Therefore, the technical scope of this disclosure is not limited to what is described in the detailed description of the specification, but should be determined by the claims, in which its functional equivalents are included.

Claims

1. A display panel, the display panel comprising: Matrix substrate; A circuit layer, above the substrate, includes transistors; A pixel defining layer is located above the circuit layer and defines an emission opening portion; An auxiliary layer, located above the pixel defining layer, comprises a transparent metal oxide. The separator, above the auxiliary layer, includes a black component and has an edge that protrudes further toward the emission opening portion than the edge of the auxiliary layer; as well as A light-emitting element, above the circuit layer, includes a first electrode in the emission opening portion, a second electrode facing the first electrode, a plurality of emission structures between the first electrode and the second electrode, and a plurality of charge-generating layers between the first electrode and the second electrode. The stepped space is defined by a portion of the bottom surface of the separator, the edge of the auxiliary layer, and a portion of the upper surface of the pixel defining layer. Wherein, at least one of the plurality of charge-generating layers is disconnected at the step space.

2. The display panel according to claim 1, further comprising a cavity in the stepped space, wherein the plurality of emitting structures and the plurality of charge generating layers are discontinuous at the cavity.

3. The display panel according to claim 1, wherein, At least one of the plurality of charge generating layers includes one end above the pixel defining layer and the other end above the separator.

4. The display panel according to claim 1, wherein, The plurality of emission structures include a first emission structure, a second emission structure, a third emission structure, and a fourth emission structure that are stacked in the thickness direction and include emission layers. The plurality of charge generation layers include a first charge generation layer between the first emission structure and the second emission structure, a second charge generation layer between the second emission structure and the third emission structure, and a third charge generation layer between the third emission structure and the fourth emission structure. Wherein, at least one of the first emission structure, the second emission structure, the third emission structure and the fourth emission structure is disconnected from at least one of the first charge generation layer, the second charge generation layer and the third charge generation layer at the step space.

5. The display panel according to claim 1, wherein, The separator includes an organic membrane, which includes the black component.

6. The display panel according to claim 1, wherein, The separator overlaps only with a portion of the pixel-defining layer.

7. The display panel according to claim 1, wherein, The auxiliary layer includes: Transparent conductive oxide materials crystallize at temperatures of 260°C or higher; and The transparent conductive oxide material includes indium gallium zinc oxide or indium zinc oxide having an indium to zinc weight ratio of 9:1 to 1:

1.

8. The display panel according to claim 1, wherein, The thickness of the auxiliary layer is 100 Å to 1000 Å.

9. The display panel according to claim 1, wherein, The side surface of the separator is inclined at an angle of 50 to 90 degrees to the substrate.

10. The display panel according to claim 1, wherein, The transistor includes a semiconductor pattern and a gate above the semiconductor pattern. The semiconductor pattern includes a metal oxide, which includes at least one of indium, gallium, zinc, tin, and titanium. The semiconductor pattern is divided into an active body, a source, and a drain.

11. A display panel, the display panel comprising: Matrix substrate; A circuit layer, above the substrate, includes transistors; as well as A display layer, above the circuit layer, defines mutually separated emission regions and includes: a pixel defining layer, above the circuit layer, defining emission openings corresponding to the emission regions; an auxiliary layer, above the pixel defining layer, comprising a transparent metal oxide; a separator, above the auxiliary layer, comprising a black component and having an edge that protrudes further towards the emission openings than the edge of the auxiliary layer; and a light-emitting element, above the circuit layer, comprising a first electrode, a second electrode facing the first electrode, a plurality of emission structures between the first electrode and the second electrode, and a plurality of charge-generating layers between the first electrode and the second electrode. The stepped space with an undercut shape is defined by a portion of the bottom surface of the separator, the edge of the auxiliary layer, and a portion of the upper surface of the pixel defining layer. Wherein, at least one of the plurality of charge-generating layers is disconnected at the step space.

12. The display panel according to claim 11, wherein, On a plane, the emission region has a polygonal shape, the polygonal shape having a short side extending in a first direction and a long side extending in a second direction intersecting the first direction, and The separator has a shape extending in the second direction between adjacent emission regions in the first direction, and includes: The main part is located between the adjacent launch areas within the launch area; The secondary portion is spaced apart from the primary portion and, in the second direction, spaced apart from at least one of the adjacent transmission regions in the transmission region. The main portion includes a curved portion having a shape that surrounds at least a portion of a corner of at least one of the adjacent emission regions in the emission region.

13. The display panel according to claim 11, wherein, The separator includes an organic membrane, which includes the black component.

14. The display panel according to claim 11, wherein, The auxiliary layer comprises indium zinc oxide having an indium to zinc weight ratio of 9:1 to 1:

1.

15. The display panel according to claim 11, wherein, The emission structure includes at least one green emission structure and at least one blue emission structure.

16. An electronic device, the electronic device comprising: The display panel includes a first emitting region, a second emitting region, and a third emitting region spaced apart on a plane, arranged sequentially in a first direction, and configured as emitting source light. as well as A light control panel is located above the display panel and is configured to transmit the source light or convert the wavelength of the source light. The display panel includes: a substrate; a circuit layer above the substrate and including transistors; a pixel defining layer above the circuit layer and defining an emission opening portion; an auxiliary layer above the pixel defining layer and including a transparent metal oxide; a separator above the auxiliary layer, including a black component and having an edge that protrudes further into the emission opening portion than the edge of the auxiliary layer; and a light-emitting element above the circuit layer and including a first electrode in the emission opening portion, a second electrode facing the first electrode, a plurality of emission structures between the first electrode and the second electrode, and a plurality of charge-generating layers between the first electrode and the second electrode. The stepped space is defined by a portion of the bottom surface of the separator, the edge of the auxiliary layer, and a portion of the upper surface of the pixel defining layer. Wherein, at least one of the plurality of charge-generating layers is disconnected at the step space.

17. The electronic device according to claim 16, wherein, The electronic device also includes at least one of a processor, a memory, and a power module.

18. The electronic device according to claim 16, wherein, The electronic device is an image display device, a wearable device, or a device for use in a vehicle.

19. The electronic device of claim 16, further comprising a cavity in the stepped space, at which the plurality of emitting structures and the plurality of charge-generating layers are discontinuous. in, At least one of the plurality of charge generating layers includes one end above the pixel defining layer and the other end above the separator.

20. The electronic device according to claim 16, wherein, The separator includes an organic membrane, the organic membrane including the black component, and The separators are configured in multiple locations, respectively, in the space between the first and second transmission regions and between the second and third transmission regions.

Images