Semiconductor device and manufacturing method and testing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method and a testing method thereof. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure comprises a first to-be-tested component and a first test component, and the first test component is located on one side of the first to-be-tested component in the first direction and used for testing the first to-be-tested component. The second semiconductor structure is located on one side of the first semiconductor structure in the second direction and comprises a second to-be-tested component and a second test component, and the second test component is located on one side of the second to-be-tested component in the first direction and used for testing the second to-be-tested component. Wherein the first to-be-tested component and the second to-be-tested component are stacked in the second direction, the first test component and the second test component are stacked in the second direction, and the first direction and the second direction intersect.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method for manufacturing a semiconductor device, and a method for testing a semiconductor device. Background Technology

[0002] After wafer fabrication is complete, wafer testing is a crucial step in monitoring the wafer's electrical properties and process. As the planar integration of functional circuits within the wafer increases, reducing the planar area of ​​test components for those functional circuits becomes a bottleneck. Summary of the Invention

[0003] In a first aspect, some embodiments of this application provide a semiconductor device. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first component under test (SUPT) and a first test component, the first test component being located on one side of the first SUPT in a first direction and used for testing the first SUPT. The second semiconductor structure is located on one side of the first semiconductor structure in a second direction and includes a second SUPT and a second test component, the second test component being located on one side of the second SUPT in the first direction and used for testing the second SUPT. The first SUPT and the second SUPT are stacked in the second direction, and the first test component and the second test component are also stacked in the second direction, with the first and second directions intersecting.

[0004] In an exemplary embodiment, the first semiconductor structure includes a memory array structure, and the second semiconductor structure includes a peripheral circuit structure.

[0005] In an exemplary embodiment, the first test component is used to perform one or more test types on the first component to be tested, and the second test component is used to perform one or more test types on the second component to be tested.

[0006] In an exemplary embodiment, the semiconductor device further includes a third test component located on the side of the first test component and / or the second test component facing the third direction, and is used to test the third test component formed by the connection of the first test component and the second test component, wherein the first direction, the second direction and the third direction intersect each other.

[0007] In an exemplary embodiment, the third test component is used to perform one or more types of tests on the third component to be tested.

[0008] In an exemplary implementation, the test types include peripheral device functional testing, storage device functional testing, design rule testing, and reliability testing.

[0009] In an exemplary embodiment, the first test component, the second test component, and the third test component are located within the cutting channel area.

[0010] In an exemplary embodiment, the semiconductor device further includes a first test pad located in the first semiconductor structure and connected to the first test component.

[0011] In an exemplary embodiment, the semiconductor device further includes a second test pad and a third test pad, the second test pad being located in the second semiconductor structure and connected to the second test component; the third test pad being located in the second semiconductor structure and connected to the third test component.

[0012] Secondly, some embodiments of this application provide a method for manufacturing a semiconductor device. The method includes: forming a first semiconductor structure, wherein the first semiconductor structure includes a first component under test and a first test component, the first test component being located on one side of the first component under test in a first direction and used for testing the first component under test; forming a second semiconductor structure, wherein the second semiconductor structure includes a second component under test and a second test component, the second test component being located on one side of the second component under test in the first direction and used for testing the second component under test; and disposing the second semiconductor structure on one side of the first semiconductor structure in a second direction, wherein the first test component and the second test component are stacked in the second direction, the first component under test and the second component under test are stacked in the second direction, and the first and second directions intersect.

[0013] In an exemplary embodiment, the method of manufacturing the semiconductor device further includes: forming a third test component on a third-direction side of the first test component and / or the second test component, wherein the third test component is used to test the third test component formed by connecting the first test component and the second test component, and the first direction, the second direction and the third direction intersect each other.

[0014] In an exemplary embodiment, the first test component, the second test component, and the third test component are located within the cutting channel area.

[0015] Thirdly, some embodiments of this application provide a method for testing a semiconductor device. The method includes: testing a first component under test using a first test component in a first semiconductor structure, wherein the first test component is located on one side of the first component under test in a first direction; disposing a second semiconductor structure on one side of the first semiconductor structure in a second direction; and testing a second component under test using a second test component in the second semiconductor structure, wherein the second test component is located on one side of the second component under test in the first direction; wherein the first test component and the second test component are stacked in the second direction, and the first component under test and the second component under test are also stacked in the second direction.

[0016] In an exemplary embodiment, the first semiconductor structure includes a peripheral circuit structure, and the second semiconductor structure includes a memory array structure.

[0017] In an exemplary embodiment, testing the first component under test using the first test component in the first semiconductor structure includes performing one or more test types on the first component under test; wherein, testing the second component under test using the second test component in the second semiconductor structure includes performing one or more test types on the second component under test.

[0018] In an exemplary embodiment, the testing method for the semiconductor device further includes: testing a third test component formed by connecting the first test component and the second test component using a third test component; wherein the third test component is located on the side of the first test component and / or the second test component in a third direction, and the first direction, the second direction, and the third direction intersect each other.

[0019] In an exemplary embodiment, testing a third component to be tested, which is formed by connecting a first component to be tested and a second component to be tested, using a third test component includes performing one or more types of tests on the third component to be tested.

[0020] In an exemplary embodiment, the third component is tested during the testing of the second component to be tested. Attached Figure Description

[0021] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0022] Figure 1 This is a top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0023] Figure 2 yes Figure 1 A magnified view of a portion of region A is shown;

[0024] Figure 3 It is along Figure 2 The diagram shows a cross-sectional view of a semiconductor device taken by line B-B'.

[0025] Figure 4 It is along Figure 2 The diagram shows a cross-sectional view of a semiconductor device taken along line C-C'.

[0026] Figure 5 This is a schematic flowchart of a method for manufacturing a semiconductor device provided in an embodiment of this application;

[0027] Figure 6 This is a flowchart illustrating the testing method for a semiconductor device provided in an embodiment of this application; and

[0028] Figure 7 , Figure 8A as well as Figure 8B This is a schematic diagram of the semiconductor device provided in the embodiments of this application during the testing process. Detailed Implementation

[0029] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first semiconductor structure discussed herein may also be referred to as the second semiconductor structure, and vice versa.

[0031] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0032] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0033] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0035] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0036] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] Some embodiments of this application provide a semiconductor device. Figure 1 This is a top view schematic diagram of the semiconductor device provided in the embodiments of this application. Figure 2 yes Figure 1 A magnified view of a portion of region A is shown. Figure 3 It is along Figure 2 The diagram shows a cross-sectional view of a semiconductor device taken by line B-B'. Figure 4 It is along Figure 2 The diagram shows a cross-sectional view of a semiconductor device taken along line C-C'.

[0038] It should be noted that the D1 direction (corresponding to the first direction), D2 direction (corresponding to the second direction), and D3 direction (corresponding to the third direction) in the various figures illustrate the spatial relationship of the components in the semiconductor device. For example, the D2 direction may be the stacking direction of the first semiconductor structure and the second semiconductor structure, and the D1 and D3 directions may be two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to the D3 direction. The same concepts will be used throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0039] like Figures 1 to 3 As shown, the semiconductor device 10 may include a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 may include a first component under test 110 and a first test component 120. The first test component 120 may be located on one side of the first component under test 110 in the D1 direction and is used to test the first component under test 110. The second semiconductor structure 200 may be located on one side of the first semiconductor structure 100 in the D2 direction and may include a second component under test 210 and a second test component 220. The second test component 220 may be located on one side of the second component under test 210 in the D2 direction and can be used to test the second component under test 210. The first component under test 110 and the second component under test 210 are stacked on D2, and the first test component 120 and the second test component 220 are stacked on D2.

[0040] According to the semiconductor device 100 provided in the above embodiments, the first test component 120 for testing the first test component 110 and the second test component 220 for testing the second test component 210 are stacked in the D2 direction, which can save the planar area of ​​the first test component 120 and the second test component 220, and can solve the problem of increased planar area requirements of the first test component 120 and the second test component 220 due to the improved planar integration of the first test component 110 and the second test component 210.

[0041] In some embodiments, the first semiconductor structure 100 may be a first wafer that is not diced into a plurality of first dies. The plurality of first dies in the first wafer are spaced apart from each other. Each first die may contain a first functional circuit. The first functional circuit, or a portion thereof, may be a first device under test 110. For example, each first die may contain the same first functional circuit.

[0042] In some embodiments, the second semiconductor structure 200 may be a second wafer that is not diced into a plurality of second dies. The plurality of second dies in the second wafer are spaced apart from each other. Each second die may contain a second functional circuit. For example, the first functional circuit and the second functional circuit are different from each other. The second functional circuit, or a portion thereof, may be a second device under test 210. For example, each second die may contain the same second functional circuit.

[0043] In some embodiments, the first semiconductor structure 100 and the second semiconductor structure 200 may be connected by wafer bonding technology. The wafer bonding technology referred to in this application may include, but is not limited to, fused bonding, eutectic bonding, hybrid bonding, and anodic bonding. In the semiconductor device 10, a plurality of first bare dies in the first semiconductor structure 100 and a plurality of second bare dies in the second semiconductor structure 200 correspond one-to-one. For example, the number and arrangement of the plurality of first bare dies and the plurality of second bare dies are the same. For another example, viewed from the D2 direction, each first bare die and its corresponding second bare die overlap. Thus, viewed from the D2 direction, the semiconductor device 10 may include a plurality of bare die regions DR and dicing channels SLR. The plurality of bare die regions DR are spaced apart from each other and arrayed in the D1 and D3 directions. Both the first and second bare dies are located within the bare die regions DR. The dicing channels SLR are located between adjacent bare die regions DR. For example, for a single bare die region DR, the dicing channels SLR may be located on opposite sides of the single bare die region DR in the D2 direction and on opposite sides in the D3 direction. For example, when the first semiconductor structure 100 and the second semiconductor structure 200 are connected, the first functional circuit in the first bare die and the second functional circuit in the corresponding second bare die can achieve electrical conduction, that is, the first test component 110 and the second test component 210 can achieve electrical conduction.

[0044] In some embodiments, the first semiconductor structure 100 may include a memory array structure, and the second semiconductor structure 200 may include a peripheral circuit structure. For example, each of the first bare dies in the first semiconductor structure 100 includes a memory array structure, and each of the second bare dies in the second semiconductor structure 200 includes a peripheral circuit structure. In the semiconductor device 10, the memory array structure and the peripheral circuit structure are stacked in the D2 direction and are capable of electrical conduction.

[0045] In some implementations, the memory array structure may include an array of memory cells consisting of one or more of the following: multiple NAND memory cells, multiple DRAM memory cells, multiple PCM memory cells, multiple RRAM memory cells, multiple FeRAM memory cells, multiple FeFET memory cells, multiple MRAM memory cells, or any other type of memory cells. For example, the memory array structure may be a NAND memory cell array. The peripheral circuit structure may include any suitable digital, analog, and / or mixed-signal functional circuitry for supporting the functionality of the memory cell array, such as row decoders (or word line drivers), column decoders (or bit line drivers), page buffers (or sense amplifiers), voltage generators, logic control circuitry, input / output (I / O) circuitry, and data buses, etc. For example, the aforementioned functional circuitry may include one or more of any active or passive devices (e.g., transistors, diodes, resistors, or capacitors). Vertically integrating the memory array structure and the peripheral circuit structure is beneficial for reducing planar area and improving the transmission speed between the peripheral circuitry and the memory cell array.

[0046] Chip probing (CP testing) is one of the earlier stages of chip manufacturing, also known as die sorting. It's the testing phase before wafer dicing and thinning. The main purpose of wafer probing is to check whether each die on the wafer meets design requirements and possesses the basic electrical characteristics that each die should have, such as voltage, current, and functionality. Through wafer probing, defective dies can be identified, avoiding wasted costs in subsequent packaging processes. Typically, wafer probing is performed using test components.

[0047] In some embodiments, both the first test component 120 and the second test component 220 can be located in the cut track region (SLR). For example, viewed from the D2 direction, the first test component 120 and the second test component 220 can substantially overlap. For example, the first test component 120 can be located on one side of the first test component 110 in the D1 direction, and the second test component 220 can be located on one side of the second test component 210 in the D1 direction. Alternatively, the first test component 120 can be located on opposite sides of the first test component 110 in the D1 direction, and the second test component 220 can be located on opposite sides of the second test component 210 in the D1 direction. Optionally, the first test component 120 can also be located on one side or opposite sides of the first test component 110 in the D3 direction, and the second test component 220 can also be located on one side or opposite sides of the second test component 210 in the D3 direction. The placement of the first test component 120 and the second test component 220 is related to their planar area requirements. As the planar area requirements of the first test component 120 and the second test component 220 increase, the first test component 120 and the second test component 220 can be placed on one side, two sides, three sides, and four sides of the first test component 110 and the second test component 210, respectively. This application does not impose specific restrictions on this.

[0048] In some embodiments, the first test component 120 may include any combination of passive or active devices such as resistors, capacitors, MOS transistors, parasitic MOS transistors, diodes, and bipolar transistors. The first test component 120 may also include alternating layers of first interconnect lines and first interconnect channels. The first test component 120 may be connected to the first component under test 110. For example, the first test component 120 and the first component under test 110 may be connected via a first interconnect line. Thus, the first test component 120 and the first component under test 110 can achieve electrical conduction.

[0049] In some embodiments, the semiconductor device 10 may further include a first test pad 130. The first test pad 130 may be located in the first semiconductor structure 100 and may be connected to the first test component 120. For example, the first test pad 130 may contact the second semiconductor structure 200 and may be connected to the first interconnect or first interconnect channel in the first test component 120 that is closest to the second semiconductor structure 200. The first test pad 130 may be used to transmit test signals and test data of the first component under test 110.

[0050] In some embodiments, the second test component 220 may include any combination of passive or active devices such as resistors, capacitors, MOS transistors, parasitic MOS transistors, diodes, and bipolar transistors. The second test component 220 may also include alternately stacked second interconnects and second interconnect channels. The second test component 220 may be connected to the second component under test 210. For example, the second test component 220 and the second component under test 210 may be connected via a second interconnect. Thus, the second test component 220 and the second component under test 210 can achieve electrical conduction.

[0051] In some embodiments, the semiconductor device 10 may further include a second test pad 230. The second test pad 230 may be located within the second semiconductor structure 200 and may be connected to the second test component 220. For example, the second test pad 230 may be exposed on the surface of the second semiconductor structure 200 opposite to the first semiconductor structure 100 and may be connected to a second interconnect or second interconnect channel in the second test component 220 that is furthest from the first semiconductor structure 100. The second test pad 230 may be used to transmit test signals and test data of the second component under test 210.

[0052] In some embodiments, the first test component 120 can be used to perform one or more types of tests on the first component under test 110, and the second test component 220 can be used to perform one or more types of tests on the second component under test 210. The test types may include, but are not limited to, peripheral device functional testing, storage device functional testing, design rule testing, and reliability testing. Peripheral device functional testing aims to test the functionality of peripheral devices, such as electrical connectivity testing, parameter testing, and functional testing. Electrical connectivity testing verifies the correctness of the connections between peripheral devices. Parameter testing measures whether electrical parameters such as voltage and current meet design requirements. Functional testing verifies whether the expected functions are present. Storage device functional testing aims to test the functionality of storage cells. Simply put, the test method involves writing data and then reading it back and comparing it with the original data. If they match, the function passes; otherwise, it fails. Design rule testing aims to check for potential open circuits, short circuits, or adverse effects caused by violations of design rules in the layout. Reliability testing aims to evaluate the operational stability and lifespan under different environmental conditions.

[0053] In some embodiments, where the first semiconductor structure 100 includes a memory array structure and the second semiconductor structure 200 may include a peripheral circuit structure, the first test component 120 can be used to perform memory device functional testing on the first component under test 110, and the second test component 220 can be used to perform peripheral device functional testing on the second component under test 210. Generally, the device composition and interconnect patterns of test components suitable for different types of tests are different from each other.

[0054] In some implementations, such as Figure 1 , Figure 2 as well as Figure 4 As shown, the semiconductor device 10 may further include a third test component 320. The third test component 320 may be located on one side of the first test component 110 and / or the second test component 210 in the D3 direction, and is used to test the third test component 310 formed by the connection of the first test component 110 and the second test component 210. As described above, the first functional circuit or a portion thereof contained in the first bare die of the first semiconductor structure 100 may be the first test component 110, and the second functional circuit or a portion thereof contained in the second bare die of the second semiconductor structure 200 may be the second test component 210. In the semiconductor device 10, the first functional circuit and the second functional circuit (e.g., physically) connected to form a circuit may constitute the third test component 310.

[0055] In some embodiments, the third test component 320 may be located in the cleaved track region (SLR). For example, the third test component 320 may be located in the cleaved track region (SLR) of the first semiconductor structure 100 and the second semiconductor structure 200. Alternatively, the third test component 320 may be located in the cleaved track region (SLR) of one of the first semiconductor structure 100 and the second semiconductor structure 200. The third test component 320 may be located on one side or opposite sides of the first test component 110 and / or the second test component 210 in the D3 direction. Optionally, the third test component 320 may also be located on one side or opposite sides of the first test component 110 and / or the second test component 210 in the D2 direction. The location of the third test component 320 is related to its planar area requirement. As the planar area requirement of the third test component 320 increases, the third test component 320 may be located on one side, two sides, three sides, or four sides of the first test component 110 and / or the second test component 210. This application does not impose specific limitations on this.

[0056] In some embodiments, the third test component 320 may include any combination of passive or active devices such as resistors, capacitors, MOS transistors, parasitic MOS transistors, diodes, and bipolar transistors. The third test component 320 may also include alternately stacked third interconnects and third interconnect channels. The third test component 320 may be connected to the third component under test 310. For example, the third test component 320 and the third component under test 310 may be connected via a third interconnect. Thus, the third test component 320 and the third component under test 310 can achieve electrical conduction.

[0057] In some embodiments, the semiconductor device 10 may further include a third test pad 330. The third test pad 330 may be located within the second semiconductor structure 200 and may be connected to the third test component 320. For example, the third test pad 330 may be exposed on the surface of the second semiconductor structure 200 opposite to the first semiconductor structure 100 and may be connected to the third interconnect or third interconnect channel in the third test component 320 that is furthest from the first semiconductor structure 100. The third test pad 330 may be used to transmit test signals and test data of the third component under test 310.

[0058] In some embodiments, the third test component 320 can be used to perform one or more types of tests on the third component under test 310. As described above, the test types may include peripheral device functional testing, storage device functional testing, design rule testing, and reliability testing. For example, the third test component 320 can be used to perform multiple types of tests on the third component under test 310.

[0059] This application also provides a method for manufacturing a semiconductor device. Figure 5 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 5 As shown, in the semiconductor device manufacturing method 20, firstly, a first semiconductor structure may be formed, wherein the first semiconductor structure includes a first component under test and a first test component, the first test component being located on one side of the first component under test in a first direction and used to test the first component under test. Then, a second semiconductor structure may be formed, wherein the second semiconductor structure includes a second component under test and a second test component, the second test component being located on one side of the second component under test in the first direction and used to test the second component under test. Next, the second semiconductor structure may be disposed on one side of the first semiconductor structure in a second direction, wherein the first test component and the second test component are stacked in the second direction, and the first component under test and the second component under test are also stacked in the second direction.

[0060] According to the above embodiments, a method for manufacturing a semiconductor device is provided. In the process of constructing a first semiconductor structure and a second semiconductor structure, the layout of the first test component, the first test component, the second test component, and the second test component is reasonably optimized. After the second semiconductor structure is disposed on one side of the first semiconductor structure in a second direction, the first test component for testing the first test component and the second test component for testing the second test component are stacked in the second direction. This can save the planar area of ​​the first test component and the second test component and can address the problem of increased planar area requirements of the first test component and the second test component due to the increased planar integration of the first test component and the second test component.

[0061] The following provides examples to illustrate steps S21 to S23 above.

[0062] In step S21, a first semiconductor structure comprising a first device under test and a first test component may be formed using a process such as photolithography, etching, thin film deposition, doping, oxidation, or any other suitable semiconductor process. For example, the first device under test may be implemented as a memory array structure. For example, the first test component may be formed in a diced region.

[0063] In some embodiments, at least a portion of a third test component may be formed during the formation of the first semiconductor structure. For example, at least a portion of the third test component may be formed in the dicing region. This at least a portion of the third test component may be located on the third-party-oriented side of the first component under test and can be used to test the third component under test formed by the connection of the first component under test and the second component under test. For example, part or all of the third test component may be formed on one side of the first component under test. When a portion of the third test component is formed on one side of the first component under test, the third test component will be used together with another portion of the third test component formed in the second semiconductor structure to test the third component under test. It should be noted that the third test component may not be formed in the first semiconductor structure; in other words, the step of forming at least a portion of the third test component may be omitted during the formation of the first semiconductor structure.

[0064] In step S22, a second semiconductor structure comprising a second component under test and a second test component may be formed using methods such as photolithography, etching, thin film deposition, doping, oxidation, or any other suitable semiconductor process. For example, the second component under test may be implemented as a peripheral circuit structure. For example, the second test component may also be formed in a diced area.

[0065] In some embodiments, at least a portion of a third test component may be formed during the formation of the second semiconductor structure. For example, at least a portion of the third test component may be formed in the dicing region. This at least a portion of the third test component may be located on the third-side upward side of the second component under test and can be used to test the third component under test formed by the connection of the first and second components under test. For example, part or all of the third test component may be formed on one side of the second component under test. In the case where a portion of the third test component is formed on one side of the first component under test, another portion of the third test component formed in the second semiconductor structure is used together to test the third component under test.

[0066] It should be noted that steps S21 and S22 can be executed in parallel or sequentially, and this application does not impose any specific restrictions. When steps S21 and S22 are executed in parallel, manufacturing efficiency can be improved and the mutual influence of thermal effects between the first semiconductor structure and the second semiconductor structure during the manufacturing process can be reduced.

[0067] In step S23, the second semiconductor structure can be connected to one side of the first semiconductor structure in the second direction using any suitable wafer bonding technology. This enables electrical conduction between the first and second semiconductor structures. Furthermore, by appropriately arranging the relative positions of the first test component with respect to the first component under test, and the relative positions of the second test component with respect to the second component under test, the first and second components under test can be stacked in the second direction, and the first and second test components are also stacked in the second direction. In other words, from the second direction, the first and second test components approximately overlap.

[0068] This application also provides a method for testing semiconductor devices. Figure 6 This is a schematic flowchart of a testing method for a semiconductor device provided in an embodiment of this application. Figure 7 , Figure 8A as well as Figure 8B This is a schematic diagram of the semiconductor device provided in the embodiments of this application during the testing process. Figure 8A and Figure 8B Semiconductor device 10 is shown as cuts taken from different planes.

[0069] like Figure 6 As shown, in the semiconductor device testing method 30, firstly, a first device under test (DUT) is tested using a first test component in a first semiconductor structure, wherein the first test component is located on one side of the DUT in a first direction. Then, a second semiconductor structure is disposed on one side of the first semiconductor structure in a second direction. Next, a second DUT is tested using a second test component in the second semiconductor structure, wherein the second test component is located on one side of the second DUT in the first direction. Furthermore, the first test component and the second test component are stacked in the second direction, and the first DUT and the second DUT are also stacked in the second direction.

[0070] According to the semiconductor device testing method 30 provided in the above embodiment, before the second semiconductor structure is disposed on one side of the first semiconductor structure in the second direction, the first component to be tested therein is tested using the first test component disposed in the first semiconductor structure. After the second semiconductor structure is disposed on one side of the first semiconductor structure in the second direction, the second component to be tested therein is tested using the second test component disposed in the second semiconductor structure. This can improve testing efficiency and shorten testing time.

[0071] The following is combined Figure 7 , Figure 8A as well as Figure 8B Examples are given for the above steps S31 to S33.

[0072] In step S31, for example, as Figure 7 As shown, the first semiconductor structure 100 may further include a first test pad 130. The first test pad 130 may be exposed on the surface of the first semiconductor structure 100 in the D2 direction. The first test pad 130 may be connected to a first test component 120, and the first test component 120 may be connected to a first component under test 110. Since the internal structure of the first semiconductor structure 100 has been described in detail above, it will not be repeated here.

[0073] During the testing of the first component under test 110, the probe 40 in the external testing equipment can contact the first test pad 130 and transmit test signals to the first test component 120 through the first test pad 130. The first test component 120 is used to perform one or more types of tests on the first component under test 110. In addition, the probe 40 also transmits test data to the external testing equipment to evaluate the test results.

[0074] In some embodiments, the first semiconductor structure 100 may include a peripheral circuit structure, in which case the first test component 120 may be used to perform peripheral device functional testing on the first component under test 110.

[0075] In step S32, as Figure 8A and Figure 8B As shown, the second semiconductor structure 200 can be connected to one side of the first semiconductor structure 100 in the D2 direction using any suitable wafer bonding technique. Thus, the first semiconductor structure 100 and the second semiconductor structure 200 can achieve electrical conductivity. The first component under test 110 and the second component under test 210 can achieve electrical conductivity. For example, the connection of the first component under test 110 and the second component under test 210 can constitute a third component under test 310.

[0076] In step S33, for example, continue to refer to Figure 8A and Figure 8B The second semiconductor structure 200 may further include a second test pad 230. The second test pad 230 may be exposed on the surface of the second semiconductor structure 200 opposite to the first semiconductor structure 100. The second test pad 230 may be connected to a second test component 220, and the second test component 220 may be connected to a second component under test 210. Since the internal structure of the second semiconductor structure 200 has been described in detail above, it will not be repeated here.

[0077] During the testing of the second component under test 210, the probe 40 in the external testing equipment can contact the second test pad 230 and transmit test signals to the second test component 220 through the second test pad 230. The second test component 220 is used to perform one or more types of tests on the second component under test 210. In addition, the probe 40 also transmits test data to the external testing equipment to evaluate the test results.

[0078] In some embodiments, the second semiconductor structure 200 may include a memory array structure, in which case the second test component 220 may be used to perform memory device functional testing on the second component under test 210.

[0079] In some embodiments, the semiconductor device 10 may further include a third test component 320. The third test component 320 may be located on one side of the first component under test 110 and / or the second component under test 210 in the D3 direction. Since the arrangement of the third test component 320 has been described in detail above, it will not be repeated here. Furthermore, the semiconductor device 10 may also include a third test pad 330. The third test pad 330 may be exposed on the surface of the second semiconductor structure 200 opposite to the first semiconductor structure 100. The third test pad 330 may be connected to the third test component 320, and the third test component 320 may be connected to the third component under test 310.

[0080] During the testing of the third component under test 310, the probe 40 in the external test equipment can contact the third test pad 330 and transmit test signals to the third test component 320 through the third test pad 330. The third test component 320 is used to perform one or more types of tests on the third component under test 310. In addition, the probe 40 also transmits test data to the external test equipment to evaluate the test results.

[0081] In some embodiments, when the first semiconductor structure 100 includes a peripheral circuit structure and the second semiconductor structure 200 includes a memory array structure, the third test component 120 can be used to perform tests on the first component under test, such as peripheral device function tests, memory function tests, design rule tests, reliability tests, etc.

[0082] In some implementations, the third component 310 can be tested during the testing of the second component 210. This further improves testing efficiency and saves testing time.

[0083] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, comprising: A first semiconductor structure includes a first component under test and a first test component, wherein the first test component is located on one side of the first component under test in a first direction and is used to test the first component under test; as well as A second semiconductor structure is located on one side of the first semiconductor structure in the second direction, and includes a second component to be tested and a second test component. The second test component is located on one side of the second component to be tested in the first direction and is used to test the second component to be tested. The first component to be tested and the second component to be tested are stacked in the second direction, and the first test component and the second test component are stacked in the second direction, wherein the first direction and the second direction intersect.

2. The semiconductor device according to claim 1, wherein, The first semiconductor structure includes a memory array structure, and the second semiconductor structure includes a peripheral circuit structure.

3. The semiconductor device according to claim 1, wherein, The first test component is used to perform one or more types of tests on the first component under test, and the second test component is used to perform one or more types of tests on the second component under test.

4. The semiconductor device according to claim 3, wherein, The semiconductor device further includes: A third test component is located on the side of the first test component and / or the second test component in the third direction, and is used to test the third test component formed by the connection of the first test component and the second test component, wherein the first direction, the second direction and the third direction intersect each other.

5. The semiconductor device according to claim 4, wherein, The third test component is used to perform one or more types of tests on the third component to be tested.

6. The semiconductor device according to claim 5, wherein, The test types include peripheral device functional testing, storage device functional testing, design rule testing, and reliability testing.

7. The semiconductor device according to claim 4, wherein, The first test component, the second test component, and the third test component are located within the cutting channel area.

8. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: The first test pad is located in the first semiconductor structure and is connected to the first test component.

9. The semiconductor device according to claim 3, wherein, The semiconductor device further includes: The second test pad is located in the second semiconductor structure and is connected to the second test component; and The third test pad is located in the second semiconductor structure and is connected to the third test component.

10. A method for manufacturing a semiconductor device, comprising: A first semiconductor structure is formed, wherein the first semiconductor structure includes a first component under test and a first test component, the first test component being located on one side of the first component under test in a first direction and used to test the first component under test; A second semiconductor structure is formed, wherein the second semiconductor structure includes a second device under test (DUT) and a second test component, the second test component being located on one side of the second DUT in the first direction and used to test the second DUT; and The second semiconductor structure is disposed on one side of the first semiconductor structure in the second direction, wherein the first test component and the second test component are stacked in the second direction, the first component to be tested and the second component to be tested are stacked in the second direction, and the first direction and the second direction intersect.

11. The manufacturing method according to claim 10, wherein, The manufacturing method further includes: A third test component is formed on one side of the first test component and / or the second test component in the third direction, wherein the third test component is used to test the third test component formed by the connection of the first test component and the second test component, and the first direction, the second direction and the third direction intersect each other.

12. The manufacturing method according to claim 11, wherein, The first test component, the second test component, and the third test component are located within the cutting channel area.

13. A method for testing a semiconductor device, comprising: The first test component in the first semiconductor structure is used to test the first component under test, wherein the first test component is located on one side of the first component under test in a first direction; The second semiconductor structure is disposed on one side of the first semiconductor structure in the second direction; and The second test component in the second semiconductor structure is used to test the second component under test, wherein the second test component is located on one side of the second component under test in the first direction; The first test component and the second test component are stacked in the second direction, and the first component to be tested and the second component to be tested are stacked in the second direction.

14. The test method according to claim 13, wherein, The first semiconductor structure includes a peripheral circuit structure, and the second semiconductor structure includes a memory array structure.

15. The test method according to claim 13, wherein, Testing the first component under test using the first test component in the first semiconductor structure includes: Perform one or more types of tests on the first component to be tested; The testing of the second component under test using the second test component in the second semiconductor structure includes: Perform one or more test types on the second component to be tested.

16. The test method according to claim 13, wherein, The testing method also includes: The third test component is used to test the third test component formed by connecting the first test component and the second test component; The third test component is located on the side of the first test component and / or the second test component in the third direction, and the first direction, the second direction, and the third direction intersect each other.

17. The test method according to claim 16, wherein, Testing the third component under test, which is formed by connecting the first component under test and the second component under test, using a third test component includes: One or more test types are performed on the third component to be tested.

18. The test method according to claim 16, wherein, During the testing of the second component to be tested, the third component to be tested is also tested.

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