HEMT packaging structure

Abstract

The invention relates to the technical field of semiconductors, in particular to an HEMT (High Electron Mobility Transistor) packaging structure, which comprises a plastic packaging body, and the plastic packaging body comprises a first surface, a second surface and a peripheral side part, an active region of the semiconductor device comprises a plurality of cellular units, and each cellular unit comprises a substrate, an III-V epitaxial layer arranged on the front surface of the substrate, a first electrode and a second electrode which are arranged on the III-V epitaxial layer, a control electrode arranged between the first electrode and the second electrode, and a dielectric layer covering the first electrode, the second electrode and the control electrode; the first heat dissipation metal body covers the surface of the active region and is configured to expose the first surface of the plastic package body, and the first heat dissipation metal body is insulated from the first electrode, the second electrode and the control electrode; the second heat dissipation metal body covers the back surface of the substrate and is configured to expose the second surface of the plastic package body. Compared with the prior art, the packaging structure adopts a double-sided heat dissipation packaging design and other structures, so that the heat dissipation capability of the semiconductor device is remarkably enhanced, and the heat dissipation efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a HEMT packaging structure. Background Technology

[0002] With the rapid development of semiconductor technology, especially the widespread application of new materials such as gallium nitride (GaN) in high-power, high-frequency electronic devices, the heat dissipation problem of semiconductor devices has become increasingly prominent, becoming a key factor restricting their performance improvement and widespread application. Traditional single-sided heat dissipation packaging technology mainly conducts the heat generated by the chip to the heat sink through the bottom heat dissipation path. However, this method has a large thermal resistance and limited heat transfer channels, which is difficult to meet the heat dissipation requirements of high-power gallium nitride devices. Under high-power operation, gallium nitride devices will generate a lot of heat. If it cannot be dissipated in time and effectively, the chip temperature will rise, which will affect the performance and reliability of the device. The temperature rise will not only reduce the current load capacity and gate voltage stability of the device, but may also cause failure problems such as wire bonding detachment, solder delamination, and mold package cracking, or even directly cause the device to burn out. In addition, due to the difference in the thermal expansion coefficient of the packaging materials, high temperature will also aggravate the accumulation of thermal stress inside the device, further aggravating the risk of failure.

[0003] However, existing technologies mostly focus on optimizing a single heat dissipation path, such as using high thermal conductivity materials and improving heat dissipation structures. But under the dual pressure of high power density and compact packaging requirements, these measures often fail to achieve ideal heat dissipation effects. Therefore, in order to address the shortcomings of existing technologies in heat dissipation of high-power semiconductor devices, there is an urgent need to provide a high-heat-dissipation semiconductor packaging technology that can simultaneously enhance the heat dissipation paths on both the front and back of the chip, achieving rapid and balanced heat dissipation, thereby significantly improving the heat dissipation performance and reliability of gallium nitride devices in high-power applications. Summary of the Invention

[0004] To address the above technical problems, this invention provides a HEMT packaging structure, comprising:

[0005] A molding compound, the molding compound comprising a first surface, a second surface, and a peripheral portion connecting the first surface and the second surface;

[0006] A semiconductor device, wherein the molding compound encapsulates the semiconductor device, the semiconductor device including an active region and a passive region; the active region includes a plurality of cell units, the cell units including a substrate, the substrate including a front side and a back side, a III-V epitaxial layer disposed on the front side of the substrate, and a first electrode, a second electrode and a control electrode disposed on the III-V epitaxial layer and disposed between the first electrode and the second electrode, and a dielectric layer covering the first electrode, the second electrode and the control electrode;

[0007] A first heat dissipation metal body covers the surface of the active region and is configured to expose a first side of the encapsulation body. The first heat dissipation metal body is insulated from the first electrode, the second electrode, and the control electrode.

[0008] A second heat dissipation metal body covers the back side of the substrate and is configured to expose the second side of the encapsulation. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the HEMT package structure provided by some embodiments of the present invention;

[0010] Figure 2 This is a cross-sectional schematic diagram of a high heat dissipation semiconductor packaging structure provided in some embodiments of the present invention;

[0011] Figure 3 This is a schematic diagram of the arrangement of a double-sided heat dissipation system provided in some embodiments of the present invention;

[0012] Figure 4 This is a top view schematic diagram of the HEMT package structure provided in some embodiments of the present invention;

[0013] Figure 5 This is a schematic diagram of a single cell structure of a HEMT packaging structure provided by some embodiments of the present invention;

[0014] Figure 6 This is a schematic diagram of a single cell structure of another HEMT packaging structure provided by some embodiments of the present invention;

[0015] Figure 7 This is a schematic diagram of a single cell unit structure of another HEMT packaging structure provided by some embodiments of the present invention;

[0016] Figure 8 This is a schematic diagram of a multi-cell unit structure of a HEMT packaging structure provided by some embodiments of the present invention;

[0017] Figure 9 This is a cross-sectional schematic diagram of a multi-cell unit structure of a HEMT packaging structure provided by some embodiments of the present invention. Detailed Implementation

[0018] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. The embodiments are given for illustrative purposes only and should not be construed as limiting the present invention. The accompanying drawings are for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0019] refer to Figure 1 , Figure 2 Some embodiments of the present invention provide a HEMT packaging structure, such as Figure 1 , Figure 2 As shown, the HEMT package structure includes a molding compound 1, a semiconductor device 15, a first heat dissipation metal body 13, and a second heat dissipation metal body 19. In some embodiments of the present invention, the molding compound 1 includes a first surface 111, a second surface 121, and a peripheral side portion connecting the first surface and the second surface. The molding compound effectively prevents the corrosion of the external environment by providing protection for the internal package, and at the same time serves as a support platform for the heat dissipation structure, ensuring the stability of the overall structure.

[0020] The molding compound is used to encapsulate the semiconductor device 15, which includes an active region and a passive region. The active region is the core area in the HEMT device responsible for current amplification and signal processing. The active region includes several cell units, each of which is a basic functional unit constituting the HEMT device. The cell unit includes a substrate, a III-V epitaxial layer, a first electrode, a second electrode, a control electrode, and a dielectric layer 14 covering the electrodes. These elements together constitute the current channel and control mechanism of the HEMT device. In some embodiments of the present invention, the substrate includes a front side and a back side. The III-V epitaxial layer is disposed on the front side of the substrate. The first electrode and the second electrode are disposed on the III-V epitaxial layer. The control electrode is disposed between the first electrode and the second electrode. The dielectric layer covers the first electrode, the second electrode, and the control electrode.

[0021] The passive region of a semiconductor device mainly includes a first electrode pad connected to a first electrode of a plurality of cell units, a second electrode pad connected to a second electrode of a plurality of cell units, and a control electrode pad connected to a control of a plurality of cell units. The first electrode pad is configured to extend from the peripheral side via a first pin 17, the second electrode pad is configured to extend from the peripheral side via a second pin 16, and the control electrode pad is configured to extend from the peripheral side via a third pin 18. The electrode pad is a metal area connected to the electrode in the active region, primarily used for connection to external circuits. The pin is a metal line extending from the edge of the device package, used to connect the electrode pad to the external circuit.

[0022] In some embodiments of the present invention, such as Figure 3As shown, the first heat dissipation metal body and the second heat dissipation metal body together constitute a double-sided heat dissipation system. The first heat dissipation metal body covers the surface of the active region and is configured to expose the first side of the molded body. The first heat dissipation metal body is insulated from the first electrode, the second electrode, and the control electrode. The second heat dissipation metal body covers the back side of the substrate and is configured to expose the second side of the molded body. In order to significantly enhance the heat dissipation surface area of ​​the package structure, some embodiments of the present invention configure the first heat dissipation metal body to expose the first side of the molded body with a larger area than the active region, forming an extension region 11 of the first heat dissipation metal body. By covering the first side of the molded body with a larger area than the active region, additional heat dissipation surface area is provided, which can more effectively conduct and dissipate heat, thereby further optimizing the heat dissipation performance of the entire package structure and ensuring that the semiconductor device can operate stably under high power or high frequency operating conditions.

[0023] In some embodiments of the present invention, the first heat dissipation metal body includes a first metal connection layer 150, a first metal layer 151, and a first solder layer 31 connected to the first metal layer 151 disposed on the surface of the dielectric layer of the active region. The material of the first metal connection layer may be selected from one or more of gold, aluminum, and copper; and / or, the material of the first metal layer may be selected from one or more of gold, aluminum, and copper. The material of the first solder layer may be made of heat-dissipating solder or adhesive (such as gold-tin solder, conductive silver paste, etc.). Those skilled in the art can adjust the materials of the first metal connection layer, the first metal layer, and the first solder layer according to specific implementation details, and are not limited to some embodiments of the present invention. Figure 4 This is a top view of the HEMT package structure, where S represents the source, D represents the drain, and G represents the gate. The first heat sink contacts the active region surface of the semiconductor device through a solder layer, achieving efficient heat conduction and effectively reducing the operating temperature of the semiconductor device. To ensure that the first heat sink fully covers and tightly adheres to the critical heat-generating areas of the semiconductor device, maximizing heat dissipation efficiency, this embodiment sets the area covered by the first heat sink on the active region surface to not exceed the active region. Figure 1 In this design, the horizontal length L3 of the first heat dissipation metal body is not greater than the horizontal length L1 of the active region of the semiconductor device. At the same time, the distance L2 between the first electrode pad, the second electrode pad, and the control electrode pad and the active region is set to be greater than 50 μm, i.e., L3≤L1, L2>50 μm, so that the first heat dissipation metal body can fully cover and effectively contact the main heat source area on the semiconductor device, thereby achieving efficient heat dissipation.

[0024] In some embodiments of the present invention, the second heat dissipation metal body includes a second metal connection layer 160 disposed on the back side of the substrate, a second metal layer, and a second solder layer 41 connecting the second metal layer. The material of the second metal connection layer is selected from one or more of gold, aluminum, and copper; and / or the material of the second metal layer is selected from one or more of gold, aluminum, and copper. Similarly, the material of the second solder layer can be made of heat dissipation solder or adhesive (such as gold-tin solder, conductive silver paste, etc.). Those skilled in the art can adjust the materials of the first metal connection layer, the first metal layer, and the first solder layer according to the specific implementation, and are not limited to some embodiments of the present invention.

[0025] In traditional semiconductor devices, thermally conductive metal blocks are typically connected to the electrodes on the semiconductor device to achieve heat dissipation. However, while this connection method can achieve heat dissipation to a certain extent, it introduces additional parasitic capacitance and inductance, which can negatively impact circuit performance. For example, these parasitic elements can interfere with normal circuit operation or pose a potential risk of electrical short circuits. Therefore, compared to the traditional method of connecting thermally conductive metal blocks to electrodes, some embodiments of the present invention configure the thermally conductive metal layer to be unconnected to all electrodes in the semiconductor chip, effectively avoiding the generation of parasitic capacitance and inductance, improving circuit performance and system reliability. At the same time, by maximizing the proximity of the metal layer to the heat source area of ​​the semiconductor chip, the heat conduction path is greatly shortened, allowing the heat generated by the semiconductor device during operation to be quickly and efficiently conducted and dissipated from the heat source area to the external environment, thereby keeping the semiconductor device at a stable operating temperature.

[0026] The following will combine Figures 1 to 9 This invention provides a detailed description of the HEMT package structure. In some embodiments of the invention, a first groove 21 is provided on the surface of the dielectric layer of the active region. The first groove is configured to span several cell units of the active region. The first heat dissipation metal body includes a first metal connection layer disposed in the first groove, a first solder layer disposed on the first metal connection layer, and a first metal layer disposed on the first solder layer. Specifically, in some embodiments of the invention, a first groove can be provided on the surface of the dielectric layer of the active region, and the first metal connection layer can be disposed in the first groove to achieve electrical connection with other circuits or components. In some embodiments of the invention, the first groove can be, but is not limited to, a spherical groove, an arc-shaped groove, or a rectangular groove. Those skilled in the art can set it to other shapes of grooves according to specific implementation conditions.

[0027] In some embodiments of the present invention, a plurality of second grooves 22 are provided on the surface of the dielectric layer of the active region. Each second groove is disposed in the dielectric layer above the control electrode of a single cell unit. The projection of each second groove on the III-V epitaxial layer does not contact the first electrode and the second electrode in the single cell unit. The first heat dissipation metal body includes a first metal connection layer disposed in the second groove, a first solder layer disposed on the first metal connection layer, and a first metal layer disposed on the first solder layer. The first metal layer is connected as a whole on the surface of the active region of the semiconductor device, and the first metal layer forms an integrated coverage on the surface of the active region of the device, which greatly enhances the heat conduction and diffusion capabilities. In some embodiments of the present invention, the first metal connection layer is disposed in the plurality of second grooves to realize electrical connection with other circuits or components. The second grooves do not form electrical connection with any electrode inside the semiconductor device, which can ensure electrical insulation and realize reliable connection with external circuits or components, effectively suppressing the generation of parasitic capacitance and parasitic inductance.

[0028] In some embodiments of the present invention, such as Figure 6 As shown, the second groove includes a first-level sub-groove near the surface of the active region and a second-level sub-groove connected below the first-level sub-groove, wherein the opening of the first-level sub-groove is larger than the opening of the second-level sub-groove.

[0029] In some embodiments of the present invention, a fourth groove 23 is provided on the back side of the substrate of the active region, and the second heat dissipation metal body includes a second metal connection layer that fills the fourth groove and covers the back side of the substrate, a second solder layer that covers the second metal connection layer, and a second metal layer that covers the second solder layer.

[0030] In other embodiments of the present invention, based on the above embodiments, a plurality of third grooves 24 are provided on the back side of the active region substrate. The second heat dissipation metal body includes a second metal connection layer that fills the third grooves and covers the back side of the substrate, a second solder layer that covers the second metal connection layer, and a second metal layer that covers the second solder layer. In some embodiments of the present invention, the second metal connection layer is disposed in the third grooves. These grooves serve as carriers for the metal connection layer, providing an efficient heat dissipation path for the back side of the substrate. At the same time, the second metal layer is connected into a whole on the back side of the active region substrate of the semiconductor device. The second metal layer forms an integrated cover on the back side of the active region substrate of the device, further optimizing the overall heat dissipation performance to meet the back side heat dissipation requirements.

[0031] In some embodiments of the present invention, grooves are provided on both the surface of the active region dielectric layer and the back side of the substrate, and metal interconnect layers are disposed in the corresponding grooves. The metal interconnect layers act as bridges for heat conduction, effectively dispersing and dissipating heat generated inside the device to simultaneously meet the device's double-sided heat dissipation requirements. Figure 8 As shown, the surface of the first metal connection layer has several island-shaped protrusions. Those skilled in the art can set the shape of the surface protrusions of the first metal connection layer according to the specific implementation to maximize the heat dissipation effect, and are not limited to some embodiments of the present invention.

[0032] Some embodiments of the present invention provide a HEMT package structure, the HEMT package structure including a molding compound, the molding compound including a first surface, a second surface, and a peripheral portion connecting the first surface and the second surface; the molding compound encapsulates a semiconductor device, the semiconductor device including an active region and a passive region; the active region includes a plurality of cell units, the cell unit including a substrate, a III-V epitaxial layer disposed on the front side of the substrate, and a first electrode, a second electrode, and a control electrode disposed on the III-V epitaxial layer, and a dielectric layer covering the first electrode, the second electrode, and the control electrode; a first heat dissipation metal body, the first heat dissipation metal body covering the surface of the active region and configured to expose the first surface of the molding compound, the first heat dissipation metal body being insulated from the first electrode, the second electrode, and the control electrode; and a second heat dissipation metal body, the second heat dissipation metal body covering the back side of the substrate and configured to expose the second surface of the molding compound. Compared with the prior art, some embodiments of the present invention provide a HEMT packaging structure that achieves simultaneous heat dissipation on the front and back sides of the semiconductor device by integrating structures such as double-sided heat dissipation metal bodies, which significantly improves heat dissipation efficiency. At the same time, the heat dissipation metal bodies are not electrically connected to any electrodes, which not only more effectively conducts heat away from the active surface of the semiconductor chip, but also avoids parasitic capacitance and parasitic inductance caused by electrical connections, improves circuit stability, and improves the heat dissipation performance of the HEMT packaging structure.

[0033] The embodiments described above are merely preferred embodiments of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the technical principles of this invention, and these improvements and substitutions should also be considered within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the scope of the claims.

Claims

1. A HEMT packaging structure, characterized in that, include: A molding compound, the molding compound comprising a first surface, a second surface, and a peripheral portion connecting the first surface and the second surface; A semiconductor device, wherein the molding compound encapsulates the semiconductor device, the semiconductor device including an active region and a passive region; the active region includes a plurality of cell units, the cell units including a substrate, the substrate including a front side and a back side, a III-V epitaxial layer disposed on the front side of the substrate, and a first electrode, a second electrode and a control electrode disposed on the III-V epitaxial layer and disposed between the first electrode and the second electrode, and a dielectric layer covering the first electrode, the second electrode and the control electrode; A first heat dissipation metal body covers the surface of the active region and is configured to expose a first side of the encapsulation body. The first heat dissipation metal body is insulated from the first electrode, the second electrode, and the control electrode. A second heat dissipation metal body covers the back side of the substrate and is configured to expose the second side of the encapsulation.

2. The HEMT packaging structure according to claim 1, characterized in that, The passive region includes a first electrode pad connected to a first electrode of a plurality of cell units, a second electrode pad connected to a second electrode of a plurality of cell units, and a control electrode pad connected to a control of a plurality of cell units. The first electrode pad is configured to be led out from the peripheral side via a first pin, the second electrode pad is configured to be led out from the peripheral side via a second pin, and the control electrode pad is configured to be led out from the peripheral side via a third pin.

3. The HEMT packaging structure according to claim 1, characterized in that, The first heat dissipation metal body is configured to expose a larger area than the active region on the first surface of the molding compound after exposing the first surface of the molding compound.

4. The HEMT packaging structure according to any one of claims 1 to 3, characterized in that, The first heat dissipation metal body includes a first metal connection layer disposed on the surface of the dielectric layer in the active region, a first metal layer, and a first solder layer connecting the first metal layer; and / or, The second heat dissipation metal body includes a second metal connection layer disposed on the back side of the substrate, a second metal layer, and a second solder layer connecting the second metal layer.

5. The HEMT packaging structure according to claim 4, characterized in that, The material of the first metal bonding layer is selected from one or more of gold, aluminum, and copper; and / or, The material of the second metal bonding layer is selected from one or more of gold, aluminum, and copper; The material of the first metal layer is selected from one or more of gold, aluminum, and copper; and / or, The material of the second metal layer is selected from one or more of gold, aluminum, and copper.

6. The HEMT packaging structure according to claim 4, characterized in that, A first groove is provided on the surface of the dielectric layer of the active region. The first groove is configured to span several cell units of the active region. The first heat dissipation metal body includes a first metal connection layer disposed in the first groove, a first solder layer disposed on the first metal connection layer, and a first metal layer disposed on the first solder layer.

7. The HEMT packaging structure according to claim 4, characterized in that, The surface of the dielectric layer in the active region is provided with a plurality of second grooves; Each of the second grooves is disposed in a dielectric layer above the control electrode of a single cell unit, and the projection of each of the second grooves on the III-V epitaxial layer does not contact the first electrode and the second electrode in the single cell unit; The first heat dissipation metal body includes a first metal connection layer disposed in the second groove, a first solder layer disposed on the first metal connection layer, and a first metal layer disposed on the first solder layer, wherein the first metal layer is connected as a whole on the active region surface of the semiconductor device.

8. The HEMT packaging structure according to any one of claims 6 or 7, characterized in that, The surface of the first metal bonding layer has several island-shaped protrusions.

9. The HEMT packaging structure according to claim 7, characterized in that, The second groove includes a first-level sub-groove near the surface of the active region and a second-level sub-groove connected below the first-level sub-groove, wherein the opening of the first-level sub-groove is larger than the opening of the second-level sub-groove.

10. The HEMT packaging structure according to claim 4, characterized in that, The back side of the substrate of the active region is provided with a plurality of third grooves, and the second heat dissipation metal body includes a second metal connection layer that fills the third grooves and covers the back side of the substrate, a second solder layer that covers the second metal connection layer, and a second metal layer that covers the second solder layer.

11. The HEMT packaging structure according to claim 1, characterized in that, The area covered by the active region surface of the first heat dissipation metal body does not exceed the active region.

12. The HEMT packaging structure according to claim 1, characterized in that, The distances between the first electrode pad, the second electrode pad, and the control electrode pad and the active region are all greater than 50 μm.

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